1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Intel Broxton SoC pinctrl/GPIO driver |
4 | * |
5 | * Copyright (C) 2015, 2016 Intel Corporation |
6 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
7 | */ |
8 | |
9 | #include <linux/mod_devicetable.h> |
10 | #include <linux/module.h> |
11 | #include <linux/platform_device.h> |
12 | #include <linux/pm.h> |
13 | |
14 | #include <linux/pinctrl/pinctrl.h> |
15 | |
16 | #include "pinctrl-intel.h" |
17 | |
18 | #define BXT_PAD_OWN 0x020 |
19 | #define BXT_PADCFGLOCK 0x060 |
20 | #define BXT_HOSTSW_OWN 0x080 |
21 | #define BXT_GPI_IS 0x100 |
22 | #define BXT_GPI_IE 0x110 |
23 | |
24 | #define (b, s, e) \ |
25 | INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, BXT) |
26 | |
27 | /* BXT */ |
28 | static const struct pinctrl_pin_desc bxt_north_pins[] = { |
29 | PINCTRL_PIN(0, "GPIO_0" ), |
30 | PINCTRL_PIN(1, "GPIO_1" ), |
31 | PINCTRL_PIN(2, "GPIO_2" ), |
32 | PINCTRL_PIN(3, "GPIO_3" ), |
33 | PINCTRL_PIN(4, "GPIO_4" ), |
34 | PINCTRL_PIN(5, "GPIO_5" ), |
35 | PINCTRL_PIN(6, "GPIO_6" ), |
36 | PINCTRL_PIN(7, "GPIO_7" ), |
37 | PINCTRL_PIN(8, "GPIO_8" ), |
38 | PINCTRL_PIN(9, "GPIO_9" ), |
39 | PINCTRL_PIN(10, "GPIO_10" ), |
40 | PINCTRL_PIN(11, "GPIO_11" ), |
41 | PINCTRL_PIN(12, "GPIO_12" ), |
42 | PINCTRL_PIN(13, "GPIO_13" ), |
43 | PINCTRL_PIN(14, "GPIO_14" ), |
44 | PINCTRL_PIN(15, "GPIO_15" ), |
45 | PINCTRL_PIN(16, "GPIO_16" ), |
46 | PINCTRL_PIN(17, "GPIO_17" ), |
47 | PINCTRL_PIN(18, "GPIO_18" ), |
48 | PINCTRL_PIN(19, "GPIO_19" ), |
49 | PINCTRL_PIN(20, "GPIO_20" ), |
50 | PINCTRL_PIN(21, "GPIO_21" ), |
51 | PINCTRL_PIN(22, "GPIO_22" ), |
52 | PINCTRL_PIN(23, "GPIO_23" ), |
53 | PINCTRL_PIN(24, "GPIO_24" ), |
54 | PINCTRL_PIN(25, "GPIO_25" ), |
55 | PINCTRL_PIN(26, "GPIO_26" ), |
56 | PINCTRL_PIN(27, "GPIO_27" ), |
57 | PINCTRL_PIN(28, "GPIO_28" ), |
58 | PINCTRL_PIN(29, "GPIO_29" ), |
59 | PINCTRL_PIN(30, "GPIO_30" ), |
60 | PINCTRL_PIN(31, "GPIO_31" ), |
61 | PINCTRL_PIN(32, "GPIO_32" ), |
62 | PINCTRL_PIN(33, "GPIO_33" ), |
63 | PINCTRL_PIN(34, "PWM0" ), |
64 | PINCTRL_PIN(35, "PWM1" ), |
65 | PINCTRL_PIN(36, "PWM2" ), |
66 | PINCTRL_PIN(37, "PWM3" ), |
67 | PINCTRL_PIN(38, "LPSS_UART0_RXD" ), |
68 | PINCTRL_PIN(39, "LPSS_UART0_TXD" ), |
69 | PINCTRL_PIN(40, "LPSS_UART0_RTS_B" ), |
70 | PINCTRL_PIN(41, "LPSS_UART0_CTS_B" ), |
71 | PINCTRL_PIN(42, "LPSS_UART1_RXD" ), |
72 | PINCTRL_PIN(43, "LPSS_UART1_TXD" ), |
73 | PINCTRL_PIN(44, "LPSS_UART1_RTS_B" ), |
74 | PINCTRL_PIN(45, "LPSS_UART1_CTS_B" ), |
75 | PINCTRL_PIN(46, "LPSS_UART2_RXD" ), |
76 | PINCTRL_PIN(47, "LPSS_UART2_TXD" ), |
77 | PINCTRL_PIN(48, "LPSS_UART2_RTS_B" ), |
78 | PINCTRL_PIN(49, "LPSS_UART2_CTS_B" ), |
79 | PINCTRL_PIN(50, "ISH_UART0_RXD" ), |
80 | PINCTRL_PIN(51, "ISH_UART0_TXT" ), |
81 | PINCTRL_PIN(52, "ISH_UART0_RTS_B" ), |
82 | PINCTRL_PIN(53, "ISH_UART0_CTS_B" ), |
83 | PINCTRL_PIN(54, "ISH_UART1_RXD" ), |
84 | PINCTRL_PIN(55, "ISH_UART1_TXT" ), |
85 | PINCTRL_PIN(56, "ISH_UART1_RTS_B" ), |
86 | PINCTRL_PIN(57, "ISH_UART1_CTS_B" ), |
87 | PINCTRL_PIN(58, "ISH_UART2_RXD" ), |
88 | PINCTRL_PIN(59, "ISH_UART2_TXD" ), |
89 | PINCTRL_PIN(60, "ISH_UART2_RTS_B" ), |
90 | PINCTRL_PIN(61, "ISH_UART2_CTS_B" ), |
91 | PINCTRL_PIN(62, "GP_CAMERASB00" ), |
92 | PINCTRL_PIN(63, "GP_CAMERASB01" ), |
93 | PINCTRL_PIN(64, "GP_CAMERASB02" ), |
94 | PINCTRL_PIN(65, "GP_CAMERASB03" ), |
95 | PINCTRL_PIN(66, "GP_CAMERASB04" ), |
96 | PINCTRL_PIN(67, "GP_CAMERASB05" ), |
97 | PINCTRL_PIN(68, "GP_CAMERASB06" ), |
98 | PINCTRL_PIN(69, "GP_CAMERASB07" ), |
99 | PINCTRL_PIN(70, "GP_CAMERASB08" ), |
100 | PINCTRL_PIN(71, "GP_CAMERASB09" ), |
101 | PINCTRL_PIN(72, "GP_CAMERASB10" ), |
102 | PINCTRL_PIN(73, "GP_CAMERASB11" ), |
103 | PINCTRL_PIN(74, "TCK" ), |
104 | PINCTRL_PIN(75, "TRST_B" ), |
105 | PINCTRL_PIN(76, "TMS" ), |
106 | PINCTRL_PIN(77, "TDI" ), |
107 | PINCTRL_PIN(78, "CX_PMODE" ), |
108 | PINCTRL_PIN(79, "CX_PREQ_B" ), |
109 | PINCTRL_PIN(80, "JTAGX" ), |
110 | PINCTRL_PIN(81, "CX_PRDY_B" ), |
111 | PINCTRL_PIN(82, "TDO" ), |
112 | }; |
113 | |
114 | static const unsigned int bxt_north_pwm0_pins[] = { 34 }; |
115 | static const unsigned int bxt_north_pwm1_pins[] = { 35 }; |
116 | static const unsigned int bxt_north_pwm2_pins[] = { 36 }; |
117 | static const unsigned int bxt_north_pwm3_pins[] = { 37 }; |
118 | static const unsigned int bxt_north_uart0_pins[] = { 38, 39, 40, 41 }; |
119 | static const unsigned int bxt_north_uart1_pins[] = { 42, 43, 44, 45 }; |
120 | static const unsigned int bxt_north_uart2_pins[] = { 46, 47, 48, 49 }; |
121 | static const unsigned int bxt_north_uart0b_pins[] = { 50, 51, 52, 53 }; |
122 | static const unsigned int bxt_north_uart1b_pins[] = { 54, 55, 56, 57 }; |
123 | static const unsigned int bxt_north_uart2b_pins[] = { 58, 59, 60, 61 }; |
124 | static const unsigned int bxt_north_uart3_pins[] = { 58, 59, 60, 61 }; |
125 | |
126 | static const struct intel_pingroup bxt_north_groups[] = { |
127 | PIN_GROUP("pwm0_grp" , bxt_north_pwm0_pins, 1), |
128 | PIN_GROUP("pwm1_grp" , bxt_north_pwm1_pins, 1), |
129 | PIN_GROUP("pwm2_grp" , bxt_north_pwm2_pins, 1), |
130 | PIN_GROUP("pwm3_grp" , bxt_north_pwm3_pins, 1), |
131 | PIN_GROUP("uart0_grp" , bxt_north_uart0_pins, 1), |
132 | PIN_GROUP("uart1_grp" , bxt_north_uart1_pins, 1), |
133 | PIN_GROUP("uart2_grp" , bxt_north_uart2_pins, 1), |
134 | PIN_GROUP("uart0b_grp" , bxt_north_uart0b_pins, 2), |
135 | PIN_GROUP("uart1b_grp" , bxt_north_uart1b_pins, 2), |
136 | PIN_GROUP("uart2b_grp" , bxt_north_uart2b_pins, 2), |
137 | PIN_GROUP("uart3_grp" , bxt_north_uart3_pins, 3), |
138 | }; |
139 | |
140 | static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" }; |
141 | static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" }; |
142 | static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" }; |
143 | static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" }; |
144 | static const char * const bxt_north_uart0_groups[] = { |
145 | "uart0_grp" , "uart0b_grp" , |
146 | }; |
147 | static const char * const bxt_north_uart1_groups[] = { |
148 | "uart1_grp" , "uart1b_grp" , |
149 | }; |
150 | static const char * const bxt_north_uart2_groups[] = { |
151 | "uart2_grp" , "uart2b_grp" , |
152 | }; |
153 | static const char * const bxt_north_uart3_groups[] = { "uart3_grp" }; |
154 | |
155 | static const struct intel_function bxt_north_functions[] = { |
156 | FUNCTION("pwm0" , bxt_north_pwm0_groups), |
157 | FUNCTION("pwm1" , bxt_north_pwm1_groups), |
158 | FUNCTION("pwm2" , bxt_north_pwm2_groups), |
159 | FUNCTION("pwm3" , bxt_north_pwm3_groups), |
160 | FUNCTION("uart0" , bxt_north_uart0_groups), |
161 | FUNCTION("uart1" , bxt_north_uart1_groups), |
162 | FUNCTION("uart2" , bxt_north_uart2_groups), |
163 | FUNCTION("uart3" , bxt_north_uart3_groups), |
164 | }; |
165 | |
166 | static const struct intel_community bxt_north_communities[] = { |
167 | BXT_COMMUNITY(0, 0, 82), |
168 | }; |
169 | |
170 | static const struct intel_pinctrl_soc_data bxt_north_soc_data = { |
171 | .uid = "1" , |
172 | .pins = bxt_north_pins, |
173 | .npins = ARRAY_SIZE(bxt_north_pins), |
174 | .groups = bxt_north_groups, |
175 | .ngroups = ARRAY_SIZE(bxt_north_groups), |
176 | .functions = bxt_north_functions, |
177 | .nfunctions = ARRAY_SIZE(bxt_north_functions), |
178 | .communities = bxt_north_communities, |
179 | .ncommunities = ARRAY_SIZE(bxt_north_communities), |
180 | }; |
181 | |
182 | static const struct pinctrl_pin_desc bxt_northwest_pins[] = { |
183 | PINCTRL_PIN(0, "PMC_SPI_FS0" ), |
184 | PINCTRL_PIN(1, "PMC_SPI_FS1" ), |
185 | PINCTRL_PIN(2, "PMC_SPI_FS2" ), |
186 | PINCTRL_PIN(3, "PMC_SPI_RXD" ), |
187 | PINCTRL_PIN(4, "PMC_SPI_TXD" ), |
188 | PINCTRL_PIN(5, "PMC_SPI_CLK" ), |
189 | PINCTRL_PIN(6, "PMC_UART_RXD" ), |
190 | PINCTRL_PIN(7, "PMC_UART_TXD" ), |
191 | PINCTRL_PIN(8, "PMIC_PWRGOOD" ), |
192 | PINCTRL_PIN(9, "PMIC_RESET_B" ), |
193 | PINCTRL_PIN(10, "RTC_CLK" ), |
194 | PINCTRL_PIN(11, "PMIC_SDWN_B" ), |
195 | PINCTRL_PIN(12, "PMIC_BCUDISW2" ), |
196 | PINCTRL_PIN(13, "PMIC_BCUDISCRIT" ), |
197 | PINCTRL_PIN(14, "PMIC_THERMTRIP_B" ), |
198 | PINCTRL_PIN(15, "PMIC_STDBY" ), |
199 | PINCTRL_PIN(16, "SVID0_ALERT_B" ), |
200 | PINCTRL_PIN(17, "SVID0_DATA" ), |
201 | PINCTRL_PIN(18, "SVID0_CLK" ), |
202 | PINCTRL_PIN(19, "PMIC_I2C_SCL" ), |
203 | PINCTRL_PIN(20, "PMIC_I2C_SDA" ), |
204 | PINCTRL_PIN(21, "AVS_I2S1_MCLK" ), |
205 | PINCTRL_PIN(22, "AVS_I2S1_BCLK" ), |
206 | PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC" ), |
207 | PINCTRL_PIN(24, "AVS_I2S1_SDI" ), |
208 | PINCTRL_PIN(25, "AVS_I2S1_SDO" ), |
209 | PINCTRL_PIN(26, "AVS_M_CLK_A1" ), |
210 | PINCTRL_PIN(27, "AVS_M_CLK_B1" ), |
211 | PINCTRL_PIN(28, "AVS_M_DATA_1" ), |
212 | PINCTRL_PIN(29, "AVS_M_CLK_AB2" ), |
213 | PINCTRL_PIN(30, "AVS_M_DATA_2" ), |
214 | PINCTRL_PIN(31, "AVS_I2S2_MCLK" ), |
215 | PINCTRL_PIN(32, "AVS_I2S2_BCLK" ), |
216 | PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC" ), |
217 | PINCTRL_PIN(34, "AVS_I2S2_SDI" ), |
218 | PINCTRL_PIN(35, "AVS_I2S2_SDOK" ), |
219 | PINCTRL_PIN(36, "AVS_I2S3_BCLK" ), |
220 | PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC" ), |
221 | PINCTRL_PIN(38, "AVS_I2S3_SDI" ), |
222 | PINCTRL_PIN(39, "AVS_I2S3_SDO" ), |
223 | PINCTRL_PIN(40, "AVS_I2S4_BCLK" ), |
224 | PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC" ), |
225 | PINCTRL_PIN(42, "AVS_I2S4_SDI" ), |
226 | PINCTRL_PIN(43, "AVS_I2S4_SDO" ), |
227 | PINCTRL_PIN(44, "PROCHOT_B" ), |
228 | PINCTRL_PIN(45, "FST_SPI_CS0_B" ), |
229 | PINCTRL_PIN(46, "FST_SPI_CS1_B" ), |
230 | PINCTRL_PIN(47, "FST_SPI_MOSI_IO0" ), |
231 | PINCTRL_PIN(48, "FST_SPI_MISO_IO1" ), |
232 | PINCTRL_PIN(49, "FST_SPI_IO2" ), |
233 | PINCTRL_PIN(50, "FST_SPI_IO3" ), |
234 | PINCTRL_PIN(51, "FST_SPI_CLK" ), |
235 | PINCTRL_PIN(52, "FST_SPI_CLK_FB" ), |
236 | PINCTRL_PIN(53, "GP_SSP_0_CLK" ), |
237 | PINCTRL_PIN(54, "GP_SSP_0_FS0" ), |
238 | PINCTRL_PIN(55, "GP_SSP_0_FS1" ), |
239 | PINCTRL_PIN(56, "GP_SSP_0_FS2" ), |
240 | PINCTRL_PIN(57, "GP_SSP_0_RXD" ), |
241 | PINCTRL_PIN(58, "GP_SSP_0_TXD" ), |
242 | PINCTRL_PIN(59, "GP_SSP_1_CLK" ), |
243 | PINCTRL_PIN(60, "GP_SSP_1_FS0" ), |
244 | PINCTRL_PIN(61, "GP_SSP_1_FS1" ), |
245 | PINCTRL_PIN(62, "GP_SSP_1_FS2" ), |
246 | PINCTRL_PIN(63, "GP_SSP_1_FS3" ), |
247 | PINCTRL_PIN(64, "GP_SSP_1_RXD" ), |
248 | PINCTRL_PIN(65, "GP_SSP_1_TXD" ), |
249 | PINCTRL_PIN(66, "GP_SSP_2_CLK" ), |
250 | PINCTRL_PIN(67, "GP_SSP_2_FS0" ), |
251 | PINCTRL_PIN(68, "GP_SSP_2_FS1" ), |
252 | PINCTRL_PIN(69, "GP_SSP_2_FS2" ), |
253 | PINCTRL_PIN(70, "GP_SSP_2_RXD" ), |
254 | PINCTRL_PIN(71, "GP_SSP_2_TXD" ), |
255 | }; |
256 | |
257 | static const unsigned int bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 }; |
258 | static const unsigned int bxt_northwest_ssp1_pins[] = { |
259 | 59, 60, 61, 62, 63, 64, 65 |
260 | }; |
261 | static const unsigned int bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 }; |
262 | static const unsigned int bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 }; |
263 | |
264 | static const struct intel_pingroup bxt_northwest_groups[] = { |
265 | PIN_GROUP("ssp0_grp" , bxt_northwest_ssp0_pins, 1), |
266 | PIN_GROUP("ssp1_grp" , bxt_northwest_ssp1_pins, 1), |
267 | PIN_GROUP("ssp2_grp" , bxt_northwest_ssp2_pins, 1), |
268 | PIN_GROUP("uart3_grp" , bxt_northwest_uart3_pins, 2), |
269 | }; |
270 | |
271 | static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" }; |
272 | static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" }; |
273 | static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" }; |
274 | static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" }; |
275 | |
276 | static const struct intel_function bxt_northwest_functions[] = { |
277 | FUNCTION("ssp0" , bxt_northwest_ssp0_groups), |
278 | FUNCTION("ssp1" , bxt_northwest_ssp1_groups), |
279 | FUNCTION("ssp2" , bxt_northwest_ssp2_groups), |
280 | FUNCTION("uart3" , bxt_northwest_uart3_groups), |
281 | }; |
282 | |
283 | static const struct intel_community bxt_northwest_communities[] = { |
284 | BXT_COMMUNITY(0, 0, 71), |
285 | }; |
286 | |
287 | static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = { |
288 | .uid = "2" , |
289 | .pins = bxt_northwest_pins, |
290 | .npins = ARRAY_SIZE(bxt_northwest_pins), |
291 | .groups = bxt_northwest_groups, |
292 | .ngroups = ARRAY_SIZE(bxt_northwest_groups), |
293 | .functions = bxt_northwest_functions, |
294 | .nfunctions = ARRAY_SIZE(bxt_northwest_functions), |
295 | .communities = bxt_northwest_communities, |
296 | .ncommunities = ARRAY_SIZE(bxt_northwest_communities), |
297 | }; |
298 | |
299 | static const struct pinctrl_pin_desc bxt_west_pins[] = { |
300 | PINCTRL_PIN(0, "LPSS_I2C0_SDA" ), |
301 | PINCTRL_PIN(1, "LPSS_I2C0_SCL" ), |
302 | PINCTRL_PIN(2, "LPSS_I2C1_SDA" ), |
303 | PINCTRL_PIN(3, "LPSS_I2C1_SCL" ), |
304 | PINCTRL_PIN(4, "LPSS_I2C2_SDA" ), |
305 | PINCTRL_PIN(5, "LPSS_I2C2_SCL" ), |
306 | PINCTRL_PIN(6, "LPSS_I2C3_SDA" ), |
307 | PINCTRL_PIN(7, "LPSS_I2C3_SCL" ), |
308 | PINCTRL_PIN(8, "LPSS_I2C4_SDA" ), |
309 | PINCTRL_PIN(9, "LPSS_I2C4_SCL" ), |
310 | PINCTRL_PIN(10, "LPSS_I2C5_SDA" ), |
311 | PINCTRL_PIN(11, "LPSS_I2C5_SCL" ), |
312 | PINCTRL_PIN(12, "LPSS_I2C6_SDA" ), |
313 | PINCTRL_PIN(13, "LPSS_I2C6_SCL" ), |
314 | PINCTRL_PIN(14, "LPSS_I2C7_SDA" ), |
315 | PINCTRL_PIN(15, "LPSS_I2C7_SCL" ), |
316 | PINCTRL_PIN(16, "ISH_I2C0_SDA" ), |
317 | PINCTRL_PIN(17, "ISH_I2C0_SCL" ), |
318 | PINCTRL_PIN(18, "ISH_I2C1_SDA" ), |
319 | PINCTRL_PIN(19, "ISH_I2C1_SCL" ), |
320 | PINCTRL_PIN(20, "ISH_I2C2_SDA" ), |
321 | PINCTRL_PIN(21, "ISH_I2C2_SCL" ), |
322 | PINCTRL_PIN(22, "ISH_GPIO_0" ), |
323 | PINCTRL_PIN(23, "ISH_GPIO_1" ), |
324 | PINCTRL_PIN(24, "ISH_GPIO_2" ), |
325 | PINCTRL_PIN(25, "ISH_GPIO_3" ), |
326 | PINCTRL_PIN(26, "ISH_GPIO_4" ), |
327 | PINCTRL_PIN(27, "ISH_GPIO_5" ), |
328 | PINCTRL_PIN(28, "ISH_GPIO_6" ), |
329 | PINCTRL_PIN(29, "ISH_GPIO_7" ), |
330 | PINCTRL_PIN(30, "ISH_GPIO_8" ), |
331 | PINCTRL_PIN(31, "ISH_GPIO_9" ), |
332 | PINCTRL_PIN(32, "MODEM_CLKREQ" ), |
333 | PINCTRL_PIN(33, "DGCLKDBG_PMC_0" ), |
334 | PINCTRL_PIN(34, "DGCLKDBG_PMC_1" ), |
335 | PINCTRL_PIN(35, "DGCLKDBG_PMC_2" ), |
336 | PINCTRL_PIN(36, "DGCLKDBG_ICLK_0" ), |
337 | PINCTRL_PIN(37, "DGCLKDBG_ICLK_1" ), |
338 | PINCTRL_PIN(38, "OSC_CLK_OUT_0" ), |
339 | PINCTRL_PIN(39, "OSC_CLK_OUT_1" ), |
340 | PINCTRL_PIN(40, "OSC_CLK_OUT_2" ), |
341 | PINCTRL_PIN(41, "OSC_CLK_OUT_3" ), |
342 | }; |
343 | |
344 | static const unsigned int bxt_west_i2c0_pins[] = { 0, 1 }; |
345 | static const unsigned int bxt_west_i2c1_pins[] = { 2, 3 }; |
346 | static const unsigned int bxt_west_i2c2_pins[] = { 4, 5 }; |
347 | static const unsigned int bxt_west_i2c3_pins[] = { 6, 7 }; |
348 | static const unsigned int bxt_west_i2c4_pins[] = { 8, 9 }; |
349 | static const unsigned int bxt_west_i2c5_pins[] = { 10, 11 }; |
350 | static const unsigned int bxt_west_i2c6_pins[] = { 12, 13 }; |
351 | static const unsigned int bxt_west_i2c7_pins[] = { 14, 15 }; |
352 | static const unsigned int bxt_west_i2c5b_pins[] = { 16, 17 }; |
353 | static const unsigned int bxt_west_i2c6b_pins[] = { 18, 19 }; |
354 | static const unsigned int bxt_west_i2c7b_pins[] = { 20, 21 }; |
355 | |
356 | static const struct intel_pingroup bxt_west_groups[] = { |
357 | PIN_GROUP("i2c0_grp" , bxt_west_i2c0_pins, 1), |
358 | PIN_GROUP("i2c1_grp" , bxt_west_i2c1_pins, 1), |
359 | PIN_GROUP("i2c2_grp" , bxt_west_i2c2_pins, 1), |
360 | PIN_GROUP("i2c3_grp" , bxt_west_i2c3_pins, 1), |
361 | PIN_GROUP("i2c4_grp" , bxt_west_i2c4_pins, 1), |
362 | PIN_GROUP("i2c5_grp" , bxt_west_i2c5_pins, 1), |
363 | PIN_GROUP("i2c6_grp" , bxt_west_i2c6_pins, 1), |
364 | PIN_GROUP("i2c7_grp" , bxt_west_i2c7_pins, 1), |
365 | PIN_GROUP("i2c5b_grp" , bxt_west_i2c5b_pins, 2), |
366 | PIN_GROUP("i2c6b_grp" , bxt_west_i2c6b_pins, 2), |
367 | PIN_GROUP("i2c7b_grp" , bxt_west_i2c7b_pins, 2), |
368 | }; |
369 | |
370 | static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" }; |
371 | static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" }; |
372 | static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" }; |
373 | static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" }; |
374 | static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" }; |
375 | static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp" , "i2c5b_grp" }; |
376 | static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp" , "i2c6b_grp" }; |
377 | static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp" , "i2c7b_grp" }; |
378 | |
379 | static const struct intel_function bxt_west_functions[] = { |
380 | FUNCTION("i2c0" , bxt_west_i2c0_groups), |
381 | FUNCTION("i2c1" , bxt_west_i2c1_groups), |
382 | FUNCTION("i2c2" , bxt_west_i2c2_groups), |
383 | FUNCTION("i2c3" , bxt_west_i2c3_groups), |
384 | FUNCTION("i2c4" , bxt_west_i2c4_groups), |
385 | FUNCTION("i2c5" , bxt_west_i2c5_groups), |
386 | FUNCTION("i2c6" , bxt_west_i2c6_groups), |
387 | FUNCTION("i2c7" , bxt_west_i2c7_groups), |
388 | }; |
389 | |
390 | static const struct intel_community bxt_west_communities[] = { |
391 | BXT_COMMUNITY(0, 0, 41), |
392 | }; |
393 | |
394 | static const struct intel_pinctrl_soc_data bxt_west_soc_data = { |
395 | .uid = "3" , |
396 | .pins = bxt_west_pins, |
397 | .npins = ARRAY_SIZE(bxt_west_pins), |
398 | .groups = bxt_west_groups, |
399 | .ngroups = ARRAY_SIZE(bxt_west_groups), |
400 | .functions = bxt_west_functions, |
401 | .nfunctions = ARRAY_SIZE(bxt_west_functions), |
402 | .communities = bxt_west_communities, |
403 | .ncommunities = ARRAY_SIZE(bxt_west_communities), |
404 | }; |
405 | |
406 | static const struct pinctrl_pin_desc bxt_southwest_pins[] = { |
407 | PINCTRL_PIN(0, "EMMC0_CLK" ), |
408 | PINCTRL_PIN(1, "EMMC0_D0" ), |
409 | PINCTRL_PIN(2, "EMMC0_D1" ), |
410 | PINCTRL_PIN(3, "EMMC0_D2" ), |
411 | PINCTRL_PIN(4, "EMMC0_D3" ), |
412 | PINCTRL_PIN(5, "EMMC0_D4" ), |
413 | PINCTRL_PIN(6, "EMMC0_D5" ), |
414 | PINCTRL_PIN(7, "EMMC0_D6" ), |
415 | PINCTRL_PIN(8, "EMMC0_D7" ), |
416 | PINCTRL_PIN(9, "EMMC0_CMD" ), |
417 | PINCTRL_PIN(10, "SDIO_CLK" ), |
418 | PINCTRL_PIN(11, "SDIO_D0" ), |
419 | PINCTRL_PIN(12, "SDIO_D1" ), |
420 | PINCTRL_PIN(13, "SDIO_D2" ), |
421 | PINCTRL_PIN(14, "SDIO_D3" ), |
422 | PINCTRL_PIN(15, "SDIO_CMD" ), |
423 | PINCTRL_PIN(16, "SDCARD_CLK" ), |
424 | PINCTRL_PIN(17, "SDCARD_D0" ), |
425 | PINCTRL_PIN(18, "SDCARD_D1" ), |
426 | PINCTRL_PIN(19, "SDCARD_D2" ), |
427 | PINCTRL_PIN(20, "SDCARD_D3" ), |
428 | PINCTRL_PIN(21, "SDCARD_CD_B" ), |
429 | PINCTRL_PIN(22, "SDCARD_CMD" ), |
430 | PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB" ), |
431 | PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR" ), |
432 | PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR" ), |
433 | PINCTRL_PIN(26, "EMMC0_STROBE" ), |
434 | PINCTRL_PIN(27, "SDIO_PWR_DOWN_B" ), |
435 | PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B" ), |
436 | PINCTRL_PIN(29, "SDCARD_LVL_SEL" ), |
437 | PINCTRL_PIN(30, "SDCARD_LVL_WP" ), |
438 | }; |
439 | |
440 | static const unsigned int bxt_southwest_emmc0_pins[] = { |
441 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26, |
442 | }; |
443 | static const unsigned int bxt_southwest_sdio_pins[] = { |
444 | 10, 11, 12, 13, 14, 15, 27, |
445 | }; |
446 | static const unsigned int bxt_southwest_sdcard_pins[] = { |
447 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, |
448 | }; |
449 | |
450 | static const struct intel_pingroup bxt_southwest_groups[] = { |
451 | PIN_GROUP("emmc0_grp" , bxt_southwest_emmc0_pins, 1), |
452 | PIN_GROUP("sdio_grp" , bxt_southwest_sdio_pins, 1), |
453 | PIN_GROUP("sdcard_grp" , bxt_southwest_sdcard_pins, 1), |
454 | }; |
455 | |
456 | static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" }; |
457 | static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" }; |
458 | static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" }; |
459 | |
460 | static const struct intel_function bxt_southwest_functions[] = { |
461 | FUNCTION("emmc0" , bxt_southwest_emmc0_groups), |
462 | FUNCTION("sdio" , bxt_southwest_sdio_groups), |
463 | FUNCTION("sdcard" , bxt_southwest_sdcard_groups), |
464 | }; |
465 | |
466 | static const struct intel_community bxt_southwest_communities[] = { |
467 | BXT_COMMUNITY(0, 0, 30), |
468 | }; |
469 | |
470 | static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = { |
471 | .uid = "4" , |
472 | .pins = bxt_southwest_pins, |
473 | .npins = ARRAY_SIZE(bxt_southwest_pins), |
474 | .groups = bxt_southwest_groups, |
475 | .ngroups = ARRAY_SIZE(bxt_southwest_groups), |
476 | .functions = bxt_southwest_functions, |
477 | .nfunctions = ARRAY_SIZE(bxt_southwest_functions), |
478 | .communities = bxt_southwest_communities, |
479 | .ncommunities = ARRAY_SIZE(bxt_southwest_communities), |
480 | }; |
481 | |
482 | static const struct pinctrl_pin_desc bxt_south_pins[] = { |
483 | PINCTRL_PIN(0, "HV_DDI0_DDC_SDA" ), |
484 | PINCTRL_PIN(1, "HV_DDI0_DDC_SCL" ), |
485 | PINCTRL_PIN(2, "HV_DDI1_DDC_SDA" ), |
486 | PINCTRL_PIN(3, "HV_DDI1_DDC_SCL" ), |
487 | PINCTRL_PIN(4, "DBI_SDA" ), |
488 | PINCTRL_PIN(5, "DBI_SCL" ), |
489 | PINCTRL_PIN(6, "PANEL0_VDDEN" ), |
490 | PINCTRL_PIN(7, "PANEL0_BKLTEN" ), |
491 | PINCTRL_PIN(8, "PANEL0_BKLTCTL" ), |
492 | PINCTRL_PIN(9, "PANEL1_VDDEN" ), |
493 | PINCTRL_PIN(10, "PANEL1_BKLTEN" ), |
494 | PINCTRL_PIN(11, "PANEL1_BKLTCTL" ), |
495 | PINCTRL_PIN(12, "DBI_CSX" ), |
496 | PINCTRL_PIN(13, "DBI_RESX" ), |
497 | PINCTRL_PIN(14, "GP_INTD_DSI_TE1" ), |
498 | PINCTRL_PIN(15, "GP_INTD_DSI_TE2" ), |
499 | PINCTRL_PIN(16, "USB_OC0_B" ), |
500 | PINCTRL_PIN(17, "USB_OC1_B" ), |
501 | PINCTRL_PIN(18, "MEX_WAKE0_B" ), |
502 | PINCTRL_PIN(19, "MEX_WAKE1_B" ), |
503 | }; |
504 | |
505 | static const struct intel_community bxt_south_communities[] = { |
506 | BXT_COMMUNITY(0, 0, 19), |
507 | }; |
508 | |
509 | static const struct intel_pinctrl_soc_data bxt_south_soc_data = { |
510 | .uid = "5" , |
511 | .pins = bxt_south_pins, |
512 | .npins = ARRAY_SIZE(bxt_south_pins), |
513 | .communities = bxt_south_communities, |
514 | .ncommunities = ARRAY_SIZE(bxt_south_communities), |
515 | }; |
516 | |
517 | static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = { |
518 | &bxt_north_soc_data, |
519 | &bxt_northwest_soc_data, |
520 | &bxt_west_soc_data, |
521 | &bxt_southwest_soc_data, |
522 | &bxt_south_soc_data, |
523 | NULL |
524 | }; |
525 | |
526 | /* APL */ |
527 | static const struct pinctrl_pin_desc apl_north_pins[] = { |
528 | PINCTRL_PIN(0, "GPIO_0" ), |
529 | PINCTRL_PIN(1, "GPIO_1" ), |
530 | PINCTRL_PIN(2, "GPIO_2" ), |
531 | PINCTRL_PIN(3, "GPIO_3" ), |
532 | PINCTRL_PIN(4, "GPIO_4" ), |
533 | PINCTRL_PIN(5, "GPIO_5" ), |
534 | PINCTRL_PIN(6, "GPIO_6" ), |
535 | PINCTRL_PIN(7, "GPIO_7" ), |
536 | PINCTRL_PIN(8, "GPIO_8" ), |
537 | PINCTRL_PIN(9, "GPIO_9" ), |
538 | PINCTRL_PIN(10, "GPIO_10" ), |
539 | PINCTRL_PIN(11, "GPIO_11" ), |
540 | PINCTRL_PIN(12, "GPIO_12" ), |
541 | PINCTRL_PIN(13, "GPIO_13" ), |
542 | PINCTRL_PIN(14, "GPIO_14" ), |
543 | PINCTRL_PIN(15, "GPIO_15" ), |
544 | PINCTRL_PIN(16, "GPIO_16" ), |
545 | PINCTRL_PIN(17, "GPIO_17" ), |
546 | PINCTRL_PIN(18, "GPIO_18" ), |
547 | PINCTRL_PIN(19, "GPIO_19" ), |
548 | PINCTRL_PIN(20, "GPIO_20" ), |
549 | PINCTRL_PIN(21, "GPIO_21" ), |
550 | PINCTRL_PIN(22, "GPIO_22" ), |
551 | PINCTRL_PIN(23, "GPIO_23" ), |
552 | PINCTRL_PIN(24, "GPIO_24" ), |
553 | PINCTRL_PIN(25, "GPIO_25" ), |
554 | PINCTRL_PIN(26, "GPIO_26" ), |
555 | PINCTRL_PIN(27, "GPIO_27" ), |
556 | PINCTRL_PIN(28, "GPIO_28" ), |
557 | PINCTRL_PIN(29, "GPIO_29" ), |
558 | PINCTRL_PIN(30, "GPIO_30" ), |
559 | PINCTRL_PIN(31, "GPIO_31" ), |
560 | PINCTRL_PIN(32, "GPIO_32" ), |
561 | PINCTRL_PIN(33, "GPIO_33" ), |
562 | PINCTRL_PIN(34, "PWM0" ), |
563 | PINCTRL_PIN(35, "PWM1" ), |
564 | PINCTRL_PIN(36, "PWM2" ), |
565 | PINCTRL_PIN(37, "PWM3" ), |
566 | PINCTRL_PIN(38, "LPSS_UART0_RXD" ), |
567 | PINCTRL_PIN(39, "LPSS_UART0_TXD" ), |
568 | PINCTRL_PIN(40, "LPSS_UART0_RTS_B" ), |
569 | PINCTRL_PIN(41, "LPSS_UART0_CTS_B" ), |
570 | PINCTRL_PIN(42, "LPSS_UART1_RXD" ), |
571 | PINCTRL_PIN(43, "LPSS_UART1_TXD" ), |
572 | PINCTRL_PIN(44, "LPSS_UART1_RTS_B" ), |
573 | PINCTRL_PIN(45, "LPSS_UART1_CTS_B" ), |
574 | PINCTRL_PIN(46, "LPSS_UART2_RXD" ), |
575 | PINCTRL_PIN(47, "LPSS_UART2_TXD" ), |
576 | PINCTRL_PIN(48, "LPSS_UART2_RTS_B" ), |
577 | PINCTRL_PIN(49, "LPSS_UART2_CTS_B" ), |
578 | PINCTRL_PIN(50, "GP_CAMERASB00" ), |
579 | PINCTRL_PIN(51, "GP_CAMERASB01" ), |
580 | PINCTRL_PIN(52, "GP_CAMERASB02" ), |
581 | PINCTRL_PIN(53, "GP_CAMERASB03" ), |
582 | PINCTRL_PIN(54, "GP_CAMERASB04" ), |
583 | PINCTRL_PIN(55, "GP_CAMERASB05" ), |
584 | PINCTRL_PIN(56, "GP_CAMERASB06" ), |
585 | PINCTRL_PIN(57, "GP_CAMERASB07" ), |
586 | PINCTRL_PIN(58, "GP_CAMERASB08" ), |
587 | PINCTRL_PIN(59, "GP_CAMERASB09" ), |
588 | PINCTRL_PIN(60, "GP_CAMERASB10" ), |
589 | PINCTRL_PIN(61, "GP_CAMERASB11" ), |
590 | PINCTRL_PIN(62, "TCK" ), |
591 | PINCTRL_PIN(63, "TRST_B" ), |
592 | PINCTRL_PIN(64, "TMS" ), |
593 | PINCTRL_PIN(65, "TDI" ), |
594 | PINCTRL_PIN(66, "CX_PMODE" ), |
595 | PINCTRL_PIN(67, "CX_PREQ_B" ), |
596 | PINCTRL_PIN(68, "JTAGX" ), |
597 | PINCTRL_PIN(69, "CX_PRDY_B" ), |
598 | PINCTRL_PIN(70, "TDO" ), |
599 | PINCTRL_PIN(71, "CNV_BRI_DT" ), |
600 | PINCTRL_PIN(72, "CNV_BRI_RSP" ), |
601 | PINCTRL_PIN(73, "CNV_RGI_DT" ), |
602 | PINCTRL_PIN(74, "CNV_RGI_RSP" ), |
603 | PINCTRL_PIN(75, "SVID0_ALERT_B" ), |
604 | PINCTRL_PIN(76, "SVID0_DATA" ), |
605 | PINCTRL_PIN(77, "SVID0_CLK" ), |
606 | }; |
607 | |
608 | static const unsigned int apl_north_pwm0_pins[] = { 34 }; |
609 | static const unsigned int apl_north_pwm1_pins[] = { 35 }; |
610 | static const unsigned int apl_north_pwm2_pins[] = { 36 }; |
611 | static const unsigned int apl_north_pwm3_pins[] = { 37 }; |
612 | static const unsigned int apl_north_uart0_pins[] = { 38, 39, 40, 41 }; |
613 | static const unsigned int apl_north_uart1_pins[] = { 42, 43, 44, 45 }; |
614 | static const unsigned int apl_north_uart2_pins[] = { 46, 47, 48, 49 }; |
615 | |
616 | static const struct intel_pingroup apl_north_groups[] = { |
617 | PIN_GROUP("pwm0_grp" , apl_north_pwm0_pins, 1), |
618 | PIN_GROUP("pwm1_grp" , apl_north_pwm1_pins, 1), |
619 | PIN_GROUP("pwm2_grp" , apl_north_pwm2_pins, 1), |
620 | PIN_GROUP("pwm3_grp" , apl_north_pwm3_pins, 1), |
621 | PIN_GROUP("uart0_grp" , apl_north_uart0_pins, 1), |
622 | PIN_GROUP("uart1_grp" , apl_north_uart1_pins, 1), |
623 | PIN_GROUP("uart2_grp" , apl_north_uart2_pins, 1), |
624 | }; |
625 | |
626 | static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" }; |
627 | static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" }; |
628 | static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" }; |
629 | static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" }; |
630 | static const char * const apl_north_uart0_groups[] = { "uart0_grp" }; |
631 | static const char * const apl_north_uart1_groups[] = { "uart1_grp" }; |
632 | static const char * const apl_north_uart2_groups[] = { "uart2_grp" }; |
633 | |
634 | static const struct intel_function apl_north_functions[] = { |
635 | FUNCTION("pwm0" , apl_north_pwm0_groups), |
636 | FUNCTION("pwm1" , apl_north_pwm1_groups), |
637 | FUNCTION("pwm2" , apl_north_pwm2_groups), |
638 | FUNCTION("pwm3" , apl_north_pwm3_groups), |
639 | FUNCTION("uart0" , apl_north_uart0_groups), |
640 | FUNCTION("uart1" , apl_north_uart1_groups), |
641 | FUNCTION("uart2" , apl_north_uart2_groups), |
642 | }; |
643 | |
644 | static const struct intel_community apl_north_communities[] = { |
645 | BXT_COMMUNITY(0, 0, 77), |
646 | }; |
647 | |
648 | static const struct intel_pinctrl_soc_data apl_north_soc_data = { |
649 | .uid = "1" , |
650 | .pins = apl_north_pins, |
651 | .npins = ARRAY_SIZE(apl_north_pins), |
652 | .groups = apl_north_groups, |
653 | .ngroups = ARRAY_SIZE(apl_north_groups), |
654 | .functions = apl_north_functions, |
655 | .nfunctions = ARRAY_SIZE(apl_north_functions), |
656 | .communities = apl_north_communities, |
657 | .ncommunities = ARRAY_SIZE(apl_north_communities), |
658 | }; |
659 | |
660 | static const struct pinctrl_pin_desc apl_northwest_pins[] = { |
661 | PINCTRL_PIN(0, "HV_DDI0_DDC_SDA" ), |
662 | PINCTRL_PIN(1, "HV_DDI0_DDC_SCL" ), |
663 | PINCTRL_PIN(2, "HV_DDI1_DDC_SDA" ), |
664 | PINCTRL_PIN(3, "HV_DDI1_DDC_SCL" ), |
665 | PINCTRL_PIN(4, "DBI_SDA" ), |
666 | PINCTRL_PIN(5, "DBI_SCL" ), |
667 | PINCTRL_PIN(6, "PANEL0_VDDEN" ), |
668 | PINCTRL_PIN(7, "PANEL0_BKLTEN" ), |
669 | PINCTRL_PIN(8, "PANEL0_BKLTCTL" ), |
670 | PINCTRL_PIN(9, "PANEL1_VDDEN" ), |
671 | PINCTRL_PIN(10, "PANEL1_BKLTEN" ), |
672 | PINCTRL_PIN(11, "PANEL1_BKLTCTL" ), |
673 | PINCTRL_PIN(12, "DBI_CSX" ), |
674 | PINCTRL_PIN(13, "DBI_RESX" ), |
675 | PINCTRL_PIN(14, "GP_INTD_DSI_TE1" ), |
676 | PINCTRL_PIN(15, "GP_INTD_DSI_TE2" ), |
677 | PINCTRL_PIN(16, "USB_OC0_B" ), |
678 | PINCTRL_PIN(17, "USB_OC1_B" ), |
679 | PINCTRL_PIN(18, "PMC_SPI_FS0" ), |
680 | PINCTRL_PIN(19, "PMC_SPI_FS1" ), |
681 | PINCTRL_PIN(20, "PMC_SPI_FS2" ), |
682 | PINCTRL_PIN(21, "PMC_SPI_RXD" ), |
683 | PINCTRL_PIN(22, "PMC_SPI_TXD" ), |
684 | PINCTRL_PIN(23, "PMC_SPI_CLK" ), |
685 | PINCTRL_PIN(24, "PMIC_PWRGOOD" ), |
686 | PINCTRL_PIN(25, "PMIC_RESET_B" ), |
687 | PINCTRL_PIN(26, "PMIC_SDWN_B" ), |
688 | PINCTRL_PIN(27, "PMIC_BCUDISW2" ), |
689 | PINCTRL_PIN(28, "PMIC_BCUDISCRIT" ), |
690 | PINCTRL_PIN(29, "PMIC_THERMTRIP_B" ), |
691 | PINCTRL_PIN(30, "PMIC_STDBY" ), |
692 | PINCTRL_PIN(31, "PROCHOT_B" ), |
693 | PINCTRL_PIN(32, "PMIC_I2C_SCL" ), |
694 | PINCTRL_PIN(33, "PMIC_I2C_SDA" ), |
695 | PINCTRL_PIN(34, "AVS_I2S1_MCLK" ), |
696 | PINCTRL_PIN(35, "AVS_I2S1_BCLK" ), |
697 | PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC" ), |
698 | PINCTRL_PIN(37, "AVS_I2S1_SDI" ), |
699 | PINCTRL_PIN(38, "AVS_I2S1_SDO" ), |
700 | PINCTRL_PIN(39, "AVS_M_CLK_A1" ), |
701 | PINCTRL_PIN(40, "AVS_M_CLK_B1" ), |
702 | PINCTRL_PIN(41, "AVS_M_DATA_1" ), |
703 | PINCTRL_PIN(42, "AVS_M_CLK_AB2" ), |
704 | PINCTRL_PIN(43, "AVS_M_DATA_2" ), |
705 | PINCTRL_PIN(44, "AVS_I2S2_MCLK" ), |
706 | PINCTRL_PIN(45, "AVS_I2S2_BCLK" ), |
707 | PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC" ), |
708 | PINCTRL_PIN(47, "AVS_I2S2_SDI" ), |
709 | PINCTRL_PIN(48, "AVS_I2S2_SDO" ), |
710 | PINCTRL_PIN(49, "AVS_I2S3_BCLK" ), |
711 | PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC" ), |
712 | PINCTRL_PIN(51, "AVS_I2S3_SDI" ), |
713 | PINCTRL_PIN(52, "AVS_I2S3_SDO" ), |
714 | PINCTRL_PIN(53, "FST_SPI_CS0_B" ), |
715 | PINCTRL_PIN(54, "FST_SPI_CS1_B" ), |
716 | PINCTRL_PIN(55, "FST_SPI_MOSI_IO0" ), |
717 | PINCTRL_PIN(56, "FST_SPI_MISO_IO1" ), |
718 | PINCTRL_PIN(57, "FST_SPI_IO2" ), |
719 | PINCTRL_PIN(58, "FST_SPI_IO3" ), |
720 | PINCTRL_PIN(59, "FST_SPI_CLK" ), |
721 | PINCTRL_PIN(60, "FST_SPI_CLK_FB" ), |
722 | PINCTRL_PIN(61, "GP_SSP_0_CLK" ), |
723 | PINCTRL_PIN(62, "GP_SSP_0_FS0" ), |
724 | PINCTRL_PIN(63, "GP_SSP_0_FS1" ), |
725 | PINCTRL_PIN(64, "GP_SSP_0_RXD" ), |
726 | PINCTRL_PIN(65, "GP_SSP_0_TXD" ), |
727 | PINCTRL_PIN(66, "GP_SSP_1_CLK" ), |
728 | PINCTRL_PIN(67, "GP_SSP_1_FS0" ), |
729 | PINCTRL_PIN(68, "GP_SSP_1_FS1" ), |
730 | PINCTRL_PIN(69, "GP_SSP_1_RXD" ), |
731 | PINCTRL_PIN(70, "GP_SSP_1_TXD" ), |
732 | PINCTRL_PIN(71, "GP_SSP_2_CLK" ), |
733 | PINCTRL_PIN(72, "GP_SSP_2_FS0" ), |
734 | PINCTRL_PIN(73, "GP_SSP_2_FS1" ), |
735 | PINCTRL_PIN(74, "GP_SSP_2_FS2" ), |
736 | PINCTRL_PIN(75, "GP_SSP_2_RXD" ), |
737 | PINCTRL_PIN(76, "GP_SSP_2_TXD" ), |
738 | }; |
739 | |
740 | static const unsigned int apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 }; |
741 | static const unsigned int apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 }; |
742 | static const unsigned int apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 }; |
743 | static const unsigned int apl_northwest_uart3_pins[] = { 67, 68, 69, 70 }; |
744 | |
745 | static const struct intel_pingroup apl_northwest_groups[] = { |
746 | PIN_GROUP("ssp0_grp" , apl_northwest_ssp0_pins, 1), |
747 | PIN_GROUP("ssp1_grp" , apl_northwest_ssp1_pins, 1), |
748 | PIN_GROUP("ssp2_grp" , apl_northwest_ssp2_pins, 1), |
749 | PIN_GROUP("uart3_grp" , apl_northwest_uart3_pins, 2), |
750 | }; |
751 | |
752 | static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" }; |
753 | static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" }; |
754 | static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" }; |
755 | static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" }; |
756 | |
757 | static const struct intel_function apl_northwest_functions[] = { |
758 | FUNCTION("ssp0" , apl_northwest_ssp0_groups), |
759 | FUNCTION("ssp1" , apl_northwest_ssp1_groups), |
760 | FUNCTION("ssp2" , apl_northwest_ssp2_groups), |
761 | FUNCTION("uart3" , apl_northwest_uart3_groups), |
762 | }; |
763 | |
764 | static const struct intel_community apl_northwest_communities[] = { |
765 | BXT_COMMUNITY(0, 0, 76), |
766 | }; |
767 | |
768 | static const struct intel_pinctrl_soc_data apl_northwest_soc_data = { |
769 | .uid = "2" , |
770 | .pins = apl_northwest_pins, |
771 | .npins = ARRAY_SIZE(apl_northwest_pins), |
772 | .groups = apl_northwest_groups, |
773 | .ngroups = ARRAY_SIZE(apl_northwest_groups), |
774 | .functions = apl_northwest_functions, |
775 | .nfunctions = ARRAY_SIZE(apl_northwest_functions), |
776 | .communities = apl_northwest_communities, |
777 | .ncommunities = ARRAY_SIZE(apl_northwest_communities), |
778 | }; |
779 | |
780 | static const struct pinctrl_pin_desc apl_west_pins[] = { |
781 | PINCTRL_PIN(0, "LPSS_I2C0_SDA" ), |
782 | PINCTRL_PIN(1, "LPSS_I2C0_SCL" ), |
783 | PINCTRL_PIN(2, "LPSS_I2C1_SDA" ), |
784 | PINCTRL_PIN(3, "LPSS_I2C1_SCL" ), |
785 | PINCTRL_PIN(4, "LPSS_I2C2_SDA" ), |
786 | PINCTRL_PIN(5, "LPSS_I2C2_SCL" ), |
787 | PINCTRL_PIN(6, "LPSS_I2C3_SDA" ), |
788 | PINCTRL_PIN(7, "LPSS_I2C3_SCL" ), |
789 | PINCTRL_PIN(8, "LPSS_I2C4_SDA" ), |
790 | PINCTRL_PIN(9, "LPSS_I2C4_SCL" ), |
791 | PINCTRL_PIN(10, "LPSS_I2C5_SDA" ), |
792 | PINCTRL_PIN(11, "LPSS_I2C5_SCL" ), |
793 | PINCTRL_PIN(12, "LPSS_I2C6_SDA" ), |
794 | PINCTRL_PIN(13, "LPSS_I2C6_SCL" ), |
795 | PINCTRL_PIN(14, "LPSS_I2C7_SDA" ), |
796 | PINCTRL_PIN(15, "LPSS_I2C7_SCL" ), |
797 | PINCTRL_PIN(16, "ISH_GPIO_0" ), |
798 | PINCTRL_PIN(17, "ISH_GPIO_1" ), |
799 | PINCTRL_PIN(18, "ISH_GPIO_2" ), |
800 | PINCTRL_PIN(19, "ISH_GPIO_3" ), |
801 | PINCTRL_PIN(20, "ISH_GPIO_4" ), |
802 | PINCTRL_PIN(21, "ISH_GPIO_5" ), |
803 | PINCTRL_PIN(22, "ISH_GPIO_6" ), |
804 | PINCTRL_PIN(23, "ISH_GPIO_7" ), |
805 | PINCTRL_PIN(24, "ISH_GPIO_8" ), |
806 | PINCTRL_PIN(25, "ISH_GPIO_9" ), |
807 | PINCTRL_PIN(26, "PCIE_CLKREQ0_B" ), |
808 | PINCTRL_PIN(27, "PCIE_CLKREQ1_B" ), |
809 | PINCTRL_PIN(28, "PCIE_CLKREQ2_B" ), |
810 | PINCTRL_PIN(29, "PCIE_CLKREQ3_B" ), |
811 | PINCTRL_PIN(30, "OSC_CLK_OUT_0" ), |
812 | PINCTRL_PIN(31, "OSC_CLK_OUT_1" ), |
813 | PINCTRL_PIN(32, "OSC_CLK_OUT_2" ), |
814 | PINCTRL_PIN(33, "OSC_CLK_OUT_3" ), |
815 | PINCTRL_PIN(34, "OSC_CLK_OUT_4" ), |
816 | PINCTRL_PIN(35, "PMU_AC_PRESENT" ), |
817 | PINCTRL_PIN(36, "PMU_BATLOW_B" ), |
818 | PINCTRL_PIN(37, "PMU_PLTRST_B" ), |
819 | PINCTRL_PIN(38, "PMU_PWRBTN_B" ), |
820 | PINCTRL_PIN(39, "PMU_RESETBUTTON_B" ), |
821 | PINCTRL_PIN(40, "PMU_SLP_S0_B" ), |
822 | PINCTRL_PIN(41, "PMU_SLP_S3_B" ), |
823 | PINCTRL_PIN(42, "PMU_SLP_S4_B" ), |
824 | PINCTRL_PIN(43, "PMU_SUSCLK" ), |
825 | PINCTRL_PIN(44, "PMU_WAKE_B" ), |
826 | PINCTRL_PIN(45, "SUS_STAT_B" ), |
827 | PINCTRL_PIN(46, "SUSPWRDNACK" ), |
828 | }; |
829 | |
830 | static const unsigned int apl_west_i2c0_pins[] = { 0, 1 }; |
831 | static const unsigned int apl_west_i2c1_pins[] = { 2, 3 }; |
832 | static const unsigned int apl_west_i2c2_pins[] = { 4, 5 }; |
833 | static const unsigned int apl_west_i2c3_pins[] = { 6, 7 }; |
834 | static const unsigned int apl_west_i2c4_pins[] = { 8, 9 }; |
835 | static const unsigned int apl_west_i2c5_pins[] = { 10, 11 }; |
836 | static const unsigned int apl_west_i2c6_pins[] = { 12, 13 }; |
837 | static const unsigned int apl_west_i2c7_pins[] = { 14, 15 }; |
838 | static const unsigned int apl_west_uart2_pins[] = { 20, 21, 22, 34 }; |
839 | |
840 | static const struct intel_pingroup apl_west_groups[] = { |
841 | PIN_GROUP("i2c0_grp" , apl_west_i2c0_pins, 1), |
842 | PIN_GROUP("i2c1_grp" , apl_west_i2c1_pins, 1), |
843 | PIN_GROUP("i2c2_grp" , apl_west_i2c2_pins, 1), |
844 | PIN_GROUP("i2c3_grp" , apl_west_i2c3_pins, 1), |
845 | PIN_GROUP("i2c4_grp" , apl_west_i2c4_pins, 1), |
846 | PIN_GROUP("i2c5_grp" , apl_west_i2c5_pins, 1), |
847 | PIN_GROUP("i2c6_grp" , apl_west_i2c6_pins, 1), |
848 | PIN_GROUP("i2c7_grp" , apl_west_i2c7_pins, 1), |
849 | PIN_GROUP("uart2_grp" , apl_west_uart2_pins, 3), |
850 | }; |
851 | |
852 | static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" }; |
853 | static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" }; |
854 | static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" }; |
855 | static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" }; |
856 | static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" }; |
857 | static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" }; |
858 | static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" }; |
859 | static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" }; |
860 | static const char * const apl_west_uart2_groups[] = { "uart2_grp" }; |
861 | |
862 | static const struct intel_function apl_west_functions[] = { |
863 | FUNCTION("i2c0" , apl_west_i2c0_groups), |
864 | FUNCTION("i2c1" , apl_west_i2c1_groups), |
865 | FUNCTION("i2c2" , apl_west_i2c2_groups), |
866 | FUNCTION("i2c3" , apl_west_i2c3_groups), |
867 | FUNCTION("i2c4" , apl_west_i2c4_groups), |
868 | FUNCTION("i2c5" , apl_west_i2c5_groups), |
869 | FUNCTION("i2c6" , apl_west_i2c6_groups), |
870 | FUNCTION("i2c7" , apl_west_i2c7_groups), |
871 | FUNCTION("uart2" , apl_west_uart2_groups), |
872 | }; |
873 | |
874 | static const struct intel_community apl_west_communities[] = { |
875 | BXT_COMMUNITY(0, 0, 46), |
876 | }; |
877 | |
878 | static const struct intel_pinctrl_soc_data apl_west_soc_data = { |
879 | .uid = "3" , |
880 | .pins = apl_west_pins, |
881 | .npins = ARRAY_SIZE(apl_west_pins), |
882 | .groups = apl_west_groups, |
883 | .ngroups = ARRAY_SIZE(apl_west_groups), |
884 | .functions = apl_west_functions, |
885 | .nfunctions = ARRAY_SIZE(apl_west_functions), |
886 | .communities = apl_west_communities, |
887 | .ncommunities = ARRAY_SIZE(apl_west_communities), |
888 | }; |
889 | |
890 | static const struct pinctrl_pin_desc apl_southwest_pins[] = { |
891 | PINCTRL_PIN(0, "PCIE_WAKE0_B" ), |
892 | PINCTRL_PIN(1, "PCIE_WAKE1_B" ), |
893 | PINCTRL_PIN(2, "PCIE_WAKE2_B" ), |
894 | PINCTRL_PIN(3, "PCIE_WAKE3_B" ), |
895 | PINCTRL_PIN(4, "EMMC0_CLK" ), |
896 | PINCTRL_PIN(5, "EMMC0_D0" ), |
897 | PINCTRL_PIN(6, "EMMC0_D1" ), |
898 | PINCTRL_PIN(7, "EMMC0_D2" ), |
899 | PINCTRL_PIN(8, "EMMC0_D3" ), |
900 | PINCTRL_PIN(9, "EMMC0_D4" ), |
901 | PINCTRL_PIN(10, "EMMC0_D5" ), |
902 | PINCTRL_PIN(11, "EMMC0_D6" ), |
903 | PINCTRL_PIN(12, "EMMC0_D7" ), |
904 | PINCTRL_PIN(13, "EMMC0_CMD" ), |
905 | PINCTRL_PIN(14, "SDIO_CLK" ), |
906 | PINCTRL_PIN(15, "SDIO_D0" ), |
907 | PINCTRL_PIN(16, "SDIO_D1" ), |
908 | PINCTRL_PIN(17, "SDIO_D2" ), |
909 | PINCTRL_PIN(18, "SDIO_D3" ), |
910 | PINCTRL_PIN(19, "SDIO_CMD" ), |
911 | PINCTRL_PIN(20, "SDCARD_CLK" ), |
912 | PINCTRL_PIN(21, "SDCARD_CLK_FB" ), |
913 | PINCTRL_PIN(22, "SDCARD_D0" ), |
914 | PINCTRL_PIN(23, "SDCARD_D1" ), |
915 | PINCTRL_PIN(24, "SDCARD_D2" ), |
916 | PINCTRL_PIN(25, "SDCARD_D3" ), |
917 | PINCTRL_PIN(26, "SDCARD_CD_B" ), |
918 | PINCTRL_PIN(27, "SDCARD_CMD" ), |
919 | PINCTRL_PIN(28, "SDCARD_LVL_WP" ), |
920 | PINCTRL_PIN(29, "EMMC0_STROBE" ), |
921 | PINCTRL_PIN(30, "SDIO_PWR_DOWN_B" ), |
922 | PINCTRL_PIN(31, "SMB_ALERTB" ), |
923 | PINCTRL_PIN(32, "SMB_CLK" ), |
924 | PINCTRL_PIN(33, "SMB_DATA" ), |
925 | PINCTRL_PIN(34, "LPC_ILB_SERIRQ" ), |
926 | PINCTRL_PIN(35, "LPC_CLKOUT0" ), |
927 | PINCTRL_PIN(36, "LPC_CLKOUT1" ), |
928 | PINCTRL_PIN(37, "LPC_AD0" ), |
929 | PINCTRL_PIN(38, "LPC_AD1" ), |
930 | PINCTRL_PIN(39, "LPC_AD2" ), |
931 | PINCTRL_PIN(40, "LPC_AD3" ), |
932 | PINCTRL_PIN(41, "LPC_CLKRUNB" ), |
933 | PINCTRL_PIN(42, "LPC_FRAMEB" ), |
934 | }; |
935 | |
936 | static const unsigned int apl_southwest_emmc0_pins[] = { |
937 | 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29, |
938 | }; |
939 | static const unsigned int apl_southwest_sdio_pins[] = { |
940 | 14, 15, 16, 17, 18, 19, 30, |
941 | }; |
942 | static const unsigned int apl_southwest_sdcard_pins[] = { |
943 | 20, 21, 22, 23, 24, 25, 26, 27, 28, |
944 | }; |
945 | static const unsigned int apl_southwest_i2c7_pins[] = { 32, 33 }; |
946 | |
947 | static const struct intel_pingroup apl_southwest_groups[] = { |
948 | PIN_GROUP("emmc0_grp" , apl_southwest_emmc0_pins, 1), |
949 | PIN_GROUP("sdio_grp" , apl_southwest_sdio_pins, 1), |
950 | PIN_GROUP("sdcard_grp" , apl_southwest_sdcard_pins, 1), |
951 | PIN_GROUP("i2c7_grp" , apl_southwest_i2c7_pins, 2), |
952 | }; |
953 | |
954 | static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" }; |
955 | static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" }; |
956 | static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" }; |
957 | static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" }; |
958 | |
959 | static const struct intel_function apl_southwest_functions[] = { |
960 | FUNCTION("emmc0" , apl_southwest_emmc0_groups), |
961 | FUNCTION("sdio" , apl_southwest_sdio_groups), |
962 | FUNCTION("sdcard" , apl_southwest_sdcard_groups), |
963 | FUNCTION("i2c7" , apl_southwest_i2c7_groups), |
964 | }; |
965 | |
966 | static const struct intel_community apl_southwest_communities[] = { |
967 | BXT_COMMUNITY(0, 0, 42), |
968 | }; |
969 | |
970 | static const struct intel_pinctrl_soc_data apl_southwest_soc_data = { |
971 | .uid = "4" , |
972 | .pins = apl_southwest_pins, |
973 | .npins = ARRAY_SIZE(apl_southwest_pins), |
974 | .groups = apl_southwest_groups, |
975 | .ngroups = ARRAY_SIZE(apl_southwest_groups), |
976 | .functions = apl_southwest_functions, |
977 | .nfunctions = ARRAY_SIZE(apl_southwest_functions), |
978 | .communities = apl_southwest_communities, |
979 | .ncommunities = ARRAY_SIZE(apl_southwest_communities), |
980 | }; |
981 | |
982 | static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = { |
983 | &apl_north_soc_data, |
984 | &apl_northwest_soc_data, |
985 | &apl_west_soc_data, |
986 | &apl_southwest_soc_data, |
987 | NULL |
988 | }; |
989 | |
990 | static const struct acpi_device_id bxt_pinctrl_acpi_match[] = { |
991 | { "INT3452" , (kernel_ulong_t)apl_pinctrl_soc_data }, |
992 | { "INT34D1" , (kernel_ulong_t)bxt_pinctrl_soc_data }, |
993 | { } |
994 | }; |
995 | MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match); |
996 | |
997 | static const struct platform_device_id bxt_pinctrl_platform_ids[] = { |
998 | { "apollolake-pinctrl" , (kernel_ulong_t)apl_pinctrl_soc_data }, |
999 | { "broxton-pinctrl" , (kernel_ulong_t)bxt_pinctrl_soc_data }, |
1000 | { } |
1001 | }; |
1002 | MODULE_DEVICE_TABLE(platform, bxt_pinctrl_platform_ids); |
1003 | |
1004 | static struct platform_driver bxt_pinctrl_driver = { |
1005 | .probe = intel_pinctrl_probe_by_uid, |
1006 | .driver = { |
1007 | .name = "broxton-pinctrl" , |
1008 | .acpi_match_table = bxt_pinctrl_acpi_match, |
1009 | .pm = pm_sleep_ptr(&intel_pinctrl_pm_ops), |
1010 | }, |
1011 | .id_table = bxt_pinctrl_platform_ids, |
1012 | }; |
1013 | |
1014 | static int __init bxt_pinctrl_init(void) |
1015 | { |
1016 | return platform_driver_register(&bxt_pinctrl_driver); |
1017 | } |
1018 | subsys_initcall(bxt_pinctrl_init); |
1019 | |
1020 | static void __exit bxt_pinctrl_exit(void) |
1021 | { |
1022 | platform_driver_unregister(&bxt_pinctrl_driver); |
1023 | } |
1024 | module_exit(bxt_pinctrl_exit); |
1025 | |
1026 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>" ); |
1027 | MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver" ); |
1028 | MODULE_LICENSE("GPL v2" ); |
1029 | MODULE_IMPORT_NS(PINCTRL_INTEL); |
1030 | |