1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Intel Gemini Lake SoC pinctrl/GPIO driver |
4 | * |
5 | * Copyright (C) 2017 Intel Corporation |
6 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
7 | */ |
8 | |
9 | #include <linux/mod_devicetable.h> |
10 | #include <linux/module.h> |
11 | #include <linux/platform_device.h> |
12 | #include <linux/pm.h> |
13 | |
14 | #include <linux/pinctrl/pinctrl.h> |
15 | |
16 | #include "pinctrl-intel.h" |
17 | |
18 | #define GLK_PAD_OWN 0x020 |
19 | #define GLK_PADCFGLOCK 0x080 |
20 | #define GLK_HOSTSW_OWN 0x0b0 |
21 | #define GLK_GPI_IS 0x100 |
22 | #define GLK_GPI_IE 0x110 |
23 | |
24 | #define (b, s, e) \ |
25 | INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, GLK) |
26 | |
27 | /* GLK */ |
28 | static const struct pinctrl_pin_desc glk_northwest_pins[] = { |
29 | PINCTRL_PIN(0, "TCK" ), |
30 | PINCTRL_PIN(1, "TRST_B" ), |
31 | PINCTRL_PIN(2, "TMS" ), |
32 | PINCTRL_PIN(3, "TDI" ), |
33 | PINCTRL_PIN(4, "TDO" ), |
34 | PINCTRL_PIN(5, "JTAGX" ), |
35 | PINCTRL_PIN(6, "CX_PREQ_B" ), |
36 | PINCTRL_PIN(7, "CX_PRDY_B" ), |
37 | PINCTRL_PIN(8, "GPIO_8" ), |
38 | PINCTRL_PIN(9, "GPIO_9" ), |
39 | PINCTRL_PIN(10, "GPIO_10" ), |
40 | PINCTRL_PIN(11, "GPIO_11" ), |
41 | PINCTRL_PIN(12, "GPIO_12" ), |
42 | PINCTRL_PIN(13, "GPIO_13" ), |
43 | PINCTRL_PIN(14, "GPIO_14" ), |
44 | PINCTRL_PIN(15, "GPIO_15" ), |
45 | PINCTRL_PIN(16, "GPIO_16" ), |
46 | PINCTRL_PIN(17, "GPIO_17" ), |
47 | PINCTRL_PIN(18, "GPIO_18" ), |
48 | PINCTRL_PIN(19, "GPIO_19" ), |
49 | PINCTRL_PIN(20, "GPIO_20" ), |
50 | PINCTRL_PIN(21, "GPIO_21" ), |
51 | PINCTRL_PIN(22, "GPIO_22" ), |
52 | PINCTRL_PIN(23, "GPIO_23" ), |
53 | PINCTRL_PIN(24, "GPIO_24" ), |
54 | PINCTRL_PIN(25, "GPIO_25" ), |
55 | PINCTRL_PIN(26, "ISH_GPIO_0" ), |
56 | PINCTRL_PIN(27, "ISH_GPIO_1" ), |
57 | PINCTRL_PIN(28, "ISH_GPIO_2" ), |
58 | PINCTRL_PIN(29, "ISH_GPIO_3" ), |
59 | PINCTRL_PIN(30, "ISH_GPIO_4" ), |
60 | PINCTRL_PIN(31, "ISH_GPIO_5" ), |
61 | PINCTRL_PIN(32, "ISH_GPIO_6" ), |
62 | PINCTRL_PIN(33, "ISH_GPIO_7" ), |
63 | PINCTRL_PIN(34, "ISH_GPIO_8" ), |
64 | PINCTRL_PIN(35, "ISH_GPIO_9" ), |
65 | PINCTRL_PIN(36, "GPIO_36" ), |
66 | PINCTRL_PIN(37, "GPIO_37" ), |
67 | PINCTRL_PIN(38, "GPIO_38" ), |
68 | PINCTRL_PIN(39, "GPIO_39" ), |
69 | PINCTRL_PIN(40, "GPIO_40" ), |
70 | PINCTRL_PIN(41, "GPIO_41" ), |
71 | PINCTRL_PIN(42, "GP_INTD_DSI_TE1" ), |
72 | PINCTRL_PIN(43, "GP_INTD_DSI_TE2" ), |
73 | PINCTRL_PIN(44, "USB_OC0_B" ), |
74 | PINCTRL_PIN(45, "USB_OC1_B" ), |
75 | PINCTRL_PIN(46, "DSI_I2C_SDA" ), |
76 | PINCTRL_PIN(47, "DSI_I2C_SCL" ), |
77 | PINCTRL_PIN(48, "PMC_I2C_SDA" ), |
78 | PINCTRL_PIN(49, "PMC_I2C_SCL" ), |
79 | PINCTRL_PIN(50, "LPSS_I2C0_SDA" ), |
80 | PINCTRL_PIN(51, "LPSS_I2C0_SCL" ), |
81 | PINCTRL_PIN(52, "LPSS_I2C1_SDA" ), |
82 | PINCTRL_PIN(53, "LPSS_I2C1_SCL" ), |
83 | PINCTRL_PIN(54, "LPSS_I2C2_SDA" ), |
84 | PINCTRL_PIN(55, "LPSS_I2C2_SCL" ), |
85 | PINCTRL_PIN(56, "LPSS_I2C3_SDA" ), |
86 | PINCTRL_PIN(57, "LPSS_I2C3_SCL" ), |
87 | PINCTRL_PIN(58, "LPSS_I2C4_SDA" ), |
88 | PINCTRL_PIN(59, "LPSS_I2C4_SCL" ), |
89 | PINCTRL_PIN(60, "LPSS_UART0_RXD" ), |
90 | PINCTRL_PIN(61, "LPSS_UART0_TXD" ), |
91 | PINCTRL_PIN(62, "LPSS_UART0_RTS_B" ), |
92 | PINCTRL_PIN(63, "LPSS_UART0_CTS_B" ), |
93 | PINCTRL_PIN(64, "LPSS_UART2_RXD" ), |
94 | PINCTRL_PIN(65, "LPSS_UART2_TXD" ), |
95 | PINCTRL_PIN(66, "LPSS_UART2_RTS_B" ), |
96 | PINCTRL_PIN(67, "LPSS_UART2_CTS_B" ), |
97 | PINCTRL_PIN(68, "PMC_SPI_FS0" ), |
98 | PINCTRL_PIN(69, "PMC_SPI_FS1" ), |
99 | PINCTRL_PIN(70, "PMC_SPI_FS2" ), |
100 | PINCTRL_PIN(71, "PMC_SPI_RXD" ), |
101 | PINCTRL_PIN(72, "PMC_SPI_TXD" ), |
102 | PINCTRL_PIN(73, "PMC_SPI_CLK" ), |
103 | PINCTRL_PIN(74, "THERMTRIP_B" ), |
104 | PINCTRL_PIN(75, "PROCHOT_B" ), |
105 | PINCTRL_PIN(76, "EMMC_RST_B" ), |
106 | PINCTRL_PIN(77, "GPIO_212" ), |
107 | PINCTRL_PIN(78, "GPIO_213" ), |
108 | PINCTRL_PIN(79, "GPIO_214" ), |
109 | }; |
110 | |
111 | static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 }; |
112 | static const unsigned int glk_northwest_pwm0_pins[] = { 42 }; |
113 | static const unsigned int glk_northwest_pwm1_pins[] = { 43 }; |
114 | static const unsigned int glk_northwest_pwm2_pins[] = { 44 }; |
115 | static const unsigned int glk_northwest_pwm3_pins[] = { 45 }; |
116 | static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 }; |
117 | static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 }; |
118 | static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 }; |
119 | static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 }; |
120 | static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 }; |
121 | static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 }; |
122 | static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 }; |
123 | |
124 | static const struct intel_pingroup glk_northwest_groups[] = { |
125 | PIN_GROUP("uart1_grp" , glk_northwest_uart1_pins, 2), |
126 | PIN_GROUP("pwm0_grp" , glk_northwest_pwm0_pins, 2), |
127 | PIN_GROUP("pwm1_grp" , glk_northwest_pwm1_pins, 2), |
128 | PIN_GROUP("pwm2_grp" , glk_northwest_pwm2_pins, 2), |
129 | PIN_GROUP("pwm3_grp" , glk_northwest_pwm3_pins, 2), |
130 | PIN_GROUP("i2c0_grp" , glk_northwest_i2c0_pins, 1), |
131 | PIN_GROUP("i2c1_grp" , glk_northwest_i2c1_pins, 1), |
132 | PIN_GROUP("i2c2_grp" , glk_northwest_i2c2_pins, 1), |
133 | PIN_GROUP("i2c3_grp" , glk_northwest_i2c3_pins, 1), |
134 | PIN_GROUP("i2c4_grp" , glk_northwest_i2c4_pins, 1), |
135 | PIN_GROUP("uart0_grp" , glk_northwest_uart0_pins, 1), |
136 | PIN_GROUP("uart2_grp" , glk_northwest_uart2_pins, 1), |
137 | }; |
138 | |
139 | static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" }; |
140 | static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" }; |
141 | static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" }; |
142 | static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" }; |
143 | static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" }; |
144 | static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" }; |
145 | static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" }; |
146 | static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" }; |
147 | static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" }; |
148 | static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" }; |
149 | static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" }; |
150 | static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" }; |
151 | |
152 | static const struct intel_function glk_northwest_functions[] = { |
153 | FUNCTION("uart1" , glk_northwest_uart1_groups), |
154 | FUNCTION("pmw0" , glk_northwest_pwm0_groups), |
155 | FUNCTION("pmw1" , glk_northwest_pwm1_groups), |
156 | FUNCTION("pmw2" , glk_northwest_pwm2_groups), |
157 | FUNCTION("pmw3" , glk_northwest_pwm3_groups), |
158 | FUNCTION("i2c0" , glk_northwest_i2c0_groups), |
159 | FUNCTION("i2c1" , glk_northwest_i2c1_groups), |
160 | FUNCTION("i2c2" , glk_northwest_i2c2_groups), |
161 | FUNCTION("i2c3" , glk_northwest_i2c3_groups), |
162 | FUNCTION("i2c4" , glk_northwest_i2c4_groups), |
163 | FUNCTION("uart0" , glk_northwest_uart0_groups), |
164 | FUNCTION("uart2" , glk_northwest_uart2_groups), |
165 | }; |
166 | |
167 | static const struct intel_community glk_northwest_communities[] = { |
168 | GLK_COMMUNITY(0, 0, 79), |
169 | }; |
170 | |
171 | static const struct intel_pinctrl_soc_data glk_northwest_soc_data = { |
172 | .uid = "1" , |
173 | .pins = glk_northwest_pins, |
174 | .npins = ARRAY_SIZE(glk_northwest_pins), |
175 | .groups = glk_northwest_groups, |
176 | .ngroups = ARRAY_SIZE(glk_northwest_groups), |
177 | .functions = glk_northwest_functions, |
178 | .nfunctions = ARRAY_SIZE(glk_northwest_functions), |
179 | .communities = glk_northwest_communities, |
180 | .ncommunities = ARRAY_SIZE(glk_northwest_communities), |
181 | }; |
182 | |
183 | static const struct pinctrl_pin_desc glk_north_pins[] = { |
184 | PINCTRL_PIN(0, "SVID0_ALERT_B" ), |
185 | PINCTRL_PIN(1, "SVID0_DATA" ), |
186 | PINCTRL_PIN(2, "SVID0_CLK" ), |
187 | PINCTRL_PIN(3, "LPSS_SPI_0_CLK" ), |
188 | PINCTRL_PIN(4, "LPSS_SPI_0_FS0" ), |
189 | PINCTRL_PIN(5, "LPSS_SPI_0_FS1" ), |
190 | PINCTRL_PIN(6, "LPSS_SPI_0_RXD" ), |
191 | PINCTRL_PIN(7, "LPSS_SPI_0_TXD" ), |
192 | PINCTRL_PIN(8, "LPSS_SPI_2_CLK" ), |
193 | PINCTRL_PIN(9, "LPSS_SPI_2_FS0" ), |
194 | PINCTRL_PIN(10, "LPSS_SPI_2_FS1" ), |
195 | PINCTRL_PIN(11, "LPSS_SPI_2_FS2" ), |
196 | PINCTRL_PIN(12, "LPSS_SPI_2_RXD" ), |
197 | PINCTRL_PIN(13, "LPSS_SPI_2_TXD" ), |
198 | PINCTRL_PIN(14, "FST_SPI_CS0_B" ), |
199 | PINCTRL_PIN(15, "FST_SPI_CS1_B" ), |
200 | PINCTRL_PIN(16, "FST_SPI_MOSI_IO0" ), |
201 | PINCTRL_PIN(17, "FST_SPI_MISO_IO1" ), |
202 | PINCTRL_PIN(18, "FST_SPI_IO2" ), |
203 | PINCTRL_PIN(19, "FST_SPI_IO3" ), |
204 | PINCTRL_PIN(20, "FST_SPI_CLK" ), |
205 | PINCTRL_PIN(21, "FST_SPI_CLK_FB" ), |
206 | PINCTRL_PIN(22, "PMU_PLTRST_B" ), |
207 | PINCTRL_PIN(23, "PMU_PWRBTN_B" ), |
208 | PINCTRL_PIN(24, "PMU_SLP_S0_B" ), |
209 | PINCTRL_PIN(25, "PMU_SLP_S3_B" ), |
210 | PINCTRL_PIN(26, "PMU_SLP_S4_B" ), |
211 | PINCTRL_PIN(27, "SUSPWRDNACK" ), |
212 | PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B" ), |
213 | PINCTRL_PIN(29, "GPIO_105" ), |
214 | PINCTRL_PIN(30, "PMU_BATLOW_B" ), |
215 | PINCTRL_PIN(31, "PMU_RESETBUTTON_B" ), |
216 | PINCTRL_PIN(32, "PMU_SUSCLK" ), |
217 | PINCTRL_PIN(33, "SUS_STAT_B" ), |
218 | PINCTRL_PIN(34, "LPSS_I2C5_SDA" ), |
219 | PINCTRL_PIN(35, "LPSS_I2C5_SCL" ), |
220 | PINCTRL_PIN(36, "LPSS_I2C6_SDA" ), |
221 | PINCTRL_PIN(37, "LPSS_I2C6_SCL" ), |
222 | PINCTRL_PIN(38, "LPSS_I2C7_SDA" ), |
223 | PINCTRL_PIN(39, "LPSS_I2C7_SCL" ), |
224 | PINCTRL_PIN(40, "PCIE_WAKE0_B" ), |
225 | PINCTRL_PIN(41, "PCIE_WAKE1_B" ), |
226 | PINCTRL_PIN(42, "PCIE_WAKE2_B" ), |
227 | PINCTRL_PIN(43, "PCIE_WAKE3_B" ), |
228 | PINCTRL_PIN(44, "PCIE_CLKREQ0_B" ), |
229 | PINCTRL_PIN(45, "PCIE_CLKREQ1_B" ), |
230 | PINCTRL_PIN(46, "PCIE_CLKREQ2_B" ), |
231 | PINCTRL_PIN(47, "PCIE_CLKREQ3_B" ), |
232 | PINCTRL_PIN(48, "HV_DDI0_DDC_SDA" ), |
233 | PINCTRL_PIN(49, "HV_DDI0_DDC_SCL" ), |
234 | PINCTRL_PIN(50, "HV_DDI1_DDC_SDA" ), |
235 | PINCTRL_PIN(51, "HV_DDI1_DDC_SCL" ), |
236 | PINCTRL_PIN(52, "PANEL0_VDDEN" ), |
237 | PINCTRL_PIN(53, "PANEL0_BKLTEN" ), |
238 | PINCTRL_PIN(54, "PANEL0_BKLTCTL" ), |
239 | PINCTRL_PIN(55, "HV_DDI0_HPD" ), |
240 | PINCTRL_PIN(56, "HV_DDI1_HPD" ), |
241 | PINCTRL_PIN(57, "HV_EDP_HPD" ), |
242 | PINCTRL_PIN(58, "GPIO_134" ), |
243 | PINCTRL_PIN(59, "GPIO_135" ), |
244 | PINCTRL_PIN(60, "GPIO_136" ), |
245 | PINCTRL_PIN(61, "GPIO_137" ), |
246 | PINCTRL_PIN(62, "GPIO_138" ), |
247 | PINCTRL_PIN(63, "GPIO_139" ), |
248 | PINCTRL_PIN(64, "GPIO_140" ), |
249 | PINCTRL_PIN(65, "GPIO_141" ), |
250 | PINCTRL_PIN(66, "GPIO_142" ), |
251 | PINCTRL_PIN(67, "GPIO_143" ), |
252 | PINCTRL_PIN(68, "GPIO_144" ), |
253 | PINCTRL_PIN(69, "GPIO_145" ), |
254 | PINCTRL_PIN(70, "GPIO_146" ), |
255 | PINCTRL_PIN(71, "LPC_ILB_SERIRQ" ), |
256 | PINCTRL_PIN(72, "LPC_CLKOUT0" ), |
257 | PINCTRL_PIN(73, "LPC_CLKOUT1" ), |
258 | PINCTRL_PIN(74, "LPC_AD0" ), |
259 | PINCTRL_PIN(75, "LPC_AD1" ), |
260 | PINCTRL_PIN(76, "LPC_AD2" ), |
261 | PINCTRL_PIN(77, "LPC_AD3" ), |
262 | PINCTRL_PIN(78, "LPC_CLKRUNB" ), |
263 | PINCTRL_PIN(79, "LPC_FRAMEB" ), |
264 | }; |
265 | |
266 | static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 }; |
267 | static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 }; |
268 | static const unsigned int glk_north_i2c5_pins[] = { 34, 35 }; |
269 | static const unsigned int glk_north_i2c6_pins[] = { 36, 37 }; |
270 | static const unsigned int glk_north_i2c7_pins[] = { 38, 39 }; |
271 | static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 }; |
272 | static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 }; |
273 | |
274 | static const struct intel_pingroup glk_north_groups[] = { |
275 | PIN_GROUP("spi0_grp" , glk_north_spi0_pins, 1), |
276 | PIN_GROUP("spi1_grp" , glk_north_spi1_pins, 1), |
277 | PIN_GROUP("i2c5_grp" , glk_north_i2c5_pins, 1), |
278 | PIN_GROUP("i2c6_grp" , glk_north_i2c6_pins, 1), |
279 | PIN_GROUP("i2c7_grp" , glk_north_i2c7_pins, 1), |
280 | PIN_GROUP("uart0_grp" , glk_north_uart0_pins, 2), |
281 | PIN_GROUP("spi0b_grp" , glk_north_spi0b_pins, 2), |
282 | }; |
283 | |
284 | static const char * const glk_north_spi0_groups[] = { "spi0_grp" , "spi0b_grp" }; |
285 | static const char * const glk_north_spi1_groups[] = { "spi1_grp" }; |
286 | static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" }; |
287 | static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" }; |
288 | static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" }; |
289 | static const char * const glk_north_uart0_groups[] = { "uart0_grp" }; |
290 | |
291 | static const struct intel_function glk_north_functions[] = { |
292 | FUNCTION("spi0" , glk_north_spi0_groups), |
293 | FUNCTION("spi1" , glk_north_spi1_groups), |
294 | FUNCTION("i2c5" , glk_north_i2c5_groups), |
295 | FUNCTION("i2c6" , glk_north_i2c6_groups), |
296 | FUNCTION("i2c7" , glk_north_i2c7_groups), |
297 | FUNCTION("uart0" , glk_north_uart0_groups), |
298 | }; |
299 | |
300 | static const struct intel_community glk_north_communities[] = { |
301 | GLK_COMMUNITY(0, 0, 79), |
302 | }; |
303 | |
304 | static const struct intel_pinctrl_soc_data glk_north_soc_data = { |
305 | .uid = "2" , |
306 | .pins = glk_north_pins, |
307 | .npins = ARRAY_SIZE(glk_north_pins), |
308 | .groups = glk_north_groups, |
309 | .ngroups = ARRAY_SIZE(glk_north_groups), |
310 | .functions = glk_north_functions, |
311 | .nfunctions = ARRAY_SIZE(glk_north_functions), |
312 | .communities = glk_north_communities, |
313 | .ncommunities = ARRAY_SIZE(glk_north_communities), |
314 | }; |
315 | |
316 | static const struct pinctrl_pin_desc glk_audio_pins[] = { |
317 | PINCTRL_PIN(0, "AVS_I2S0_MCLK" ), |
318 | PINCTRL_PIN(1, "AVS_I2S0_BCLK" ), |
319 | PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC" ), |
320 | PINCTRL_PIN(3, "AVS_I2S0_SDI" ), |
321 | PINCTRL_PIN(4, "AVS_I2S0_SDO" ), |
322 | PINCTRL_PIN(5, "AVS_I2S1_MCLK" ), |
323 | PINCTRL_PIN(6, "AVS_I2S1_BCLK" ), |
324 | PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC" ), |
325 | PINCTRL_PIN(8, "AVS_I2S1_SDI" ), |
326 | PINCTRL_PIN(9, "AVS_I2S1_SDO" ), |
327 | PINCTRL_PIN(10, "AVS_HDA_BCLK" ), |
328 | PINCTRL_PIN(11, "AVS_HDA_WS_SYNC" ), |
329 | PINCTRL_PIN(12, "AVS_HDA_SDI" ), |
330 | PINCTRL_PIN(13, "AVS_HDA_SDO" ), |
331 | PINCTRL_PIN(14, "AVS_HDA_RSTB" ), |
332 | PINCTRL_PIN(15, "AVS_M_CLK_A1" ), |
333 | PINCTRL_PIN(16, "AVS_M_CLK_B1" ), |
334 | PINCTRL_PIN(17, "AVS_M_DATA_1" ), |
335 | PINCTRL_PIN(18, "AVS_M_CLK_AB2" ), |
336 | PINCTRL_PIN(19, "AVS_M_DATA_2" ), |
337 | }; |
338 | |
339 | static const struct intel_community glk_audio_communities[] = { |
340 | GLK_COMMUNITY(0, 0, 19), |
341 | }; |
342 | |
343 | static const struct intel_pinctrl_soc_data glk_audio_soc_data = { |
344 | .uid = "3" , |
345 | .pins = glk_audio_pins, |
346 | .npins = ARRAY_SIZE(glk_audio_pins), |
347 | .communities = glk_audio_communities, |
348 | .ncommunities = ARRAY_SIZE(glk_audio_communities), |
349 | }; |
350 | |
351 | static const struct pinctrl_pin_desc glk_scc_pins[] = { |
352 | PINCTRL_PIN(0, "SMB_ALERTB" ), |
353 | PINCTRL_PIN(1, "SMB_CLK" ), |
354 | PINCTRL_PIN(2, "SMB_DATA" ), |
355 | PINCTRL_PIN(3, "SDCARD_LVL_WP" ), |
356 | PINCTRL_PIN(4, "SDCARD_CLK" ), |
357 | PINCTRL_PIN(5, "SDCARD_CLK_FB" ), |
358 | PINCTRL_PIN(6, "SDCARD_D0" ), |
359 | PINCTRL_PIN(7, "SDCARD_D1" ), |
360 | PINCTRL_PIN(8, "SDCARD_D2" ), |
361 | PINCTRL_PIN(9, "SDCARD_D3" ), |
362 | PINCTRL_PIN(10, "SDCARD_CMD" ), |
363 | PINCTRL_PIN(11, "SDCARD_CD_B" ), |
364 | PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B" ), |
365 | PINCTRL_PIN(13, "GPIO_210" ), |
366 | PINCTRL_PIN(14, "OSC_CLK_OUT_0" ), |
367 | PINCTRL_PIN(15, "OSC_CLK_OUT_1" ), |
368 | PINCTRL_PIN(16, "CNV_BRI_DT" ), |
369 | PINCTRL_PIN(17, "CNV_BRI_RSP" ), |
370 | PINCTRL_PIN(18, "CNV_RGI_DT" ), |
371 | PINCTRL_PIN(19, "CNV_RGI_RSP" ), |
372 | PINCTRL_PIN(20, "CNV_RF_RESET_B" ), |
373 | PINCTRL_PIN(21, "XTAL_CLKREQ" ), |
374 | PINCTRL_PIN(22, "SDIO_CLK_FB" ), |
375 | PINCTRL_PIN(23, "EMMC0_CLK" ), |
376 | PINCTRL_PIN(24, "EMMC0_CLK_FB" ), |
377 | PINCTRL_PIN(25, "EMMC0_D0" ), |
378 | PINCTRL_PIN(26, "EMMC0_D1" ), |
379 | PINCTRL_PIN(27, "EMMC0_D2" ), |
380 | PINCTRL_PIN(28, "EMMC0_D3" ), |
381 | PINCTRL_PIN(29, "EMMC0_D4" ), |
382 | PINCTRL_PIN(30, "EMMC0_D5" ), |
383 | PINCTRL_PIN(31, "EMMC0_D6" ), |
384 | PINCTRL_PIN(32, "EMMC0_D7" ), |
385 | PINCTRL_PIN(33, "EMMC0_CMD" ), |
386 | PINCTRL_PIN(34, "EMMC0_STROBE" ), |
387 | }; |
388 | |
389 | static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 }; |
390 | static const unsigned int glk_scc_sdcard_pins[] = { |
391 | 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, |
392 | }; |
393 | static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 }; |
394 | static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 }; |
395 | static const unsigned int glk_scc_emmc_pins[] = { |
396 | 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, |
397 | }; |
398 | |
399 | static const struct intel_pingroup glk_scc_groups[] = { |
400 | PIN_GROUP("i2c7_grp" , glk_scc_i2c7_pins, 2), |
401 | PIN_GROUP("sdcard_grp" , glk_scc_sdcard_pins, 1), |
402 | PIN_GROUP("sdio_grp" , glk_scc_sdio_pins, 2), |
403 | PIN_GROUP("uart1_grp" , glk_scc_uart1_pins, 3), |
404 | PIN_GROUP("emmc_grp" , glk_scc_emmc_pins, 1), |
405 | }; |
406 | |
407 | static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" }; |
408 | static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" }; |
409 | static const char * const glk_scc_sdio_groups[] = { "sdio_grp" }; |
410 | static const char * const glk_scc_uart1_groups[] = { "uart1_grp" }; |
411 | static const char * const glk_scc_emmc_groups[] = { "emmc_grp" }; |
412 | |
413 | static const struct intel_function glk_scc_functions[] = { |
414 | FUNCTION("i2c7" , glk_scc_i2c7_groups), |
415 | FUNCTION("sdcard" , glk_scc_sdcard_groups), |
416 | FUNCTION("sdio" , glk_scc_sdio_groups), |
417 | FUNCTION("uart1" , glk_scc_uart1_groups), |
418 | FUNCTION("emmc" , glk_scc_emmc_groups), |
419 | }; |
420 | |
421 | static const struct intel_community glk_scc_communities[] = { |
422 | GLK_COMMUNITY(0, 0, 34), |
423 | }; |
424 | |
425 | static const struct intel_pinctrl_soc_data glk_scc_soc_data = { |
426 | .uid = "4" , |
427 | .pins = glk_scc_pins, |
428 | .npins = ARRAY_SIZE(glk_scc_pins), |
429 | .groups = glk_scc_groups, |
430 | .ngroups = ARRAY_SIZE(glk_scc_groups), |
431 | .functions = glk_scc_functions, |
432 | .nfunctions = ARRAY_SIZE(glk_scc_functions), |
433 | .communities = glk_scc_communities, |
434 | .ncommunities = ARRAY_SIZE(glk_scc_communities), |
435 | }; |
436 | |
437 | static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = { |
438 | &glk_northwest_soc_data, |
439 | &glk_north_soc_data, |
440 | &glk_audio_soc_data, |
441 | &glk_scc_soc_data, |
442 | NULL |
443 | }; |
444 | |
445 | static const struct acpi_device_id glk_pinctrl_acpi_match[] = { |
446 | { "INT3453" , (kernel_ulong_t)glk_pinctrl_soc_data }, |
447 | { } |
448 | }; |
449 | MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match); |
450 | |
451 | static struct platform_driver glk_pinctrl_driver = { |
452 | .probe = intel_pinctrl_probe_by_uid, |
453 | .driver = { |
454 | .name = "geminilake-pinctrl" , |
455 | .acpi_match_table = glk_pinctrl_acpi_match, |
456 | .pm = pm_sleep_ptr(&intel_pinctrl_pm_ops), |
457 | }, |
458 | }; |
459 | |
460 | static int __init glk_pinctrl_init(void) |
461 | { |
462 | return platform_driver_register(&glk_pinctrl_driver); |
463 | } |
464 | subsys_initcall(glk_pinctrl_init); |
465 | |
466 | static void __exit glk_pinctrl_exit(void) |
467 | { |
468 | platform_driver_unregister(&glk_pinctrl_driver); |
469 | } |
470 | module_exit(glk_pinctrl_exit); |
471 | |
472 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>" ); |
473 | MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver" ); |
474 | MODULE_LICENSE("GPL v2" ); |
475 | MODULE_IMPORT_NS(PINCTRL_INTEL); |
476 | |