1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Intel Tiger Lake PCH pinctrl/GPIO driver |
4 | * |
5 | * Copyright (C) 2019 - 2020, Intel Corporation |
6 | * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
7 | * Mika Westerberg <mika.westerberg@linux.intel.com> |
8 | */ |
9 | |
10 | #include <linux/mod_devicetable.h> |
11 | #include <linux/module.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/pm.h> |
14 | |
15 | #include <linux/pinctrl/pinctrl.h> |
16 | |
17 | #include "pinctrl-intel.h" |
18 | |
19 | #define TGL_LP_PAD_OWN 0x020 |
20 | #define TGL_LP_PADCFGLOCK 0x080 |
21 | #define TGL_LP_HOSTSW_OWN 0x0b0 |
22 | #define TGL_LP_GPI_IS 0x100 |
23 | #define TGL_LP_GPI_IE 0x120 |
24 | |
25 | #define TGL_H_PAD_OWN 0x020 |
26 | #define TGL_H_PADCFGLOCK 0x090 |
27 | #define TGL_H_HOSTSW_OWN 0x0c0 |
28 | #define TGL_H_GPI_IS 0x100 |
29 | #define TGL_H_GPI_IE 0x120 |
30 | |
31 | #define TGL_GPP(r, s, e, g) \ |
32 | { \ |
33 | .reg_num = (r), \ |
34 | .base = (s), \ |
35 | .size = ((e) - (s) + 1), \ |
36 | .gpio_base = (g), \ |
37 | } |
38 | |
39 | #define (b, s, e, g) \ |
40 | INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP) |
41 | |
42 | #define (b, s, e, g) \ |
43 | INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_H) |
44 | |
45 | /* Tiger Lake-LP */ |
46 | static const struct pinctrl_pin_desc tgllp_pins[] = { |
47 | /* GPP_B */ |
48 | PINCTRL_PIN(0, "CORE_VID_0" ), |
49 | PINCTRL_PIN(1, "CORE_VID_1" ), |
50 | PINCTRL_PIN(2, "VRALERTB" ), |
51 | PINCTRL_PIN(3, "CPU_GP_2" ), |
52 | PINCTRL_PIN(4, "CPU_GP_3" ), |
53 | PINCTRL_PIN(5, "ISH_I2C0_SDA" ), |
54 | PINCTRL_PIN(6, "ISH_I2C0_SCL" ), |
55 | PINCTRL_PIN(7, "ISH_I2C1_SDA" ), |
56 | PINCTRL_PIN(8, "ISH_I2C1_SCL" ), |
57 | PINCTRL_PIN(9, "I2C5_SDA" ), |
58 | PINCTRL_PIN(10, "I2C5_SCL" ), |
59 | PINCTRL_PIN(11, "PMCALERTB" ), |
60 | PINCTRL_PIN(12, "SLP_S0B" ), |
61 | PINCTRL_PIN(13, "PLTRSTB" ), |
62 | PINCTRL_PIN(14, "SPKR" ), |
63 | PINCTRL_PIN(15, "GSPI0_CS0B" ), |
64 | PINCTRL_PIN(16, "GSPI0_CLK" ), |
65 | PINCTRL_PIN(17, "GSPI0_MISO" ), |
66 | PINCTRL_PIN(18, "GSPI0_MOSI" ), |
67 | PINCTRL_PIN(19, "GSPI1_CS0B" ), |
68 | PINCTRL_PIN(20, "GSPI1_CLK" ), |
69 | PINCTRL_PIN(21, "GSPI1_MISO" ), |
70 | PINCTRL_PIN(22, "GSPI1_MOSI" ), |
71 | PINCTRL_PIN(23, "SML1ALERTB" ), |
72 | PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK" ), |
73 | PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK" ), |
74 | /* GPP_T */ |
75 | PINCTRL_PIN(26, "I2C6_SDA" ), |
76 | PINCTRL_PIN(27, "I2C6_SCL" ), |
77 | PINCTRL_PIN(28, "I2C7_SDA" ), |
78 | PINCTRL_PIN(29, "I2C7_SCL" ), |
79 | PINCTRL_PIN(30, "UART4_RXD" ), |
80 | PINCTRL_PIN(31, "UART4_TXD" ), |
81 | PINCTRL_PIN(32, "UART4_RTSB" ), |
82 | PINCTRL_PIN(33, "UART4_CTSB" ), |
83 | PINCTRL_PIN(34, "UART5_RXD" ), |
84 | PINCTRL_PIN(35, "UART5_TXD" ), |
85 | PINCTRL_PIN(36, "UART5_RTSB" ), |
86 | PINCTRL_PIN(37, "UART5_CTSB" ), |
87 | PINCTRL_PIN(38, "UART6_RXD" ), |
88 | PINCTRL_PIN(39, "UART6_TXD" ), |
89 | PINCTRL_PIN(40, "UART6_RTSB" ), |
90 | PINCTRL_PIN(41, "UART6_CTSB" ), |
91 | /* GPP_A */ |
92 | PINCTRL_PIN(42, "ESPI_IO_0" ), |
93 | PINCTRL_PIN(43, "ESPI_IO_1" ), |
94 | PINCTRL_PIN(44, "ESPI_IO_2" ), |
95 | PINCTRL_PIN(45, "ESPI_IO_3" ), |
96 | PINCTRL_PIN(46, "ESPI_CSB" ), |
97 | PINCTRL_PIN(47, "ESPI_CLK" ), |
98 | PINCTRL_PIN(48, "ESPI_RESETB" ), |
99 | PINCTRL_PIN(49, "I2S2_SCLK" ), |
100 | PINCTRL_PIN(50, "I2S2_SFRM" ), |
101 | PINCTRL_PIN(51, "I2S2_TXD" ), |
102 | PINCTRL_PIN(52, "I2S2_RXD" ), |
103 | PINCTRL_PIN(53, "PMC_I2C_SDA" ), |
104 | PINCTRL_PIN(54, "SATAXPCIE_1" ), |
105 | PINCTRL_PIN(55, "PMC_I2C_SCL" ), |
106 | PINCTRL_PIN(56, "USB2_OCB_1" ), |
107 | PINCTRL_PIN(57, "USB2_OCB_2" ), |
108 | PINCTRL_PIN(58, "USB2_OCB_3" ), |
109 | PINCTRL_PIN(59, "DDSP_HPD_C" ), |
110 | PINCTRL_PIN(60, "DDSP_HPD_B" ), |
111 | PINCTRL_PIN(61, "DDSP_HPD_1" ), |
112 | PINCTRL_PIN(62, "DDSP_HPD_2" ), |
113 | PINCTRL_PIN(63, "GPPC_A_21" ), |
114 | PINCTRL_PIN(64, "GPPC_A_22" ), |
115 | PINCTRL_PIN(65, "I2S1_SCLK" ), |
116 | PINCTRL_PIN(66, "ESPI_CLK_LOOPBK" ), |
117 | /* GPP_S */ |
118 | PINCTRL_PIN(67, "SNDW0_CLK" ), |
119 | PINCTRL_PIN(68, "SNDW0_DATA" ), |
120 | PINCTRL_PIN(69, "SNDW1_CLK" ), |
121 | PINCTRL_PIN(70, "SNDW1_DATA" ), |
122 | PINCTRL_PIN(71, "SNDW2_CLK" ), |
123 | PINCTRL_PIN(72, "SNDW2_DATA" ), |
124 | PINCTRL_PIN(73, "SNDW3_CLK" ), |
125 | PINCTRL_PIN(74, "SNDW3_DATA" ), |
126 | /* GPP_H */ |
127 | PINCTRL_PIN(75, "GPPC_H_0" ), |
128 | PINCTRL_PIN(76, "GPPC_H_1" ), |
129 | PINCTRL_PIN(77, "GPPC_H_2" ), |
130 | PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB" ), |
131 | PINCTRL_PIN(79, "I2C2_SDA" ), |
132 | PINCTRL_PIN(80, "I2C2_SCL" ), |
133 | PINCTRL_PIN(81, "I2C3_SDA" ), |
134 | PINCTRL_PIN(82, "I2C3_SCL" ), |
135 | PINCTRL_PIN(83, "I2C4_SDA" ), |
136 | PINCTRL_PIN(84, "I2C4_SCL" ), |
137 | PINCTRL_PIN(85, "SRCCLKREQB_4" ), |
138 | PINCTRL_PIN(86, "SRCCLKREQB_5" ), |
139 | PINCTRL_PIN(87, "M2_SKT2_CFG_0" ), |
140 | PINCTRL_PIN(88, "M2_SKT2_CFG_1" ), |
141 | PINCTRL_PIN(89, "M2_SKT2_CFG_2" ), |
142 | PINCTRL_PIN(90, "M2_SKT2_CFG_3" ), |
143 | PINCTRL_PIN(91, "DDPB_CTRLCLK" ), |
144 | PINCTRL_PIN(92, "DDPB_CTRLDATA" ), |
145 | PINCTRL_PIN(93, "CPU_C10_GATEB" ), |
146 | PINCTRL_PIN(94, "TIME_SYNC_0" ), |
147 | PINCTRL_PIN(95, "IMGCLKOUT_1" ), |
148 | PINCTRL_PIN(96, "IMGCLKOUT_2" ), |
149 | PINCTRL_PIN(97, "IMGCLKOUT_3" ), |
150 | PINCTRL_PIN(98, "IMGCLKOUT_4" ), |
151 | /* GPP_D */ |
152 | PINCTRL_PIN(99, "ISH_GP_0" ), |
153 | PINCTRL_PIN(100, "ISH_GP_1" ), |
154 | PINCTRL_PIN(101, "ISH_GP_2" ), |
155 | PINCTRL_PIN(102, "ISH_GP_3" ), |
156 | PINCTRL_PIN(103, "IMGCLKOUT_0" ), |
157 | PINCTRL_PIN(104, "SRCCLKREQB_0" ), |
158 | PINCTRL_PIN(105, "SRCCLKREQB_1" ), |
159 | PINCTRL_PIN(106, "SRCCLKREQB_2" ), |
160 | PINCTRL_PIN(107, "SRCCLKREQB_3" ), |
161 | PINCTRL_PIN(108, "ISH_SPI_CSB" ), |
162 | PINCTRL_PIN(109, "ISH_SPI_CLK" ), |
163 | PINCTRL_PIN(110, "ISH_SPI_MISO" ), |
164 | PINCTRL_PIN(111, "ISH_SPI_MOSI" ), |
165 | PINCTRL_PIN(112, "ISH_UART0_RXD" ), |
166 | PINCTRL_PIN(113, "ISH_UART0_TXD" ), |
167 | PINCTRL_PIN(114, "ISH_UART0_RTSB" ), |
168 | PINCTRL_PIN(115, "ISH_UART0_CTSB" ), |
169 | PINCTRL_PIN(116, "ISH_GP_4" ), |
170 | PINCTRL_PIN(117, "ISH_GP_5" ), |
171 | PINCTRL_PIN(118, "I2S_MCLK1_OUT" ), |
172 | PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK" ), |
173 | /* GPP_U */ |
174 | PINCTRL_PIN(120, "UART3_RXD" ), |
175 | PINCTRL_PIN(121, "UART3_TXD" ), |
176 | PINCTRL_PIN(122, "UART3_RTSB" ), |
177 | PINCTRL_PIN(123, "UART3_CTSB" ), |
178 | PINCTRL_PIN(124, "GSPI3_CS0B" ), |
179 | PINCTRL_PIN(125, "GSPI3_CLK" ), |
180 | PINCTRL_PIN(126, "GSPI3_MISO" ), |
181 | PINCTRL_PIN(127, "GSPI3_MOSI" ), |
182 | PINCTRL_PIN(128, "GSPI4_CS0B" ), |
183 | PINCTRL_PIN(129, "GSPI4_CLK" ), |
184 | PINCTRL_PIN(130, "GSPI4_MISO" ), |
185 | PINCTRL_PIN(131, "GSPI4_MOSI" ), |
186 | PINCTRL_PIN(132, "GSPI5_CS0B" ), |
187 | PINCTRL_PIN(133, "GSPI5_CLK" ), |
188 | PINCTRL_PIN(134, "GSPI5_MISO" ), |
189 | PINCTRL_PIN(135, "GSPI5_MOSI" ), |
190 | PINCTRL_PIN(136, "GSPI6_CS0B" ), |
191 | PINCTRL_PIN(137, "GSPI6_CLK" ), |
192 | PINCTRL_PIN(138, "GSPI6_MISO" ), |
193 | PINCTRL_PIN(139, "GSPI6_MOSI" ), |
194 | PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK" ), |
195 | PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK" ), |
196 | PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK" ), |
197 | PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK" ), |
198 | /* vGPIO */ |
199 | PINCTRL_PIN(144, "CNV_BTEN" ), |
200 | PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB" ), |
201 | PINCTRL_PIN(146, "CNV_BT_IF_SELECT" ), |
202 | PINCTRL_PIN(147, "vCNV_BT_UART_TXD" ), |
203 | PINCTRL_PIN(148, "vCNV_BT_UART_RXD" ), |
204 | PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B" ), |
205 | PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B" ), |
206 | PINCTRL_PIN(151, "vCNV_MFUART1_TXD" ), |
207 | PINCTRL_PIN(152, "vCNV_MFUART1_RXD" ), |
208 | PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B" ), |
209 | PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B" ), |
210 | PINCTRL_PIN(155, "vUART0_TXD" ), |
211 | PINCTRL_PIN(156, "vUART0_RXD" ), |
212 | PINCTRL_PIN(157, "vUART0_CTS_B" ), |
213 | PINCTRL_PIN(158, "vUART0_RTS_B" ), |
214 | PINCTRL_PIN(159, "vISH_UART0_TXD" ), |
215 | PINCTRL_PIN(160, "vISH_UART0_RXD" ), |
216 | PINCTRL_PIN(161, "vISH_UART0_CTS_B" ), |
217 | PINCTRL_PIN(162, "vISH_UART0_RTS_B" ), |
218 | PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK" ), |
219 | PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC" ), |
220 | PINCTRL_PIN(165, "vCNV_BT_I2S_SDO" ), |
221 | PINCTRL_PIN(166, "vCNV_BT_I2S_SDI" ), |
222 | PINCTRL_PIN(167, "vI2S2_SCLK" ), |
223 | PINCTRL_PIN(168, "vI2S2_SFRM" ), |
224 | PINCTRL_PIN(169, "vI2S2_TXD" ), |
225 | PINCTRL_PIN(170, "vI2S2_RXD" ), |
226 | /* GPP_C */ |
227 | PINCTRL_PIN(171, "SMBCLK" ), |
228 | PINCTRL_PIN(172, "SMBDATA" ), |
229 | PINCTRL_PIN(173, "SMBALERTB" ), |
230 | PINCTRL_PIN(174, "SML0CLK" ), |
231 | PINCTRL_PIN(175, "SML0DATA" ), |
232 | PINCTRL_PIN(176, "SML0ALERTB" ), |
233 | PINCTRL_PIN(177, "SML1CLK" ), |
234 | PINCTRL_PIN(178, "SML1DATA" ), |
235 | PINCTRL_PIN(179, "UART0_RXD" ), |
236 | PINCTRL_PIN(180, "UART0_TXD" ), |
237 | PINCTRL_PIN(181, "UART0_RTSB" ), |
238 | PINCTRL_PIN(182, "UART0_CTSB" ), |
239 | PINCTRL_PIN(183, "UART1_RXD" ), |
240 | PINCTRL_PIN(184, "UART1_TXD" ), |
241 | PINCTRL_PIN(185, "UART1_RTSB" ), |
242 | PINCTRL_PIN(186, "UART1_CTSB" ), |
243 | PINCTRL_PIN(187, "I2C0_SDA" ), |
244 | PINCTRL_PIN(188, "I2C0_SCL" ), |
245 | PINCTRL_PIN(189, "I2C1_SDA" ), |
246 | PINCTRL_PIN(190, "I2C1_SCL" ), |
247 | PINCTRL_PIN(191, "UART2_RXD" ), |
248 | PINCTRL_PIN(192, "UART2_TXD" ), |
249 | PINCTRL_PIN(193, "UART2_RTSB" ), |
250 | PINCTRL_PIN(194, "UART2_CTSB" ), |
251 | /* GPP_F */ |
252 | PINCTRL_PIN(195, "CNV_BRI_DT" ), |
253 | PINCTRL_PIN(196, "CNV_BRI_RSP" ), |
254 | PINCTRL_PIN(197, "CNV_RGI_DT" ), |
255 | PINCTRL_PIN(198, "CNV_RGI_RSP" ), |
256 | PINCTRL_PIN(199, "CNV_RF_RESET_B" ), |
257 | PINCTRL_PIN(200, "GPPC_F_5" ), |
258 | PINCTRL_PIN(201, "CNV_PA_BLANKING" ), |
259 | PINCTRL_PIN(202, "GPPC_F_7" ), |
260 | PINCTRL_PIN(203, "I2S_MCLK2_INOUT" ), |
261 | PINCTRL_PIN(204, "BOOTMPC" ), |
262 | PINCTRL_PIN(205, "GPPC_F_10" ), |
263 | PINCTRL_PIN(206, "GPPC_F_11" ), |
264 | PINCTRL_PIN(207, "GSXDOUT" ), |
265 | PINCTRL_PIN(208, "GSXSLOAD" ), |
266 | PINCTRL_PIN(209, "GSXDIN" ), |
267 | PINCTRL_PIN(210, "GSXSRESETB" ), |
268 | PINCTRL_PIN(211, "GSXCLK" ), |
269 | PINCTRL_PIN(212, "GMII_MDC" ), |
270 | PINCTRL_PIN(213, "GMII_MDIO" ), |
271 | PINCTRL_PIN(214, "SRCCLKREQB_6" ), |
272 | PINCTRL_PIN(215, "EXT_PWR_GATEB" ), |
273 | PINCTRL_PIN(216, "EXT_PWR_GATE2B" ), |
274 | PINCTRL_PIN(217, "VNN_CTRL" ), |
275 | PINCTRL_PIN(218, "V1P05_CTRL" ), |
276 | PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK" ), |
277 | /* HVCMOS */ |
278 | PINCTRL_PIN(220, "L_BKLTEN" ), |
279 | PINCTRL_PIN(221, "L_BKLTCTL" ), |
280 | PINCTRL_PIN(222, "L_VDDEN" ), |
281 | PINCTRL_PIN(223, "SYS_PWROK" ), |
282 | PINCTRL_PIN(224, "SYS_RESETB" ), |
283 | PINCTRL_PIN(225, "MLK_RSTB" ), |
284 | /* GPP_E */ |
285 | PINCTRL_PIN(226, "SATAXPCIE_0" ), |
286 | PINCTRL_PIN(227, "SPI1_IO_2" ), |
287 | PINCTRL_PIN(228, "SPI1_IO_3" ), |
288 | PINCTRL_PIN(229, "CPU_GP_0" ), |
289 | PINCTRL_PIN(230, "SATA_DEVSLP_0" ), |
290 | PINCTRL_PIN(231, "SATA_DEVSLP_1" ), |
291 | PINCTRL_PIN(232, "GPPC_E_6" ), |
292 | PINCTRL_PIN(233, "CPU_GP_1" ), |
293 | PINCTRL_PIN(234, "SPI1_CS1B" ), |
294 | PINCTRL_PIN(235, "USB2_OCB_0" ), |
295 | PINCTRL_PIN(236, "SPI1_CSB" ), |
296 | PINCTRL_PIN(237, "SPI1_CLK" ), |
297 | PINCTRL_PIN(238, "SPI1_MISO_IO_1" ), |
298 | PINCTRL_PIN(239, "SPI1_MOSI_IO_0" ), |
299 | PINCTRL_PIN(240, "DDSP_HPD_A" ), |
300 | PINCTRL_PIN(241, "ISH_GP_6" ), |
301 | PINCTRL_PIN(242, "ISH_GP_7" ), |
302 | PINCTRL_PIN(243, "GPPC_E_17" ), |
303 | PINCTRL_PIN(244, "DDP1_CTRLCLK" ), |
304 | PINCTRL_PIN(245, "DDP1_CTRLDATA" ), |
305 | PINCTRL_PIN(246, "DDP2_CTRLCLK" ), |
306 | PINCTRL_PIN(247, "DDP2_CTRLDATA" ), |
307 | PINCTRL_PIN(248, "DDPA_CTRLCLK" ), |
308 | PINCTRL_PIN(249, "DDPA_CTRLDATA" ), |
309 | PINCTRL_PIN(250, "SPI1_CLK_LOOPBK" ), |
310 | /* JTAG */ |
311 | PINCTRL_PIN(251, "JTAG_TDO" ), |
312 | PINCTRL_PIN(252, "JTAGX" ), |
313 | PINCTRL_PIN(253, "PRDYB" ), |
314 | PINCTRL_PIN(254, "PREQB" ), |
315 | PINCTRL_PIN(255, "CPU_TRSTB" ), |
316 | PINCTRL_PIN(256, "JTAG_TDI" ), |
317 | PINCTRL_PIN(257, "JTAG_TMS" ), |
318 | PINCTRL_PIN(258, "JTAG_TCK" ), |
319 | PINCTRL_PIN(259, "DBG_PMODE" ), |
320 | /* GPP_R */ |
321 | PINCTRL_PIN(260, "HDA_BCLK" ), |
322 | PINCTRL_PIN(261, "HDA_SYNC" ), |
323 | PINCTRL_PIN(262, "HDA_SDO" ), |
324 | PINCTRL_PIN(263, "HDA_SDI_0" ), |
325 | PINCTRL_PIN(264, "HDA_RSTB" ), |
326 | PINCTRL_PIN(265, "HDA_SDI_1" ), |
327 | PINCTRL_PIN(266, "GPP_R_6" ), |
328 | PINCTRL_PIN(267, "GPP_R_7" ), |
329 | /* SPI */ |
330 | PINCTRL_PIN(268, "SPI0_IO_2" ), |
331 | PINCTRL_PIN(269, "SPI0_IO_3" ), |
332 | PINCTRL_PIN(270, "SPI0_MOSI_IO_0" ), |
333 | PINCTRL_PIN(271, "SPI0_MISO_IO_1" ), |
334 | PINCTRL_PIN(272, "SPI0_TPM_CSB" ), |
335 | PINCTRL_PIN(273, "SPI0_FLASH_0_CSB" ), |
336 | PINCTRL_PIN(274, "SPI0_FLASH_1_CSB" ), |
337 | PINCTRL_PIN(275, "SPI0_CLK" ), |
338 | PINCTRL_PIN(276, "SPI0_CLK_LOOPBK" ), |
339 | }; |
340 | |
341 | static const struct intel_padgroup [] = { |
342 | TGL_GPP(0, 0, 25, 0), /* GPP_B */ |
343 | TGL_GPP(1, 26, 41, 32), /* GPP_T */ |
344 | TGL_GPP(2, 42, 66, 64), /* GPP_A */ |
345 | }; |
346 | |
347 | static const struct intel_padgroup [] = { |
348 | TGL_GPP(0, 67, 74, 96), /* GPP_S */ |
349 | TGL_GPP(1, 75, 98, 128), /* GPP_H */ |
350 | TGL_GPP(2, 99, 119, 160), /* GPP_D */ |
351 | TGL_GPP(3, 120, 143, 192), /* GPP_U */ |
352 | TGL_GPP(4, 144, 170, 224), /* vGPIO */ |
353 | }; |
354 | |
355 | static const struct intel_padgroup [] = { |
356 | TGL_GPP(0, 171, 194, 256), /* GPP_C */ |
357 | TGL_GPP(1, 195, 219, 288), /* GPP_F */ |
358 | TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ |
359 | TGL_GPP(3, 226, 250, 320), /* GPP_E */ |
360 | TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
361 | }; |
362 | |
363 | static const struct intel_padgroup [] = { |
364 | TGL_GPP(0, 260, 267, 352), /* GPP_R */ |
365 | TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ |
366 | }; |
367 | |
368 | static const struct intel_community tgllp_communities[] = { |
369 | TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps), |
370 | TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps), |
371 | TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps), |
372 | TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps), |
373 | }; |
374 | |
375 | static const struct intel_pinctrl_soc_data tgllp_soc_data = { |
376 | .pins = tgllp_pins, |
377 | .npins = ARRAY_SIZE(tgllp_pins), |
378 | .communities = tgllp_communities, |
379 | .ncommunities = ARRAY_SIZE(tgllp_communities), |
380 | }; |
381 | |
382 | /* Tiger Lake-H */ |
383 | static const struct pinctrl_pin_desc tglh_pins[] = { |
384 | /* GPP_A */ |
385 | PINCTRL_PIN(0, "SPI0_IO_2" ), |
386 | PINCTRL_PIN(1, "SPI0_IO_3" ), |
387 | PINCTRL_PIN(2, "SPI0_MOSI_IO_0" ), |
388 | PINCTRL_PIN(3, "SPI0_MISO_IO_1" ), |
389 | PINCTRL_PIN(4, "SPI0_TPM_CSB" ), |
390 | PINCTRL_PIN(5, "SPI0_FLASH_0_CSB" ), |
391 | PINCTRL_PIN(6, "SPI0_FLASH_1_CSB" ), |
392 | PINCTRL_PIN(7, "SPI0_CLK" ), |
393 | PINCTRL_PIN(8, "ESPI_IO_0" ), |
394 | PINCTRL_PIN(9, "ESPI_IO_1" ), |
395 | PINCTRL_PIN(10, "ESPI_IO_2" ), |
396 | PINCTRL_PIN(11, "ESPI_IO_3" ), |
397 | PINCTRL_PIN(12, "ESPI_CS0B" ), |
398 | PINCTRL_PIN(13, "ESPI_CLK" ), |
399 | PINCTRL_PIN(14, "ESPI_RESETB" ), |
400 | PINCTRL_PIN(15, "ESPI_CS1B" ), |
401 | PINCTRL_PIN(16, "ESPI_CS2B" ), |
402 | PINCTRL_PIN(17, "ESPI_CS3B" ), |
403 | PINCTRL_PIN(18, "ESPI_ALERT0B" ), |
404 | PINCTRL_PIN(19, "ESPI_ALERT1B" ), |
405 | PINCTRL_PIN(20, "ESPI_ALERT2B" ), |
406 | PINCTRL_PIN(21, "ESPI_ALERT3B" ), |
407 | PINCTRL_PIN(22, "GPPC_A_14" ), |
408 | PINCTRL_PIN(23, "SPI0_CLK_LOOPBK" ), |
409 | PINCTRL_PIN(24, "ESPI_CLK_LOOPBK" ), |
410 | /* GPP_R */ |
411 | PINCTRL_PIN(25, "HDA_BCLK" ), |
412 | PINCTRL_PIN(26, "HDA_SYNC" ), |
413 | PINCTRL_PIN(27, "HDA_SDO" ), |
414 | PINCTRL_PIN(28, "HDA_SDI_0" ), |
415 | PINCTRL_PIN(29, "HDA_RSTB" ), |
416 | PINCTRL_PIN(30, "HDA_SDI_1" ), |
417 | PINCTRL_PIN(31, "GPP_R_6" ), |
418 | PINCTRL_PIN(32, "GPP_R_7" ), |
419 | PINCTRL_PIN(33, "GPP_R_8" ), |
420 | PINCTRL_PIN(34, "PCIE_LNK_DOWN" ), |
421 | PINCTRL_PIN(35, "ISH_UART0_RTSB" ), |
422 | PINCTRL_PIN(36, "SX_EXIT_HOLDOFFB" ), |
423 | PINCTRL_PIN(37, "CLKOUT_48" ), |
424 | PINCTRL_PIN(38, "ISH_GP_7" ), |
425 | PINCTRL_PIN(39, "ISH_GP_0" ), |
426 | PINCTRL_PIN(40, "ISH_GP_1" ), |
427 | PINCTRL_PIN(41, "ISH_GP_2" ), |
428 | PINCTRL_PIN(42, "ISH_GP_3" ), |
429 | PINCTRL_PIN(43, "ISH_GP_4" ), |
430 | PINCTRL_PIN(44, "ISH_GP_5" ), |
431 | /* GPP_B */ |
432 | PINCTRL_PIN(45, "GSPI0_CS1B" ), |
433 | PINCTRL_PIN(46, "GSPI1_CS1B" ), |
434 | PINCTRL_PIN(47, "VRALERTB" ), |
435 | PINCTRL_PIN(48, "CPU_GP_2" ), |
436 | PINCTRL_PIN(49, "CPU_GP_3" ), |
437 | PINCTRL_PIN(50, "SRCCLKREQB_0" ), |
438 | PINCTRL_PIN(51, "SRCCLKREQB_1" ), |
439 | PINCTRL_PIN(52, "SRCCLKREQB_2" ), |
440 | PINCTRL_PIN(53, "SRCCLKREQB_3" ), |
441 | PINCTRL_PIN(54, "SRCCLKREQB_4" ), |
442 | PINCTRL_PIN(55, "SRCCLKREQB_5" ), |
443 | PINCTRL_PIN(56, "I2S_MCLK" ), |
444 | PINCTRL_PIN(57, "SLP_S0B" ), |
445 | PINCTRL_PIN(58, "PLTRSTB" ), |
446 | PINCTRL_PIN(59, "SPKR" ), |
447 | PINCTRL_PIN(60, "GSPI0_CS0B" ), |
448 | PINCTRL_PIN(61, "GSPI0_CLK" ), |
449 | PINCTRL_PIN(62, "GSPI0_MISO" ), |
450 | PINCTRL_PIN(63, "GSPI0_MOSI" ), |
451 | PINCTRL_PIN(64, "GSPI1_CS0B" ), |
452 | PINCTRL_PIN(65, "GSPI1_CLK" ), |
453 | PINCTRL_PIN(66, "GSPI1_MISO" ), |
454 | PINCTRL_PIN(67, "GSPI1_MOSI" ), |
455 | PINCTRL_PIN(68, "SML1ALERTB" ), |
456 | PINCTRL_PIN(69, "GSPI0_CLK_LOOPBK" ), |
457 | PINCTRL_PIN(70, "GSPI1_CLK_LOOPBK" ), |
458 | /* vGPIO_0 */ |
459 | PINCTRL_PIN(71, "ESPI_USB_OCB_0" ), |
460 | PINCTRL_PIN(72, "ESPI_USB_OCB_1" ), |
461 | PINCTRL_PIN(73, "ESPI_USB_OCB_2" ), |
462 | PINCTRL_PIN(74, "ESPI_USB_OCB_3" ), |
463 | PINCTRL_PIN(75, "USB_CPU_OCB_0" ), |
464 | PINCTRL_PIN(76, "USB_CPU_OCB_1" ), |
465 | PINCTRL_PIN(77, "USB_CPU_OCB_2" ), |
466 | PINCTRL_PIN(78, "USB_CPU_OCB_3" ), |
467 | /* GPP_D */ |
468 | PINCTRL_PIN(79, "SPI1_CSB" ), |
469 | PINCTRL_PIN(80, "SPI1_CLK" ), |
470 | PINCTRL_PIN(81, "SPI1_MISO_IO_1" ), |
471 | PINCTRL_PIN(82, "SPI1_MOSI_IO_0" ), |
472 | PINCTRL_PIN(83, "SML1CLK" ), |
473 | PINCTRL_PIN(84, "I2S2_SFRM" ), |
474 | PINCTRL_PIN(85, "I2S2_TXD" ), |
475 | PINCTRL_PIN(86, "I2S2_RXD" ), |
476 | PINCTRL_PIN(87, "I2S2_SCLK" ), |
477 | PINCTRL_PIN(88, "SML0CLK" ), |
478 | PINCTRL_PIN(89, "SML0DATA" ), |
479 | PINCTRL_PIN(90, "GPP_D_11" ), |
480 | PINCTRL_PIN(91, "ISH_UART0_CTSB" ), |
481 | PINCTRL_PIN(92, "SPI1_IO_2" ), |
482 | PINCTRL_PIN(93, "SPI1_IO_3" ), |
483 | PINCTRL_PIN(94, "SML1DATA" ), |
484 | PINCTRL_PIN(95, "GSPI3_CS0B" ), |
485 | PINCTRL_PIN(96, "GSPI3_CLK" ), |
486 | PINCTRL_PIN(97, "GSPI3_MISO" ), |
487 | PINCTRL_PIN(98, "GSPI3_MOSI" ), |
488 | PINCTRL_PIN(99, "UART3_RXD" ), |
489 | PINCTRL_PIN(100, "UART3_TXD" ), |
490 | PINCTRL_PIN(101, "UART3_RTSB" ), |
491 | PINCTRL_PIN(102, "UART3_CTSB" ), |
492 | PINCTRL_PIN(103, "SPI1_CLK_LOOPBK" ), |
493 | PINCTRL_PIN(104, "GSPI3_CLK_LOOPBK" ), |
494 | /* GPP_C */ |
495 | PINCTRL_PIN(105, "SMBCLK" ), |
496 | PINCTRL_PIN(106, "SMBDATA" ), |
497 | PINCTRL_PIN(107, "SMBALERTB" ), |
498 | PINCTRL_PIN(108, "ISH_UART0_RXD" ), |
499 | PINCTRL_PIN(109, "ISH_UART0_TXD" ), |
500 | PINCTRL_PIN(110, "SML0ALERTB" ), |
501 | PINCTRL_PIN(111, "ISH_I2C2_SDA" ), |
502 | PINCTRL_PIN(112, "ISH_I2C2_SCL" ), |
503 | PINCTRL_PIN(113, "UART0_RXD" ), |
504 | PINCTRL_PIN(114, "UART0_TXD" ), |
505 | PINCTRL_PIN(115, "UART0_RTSB" ), |
506 | PINCTRL_PIN(116, "UART0_CTSB" ), |
507 | PINCTRL_PIN(117, "UART1_RXD" ), |
508 | PINCTRL_PIN(118, "UART1_TXD" ), |
509 | PINCTRL_PIN(119, "UART1_RTSB" ), |
510 | PINCTRL_PIN(120, "UART1_CTSB" ), |
511 | PINCTRL_PIN(121, "I2C0_SDA" ), |
512 | PINCTRL_PIN(122, "I2C0_SCL" ), |
513 | PINCTRL_PIN(123, "I2C1_SDA" ), |
514 | PINCTRL_PIN(124, "I2C1_SCL" ), |
515 | PINCTRL_PIN(125, "UART2_RXD" ), |
516 | PINCTRL_PIN(126, "UART2_TXD" ), |
517 | PINCTRL_PIN(127, "UART2_RTSB" ), |
518 | PINCTRL_PIN(128, "UART2_CTSB" ), |
519 | /* GPP_S */ |
520 | PINCTRL_PIN(129, "SNDW1_CLK" ), |
521 | PINCTRL_PIN(130, "SNDW1_DATA" ), |
522 | PINCTRL_PIN(131, "SNDW2_CLK" ), |
523 | PINCTRL_PIN(132, "SNDW2_DATA" ), |
524 | PINCTRL_PIN(133, "SNDW3_CLK" ), |
525 | PINCTRL_PIN(134, "SNDW3_DATA" ), |
526 | PINCTRL_PIN(135, "SNDW4_CLK" ), |
527 | PINCTRL_PIN(136, "SNDW4_DATA" ), |
528 | /* GPP_G */ |
529 | PINCTRL_PIN(137, "DDPA_CTRLCLK" ), |
530 | PINCTRL_PIN(138, "DDPA_CTRLDATA" ), |
531 | PINCTRL_PIN(139, "DNX_FORCE_RELOAD" ), |
532 | PINCTRL_PIN(140, "GMII_MDC_0" ), |
533 | PINCTRL_PIN(141, "GMII_MDIO_0" ), |
534 | PINCTRL_PIN(142, "SLP_DRAMB" ), |
535 | PINCTRL_PIN(143, "GPPC_G_6" ), |
536 | PINCTRL_PIN(144, "GPPC_G_7" ), |
537 | PINCTRL_PIN(145, "ISH_SPI_CSB" ), |
538 | PINCTRL_PIN(146, "ISH_SPI_CLK" ), |
539 | PINCTRL_PIN(147, "ISH_SPI_MISO" ), |
540 | PINCTRL_PIN(148, "ISH_SPI_MOSI" ), |
541 | PINCTRL_PIN(149, "DDP1_CTRLCLK" ), |
542 | PINCTRL_PIN(150, "DDP1_CTRLDATA" ), |
543 | PINCTRL_PIN(151, "DDP2_CTRLCLK" ), |
544 | PINCTRL_PIN(152, "DDP2_CTRLDATA" ), |
545 | PINCTRL_PIN(153, "GSPI2_CLK_LOOPBK" ), |
546 | /* vGPIO */ |
547 | PINCTRL_PIN(154, "CNV_BTEN" ), |
548 | PINCTRL_PIN(155, "CNV_BT_HOST_WAKEB" ), |
549 | PINCTRL_PIN(156, "CNV_BT_IF_SELECT" ), |
550 | PINCTRL_PIN(157, "vCNV_BT_UART_TXD" ), |
551 | PINCTRL_PIN(158, "vCNV_BT_UART_RXD" ), |
552 | PINCTRL_PIN(159, "vCNV_BT_UART_CTS_B" ), |
553 | PINCTRL_PIN(160, "vCNV_BT_UART_RTS_B" ), |
554 | PINCTRL_PIN(161, "vCNV_MFUART1_TXD" ), |
555 | PINCTRL_PIN(162, "vCNV_MFUART1_RXD" ), |
556 | PINCTRL_PIN(163, "vCNV_MFUART1_CTS_B" ), |
557 | PINCTRL_PIN(164, "vCNV_MFUART1_RTS_B" ), |
558 | PINCTRL_PIN(165, "vUART0_TXD" ), |
559 | PINCTRL_PIN(166, "vUART0_RXD" ), |
560 | PINCTRL_PIN(167, "vUART0_CTS_B" ), |
561 | PINCTRL_PIN(168, "vUART0_RTS_B" ), |
562 | PINCTRL_PIN(169, "vISH_UART0_TXD" ), |
563 | PINCTRL_PIN(170, "vISH_UART0_RXD" ), |
564 | PINCTRL_PIN(171, "vISH_UART0_CTS_B" ), |
565 | PINCTRL_PIN(172, "vISH_UART0_RTS_B" ), |
566 | PINCTRL_PIN(173, "vCNV_BT_I2S_BCLK" ), |
567 | PINCTRL_PIN(174, "vCNV_BT_I2S_WS_SYNC" ), |
568 | PINCTRL_PIN(175, "vCNV_BT_I2S_SDO" ), |
569 | PINCTRL_PIN(176, "vCNV_BT_I2S_SDI" ), |
570 | PINCTRL_PIN(177, "vI2S2_SCLK" ), |
571 | PINCTRL_PIN(178, "vI2S2_SFRM" ), |
572 | PINCTRL_PIN(179, "vI2S2_TXD" ), |
573 | PINCTRL_PIN(180, "vI2S2_RXD" ), |
574 | /* GPP_E */ |
575 | PINCTRL_PIN(181, "SATAXPCIE_0" ), |
576 | PINCTRL_PIN(182, "SATAXPCIE_1" ), |
577 | PINCTRL_PIN(183, "SATAXPCIE_2" ), |
578 | PINCTRL_PIN(184, "CPU_GP_0" ), |
579 | PINCTRL_PIN(185, "SATA_DEVSLP_0" ), |
580 | PINCTRL_PIN(186, "SATA_DEVSLP_1" ), |
581 | PINCTRL_PIN(187, "SATA_DEVSLP_2" ), |
582 | PINCTRL_PIN(188, "CPU_GP_1" ), |
583 | PINCTRL_PIN(189, "SATA_LEDB" ), |
584 | PINCTRL_PIN(190, "USB2_OCB_0" ), |
585 | PINCTRL_PIN(191, "USB2_OCB_1" ), |
586 | PINCTRL_PIN(192, "USB2_OCB_2" ), |
587 | PINCTRL_PIN(193, "USB2_OCB_3" ), |
588 | /* GPP_F */ |
589 | PINCTRL_PIN(194, "SATAXPCIE_3" ), |
590 | PINCTRL_PIN(195, "SATAXPCIE_4" ), |
591 | PINCTRL_PIN(196, "SATAXPCIE_5" ), |
592 | PINCTRL_PIN(197, "SATAXPCIE_6" ), |
593 | PINCTRL_PIN(198, "SATAXPCIE_7" ), |
594 | PINCTRL_PIN(199, "SATA_DEVSLP_3" ), |
595 | PINCTRL_PIN(200, "SATA_DEVSLP_4" ), |
596 | PINCTRL_PIN(201, "SATA_DEVSLP_5" ), |
597 | PINCTRL_PIN(202, "SATA_DEVSLP_6" ), |
598 | PINCTRL_PIN(203, "SATA_DEVSLP_7" ), |
599 | PINCTRL_PIN(204, "SATA_SCLOCK" ), |
600 | PINCTRL_PIN(205, "SATA_SLOAD" ), |
601 | PINCTRL_PIN(206, "SATA_SDATAOUT1" ), |
602 | PINCTRL_PIN(207, "SATA_SDATAOUT0" ), |
603 | PINCTRL_PIN(208, "PS_ONB" ), |
604 | PINCTRL_PIN(209, "M2_SKT2_CFG_0" ), |
605 | PINCTRL_PIN(210, "M2_SKT2_CFG_1" ), |
606 | PINCTRL_PIN(211, "M2_SKT2_CFG_2" ), |
607 | PINCTRL_PIN(212, "M2_SKT2_CFG_3" ), |
608 | PINCTRL_PIN(213, "L_VDDEN" ), |
609 | PINCTRL_PIN(214, "L_BKLTEN" ), |
610 | PINCTRL_PIN(215, "L_BKLTCTL" ), |
611 | PINCTRL_PIN(216, "VNN_CTRL" ), |
612 | PINCTRL_PIN(217, "GPP_F_23" ), |
613 | /* GPP_H */ |
614 | PINCTRL_PIN(218, "SRCCLKREQB_6" ), |
615 | PINCTRL_PIN(219, "SRCCLKREQB_7" ), |
616 | PINCTRL_PIN(220, "SRCCLKREQB_8" ), |
617 | PINCTRL_PIN(221, "SRCCLKREQB_9" ), |
618 | PINCTRL_PIN(222, "SRCCLKREQB_10" ), |
619 | PINCTRL_PIN(223, "SRCCLKREQB_11" ), |
620 | PINCTRL_PIN(224, "SRCCLKREQB_12" ), |
621 | PINCTRL_PIN(225, "SRCCLKREQB_13" ), |
622 | PINCTRL_PIN(226, "SRCCLKREQB_14" ), |
623 | PINCTRL_PIN(227, "SRCCLKREQB_15" ), |
624 | PINCTRL_PIN(228, "SML2CLK" ), |
625 | PINCTRL_PIN(229, "SML2DATA" ), |
626 | PINCTRL_PIN(230, "SML2ALERTB" ), |
627 | PINCTRL_PIN(231, "SML3CLK" ), |
628 | PINCTRL_PIN(232, "SML3DATA" ), |
629 | PINCTRL_PIN(233, "SML3ALERTB" ), |
630 | PINCTRL_PIN(234, "SML4CLK" ), |
631 | PINCTRL_PIN(235, "SML4DATA" ), |
632 | PINCTRL_PIN(236, "SML4ALERTB" ), |
633 | PINCTRL_PIN(237, "ISH_I2C0_SDA" ), |
634 | PINCTRL_PIN(238, "ISH_I2C0_SCL" ), |
635 | PINCTRL_PIN(239, "ISH_I2C1_SDA" ), |
636 | PINCTRL_PIN(240, "ISH_I2C1_SCL" ), |
637 | PINCTRL_PIN(241, "TIME_SYNC_0" ), |
638 | /* GPP_J */ |
639 | PINCTRL_PIN(242, "CNV_PA_BLANKING" ), |
640 | PINCTRL_PIN(243, "CPU_C10_GATEB" ), |
641 | PINCTRL_PIN(244, "CNV_BRI_DT" ), |
642 | PINCTRL_PIN(245, "CNV_BRI_RSP" ), |
643 | PINCTRL_PIN(246, "CNV_RGI_DT" ), |
644 | PINCTRL_PIN(247, "CNV_RGI_RSP" ), |
645 | PINCTRL_PIN(248, "CNV_MFUART2_RXD" ), |
646 | PINCTRL_PIN(249, "CNV_MFUART2_TXD" ), |
647 | PINCTRL_PIN(250, "GPP_J_8" ), |
648 | PINCTRL_PIN(251, "GPP_J_9" ), |
649 | /* GPP_K */ |
650 | PINCTRL_PIN(252, "GSXDOUT" ), |
651 | PINCTRL_PIN(253, "GSXSLOAD" ), |
652 | PINCTRL_PIN(254, "GSXDIN" ), |
653 | PINCTRL_PIN(255, "GSXSRESETB" ), |
654 | PINCTRL_PIN(256, "GSXCLK" ), |
655 | PINCTRL_PIN(257, "ADR_COMPLETE" ), |
656 | PINCTRL_PIN(258, "DDSP_HPD_A" ), |
657 | PINCTRL_PIN(259, "DDSP_HPD_B" ), |
658 | PINCTRL_PIN(260, "CORE_VID_0" ), |
659 | PINCTRL_PIN(261, "CORE_VID_1" ), |
660 | PINCTRL_PIN(262, "DDSP_HPD_C" ), |
661 | PINCTRL_PIN(263, "GPP_K_11" ), |
662 | PINCTRL_PIN(264, "SYS_PWROK" ), |
663 | PINCTRL_PIN(265, "SYS_RESETB" ), |
664 | PINCTRL_PIN(266, "MLK_RSTB" ), |
665 | /* GPP_I */ |
666 | PINCTRL_PIN(267, "PMCALERTB" ), |
667 | PINCTRL_PIN(268, "DDSP_HPD_1" ), |
668 | PINCTRL_PIN(269, "DDSP_HPD_2" ), |
669 | PINCTRL_PIN(270, "DDSP_HPD_3" ), |
670 | PINCTRL_PIN(271, "DDSP_HPD_4" ), |
671 | PINCTRL_PIN(272, "DDPB_CTRLCLK" ), |
672 | PINCTRL_PIN(273, "DDPB_CTRLDATA" ), |
673 | PINCTRL_PIN(274, "DDPC_CTRLCLK" ), |
674 | PINCTRL_PIN(275, "DDPC_CTRLDATA" ), |
675 | PINCTRL_PIN(276, "FUSA_DIAGTEST_EN" ), |
676 | PINCTRL_PIN(277, "FUSA_DIAGTEST_MODE" ), |
677 | PINCTRL_PIN(278, "USB2_OCB_4" ), |
678 | PINCTRL_PIN(279, "USB2_OCB_5" ), |
679 | PINCTRL_PIN(280, "USB2_OCB_6" ), |
680 | PINCTRL_PIN(281, "USB2_OCB_7" ), |
681 | /* JTAG */ |
682 | PINCTRL_PIN(282, "JTAG_TDO" ), |
683 | PINCTRL_PIN(283, "JTAGX" ), |
684 | PINCTRL_PIN(284, "PRDYB" ), |
685 | PINCTRL_PIN(285, "PREQB" ), |
686 | PINCTRL_PIN(286, "JTAG_TDI" ), |
687 | PINCTRL_PIN(287, "JTAG_TMS" ), |
688 | PINCTRL_PIN(288, "JTAG_TCK" ), |
689 | PINCTRL_PIN(289, "DBG_PMODE" ), |
690 | PINCTRL_PIN(290, "CPU_TRSTB" ), |
691 | }; |
692 | |
693 | static const struct intel_padgroup [] = { |
694 | TGL_GPP(0, 0, 24, 0), /* GPP_A */ |
695 | TGL_GPP(1, 25, 44, 32), /* GPP_R */ |
696 | TGL_GPP(2, 45, 70, 64), /* GPP_B */ |
697 | TGL_GPP(3, 71, 78, 96), /* vGPIO_0 */ |
698 | }; |
699 | |
700 | static const struct intel_padgroup [] = { |
701 | TGL_GPP(0, 79, 104, 128), /* GPP_D */ |
702 | TGL_GPP(1, 105, 128, 160), /* GPP_C */ |
703 | TGL_GPP(2, 129, 136, 192), /* GPP_S */ |
704 | TGL_GPP(3, 137, 153, 224), /* GPP_G */ |
705 | TGL_GPP(4, 154, 180, 256), /* vGPIO */ |
706 | }; |
707 | |
708 | static const struct intel_padgroup [] = { |
709 | TGL_GPP(0, 181, 193, 288), /* GPP_E */ |
710 | TGL_GPP(1, 194, 217, 320), /* GPP_F */ |
711 | }; |
712 | |
713 | static const struct intel_padgroup [] = { |
714 | TGL_GPP(0, 218, 241, 352), /* GPP_H */ |
715 | TGL_GPP(1, 242, 251, 384), /* GPP_J */ |
716 | TGL_GPP(2, 252, 266, 416), /* GPP_K */ |
717 | }; |
718 | |
719 | static const struct intel_padgroup [] = { |
720 | TGL_GPP(0, 267, 281, 448), /* GPP_I */ |
721 | TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */ |
722 | }; |
723 | |
724 | static const struct intel_community tglh_communities[] = { |
725 | TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps), |
726 | TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps), |
727 | TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps), |
728 | TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps), |
729 | TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps), |
730 | }; |
731 | |
732 | static const struct intel_pinctrl_soc_data tglh_soc_data = { |
733 | .pins = tglh_pins, |
734 | .npins = ARRAY_SIZE(tglh_pins), |
735 | .communities = tglh_communities, |
736 | .ncommunities = ARRAY_SIZE(tglh_communities), |
737 | }; |
738 | |
739 | static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { |
740 | { "INT34C5" , (kernel_ulong_t)&tgllp_soc_data }, |
741 | { "INT34C6" , (kernel_ulong_t)&tglh_soc_data }, |
742 | { "INTC1055" , (kernel_ulong_t)&tgllp_soc_data }, |
743 | { } |
744 | }; |
745 | MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); |
746 | |
747 | static struct platform_driver tgl_pinctrl_driver = { |
748 | .probe = intel_pinctrl_probe_by_hid, |
749 | .driver = { |
750 | .name = "tigerlake-pinctrl" , |
751 | .acpi_match_table = tgl_pinctrl_acpi_match, |
752 | .pm = pm_sleep_ptr(&intel_pinctrl_pm_ops), |
753 | }, |
754 | }; |
755 | module_platform_driver(tgl_pinctrl_driver); |
756 | |
757 | MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>" ); |
758 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>" ); |
759 | MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver" ); |
760 | MODULE_LICENSE("GPL v2" ); |
761 | MODULE_IMPORT_NS(PINCTRL_INTEL); |
762 | |