1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Pin controller and GPIO driver for Amlogic Meson SoCs |
4 | * |
5 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> |
6 | */ |
7 | |
8 | /* |
9 | * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, |
10 | * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and |
11 | * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a |
12 | * variable number of pins. |
13 | * |
14 | * The AO bank is special because it belongs to the Always-On power |
15 | * domain which can't be powered off; the bank also uses a set of |
16 | * registers different from the other banks. |
17 | * |
18 | * For each pin controller there are 4 different register ranges that |
19 | * control the following properties of the pins: |
20 | * 1) pin muxing |
21 | * 2) pull enable/disable |
22 | * 3) pull up/down |
23 | * 4) GPIO direction, output value, input value |
24 | * |
25 | * In some cases the register ranges for pull enable and pull |
26 | * direction are the same and thus there are only 3 register ranges. |
27 | * |
28 | * Since Meson G12A SoC, the ao register ranges for gpio, pull enable |
29 | * and pull direction are the same, so there are only 2 register ranges. |
30 | * |
31 | * For the pull and GPIO configuration every bank uses a contiguous |
32 | * set of bits in the register sets described above; the same register |
33 | * can be shared by more banks with different offsets. |
34 | * |
35 | * In addition to this there are some registers shared between all |
36 | * banks that control the IRQ functionality. This feature is not |
37 | * supported at the moment by the driver. |
38 | */ |
39 | |
40 | #include <linux/device.h> |
41 | #include <linux/gpio/driver.h> |
42 | #include <linux/init.h> |
43 | #include <linux/io.h> |
44 | #include <linux/of.h> |
45 | #include <linux/of_address.h> |
46 | #include <linux/pinctrl/pinconf-generic.h> |
47 | #include <linux/pinctrl/pinconf.h> |
48 | #include <linux/pinctrl/pinctrl.h> |
49 | #include <linux/pinctrl/pinmux.h> |
50 | #include <linux/platform_device.h> |
51 | #include <linux/property.h> |
52 | #include <linux/regmap.h> |
53 | #include <linux/seq_file.h> |
54 | |
55 | #include "../core.h" |
56 | #include "../pinctrl-utils.h" |
57 | #include "pinctrl-meson.h" |
58 | |
59 | static const unsigned int meson_bit_strides[] = { |
60 | 1, 1, 1, 1, 1, 2, 1 |
61 | }; |
62 | |
63 | /** |
64 | * meson_get_bank() - find the bank containing a given pin |
65 | * |
66 | * @pc: the pinctrl instance |
67 | * @pin: the pin number |
68 | * @bank: the found bank |
69 | * |
70 | * Return: 0 on success, a negative value on error |
71 | */ |
72 | static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin, |
73 | struct meson_bank **bank) |
74 | { |
75 | int i; |
76 | |
77 | for (i = 0; i < pc->data->num_banks; i++) { |
78 | if (pin >= pc->data->banks[i].first && |
79 | pin <= pc->data->banks[i].last) { |
80 | *bank = &pc->data->banks[i]; |
81 | return 0; |
82 | } |
83 | } |
84 | |
85 | return -EINVAL; |
86 | } |
87 | |
88 | /** |
89 | * meson_calc_reg_and_bit() - calculate register and bit for a pin |
90 | * |
91 | * @bank: the bank containing the pin |
92 | * @pin: the pin number |
93 | * @reg_type: the type of register needed (pull-enable, pull, etc...) |
94 | * @reg: the computed register offset |
95 | * @bit: the computed bit |
96 | */ |
97 | static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, |
98 | enum meson_reg_type reg_type, |
99 | unsigned int *reg, unsigned int *bit) |
100 | { |
101 | struct meson_reg_desc *desc = &bank->regs[reg_type]; |
102 | |
103 | *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type]; |
104 | *reg = (desc->reg + (*bit / 32)) * 4; |
105 | *bit &= 0x1f; |
106 | } |
107 | |
108 | static int meson_get_groups_count(struct pinctrl_dev *pcdev) |
109 | { |
110 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev: pcdev); |
111 | |
112 | return pc->data->num_groups; |
113 | } |
114 | |
115 | static const char *meson_get_group_name(struct pinctrl_dev *pcdev, |
116 | unsigned selector) |
117 | { |
118 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev: pcdev); |
119 | |
120 | return pc->data->groups[selector].name; |
121 | } |
122 | |
123 | static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, |
124 | const unsigned **pins, unsigned *num_pins) |
125 | { |
126 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev: pcdev); |
127 | |
128 | *pins = pc->data->groups[selector].pins; |
129 | *num_pins = pc->data->groups[selector].num_pins; |
130 | |
131 | return 0; |
132 | } |
133 | |
134 | static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, |
135 | unsigned offset) |
136 | { |
137 | seq_printf(m: s, fmt: " %s" , dev_name(dev: pcdev->dev)); |
138 | } |
139 | |
140 | static const struct pinctrl_ops meson_pctrl_ops = { |
141 | .get_groups_count = meson_get_groups_count, |
142 | .get_group_name = meson_get_group_name, |
143 | .get_group_pins = meson_get_group_pins, |
144 | .dt_node_to_map = pinconf_generic_dt_node_to_map_all, |
145 | .dt_free_map = pinctrl_utils_free_map, |
146 | .pin_dbg_show = meson_pin_dbg_show, |
147 | }; |
148 | |
149 | int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) |
150 | { |
151 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev: pcdev); |
152 | |
153 | return pc->data->num_funcs; |
154 | } |
155 | EXPORT_SYMBOL_GPL(meson_pmx_get_funcs_count); |
156 | |
157 | const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, |
158 | unsigned selector) |
159 | { |
160 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev: pcdev); |
161 | |
162 | return pc->data->funcs[selector].name; |
163 | } |
164 | EXPORT_SYMBOL_GPL(meson_pmx_get_func_name); |
165 | |
166 | int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, |
167 | const char * const **groups, |
168 | unsigned * const num_groups) |
169 | { |
170 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev: pcdev); |
171 | |
172 | *groups = pc->data->funcs[selector].groups; |
173 | *num_groups = pc->data->funcs[selector].num_groups; |
174 | |
175 | return 0; |
176 | } |
177 | EXPORT_SYMBOL_GPL(meson_pmx_get_groups); |
178 | |
179 | static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc, |
180 | unsigned int pin, |
181 | unsigned int reg_type, |
182 | bool arg) |
183 | { |
184 | struct meson_bank *bank; |
185 | unsigned int reg, bit; |
186 | int ret; |
187 | |
188 | ret = meson_get_bank(pc, pin, bank: &bank); |
189 | if (ret) |
190 | return ret; |
191 | |
192 | meson_calc_reg_and_bit(bank, pin, reg_type, reg: ®, bit: &bit); |
193 | return regmap_update_bits(map: pc->reg_gpio, reg, BIT(bit), |
194 | val: arg ? BIT(bit) : 0); |
195 | } |
196 | |
197 | static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc, |
198 | unsigned int pin, |
199 | unsigned int reg_type) |
200 | { |
201 | struct meson_bank *bank; |
202 | unsigned int reg, bit, val; |
203 | int ret; |
204 | |
205 | ret = meson_get_bank(pc, pin, bank: &bank); |
206 | if (ret) |
207 | return ret; |
208 | |
209 | meson_calc_reg_and_bit(bank, pin, reg_type, reg: ®, bit: &bit); |
210 | ret = regmap_read(map: pc->reg_gpio, reg, val: &val); |
211 | if (ret) |
212 | return ret; |
213 | |
214 | return BIT(bit) & val ? 1 : 0; |
215 | } |
216 | |
217 | static int meson_pinconf_set_output(struct meson_pinctrl *pc, |
218 | unsigned int pin, |
219 | bool out) |
220 | { |
221 | return meson_pinconf_set_gpio_bit(pc, pin, reg_type: MESON_REG_DIR, arg: !out); |
222 | } |
223 | |
224 | static int meson_pinconf_get_output(struct meson_pinctrl *pc, |
225 | unsigned int pin) |
226 | { |
227 | int ret = meson_pinconf_get_gpio_bit(pc, pin, reg_type: MESON_REG_DIR); |
228 | |
229 | if (ret < 0) |
230 | return ret; |
231 | |
232 | return !ret; |
233 | } |
234 | |
235 | static int meson_pinconf_set_drive(struct meson_pinctrl *pc, |
236 | unsigned int pin, |
237 | bool high) |
238 | { |
239 | return meson_pinconf_set_gpio_bit(pc, pin, reg_type: MESON_REG_OUT, arg: high); |
240 | } |
241 | |
242 | static int meson_pinconf_get_drive(struct meson_pinctrl *pc, |
243 | unsigned int pin) |
244 | { |
245 | return meson_pinconf_get_gpio_bit(pc, pin, reg_type: MESON_REG_OUT); |
246 | } |
247 | |
248 | static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc, |
249 | unsigned int pin, |
250 | bool high) |
251 | { |
252 | int ret; |
253 | |
254 | ret = meson_pinconf_set_output(pc, pin, out: true); |
255 | if (ret) |
256 | return ret; |
257 | |
258 | return meson_pinconf_set_drive(pc, pin, high); |
259 | } |
260 | |
261 | static int meson_pinconf_disable_bias(struct meson_pinctrl *pc, |
262 | unsigned int pin) |
263 | { |
264 | struct meson_bank *bank; |
265 | unsigned int reg, bit = 0; |
266 | int ret; |
267 | |
268 | ret = meson_get_bank(pc, pin, bank: &bank); |
269 | if (ret) |
270 | return ret; |
271 | |
272 | meson_calc_reg_and_bit(bank, pin, reg_type: MESON_REG_PULLEN, reg: ®, bit: &bit); |
273 | ret = regmap_update_bits(map: pc->reg_pullen, reg, BIT(bit), val: 0); |
274 | if (ret) |
275 | return ret; |
276 | |
277 | return 0; |
278 | } |
279 | |
280 | static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin, |
281 | bool pull_up) |
282 | { |
283 | struct meson_bank *bank; |
284 | unsigned int reg, bit, val = 0; |
285 | int ret; |
286 | |
287 | ret = meson_get_bank(pc, pin, bank: &bank); |
288 | if (ret) |
289 | return ret; |
290 | |
291 | meson_calc_reg_and_bit(bank, pin, reg_type: MESON_REG_PULL, reg: ®, bit: &bit); |
292 | if (pull_up) |
293 | val = BIT(bit); |
294 | |
295 | ret = regmap_update_bits(map: pc->reg_pull, reg, BIT(bit), val); |
296 | if (ret) |
297 | return ret; |
298 | |
299 | meson_calc_reg_and_bit(bank, pin, reg_type: MESON_REG_PULLEN, reg: ®, bit: &bit); |
300 | ret = regmap_update_bits(map: pc->reg_pullen, reg, BIT(bit), BIT(bit)); |
301 | if (ret) |
302 | return ret; |
303 | |
304 | return 0; |
305 | } |
306 | |
307 | static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc, |
308 | unsigned int pin, |
309 | u16 drive_strength_ua) |
310 | { |
311 | struct meson_bank *bank; |
312 | unsigned int reg, bit, ds_val; |
313 | int ret; |
314 | |
315 | if (!pc->reg_ds) { |
316 | dev_err(pc->dev, "drive-strength not supported\n" ); |
317 | return -ENOTSUPP; |
318 | } |
319 | |
320 | ret = meson_get_bank(pc, pin, bank: &bank); |
321 | if (ret) |
322 | return ret; |
323 | |
324 | meson_calc_reg_and_bit(bank, pin, reg_type: MESON_REG_DS, reg: ®, bit: &bit); |
325 | |
326 | if (drive_strength_ua <= 500) { |
327 | ds_val = MESON_PINCONF_DRV_500UA; |
328 | } else if (drive_strength_ua <= 2500) { |
329 | ds_val = MESON_PINCONF_DRV_2500UA; |
330 | } else if (drive_strength_ua <= 3000) { |
331 | ds_val = MESON_PINCONF_DRV_3000UA; |
332 | } else if (drive_strength_ua <= 4000) { |
333 | ds_val = MESON_PINCONF_DRV_4000UA; |
334 | } else { |
335 | dev_warn_once(pc->dev, |
336 | "pin %u: invalid drive-strength : %d , default to 4mA\n" , |
337 | pin, drive_strength_ua); |
338 | ds_val = MESON_PINCONF_DRV_4000UA; |
339 | } |
340 | |
341 | ret = regmap_update_bits(map: pc->reg_ds, reg, mask: 0x3 << bit, val: ds_val << bit); |
342 | if (ret) |
343 | return ret; |
344 | |
345 | return 0; |
346 | } |
347 | |
348 | static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, |
349 | unsigned long *configs, unsigned num_configs) |
350 | { |
351 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev: pcdev); |
352 | enum pin_config_param param; |
353 | unsigned int arg = 0; |
354 | int i, ret; |
355 | |
356 | for (i = 0; i < num_configs; i++) { |
357 | param = pinconf_to_config_param(config: configs[i]); |
358 | |
359 | switch (param) { |
360 | case PIN_CONFIG_DRIVE_STRENGTH_UA: |
361 | case PIN_CONFIG_OUTPUT_ENABLE: |
362 | case PIN_CONFIG_OUTPUT: |
363 | arg = pinconf_to_config_argument(config: configs[i]); |
364 | break; |
365 | |
366 | default: |
367 | break; |
368 | } |
369 | |
370 | switch (param) { |
371 | case PIN_CONFIG_BIAS_DISABLE: |
372 | ret = meson_pinconf_disable_bias(pc, pin); |
373 | break; |
374 | case PIN_CONFIG_BIAS_PULL_UP: |
375 | ret = meson_pinconf_enable_bias(pc, pin, pull_up: true); |
376 | break; |
377 | case PIN_CONFIG_BIAS_PULL_DOWN: |
378 | ret = meson_pinconf_enable_bias(pc, pin, pull_up: false); |
379 | break; |
380 | case PIN_CONFIG_DRIVE_STRENGTH_UA: |
381 | ret = meson_pinconf_set_drive_strength(pc, pin, drive_strength_ua: arg); |
382 | break; |
383 | case PIN_CONFIG_OUTPUT_ENABLE: |
384 | ret = meson_pinconf_set_output(pc, pin, out: arg); |
385 | break; |
386 | case PIN_CONFIG_OUTPUT: |
387 | ret = meson_pinconf_set_output_drive(pc, pin, high: arg); |
388 | break; |
389 | default: |
390 | ret = -ENOTSUPP; |
391 | } |
392 | |
393 | if (ret) |
394 | return ret; |
395 | } |
396 | |
397 | return 0; |
398 | } |
399 | |
400 | static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) |
401 | { |
402 | struct meson_bank *bank; |
403 | unsigned int reg, bit, val; |
404 | int ret, conf; |
405 | |
406 | ret = meson_get_bank(pc, pin, bank: &bank); |
407 | if (ret) |
408 | return ret; |
409 | |
410 | meson_calc_reg_and_bit(bank, pin, reg_type: MESON_REG_PULLEN, reg: ®, bit: &bit); |
411 | |
412 | ret = regmap_read(map: pc->reg_pullen, reg, val: &val); |
413 | if (ret) |
414 | return ret; |
415 | |
416 | if (!(val & BIT(bit))) { |
417 | conf = PIN_CONFIG_BIAS_DISABLE; |
418 | } else { |
419 | meson_calc_reg_and_bit(bank, pin, reg_type: MESON_REG_PULL, reg: ®, bit: &bit); |
420 | |
421 | ret = regmap_read(map: pc->reg_pull, reg, val: &val); |
422 | if (ret) |
423 | return ret; |
424 | |
425 | if (val & BIT(bit)) |
426 | conf = PIN_CONFIG_BIAS_PULL_UP; |
427 | else |
428 | conf = PIN_CONFIG_BIAS_PULL_DOWN; |
429 | } |
430 | |
431 | return conf; |
432 | } |
433 | |
434 | static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc, |
435 | unsigned int pin, |
436 | u16 *drive_strength_ua) |
437 | { |
438 | struct meson_bank *bank; |
439 | unsigned int reg, bit; |
440 | unsigned int val; |
441 | int ret; |
442 | |
443 | if (!pc->reg_ds) |
444 | return -ENOTSUPP; |
445 | |
446 | ret = meson_get_bank(pc, pin, bank: &bank); |
447 | if (ret) |
448 | return ret; |
449 | |
450 | meson_calc_reg_and_bit(bank, pin, reg_type: MESON_REG_DS, reg: ®, bit: &bit); |
451 | |
452 | ret = regmap_read(map: pc->reg_ds, reg, val: &val); |
453 | if (ret) |
454 | return ret; |
455 | |
456 | switch ((val >> bit) & 0x3) { |
457 | case MESON_PINCONF_DRV_500UA: |
458 | *drive_strength_ua = 500; |
459 | break; |
460 | case MESON_PINCONF_DRV_2500UA: |
461 | *drive_strength_ua = 2500; |
462 | break; |
463 | case MESON_PINCONF_DRV_3000UA: |
464 | *drive_strength_ua = 3000; |
465 | break; |
466 | case MESON_PINCONF_DRV_4000UA: |
467 | *drive_strength_ua = 4000; |
468 | break; |
469 | default: |
470 | return -EINVAL; |
471 | } |
472 | |
473 | return 0; |
474 | } |
475 | |
476 | static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, |
477 | unsigned long *config) |
478 | { |
479 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev: pcdev); |
480 | enum pin_config_param param = pinconf_to_config_param(config: *config); |
481 | u16 arg; |
482 | int ret; |
483 | |
484 | switch (param) { |
485 | case PIN_CONFIG_BIAS_DISABLE: |
486 | case PIN_CONFIG_BIAS_PULL_DOWN: |
487 | case PIN_CONFIG_BIAS_PULL_UP: |
488 | if (meson_pinconf_get_pull(pc, pin) == param) |
489 | arg = 1; |
490 | else |
491 | return -EINVAL; |
492 | break; |
493 | case PIN_CONFIG_DRIVE_STRENGTH_UA: |
494 | ret = meson_pinconf_get_drive_strength(pc, pin, drive_strength_ua: &arg); |
495 | if (ret) |
496 | return ret; |
497 | break; |
498 | case PIN_CONFIG_OUTPUT_ENABLE: |
499 | ret = meson_pinconf_get_output(pc, pin); |
500 | if (ret <= 0) |
501 | return -EINVAL; |
502 | arg = 1; |
503 | break; |
504 | case PIN_CONFIG_OUTPUT: |
505 | ret = meson_pinconf_get_output(pc, pin); |
506 | if (ret <= 0) |
507 | return -EINVAL; |
508 | |
509 | ret = meson_pinconf_get_drive(pc, pin); |
510 | if (ret < 0) |
511 | return -EINVAL; |
512 | |
513 | arg = ret; |
514 | break; |
515 | |
516 | default: |
517 | return -ENOTSUPP; |
518 | } |
519 | |
520 | *config = pinconf_to_config_packed(param, argument: arg); |
521 | dev_dbg(pc->dev, "pinconf for pin %u is %lu\n" , pin, *config); |
522 | |
523 | return 0; |
524 | } |
525 | |
526 | static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, |
527 | unsigned int num_group, |
528 | unsigned long *configs, unsigned num_configs) |
529 | { |
530 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev: pcdev); |
531 | struct meson_pmx_group *group = &pc->data->groups[num_group]; |
532 | int i; |
533 | |
534 | dev_dbg(pc->dev, "set pinconf for group %s\n" , group->name); |
535 | |
536 | for (i = 0; i < group->num_pins; i++) { |
537 | meson_pinconf_set(pcdev, pin: group->pins[i], configs, |
538 | num_configs); |
539 | } |
540 | |
541 | return 0; |
542 | } |
543 | |
544 | static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, |
545 | unsigned int group, unsigned long *config) |
546 | { |
547 | return -ENOTSUPP; |
548 | } |
549 | |
550 | static const struct pinconf_ops meson_pinconf_ops = { |
551 | .pin_config_get = meson_pinconf_get, |
552 | .pin_config_set = meson_pinconf_set, |
553 | .pin_config_group_get = meson_pinconf_group_get, |
554 | .pin_config_group_set = meson_pinconf_group_set, |
555 | .is_generic = true, |
556 | }; |
557 | |
558 | static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio) |
559 | { |
560 | struct meson_pinctrl *pc = gpiochip_get_data(gc: chip); |
561 | int ret; |
562 | |
563 | ret = meson_pinconf_get_output(pc, pin: gpio); |
564 | if (ret < 0) |
565 | return ret; |
566 | |
567 | return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; |
568 | } |
569 | |
570 | static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
571 | { |
572 | return meson_pinconf_set_output(pc: gpiochip_get_data(gc: chip), pin: gpio, out: false); |
573 | } |
574 | |
575 | static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, |
576 | int value) |
577 | { |
578 | return meson_pinconf_set_output_drive(pc: gpiochip_get_data(gc: chip), |
579 | pin: gpio, high: value); |
580 | } |
581 | |
582 | static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) |
583 | { |
584 | meson_pinconf_set_drive(pc: gpiochip_get_data(gc: chip), pin: gpio, high: value); |
585 | } |
586 | |
587 | static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) |
588 | { |
589 | struct meson_pinctrl *pc = gpiochip_get_data(gc: chip); |
590 | unsigned int reg, bit, val; |
591 | struct meson_bank *bank; |
592 | int ret; |
593 | |
594 | ret = meson_get_bank(pc, pin: gpio, bank: &bank); |
595 | if (ret) |
596 | return ret; |
597 | |
598 | meson_calc_reg_and_bit(bank, pin: gpio, reg_type: MESON_REG_IN, reg: ®, bit: &bit); |
599 | regmap_read(map: pc->reg_gpio, reg, val: &val); |
600 | |
601 | return !!(val & BIT(bit)); |
602 | } |
603 | |
604 | static int meson_gpiolib_register(struct meson_pinctrl *pc) |
605 | { |
606 | int ret; |
607 | |
608 | pc->chip.label = pc->data->name; |
609 | pc->chip.parent = pc->dev; |
610 | pc->chip.fwnode = pc->fwnode; |
611 | pc->chip.request = gpiochip_generic_request; |
612 | pc->chip.free = gpiochip_generic_free; |
613 | pc->chip.set_config = gpiochip_generic_config; |
614 | pc->chip.get_direction = meson_gpio_get_direction; |
615 | pc->chip.direction_input = meson_gpio_direction_input; |
616 | pc->chip.direction_output = meson_gpio_direction_output; |
617 | pc->chip.get = meson_gpio_get; |
618 | pc->chip.set = meson_gpio_set; |
619 | pc->chip.base = -1; |
620 | pc->chip.ngpio = pc->data->num_pins; |
621 | pc->chip.can_sleep = false; |
622 | |
623 | ret = gpiochip_add_data(&pc->chip, pc); |
624 | if (ret) { |
625 | dev_err(pc->dev, "can't add gpio chip %s\n" , |
626 | pc->data->name); |
627 | return ret; |
628 | } |
629 | |
630 | return 0; |
631 | } |
632 | |
633 | static struct regmap_config meson_regmap_config = { |
634 | .reg_bits = 32, |
635 | .val_bits = 32, |
636 | .reg_stride = 4, |
637 | }; |
638 | |
639 | static struct regmap *meson_map_resource(struct meson_pinctrl *pc, |
640 | struct device_node *node, char *name) |
641 | { |
642 | struct resource res; |
643 | void __iomem *base; |
644 | int i; |
645 | |
646 | i = of_property_match_string(np: node, propname: "reg-names" , string: name); |
647 | if (of_address_to_resource(dev: node, index: i, r: &res)) |
648 | return NULL; |
649 | |
650 | base = devm_ioremap_resource(dev: pc->dev, res: &res); |
651 | if (IS_ERR(ptr: base)) |
652 | return ERR_CAST(ptr: base); |
653 | |
654 | meson_regmap_config.max_register = resource_size(res: &res) - 4; |
655 | meson_regmap_config.name = devm_kasprintf(dev: pc->dev, GFP_KERNEL, |
656 | fmt: "%pOFn-%s" , node, |
657 | name); |
658 | if (!meson_regmap_config.name) |
659 | return ERR_PTR(error: -ENOMEM); |
660 | |
661 | return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); |
662 | } |
663 | |
664 | static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc) |
665 | { |
666 | struct device_node *gpio_np; |
667 | unsigned int chips; |
668 | |
669 | chips = gpiochip_node_count(dev: pc->dev); |
670 | if (!chips) { |
671 | dev_err(pc->dev, "no gpio node found\n" ); |
672 | return -EINVAL; |
673 | } |
674 | if (chips > 1) { |
675 | dev_err(pc->dev, "multiple gpio nodes\n" ); |
676 | return -EINVAL; |
677 | } |
678 | |
679 | pc->fwnode = gpiochip_node_get_first(dev: pc->dev); |
680 | gpio_np = to_of_node(pc->fwnode); |
681 | |
682 | pc->reg_mux = meson_map_resource(pc, node: gpio_np, name: "mux" ); |
683 | if (IS_ERR_OR_NULL(ptr: pc->reg_mux)) { |
684 | dev_err(pc->dev, "mux registers not found\n" ); |
685 | return pc->reg_mux ? PTR_ERR(ptr: pc->reg_mux) : -ENOENT; |
686 | } |
687 | |
688 | pc->reg_gpio = meson_map_resource(pc, node: gpio_np, name: "gpio" ); |
689 | if (IS_ERR_OR_NULL(ptr: pc->reg_gpio)) { |
690 | dev_err(pc->dev, "gpio registers not found\n" ); |
691 | return pc->reg_gpio ? PTR_ERR(ptr: pc->reg_gpio) : -ENOENT; |
692 | } |
693 | |
694 | pc->reg_pull = meson_map_resource(pc, node: gpio_np, name: "pull" ); |
695 | if (IS_ERR(ptr: pc->reg_pull)) |
696 | pc->reg_pull = NULL; |
697 | |
698 | pc->reg_pullen = meson_map_resource(pc, node: gpio_np, name: "pull-enable" ); |
699 | if (IS_ERR(ptr: pc->reg_pullen)) |
700 | pc->reg_pullen = NULL; |
701 | |
702 | pc->reg_ds = meson_map_resource(pc, node: gpio_np, name: "ds" ); |
703 | if (IS_ERR(ptr: pc->reg_ds)) { |
704 | dev_dbg(pc->dev, "ds registers not found - skipping\n" ); |
705 | pc->reg_ds = NULL; |
706 | } |
707 | |
708 | if (pc->data->parse_dt) |
709 | return pc->data->parse_dt(pc); |
710 | |
711 | return 0; |
712 | } |
713 | |
714 | int (struct meson_pinctrl *pc) |
715 | { |
716 | if (!pc->reg_pull) |
717 | return -EINVAL; |
718 | |
719 | pc->reg_pullen = pc->reg_pull; |
720 | |
721 | return 0; |
722 | } |
723 | EXPORT_SYMBOL_GPL(meson8_aobus_parse_dt_extra); |
724 | |
725 | int (struct meson_pinctrl *pc) |
726 | { |
727 | pc->reg_pull = pc->reg_gpio; |
728 | pc->reg_pullen = pc->reg_gpio; |
729 | pc->reg_ds = pc->reg_gpio; |
730 | |
731 | return 0; |
732 | } |
733 | EXPORT_SYMBOL_GPL(meson_a1_parse_dt_extra); |
734 | |
735 | int meson_pinctrl_probe(struct platform_device *pdev) |
736 | { |
737 | struct device *dev = &pdev->dev; |
738 | struct meson_pinctrl *pc; |
739 | int ret; |
740 | |
741 | pc = devm_kzalloc(dev, size: sizeof(struct meson_pinctrl), GFP_KERNEL); |
742 | if (!pc) |
743 | return -ENOMEM; |
744 | |
745 | pc->dev = dev; |
746 | pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); |
747 | |
748 | ret = meson_pinctrl_parse_dt(pc); |
749 | if (ret) |
750 | return ret; |
751 | |
752 | pc->desc.name = "pinctrl-meson" ; |
753 | pc->desc.owner = THIS_MODULE; |
754 | pc->desc.pctlops = &meson_pctrl_ops; |
755 | pc->desc.pmxops = pc->data->pmx_ops; |
756 | pc->desc.confops = &meson_pinconf_ops; |
757 | pc->desc.pins = pc->data->pins; |
758 | pc->desc.npins = pc->data->num_pins; |
759 | |
760 | pc->pcdev = devm_pinctrl_register(dev: pc->dev, pctldesc: &pc->desc, driver_data: pc); |
761 | if (IS_ERR(ptr: pc->pcdev)) { |
762 | dev_err(pc->dev, "can't register pinctrl device" ); |
763 | return PTR_ERR(ptr: pc->pcdev); |
764 | } |
765 | |
766 | return meson_gpiolib_register(pc); |
767 | } |
768 | EXPORT_SYMBOL_GPL(meson_pinctrl_probe); |
769 | |
770 | MODULE_LICENSE("GPL v2" ); |
771 | |