1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * at91 pinctrl driver based on at91 pinmux core |
4 | * |
5 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
6 | */ |
7 | |
8 | #include <linux/clk.h> |
9 | #include <linux/err.h> |
10 | #include <linux/gpio/driver.h> |
11 | #include <linux/init.h> |
12 | #include <linux/interrupt.h> |
13 | #include <linux/io.h> |
14 | #include <linux/of.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/pm.h> |
17 | #include <linux/property.h> |
18 | #include <linux/seq_file.h> |
19 | #include <linux/slab.h> |
20 | #include <linux/string_helpers.h> |
21 | |
22 | /* Since we request GPIOs from ourself */ |
23 | #include <linux/pinctrl/consumer.h> |
24 | #include <linux/pinctrl/machine.h> |
25 | #include <linux/pinctrl/pinconf.h> |
26 | #include <linux/pinctrl/pinctrl.h> |
27 | #include <linux/pinctrl/pinmux.h> |
28 | |
29 | #include "pinctrl-at91.h" |
30 | #include "core.h" |
31 | |
32 | #define MAX_GPIO_BANKS 5 |
33 | #define MAX_NB_GPIO_PER_BANK 32 |
34 | |
35 | struct at91_pinctrl_mux_ops; |
36 | |
37 | /** |
38 | * struct at91_gpio_chip: at91 gpio chip |
39 | * @chip: gpio chip |
40 | * @range: gpio range |
41 | * @next: bank sharing same clock |
42 | * @pioc_hwirq: PIO bank interrupt identifier on AIC |
43 | * @pioc_virq: PIO bank Linux virtual interrupt |
44 | * @regbase: PIO bank virtual address |
45 | * @clock: associated clock |
46 | * @ops: at91 pinctrl mux ops |
47 | * @wakeups: wakeup interrupts |
48 | * @backups: interrupts disabled in suspend |
49 | * @id: gpio chip identifier |
50 | */ |
51 | struct at91_gpio_chip { |
52 | struct gpio_chip chip; |
53 | struct pinctrl_gpio_range range; |
54 | struct at91_gpio_chip *next; |
55 | int pioc_hwirq; |
56 | int pioc_virq; |
57 | void __iomem *regbase; |
58 | struct clk *clock; |
59 | const struct at91_pinctrl_mux_ops *ops; |
60 | u32 wakeups; |
61 | u32 backups; |
62 | u32 id; |
63 | }; |
64 | |
65 | static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; |
66 | |
67 | static int gpio_banks; |
68 | |
69 | #define PULL_UP (1 << 0) |
70 | #define MULTI_DRIVE (1 << 1) |
71 | #define DEGLITCH (1 << 2) |
72 | #define PULL_DOWN (1 << 3) |
73 | #define DIS_SCHMIT (1 << 4) |
74 | #define DRIVE_STRENGTH_SHIFT 5 |
75 | #define DRIVE_STRENGTH_MASK 0x3 |
76 | #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) |
77 | #define OUTPUT (1 << 7) |
78 | #define OUTPUT_VAL_SHIFT 8 |
79 | #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT) |
80 | #define SLEWRATE_SHIFT 9 |
81 | #define SLEWRATE_MASK 0x1 |
82 | #define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT) |
83 | #define DEBOUNCE (1 << 16) |
84 | #define DEBOUNCE_VAL_SHIFT 17 |
85 | #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) |
86 | |
87 | /* |
88 | * These defines will translated the dt binding settings to our internal |
89 | * settings. They are not necessarily the same value as the register setting. |
90 | * The actual drive strength current of low, medium and high must be looked up |
91 | * from the corresponding device datasheet. This value is different for pins |
92 | * that are even in the same banks. It is also dependent on VCC. |
93 | * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive |
94 | * strength when there is no dt config for it. |
95 | */ |
96 | enum drive_strength_bit { |
97 | DRIVE_STRENGTH_BIT_DEF, |
98 | DRIVE_STRENGTH_BIT_LOW, |
99 | DRIVE_STRENGTH_BIT_MED, |
100 | DRIVE_STRENGTH_BIT_HI, |
101 | }; |
102 | |
103 | #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \ |
104 | DRIVE_STRENGTH_SHIFT) |
105 | |
106 | enum slewrate_bit { |
107 | SLEWRATE_BIT_ENA, |
108 | SLEWRATE_BIT_DIS, |
109 | }; |
110 | |
111 | #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT) |
112 | |
113 | /** |
114 | * struct at91_pmx_func - describes AT91 pinmux functions |
115 | * @name: the name of this specific function |
116 | * @groups: corresponding pin groups |
117 | * @ngroups: the number of groups |
118 | */ |
119 | struct at91_pmx_func { |
120 | const char *name; |
121 | const char **groups; |
122 | unsigned ngroups; |
123 | }; |
124 | |
125 | enum at91_mux { |
126 | AT91_MUX_GPIO = 0, |
127 | AT91_MUX_PERIPH_A = 1, |
128 | AT91_MUX_PERIPH_B = 2, |
129 | AT91_MUX_PERIPH_C = 3, |
130 | AT91_MUX_PERIPH_D = 4, |
131 | }; |
132 | |
133 | /** |
134 | * struct at91_pmx_pin - describes an At91 pin mux |
135 | * @bank: the bank of the pin |
136 | * @pin: the pin number in the @bank |
137 | * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. |
138 | * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... |
139 | */ |
140 | struct at91_pmx_pin { |
141 | uint32_t bank; |
142 | uint32_t pin; |
143 | enum at91_mux mux; |
144 | unsigned long conf; |
145 | }; |
146 | |
147 | /** |
148 | * struct at91_pin_group - describes an At91 pin group |
149 | * @name: the name of this specific pin group |
150 | * @pins_conf: the mux mode for each pin in this group. The size of this |
151 | * array is the same as pins. |
152 | * @pins: an array of discrete physical pins used in this group, taken |
153 | * from the driver-local pin enumeration space |
154 | * @npins: the number of pins in this group array, i.e. the number of |
155 | * elements in .pins so we can iterate over that array |
156 | */ |
157 | struct at91_pin_group { |
158 | const char *name; |
159 | struct at91_pmx_pin *pins_conf; |
160 | unsigned int *pins; |
161 | unsigned npins; |
162 | }; |
163 | |
164 | /** |
165 | * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group |
166 | * on new IP with support for periph C and D the way to mux in |
167 | * periph A and B has changed |
168 | * So provide the right call back |
169 | * if not present means the IP does not support it |
170 | * @get_periph: return the periph mode configured |
171 | * @mux_A_periph: mux as periph A |
172 | * @mux_B_periph: mux as periph B |
173 | * @mux_C_periph: mux as periph C |
174 | * @mux_D_periph: mux as periph D |
175 | * @get_deglitch: get deglitch status |
176 | * @set_deglitch: enable/disable deglitch |
177 | * @get_debounce: get debounce status |
178 | * @set_debounce: enable/disable debounce |
179 | * @get_pulldown: get pulldown status |
180 | * @set_pulldown: enable/disable pulldown |
181 | * @get_schmitt_trig: get schmitt trigger status |
182 | * @disable_schmitt_trig: disable schmitt trigger |
183 | * @get_drivestrength: get driver strength |
184 | * @set_drivestrength: set driver strength |
185 | * @get_slewrate: get slew rate |
186 | * @set_slewrate: set slew rate |
187 | * @irq_type: return irq type |
188 | */ |
189 | struct at91_pinctrl_mux_ops { |
190 | enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); |
191 | void (*mux_A_periph)(void __iomem *pio, unsigned mask); |
192 | void (*mux_B_periph)(void __iomem *pio, unsigned mask); |
193 | void (*mux_C_periph)(void __iomem *pio, unsigned mask); |
194 | void (*mux_D_periph)(void __iomem *pio, unsigned mask); |
195 | bool (*get_deglitch)(void __iomem *pio, unsigned pin); |
196 | void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); |
197 | bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); |
198 | void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); |
199 | bool (*get_pulldown)(void __iomem *pio, unsigned pin); |
200 | void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); |
201 | bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); |
202 | void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); |
203 | unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin); |
204 | void (*set_drivestrength)(void __iomem *pio, unsigned pin, |
205 | u32 strength); |
206 | unsigned (*get_slewrate)(void __iomem *pio, unsigned pin); |
207 | void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate); |
208 | /* irq */ |
209 | int (*irq_type)(struct irq_data *d, unsigned type); |
210 | }; |
211 | |
212 | static int gpio_irq_type(struct irq_data *d, unsigned type); |
213 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type); |
214 | |
215 | struct at91_pinctrl { |
216 | struct device *dev; |
217 | struct pinctrl_dev *pctl; |
218 | |
219 | int nactive_banks; |
220 | |
221 | uint32_t *mux_mask; |
222 | int nmux; |
223 | |
224 | struct at91_pmx_func *functions; |
225 | int nfunctions; |
226 | |
227 | struct at91_pin_group *groups; |
228 | int ngroups; |
229 | |
230 | const struct at91_pinctrl_mux_ops *ops; |
231 | }; |
232 | |
233 | static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name( |
234 | const struct at91_pinctrl *info, |
235 | const char *name) |
236 | { |
237 | const struct at91_pin_group *grp = NULL; |
238 | int i; |
239 | |
240 | for (i = 0; i < info->ngroups; i++) { |
241 | if (strcmp(info->groups[i].name, name)) |
242 | continue; |
243 | |
244 | grp = &info->groups[i]; |
245 | dev_dbg(info->dev, "%s: %d 0:%d\n" , name, grp->npins, grp->pins[0]); |
246 | break; |
247 | } |
248 | |
249 | return grp; |
250 | } |
251 | |
252 | static int at91_get_groups_count(struct pinctrl_dev *pctldev) |
253 | { |
254 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
255 | |
256 | return info->ngroups; |
257 | } |
258 | |
259 | static const char *at91_get_group_name(struct pinctrl_dev *pctldev, |
260 | unsigned selector) |
261 | { |
262 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
263 | |
264 | return info->groups[selector].name; |
265 | } |
266 | |
267 | static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, |
268 | const unsigned **pins, |
269 | unsigned *npins) |
270 | { |
271 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
272 | |
273 | if (selector >= info->ngroups) |
274 | return -EINVAL; |
275 | |
276 | *pins = info->groups[selector].pins; |
277 | *npins = info->groups[selector].npins; |
278 | |
279 | return 0; |
280 | } |
281 | |
282 | static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
283 | unsigned offset) |
284 | { |
285 | seq_printf(m: s, fmt: "%s" , dev_name(dev: pctldev->dev)); |
286 | } |
287 | |
288 | static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, |
289 | struct device_node *np, |
290 | struct pinctrl_map **map, unsigned *num_maps) |
291 | { |
292 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
293 | const struct at91_pin_group *grp; |
294 | struct pinctrl_map *new_map; |
295 | struct device_node *parent; |
296 | int map_num = 1; |
297 | int i; |
298 | |
299 | /* |
300 | * first find the group of this node and check if we need to create |
301 | * config maps for pins |
302 | */ |
303 | grp = at91_pinctrl_find_group_by_name(info, name: np->name); |
304 | if (!grp) { |
305 | dev_err(info->dev, "unable to find group for node %pOFn\n" , |
306 | np); |
307 | return -EINVAL; |
308 | } |
309 | |
310 | map_num += grp->npins; |
311 | new_map = devm_kcalloc(dev: pctldev->dev, n: map_num, size: sizeof(*new_map), |
312 | GFP_KERNEL); |
313 | if (!new_map) |
314 | return -ENOMEM; |
315 | |
316 | *map = new_map; |
317 | *num_maps = map_num; |
318 | |
319 | /* create mux map */ |
320 | parent = of_get_parent(node: np); |
321 | if (!parent) { |
322 | devm_kfree(dev: pctldev->dev, p: new_map); |
323 | return -EINVAL; |
324 | } |
325 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; |
326 | new_map[0].data.mux.function = parent->name; |
327 | new_map[0].data.mux.group = np->name; |
328 | of_node_put(node: parent); |
329 | |
330 | /* create config map */ |
331 | new_map++; |
332 | for (i = 0; i < grp->npins; i++) { |
333 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; |
334 | new_map[i].data.configs.group_or_pin = |
335 | pin_get_name(pctldev, pin: grp->pins[i]); |
336 | new_map[i].data.configs.configs = &grp->pins_conf[i].conf; |
337 | new_map[i].data.configs.num_configs = 1; |
338 | } |
339 | |
340 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n" , |
341 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); |
342 | |
343 | return 0; |
344 | } |
345 | |
346 | static void at91_dt_free_map(struct pinctrl_dev *pctldev, |
347 | struct pinctrl_map *map, unsigned num_maps) |
348 | { |
349 | } |
350 | |
351 | static const struct pinctrl_ops at91_pctrl_ops = { |
352 | .get_groups_count = at91_get_groups_count, |
353 | .get_group_name = at91_get_group_name, |
354 | .get_group_pins = at91_get_group_pins, |
355 | .pin_dbg_show = at91_pin_dbg_show, |
356 | .dt_node_to_map = at91_dt_node_to_map, |
357 | .dt_free_map = at91_dt_free_map, |
358 | }; |
359 | |
360 | static void __iomem *pin_to_controller(struct at91_pinctrl *info, |
361 | unsigned int bank) |
362 | { |
363 | if (!gpio_chips[bank]) |
364 | return NULL; |
365 | |
366 | return gpio_chips[bank]->regbase; |
367 | } |
368 | |
369 | static inline int pin_to_bank(unsigned pin) |
370 | { |
371 | return pin /= MAX_NB_GPIO_PER_BANK; |
372 | } |
373 | |
374 | static unsigned pin_to_mask(unsigned int pin) |
375 | { |
376 | return 1 << pin; |
377 | } |
378 | |
379 | static unsigned two_bit_pin_value_shift_amount(unsigned int pin) |
380 | { |
381 | /* return the shift value for a pin for "two bit" per pin registers, |
382 | * i.e. drive strength */ |
383 | return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) |
384 | ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); |
385 | } |
386 | |
387 | static unsigned sama5d3_get_drive_register(unsigned int pin) |
388 | { |
389 | /* drive strength is split between two registers |
390 | * with two bits per pin */ |
391 | return (pin >= MAX_NB_GPIO_PER_BANK/2) |
392 | ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1; |
393 | } |
394 | |
395 | static unsigned at91sam9x5_get_drive_register(unsigned int pin) |
396 | { |
397 | /* drive strength is split between two registers |
398 | * with two bits per pin */ |
399 | return (pin >= MAX_NB_GPIO_PER_BANK/2) |
400 | ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1; |
401 | } |
402 | |
403 | static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) |
404 | { |
405 | writel_relaxed(mask, pio + PIO_IDR); |
406 | } |
407 | |
408 | static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) |
409 | { |
410 | return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); |
411 | } |
412 | |
413 | static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) |
414 | { |
415 | if (on) |
416 | writel_relaxed(mask, pio + PIO_PPDDR); |
417 | |
418 | writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); |
419 | } |
420 | |
421 | static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val) |
422 | { |
423 | *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1; |
424 | return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1; |
425 | } |
426 | |
427 | static void at91_mux_set_output(void __iomem *pio, unsigned int mask, |
428 | bool is_on, bool val) |
429 | { |
430 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); |
431 | writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR)); |
432 | } |
433 | |
434 | static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) |
435 | { |
436 | return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; |
437 | } |
438 | |
439 | static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) |
440 | { |
441 | writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); |
442 | } |
443 | |
444 | static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) |
445 | { |
446 | writel_relaxed(mask, pio + PIO_ASR); |
447 | } |
448 | |
449 | static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) |
450 | { |
451 | writel_relaxed(mask, pio + PIO_BSR); |
452 | } |
453 | |
454 | static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) |
455 | { |
456 | |
457 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, |
458 | pio + PIO_ABCDSR1); |
459 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, |
460 | pio + PIO_ABCDSR2); |
461 | } |
462 | |
463 | static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) |
464 | { |
465 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, |
466 | pio + PIO_ABCDSR1); |
467 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, |
468 | pio + PIO_ABCDSR2); |
469 | } |
470 | |
471 | static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) |
472 | { |
473 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); |
474 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); |
475 | } |
476 | |
477 | static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) |
478 | { |
479 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); |
480 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); |
481 | } |
482 | |
483 | static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) |
484 | { |
485 | unsigned select; |
486 | |
487 | if (readl_relaxed(pio + PIO_PSR) & mask) |
488 | return AT91_MUX_GPIO; |
489 | |
490 | select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); |
491 | select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); |
492 | |
493 | return select + 1; |
494 | } |
495 | |
496 | static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) |
497 | { |
498 | unsigned select; |
499 | |
500 | if (readl_relaxed(pio + PIO_PSR) & mask) |
501 | return AT91_MUX_GPIO; |
502 | |
503 | select = readl_relaxed(pio + PIO_ABSR) & mask; |
504 | |
505 | return select + 1; |
506 | } |
507 | |
508 | static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) |
509 | { |
510 | return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; |
511 | } |
512 | |
513 | static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) |
514 | { |
515 | writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); |
516 | } |
517 | |
518 | static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) |
519 | { |
520 | if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) |
521 | return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); |
522 | |
523 | return false; |
524 | } |
525 | |
526 | static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) |
527 | { |
528 | if (is_on) |
529 | writel_relaxed(mask, pio + PIO_IFSCDR); |
530 | at91_mux_set_deglitch(pio, mask, is_on); |
531 | } |
532 | |
533 | static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) |
534 | { |
535 | *div = readl_relaxed(pio + PIO_SCDR); |
536 | |
537 | return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && |
538 | ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); |
539 | } |
540 | |
541 | static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, |
542 | bool is_on, u32 div) |
543 | { |
544 | if (is_on) { |
545 | writel_relaxed(mask, pio + PIO_IFSCER); |
546 | writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR); |
547 | writel_relaxed(mask, pio + PIO_IFER); |
548 | } else |
549 | writel_relaxed(mask, pio + PIO_IFSCDR); |
550 | } |
551 | |
552 | static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) |
553 | { |
554 | return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); |
555 | } |
556 | |
557 | static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) |
558 | { |
559 | if (is_on) |
560 | writel_relaxed(mask, pio + PIO_PUDR); |
561 | |
562 | writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); |
563 | } |
564 | |
565 | static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) |
566 | { |
567 | writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); |
568 | } |
569 | |
570 | static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) |
571 | { |
572 | return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; |
573 | } |
574 | |
575 | static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) |
576 | { |
577 | unsigned tmp = readl_relaxed(reg); |
578 | |
579 | tmp = tmp >> two_bit_pin_value_shift_amount(pin); |
580 | |
581 | return tmp & DRIVE_STRENGTH_MASK; |
582 | } |
583 | |
584 | static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, |
585 | unsigned pin) |
586 | { |
587 | unsigned tmp = read_drive_strength(reg: pio + |
588 | sama5d3_get_drive_register(pin), pin); |
589 | |
590 | /* SAMA5 strength is 1:1 with our defines, |
591 | * except 0 is equivalent to low per datasheet */ |
592 | if (!tmp) |
593 | tmp = DRIVE_STRENGTH_BIT_MSK(LOW); |
594 | |
595 | return tmp; |
596 | } |
597 | |
598 | static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, |
599 | unsigned pin) |
600 | { |
601 | unsigned tmp = read_drive_strength(reg: pio + |
602 | at91sam9x5_get_drive_register(pin), pin); |
603 | |
604 | /* strength is inverse in SAM9x5s hardware with the pinctrl defines |
605 | * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */ |
606 | tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp; |
607 | |
608 | return tmp; |
609 | } |
610 | |
611 | static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio, |
612 | unsigned pin) |
613 | { |
614 | unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); |
615 | |
616 | if (tmp & BIT(pin)) |
617 | return DRIVE_STRENGTH_BIT_HI; |
618 | |
619 | return DRIVE_STRENGTH_BIT_LOW; |
620 | } |
621 | |
622 | static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin) |
623 | { |
624 | unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); |
625 | |
626 | if ((tmp & BIT(pin))) |
627 | return SLEWRATE_BIT_ENA; |
628 | |
629 | return SLEWRATE_BIT_DIS; |
630 | } |
631 | |
632 | static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) |
633 | { |
634 | unsigned tmp = readl_relaxed(reg); |
635 | unsigned shift = two_bit_pin_value_shift_amount(pin); |
636 | |
637 | tmp &= ~(DRIVE_STRENGTH_MASK << shift); |
638 | tmp |= strength << shift; |
639 | |
640 | writel_relaxed(tmp, reg); |
641 | } |
642 | |
643 | static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, |
644 | u32 setting) |
645 | { |
646 | /* do nothing if setting is zero */ |
647 | if (!setting) |
648 | return; |
649 | |
650 | /* strength is 1 to 1 with setting for SAMA5 */ |
651 | set_drive_strength(reg: pio + sama5d3_get_drive_register(pin), pin, strength: setting); |
652 | } |
653 | |
654 | static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, |
655 | u32 setting) |
656 | { |
657 | /* do nothing if setting is zero */ |
658 | if (!setting) |
659 | return; |
660 | |
661 | /* strength is inverse on SAM9x5s with our defines |
662 | * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ |
663 | setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting; |
664 | |
665 | set_drive_strength(reg: pio + at91sam9x5_get_drive_register(pin), pin, |
666 | strength: setting); |
667 | } |
668 | |
669 | static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin, |
670 | u32 setting) |
671 | { |
672 | unsigned int tmp; |
673 | |
674 | if (setting <= DRIVE_STRENGTH_BIT_DEF || |
675 | setting == DRIVE_STRENGTH_BIT_MED || |
676 | setting > DRIVE_STRENGTH_BIT_HI) |
677 | return; |
678 | |
679 | tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); |
680 | |
681 | /* Strength is 0: low, 1: hi */ |
682 | if (setting == DRIVE_STRENGTH_BIT_LOW) |
683 | tmp &= ~BIT(pin); |
684 | else |
685 | tmp |= BIT(pin); |
686 | |
687 | writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1); |
688 | } |
689 | |
690 | static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, |
691 | u32 setting) |
692 | { |
693 | unsigned int tmp; |
694 | |
695 | if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS) |
696 | return; |
697 | |
698 | tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); |
699 | |
700 | if (setting == SLEWRATE_BIT_DIS) |
701 | tmp &= ~BIT(pin); |
702 | else |
703 | tmp |= BIT(pin); |
704 | |
705 | writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR); |
706 | } |
707 | |
708 | static const struct at91_pinctrl_mux_ops at91rm9200_ops = { |
709 | .get_periph = at91_mux_get_periph, |
710 | .mux_A_periph = at91_mux_set_A_periph, |
711 | .mux_B_periph = at91_mux_set_B_periph, |
712 | .get_deglitch = at91_mux_get_deglitch, |
713 | .set_deglitch = at91_mux_set_deglitch, |
714 | .irq_type = gpio_irq_type, |
715 | }; |
716 | |
717 | static const struct at91_pinctrl_mux_ops at91sam9x5_ops = { |
718 | .get_periph = at91_mux_pio3_get_periph, |
719 | .mux_A_periph = at91_mux_pio3_set_A_periph, |
720 | .mux_B_periph = at91_mux_pio3_set_B_periph, |
721 | .mux_C_periph = at91_mux_pio3_set_C_periph, |
722 | .mux_D_periph = at91_mux_pio3_set_D_periph, |
723 | .get_deglitch = at91_mux_pio3_get_deglitch, |
724 | .set_deglitch = at91_mux_pio3_set_deglitch, |
725 | .get_debounce = at91_mux_pio3_get_debounce, |
726 | .set_debounce = at91_mux_pio3_set_debounce, |
727 | .get_pulldown = at91_mux_pio3_get_pulldown, |
728 | .set_pulldown = at91_mux_pio3_set_pulldown, |
729 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, |
730 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, |
731 | .get_drivestrength = at91_mux_sam9x5_get_drivestrength, |
732 | .set_drivestrength = at91_mux_sam9x5_set_drivestrength, |
733 | .irq_type = alt_gpio_irq_type, |
734 | }; |
735 | |
736 | static const struct at91_pinctrl_mux_ops sam9x60_ops = { |
737 | .get_periph = at91_mux_pio3_get_periph, |
738 | .mux_A_periph = at91_mux_pio3_set_A_periph, |
739 | .mux_B_periph = at91_mux_pio3_set_B_periph, |
740 | .mux_C_periph = at91_mux_pio3_set_C_periph, |
741 | .mux_D_periph = at91_mux_pio3_set_D_periph, |
742 | .get_deglitch = at91_mux_pio3_get_deglitch, |
743 | .set_deglitch = at91_mux_pio3_set_deglitch, |
744 | .get_debounce = at91_mux_pio3_get_debounce, |
745 | .set_debounce = at91_mux_pio3_set_debounce, |
746 | .get_pulldown = at91_mux_pio3_get_pulldown, |
747 | .set_pulldown = at91_mux_pio3_set_pulldown, |
748 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, |
749 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, |
750 | .get_drivestrength = at91_mux_sam9x60_get_drivestrength, |
751 | .set_drivestrength = at91_mux_sam9x60_set_drivestrength, |
752 | .get_slewrate = at91_mux_sam9x60_get_slewrate, |
753 | .set_slewrate = at91_mux_sam9x60_set_slewrate, |
754 | .irq_type = alt_gpio_irq_type, |
755 | }; |
756 | |
757 | static const struct at91_pinctrl_mux_ops sama5d3_ops = { |
758 | .get_periph = at91_mux_pio3_get_periph, |
759 | .mux_A_periph = at91_mux_pio3_set_A_periph, |
760 | .mux_B_periph = at91_mux_pio3_set_B_periph, |
761 | .mux_C_periph = at91_mux_pio3_set_C_periph, |
762 | .mux_D_periph = at91_mux_pio3_set_D_periph, |
763 | .get_deglitch = at91_mux_pio3_get_deglitch, |
764 | .set_deglitch = at91_mux_pio3_set_deglitch, |
765 | .get_debounce = at91_mux_pio3_get_debounce, |
766 | .set_debounce = at91_mux_pio3_set_debounce, |
767 | .get_pulldown = at91_mux_pio3_get_pulldown, |
768 | .set_pulldown = at91_mux_pio3_set_pulldown, |
769 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, |
770 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, |
771 | .get_drivestrength = at91_mux_sama5d3_get_drivestrength, |
772 | .set_drivestrength = at91_mux_sama5d3_set_drivestrength, |
773 | .irq_type = alt_gpio_irq_type, |
774 | }; |
775 | |
776 | static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) |
777 | { |
778 | if (pin->mux) { |
779 | dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n" , |
780 | pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); |
781 | } else { |
782 | dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n" , |
783 | pin->bank + 'A', pin->pin, pin->conf); |
784 | } |
785 | } |
786 | |
787 | static int pin_check_config(struct at91_pinctrl *info, const char *name, |
788 | int index, const struct at91_pmx_pin *pin) |
789 | { |
790 | int mux; |
791 | |
792 | /* check if it's a valid config */ |
793 | if (pin->bank >= gpio_banks) { |
794 | dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n" , |
795 | name, index, pin->bank, gpio_banks); |
796 | return -EINVAL; |
797 | } |
798 | |
799 | if (!gpio_chips[pin->bank]) { |
800 | dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n" , |
801 | name, index, pin->bank); |
802 | return -ENXIO; |
803 | } |
804 | |
805 | if (pin->pin >= MAX_NB_GPIO_PER_BANK) { |
806 | dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n" , |
807 | name, index, pin->pin, MAX_NB_GPIO_PER_BANK); |
808 | return -EINVAL; |
809 | } |
810 | |
811 | if (!pin->mux) |
812 | return 0; |
813 | |
814 | mux = pin->mux - 1; |
815 | |
816 | if (mux >= info->nmux) { |
817 | dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n" , |
818 | name, index, mux, info->nmux); |
819 | return -EINVAL; |
820 | } |
821 | |
822 | if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { |
823 | dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n" , |
824 | name, index, mux, pin->bank + 'A', pin->pin); |
825 | return -EINVAL; |
826 | } |
827 | |
828 | return 0; |
829 | } |
830 | |
831 | static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) |
832 | { |
833 | writel_relaxed(mask, pio + PIO_PDR); |
834 | } |
835 | |
836 | static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) |
837 | { |
838 | writel_relaxed(mask, pio + PIO_PER); |
839 | writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); |
840 | } |
841 | |
842 | static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
843 | unsigned group) |
844 | { |
845 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
846 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; |
847 | const struct at91_pmx_pin *pin; |
848 | uint32_t npins = info->groups[group].npins; |
849 | int i, ret; |
850 | unsigned mask; |
851 | void __iomem *pio; |
852 | |
853 | dev_dbg(info->dev, "enable function %s group %s\n" , |
854 | info->functions[selector].name, info->groups[group].name); |
855 | |
856 | /* first check that all the pins of the group are valid with a valid |
857 | * parameter */ |
858 | for (i = 0; i < npins; i++) { |
859 | pin = &pins_conf[i]; |
860 | ret = pin_check_config(info, name: info->groups[group].name, index: i, pin); |
861 | if (ret) |
862 | return ret; |
863 | } |
864 | |
865 | for (i = 0; i < npins; i++) { |
866 | pin = &pins_conf[i]; |
867 | at91_pin_dbg(dev: info->dev, pin); |
868 | pio = pin_to_controller(info, bank: pin->bank); |
869 | |
870 | if (!pio) |
871 | continue; |
872 | |
873 | mask = pin_to_mask(pin: pin->pin); |
874 | at91_mux_disable_interrupt(pio, mask); |
875 | switch (pin->mux) { |
876 | case AT91_MUX_GPIO: |
877 | at91_mux_gpio_enable(pio, mask, input: 1); |
878 | break; |
879 | case AT91_MUX_PERIPH_A: |
880 | info->ops->mux_A_periph(pio, mask); |
881 | break; |
882 | case AT91_MUX_PERIPH_B: |
883 | info->ops->mux_B_periph(pio, mask); |
884 | break; |
885 | case AT91_MUX_PERIPH_C: |
886 | if (!info->ops->mux_C_periph) |
887 | return -EINVAL; |
888 | info->ops->mux_C_periph(pio, mask); |
889 | break; |
890 | case AT91_MUX_PERIPH_D: |
891 | if (!info->ops->mux_D_periph) |
892 | return -EINVAL; |
893 | info->ops->mux_D_periph(pio, mask); |
894 | break; |
895 | } |
896 | if (pin->mux) |
897 | at91_mux_gpio_disable(pio, mask); |
898 | } |
899 | |
900 | return 0; |
901 | } |
902 | |
903 | static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) |
904 | { |
905 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
906 | |
907 | return info->nfunctions; |
908 | } |
909 | |
910 | static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, |
911 | unsigned selector) |
912 | { |
913 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
914 | |
915 | return info->functions[selector].name; |
916 | } |
917 | |
918 | static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, |
919 | const char * const **groups, |
920 | unsigned * const num_groups) |
921 | { |
922 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
923 | |
924 | *groups = info->functions[selector].groups; |
925 | *num_groups = info->functions[selector].ngroups; |
926 | |
927 | return 0; |
928 | } |
929 | |
930 | static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, |
931 | struct pinctrl_gpio_range *range, |
932 | unsigned offset) |
933 | { |
934 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); |
935 | struct at91_gpio_chip *at91_chip; |
936 | struct gpio_chip *chip; |
937 | unsigned mask; |
938 | |
939 | if (!range) { |
940 | dev_err(npct->dev, "invalid range\n" ); |
941 | return -EINVAL; |
942 | } |
943 | if (!range->gc) { |
944 | dev_err(npct->dev, "missing GPIO chip in range\n" ); |
945 | return -EINVAL; |
946 | } |
947 | chip = range->gc; |
948 | at91_chip = gpiochip_get_data(gc: chip); |
949 | |
950 | dev_dbg(npct->dev, "enable pin %u as GPIO\n" , offset); |
951 | |
952 | mask = 1 << (offset - chip->base); |
953 | |
954 | dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n" , |
955 | offset, 'A' + range->id, offset - chip->base, mask); |
956 | |
957 | writel_relaxed(mask, at91_chip->regbase + PIO_PER); |
958 | |
959 | return 0; |
960 | } |
961 | |
962 | static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, |
963 | struct pinctrl_gpio_range *range, |
964 | unsigned offset) |
965 | { |
966 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); |
967 | |
968 | dev_dbg(npct->dev, "disable pin %u as GPIO\n" , offset); |
969 | /* Set the pin to some default state, GPIO is usually default */ |
970 | } |
971 | |
972 | static const struct pinmux_ops at91_pmx_ops = { |
973 | .get_functions_count = at91_pmx_get_funcs_count, |
974 | .get_function_name = at91_pmx_get_func_name, |
975 | .get_function_groups = at91_pmx_get_groups, |
976 | .set_mux = at91_pmx_set, |
977 | .gpio_request_enable = at91_gpio_request_enable, |
978 | .gpio_disable_free = at91_gpio_disable_free, |
979 | }; |
980 | |
981 | static int at91_pinconf_get(struct pinctrl_dev *pctldev, |
982 | unsigned pin_id, unsigned long *config) |
983 | { |
984 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
985 | void __iomem *pio; |
986 | unsigned pin; |
987 | int div; |
988 | bool out; |
989 | |
990 | *config = 0; |
991 | dev_dbg(info->dev, "%s:%d, pin_id=%d" , __func__, __LINE__, pin_id); |
992 | pio = pin_to_controller(info, bank: pin_to_bank(pin: pin_id)); |
993 | |
994 | if (!pio) |
995 | return -EINVAL; |
996 | |
997 | pin = pin_id % MAX_NB_GPIO_PER_BANK; |
998 | |
999 | if (at91_mux_get_multidrive(pio, pin)) |
1000 | *config |= MULTI_DRIVE; |
1001 | |
1002 | if (at91_mux_get_pullup(pio, pin)) |
1003 | *config |= PULL_UP; |
1004 | |
1005 | if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) |
1006 | *config |= DEGLITCH; |
1007 | if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) |
1008 | *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); |
1009 | if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) |
1010 | *config |= PULL_DOWN; |
1011 | if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) |
1012 | *config |= DIS_SCHMIT; |
1013 | if (info->ops->get_drivestrength) |
1014 | *config |= (info->ops->get_drivestrength(pio, pin) |
1015 | << DRIVE_STRENGTH_SHIFT); |
1016 | if (info->ops->get_slewrate) |
1017 | *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT); |
1018 | if (at91_mux_get_output(pio, pin, val: &out)) |
1019 | *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT); |
1020 | |
1021 | return 0; |
1022 | } |
1023 | |
1024 | static int at91_pinconf_set(struct pinctrl_dev *pctldev, |
1025 | unsigned pin_id, unsigned long *configs, |
1026 | unsigned num_configs) |
1027 | { |
1028 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
1029 | unsigned mask; |
1030 | void __iomem *pio; |
1031 | int i; |
1032 | unsigned long config; |
1033 | unsigned pin; |
1034 | |
1035 | for (i = 0; i < num_configs; i++) { |
1036 | config = configs[i]; |
1037 | |
1038 | dev_dbg(info->dev, |
1039 | "%s:%d, pin_id=%d, config=0x%lx" , |
1040 | __func__, __LINE__, pin_id, config); |
1041 | pio = pin_to_controller(info, bank: pin_to_bank(pin: pin_id)); |
1042 | |
1043 | if (!pio) |
1044 | return -EINVAL; |
1045 | |
1046 | pin = pin_id % MAX_NB_GPIO_PER_BANK; |
1047 | mask = pin_to_mask(pin); |
1048 | |
1049 | if (config & PULL_UP && config & PULL_DOWN) |
1050 | return -EINVAL; |
1051 | |
1052 | at91_mux_set_output(pio, mask, is_on: config & OUTPUT, |
1053 | val: (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT); |
1054 | at91_mux_set_pullup(pio, mask, on: config & PULL_UP); |
1055 | at91_mux_set_multidrive(pio, mask, on: config & MULTI_DRIVE); |
1056 | if (info->ops->set_deglitch) |
1057 | info->ops->set_deglitch(pio, mask, config & DEGLITCH); |
1058 | if (info->ops->set_debounce) |
1059 | info->ops->set_debounce(pio, mask, config & DEBOUNCE, |
1060 | (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); |
1061 | if (info->ops->set_pulldown) |
1062 | info->ops->set_pulldown(pio, mask, config & PULL_DOWN); |
1063 | if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) |
1064 | info->ops->disable_schmitt_trig(pio, mask); |
1065 | if (info->ops->set_drivestrength) |
1066 | info->ops->set_drivestrength(pio, pin, |
1067 | (config & DRIVE_STRENGTH) |
1068 | >> DRIVE_STRENGTH_SHIFT); |
1069 | if (info->ops->set_slewrate) |
1070 | info->ops->set_slewrate(pio, pin, |
1071 | (config & SLEWRATE) >> SLEWRATE_SHIFT); |
1072 | |
1073 | } /* for each config */ |
1074 | |
1075 | return 0; |
1076 | } |
1077 | |
1078 | #define DBG_SHOW_FLAG(flag) do { \ |
1079 | if (config & flag) { \ |
1080 | if (num_conf) \ |
1081 | seq_puts(s, "|"); \ |
1082 | seq_puts(s, #flag); \ |
1083 | num_conf++; \ |
1084 | } \ |
1085 | } while (0) |
1086 | |
1087 | #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \ |
1088 | if ((config & mask) == flag) { \ |
1089 | if (num_conf) \ |
1090 | seq_puts(s, "|"); \ |
1091 | seq_puts(s, #name); \ |
1092 | num_conf++; \ |
1093 | } \ |
1094 | } while (0) |
1095 | |
1096 | static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
1097 | struct seq_file *s, unsigned pin_id) |
1098 | { |
1099 | unsigned long config; |
1100 | int val, num_conf = 0; |
1101 | |
1102 | at91_pinconf_get(pctldev, pin_id, config: &config); |
1103 | |
1104 | DBG_SHOW_FLAG(MULTI_DRIVE); |
1105 | DBG_SHOW_FLAG(PULL_UP); |
1106 | DBG_SHOW_FLAG(PULL_DOWN); |
1107 | DBG_SHOW_FLAG(DIS_SCHMIT); |
1108 | DBG_SHOW_FLAG(DEGLITCH); |
1109 | DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW), |
1110 | DRIVE_STRENGTH_LOW); |
1111 | DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED), |
1112 | DRIVE_STRENGTH_MED); |
1113 | DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI), |
1114 | DRIVE_STRENGTH_HI); |
1115 | DBG_SHOW_FLAG(SLEWRATE); |
1116 | DBG_SHOW_FLAG(DEBOUNCE); |
1117 | if (config & DEBOUNCE) { |
1118 | val = config >> DEBOUNCE_VAL_SHIFT; |
1119 | seq_printf(m: s, fmt: "(%d)" , val); |
1120 | } |
1121 | |
1122 | return; |
1123 | } |
1124 | |
1125 | static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, |
1126 | struct seq_file *s, unsigned group) |
1127 | { |
1128 | } |
1129 | |
1130 | static const struct pinconf_ops at91_pinconf_ops = { |
1131 | .pin_config_get = at91_pinconf_get, |
1132 | .pin_config_set = at91_pinconf_set, |
1133 | .pin_config_dbg_show = at91_pinconf_dbg_show, |
1134 | .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, |
1135 | }; |
1136 | |
1137 | static struct pinctrl_desc at91_pinctrl_desc = { |
1138 | .pctlops = &at91_pctrl_ops, |
1139 | .pmxops = &at91_pmx_ops, |
1140 | .confops = &at91_pinconf_ops, |
1141 | .owner = THIS_MODULE, |
1142 | }; |
1143 | |
1144 | static const char *gpio_compat = "atmel,at91rm9200-gpio" ; |
1145 | |
1146 | static void at91_pinctrl_child_count(struct at91_pinctrl *info, |
1147 | struct device_node *np) |
1148 | { |
1149 | struct device_node *child; |
1150 | |
1151 | for_each_child_of_node(np, child) { |
1152 | if (of_device_is_compatible(device: child, gpio_compat)) { |
1153 | if (of_device_is_available(device: child)) |
1154 | info->nactive_banks++; |
1155 | } else { |
1156 | info->nfunctions++; |
1157 | info->ngroups += of_get_child_count(np: child); |
1158 | } |
1159 | } |
1160 | } |
1161 | |
1162 | static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, |
1163 | struct device_node *np) |
1164 | { |
1165 | int ret = 0; |
1166 | int size; |
1167 | const __be32 *list; |
1168 | |
1169 | list = of_get_property(node: np, name: "atmel,mux-mask" , lenp: &size); |
1170 | if (!list) { |
1171 | dev_err(info->dev, "can not read the mux-mask of %d\n" , size); |
1172 | return -EINVAL; |
1173 | } |
1174 | |
1175 | size /= sizeof(*list); |
1176 | if (!size || size % gpio_banks) { |
1177 | dev_err(info->dev, "wrong mux mask array should be by %d\n" , gpio_banks); |
1178 | return -EINVAL; |
1179 | } |
1180 | info->nmux = size / gpio_banks; |
1181 | |
1182 | info->mux_mask = devm_kcalloc(dev: info->dev, n: size, size: sizeof(u32), |
1183 | GFP_KERNEL); |
1184 | if (!info->mux_mask) |
1185 | return -ENOMEM; |
1186 | |
1187 | ret = of_property_read_u32_array(np, propname: "atmel,mux-mask" , |
1188 | out_values: info->mux_mask, sz: size); |
1189 | if (ret) |
1190 | dev_err(info->dev, "can not read the mux-mask of %d\n" , size); |
1191 | return ret; |
1192 | } |
1193 | |
1194 | static int at91_pinctrl_parse_groups(struct device_node *np, |
1195 | struct at91_pin_group *grp, |
1196 | struct at91_pinctrl *info, u32 index) |
1197 | { |
1198 | struct at91_pmx_pin *pin; |
1199 | int size; |
1200 | const __be32 *list; |
1201 | int i, j; |
1202 | |
1203 | dev_dbg(info->dev, "group(%d): %pOFn\n" , index, np); |
1204 | |
1205 | /* Initialise group */ |
1206 | grp->name = np->name; |
1207 | |
1208 | /* |
1209 | * the binding format is atmel,pins = <bank pin mux CONFIG ...>, |
1210 | * do sanity check and calculate pins number |
1211 | */ |
1212 | list = of_get_property(node: np, name: "atmel,pins" , lenp: &size); |
1213 | /* we do not check return since it's safe node passed down */ |
1214 | size /= sizeof(*list); |
1215 | if (!size || size % 4) { |
1216 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n" ); |
1217 | return -EINVAL; |
1218 | } |
1219 | |
1220 | grp->npins = size / 4; |
1221 | pin = grp->pins_conf = devm_kcalloc(dev: info->dev, |
1222 | n: grp->npins, |
1223 | size: sizeof(struct at91_pmx_pin), |
1224 | GFP_KERNEL); |
1225 | grp->pins = devm_kcalloc(dev: info->dev, n: grp->npins, size: sizeof(unsigned int), |
1226 | GFP_KERNEL); |
1227 | if (!grp->pins_conf || !grp->pins) |
1228 | return -ENOMEM; |
1229 | |
1230 | for (i = 0, j = 0; i < size; i += 4, j++) { |
1231 | pin->bank = be32_to_cpu(*list++); |
1232 | pin->pin = be32_to_cpu(*list++); |
1233 | grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; |
1234 | pin->mux = be32_to_cpu(*list++); |
1235 | pin->conf = be32_to_cpu(*list++); |
1236 | |
1237 | at91_pin_dbg(dev: info->dev, pin); |
1238 | pin++; |
1239 | } |
1240 | |
1241 | return 0; |
1242 | } |
1243 | |
1244 | static int at91_pinctrl_parse_functions(struct device_node *np, |
1245 | struct at91_pinctrl *info, u32 index) |
1246 | { |
1247 | struct device_node *child; |
1248 | struct at91_pmx_func *func; |
1249 | struct at91_pin_group *grp; |
1250 | int ret; |
1251 | static u32 grp_index; |
1252 | u32 i = 0; |
1253 | |
1254 | dev_dbg(info->dev, "parse function(%d): %pOFn\n" , index, np); |
1255 | |
1256 | func = &info->functions[index]; |
1257 | |
1258 | /* Initialise function */ |
1259 | func->name = np->name; |
1260 | func->ngroups = of_get_child_count(np); |
1261 | if (func->ngroups == 0) { |
1262 | dev_err(info->dev, "no groups defined\n" ); |
1263 | return -EINVAL; |
1264 | } |
1265 | func->groups = devm_kcalloc(dev: info->dev, |
1266 | n: func->ngroups, size: sizeof(char *), GFP_KERNEL); |
1267 | if (!func->groups) |
1268 | return -ENOMEM; |
1269 | |
1270 | for_each_child_of_node(np, child) { |
1271 | func->groups[i] = child->name; |
1272 | grp = &info->groups[grp_index++]; |
1273 | ret = at91_pinctrl_parse_groups(np: child, grp, info, index: i++); |
1274 | if (ret) { |
1275 | of_node_put(node: child); |
1276 | return ret; |
1277 | } |
1278 | } |
1279 | |
1280 | return 0; |
1281 | } |
1282 | |
1283 | static const struct of_device_id at91_pinctrl_of_match[] = { |
1284 | { .compatible = "atmel,sama5d3-pinctrl" , .data = &sama5d3_ops }, |
1285 | { .compatible = "atmel,at91sam9x5-pinctrl" , .data = &at91sam9x5_ops }, |
1286 | { .compatible = "atmel,at91rm9200-pinctrl" , .data = &at91rm9200_ops }, |
1287 | { .compatible = "microchip,sam9x60-pinctrl" , .data = &sam9x60_ops }, |
1288 | { /* sentinel */ } |
1289 | }; |
1290 | |
1291 | static int at91_pinctrl_probe_dt(struct platform_device *pdev, |
1292 | struct at91_pinctrl *info) |
1293 | { |
1294 | struct device *dev = &pdev->dev; |
1295 | int ret = 0; |
1296 | int i, j, ngpio_chips_enabled = 0; |
1297 | uint32_t *tmp; |
1298 | struct device_node *np = dev->of_node; |
1299 | struct device_node *child; |
1300 | |
1301 | if (!np) |
1302 | return -ENODEV; |
1303 | |
1304 | info->dev = &pdev->dev; |
1305 | info->ops = device_get_match_data(dev: &pdev->dev); |
1306 | at91_pinctrl_child_count(info, np); |
1307 | |
1308 | /* |
1309 | * We need all the GPIO drivers to probe FIRST, or we will not be able |
1310 | * to obtain references to the struct gpio_chip * for them, and we |
1311 | * need this to proceed. |
1312 | */ |
1313 | for (i = 0; i < MAX_GPIO_BANKS; i++) |
1314 | if (gpio_chips[i]) |
1315 | ngpio_chips_enabled++; |
1316 | |
1317 | if (ngpio_chips_enabled < info->nactive_banks) |
1318 | return -EPROBE_DEFER; |
1319 | |
1320 | ret = at91_pinctrl_mux_mask(info, np); |
1321 | if (ret) |
1322 | return ret; |
1323 | |
1324 | dev_dbg(dev, "nmux = %d\n" , info->nmux); |
1325 | |
1326 | dev_dbg(dev, "mux-mask\n" ); |
1327 | tmp = info->mux_mask; |
1328 | for (i = 0; i < gpio_banks; i++) { |
1329 | for (j = 0; j < info->nmux; j++, tmp++) { |
1330 | dev_dbg(dev, "%d:%d\t0x%x\n" , i, j, tmp[0]); |
1331 | } |
1332 | } |
1333 | |
1334 | dev_dbg(dev, "nfunctions = %d\n" , info->nfunctions); |
1335 | dev_dbg(dev, "ngroups = %d\n" , info->ngroups); |
1336 | info->functions = devm_kcalloc(dev, n: info->nfunctions, size: sizeof(*info->functions), |
1337 | GFP_KERNEL); |
1338 | if (!info->functions) |
1339 | return -ENOMEM; |
1340 | |
1341 | info->groups = devm_kcalloc(dev, n: info->ngroups, size: sizeof(*info->groups), |
1342 | GFP_KERNEL); |
1343 | if (!info->groups) |
1344 | return -ENOMEM; |
1345 | |
1346 | dev_dbg(dev, "nbanks = %d\n" , gpio_banks); |
1347 | dev_dbg(dev, "nfunctions = %d\n" , info->nfunctions); |
1348 | dev_dbg(dev, "ngroups = %d\n" , info->ngroups); |
1349 | |
1350 | i = 0; |
1351 | |
1352 | for_each_child_of_node(np, child) { |
1353 | if (of_device_is_compatible(device: child, gpio_compat)) |
1354 | continue; |
1355 | ret = at91_pinctrl_parse_functions(np: child, info, index: i++); |
1356 | if (ret) { |
1357 | of_node_put(node: child); |
1358 | return dev_err_probe(dev, err: ret, fmt: "failed to parse function\n" ); |
1359 | } |
1360 | } |
1361 | |
1362 | return 0; |
1363 | } |
1364 | |
1365 | static int at91_pinctrl_probe(struct platform_device *pdev) |
1366 | { |
1367 | struct device *dev = &pdev->dev; |
1368 | struct at91_pinctrl *info; |
1369 | struct pinctrl_pin_desc *pdesc; |
1370 | int ret, i, j, k; |
1371 | |
1372 | info = devm_kzalloc(dev, size: sizeof(*info), GFP_KERNEL); |
1373 | if (!info) |
1374 | return -ENOMEM; |
1375 | |
1376 | ret = at91_pinctrl_probe_dt(pdev, info); |
1377 | if (ret) |
1378 | return ret; |
1379 | |
1380 | at91_pinctrl_desc.name = dev_name(dev); |
1381 | at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK; |
1382 | at91_pinctrl_desc.pins = pdesc = |
1383 | devm_kcalloc(dev, n: at91_pinctrl_desc.npins, size: sizeof(*pdesc), GFP_KERNEL); |
1384 | if (!at91_pinctrl_desc.pins) |
1385 | return -ENOMEM; |
1386 | |
1387 | for (i = 0, k = 0; i < gpio_banks; i++) { |
1388 | char **names; |
1389 | |
1390 | names = devm_kasprintf_strarray(dev, prefix: "pio" , MAX_NB_GPIO_PER_BANK); |
1391 | if (IS_ERR(ptr: names)) |
1392 | return PTR_ERR(ptr: names); |
1393 | |
1394 | for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { |
1395 | char *name = names[j]; |
1396 | |
1397 | strreplace(str: name, old: '-', new: i + 'A'); |
1398 | |
1399 | pdesc->number = k; |
1400 | pdesc->name = name; |
1401 | pdesc++; |
1402 | } |
1403 | } |
1404 | |
1405 | platform_set_drvdata(pdev, data: info); |
1406 | info->pctl = devm_pinctrl_register(dev, pctldesc: &at91_pinctrl_desc, driver_data: info); |
1407 | if (IS_ERR(ptr: info->pctl)) |
1408 | return dev_err_probe(dev, err: PTR_ERR(ptr: info->pctl), fmt: "could not register AT91 pinctrl driver\n" ); |
1409 | |
1410 | /* We will handle a range of GPIO pins */ |
1411 | for (i = 0; i < gpio_banks; i++) |
1412 | if (gpio_chips[i]) |
1413 | pinctrl_add_gpio_range(pctldev: info->pctl, range: &gpio_chips[i]->range); |
1414 | |
1415 | dev_info(dev, "initialized AT91 pinctrl driver\n" ); |
1416 | |
1417 | return 0; |
1418 | } |
1419 | |
1420 | static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
1421 | { |
1422 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gc: chip); |
1423 | void __iomem *pio = at91_gpio->regbase; |
1424 | unsigned mask = 1 << offset; |
1425 | u32 osr; |
1426 | |
1427 | osr = readl_relaxed(pio + PIO_OSR); |
1428 | if (osr & mask) |
1429 | return GPIO_LINE_DIRECTION_OUT; |
1430 | |
1431 | return GPIO_LINE_DIRECTION_IN; |
1432 | } |
1433 | |
1434 | static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
1435 | { |
1436 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gc: chip); |
1437 | void __iomem *pio = at91_gpio->regbase; |
1438 | unsigned mask = 1 << offset; |
1439 | |
1440 | writel_relaxed(mask, pio + PIO_ODR); |
1441 | return 0; |
1442 | } |
1443 | |
1444 | static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) |
1445 | { |
1446 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gc: chip); |
1447 | void __iomem *pio = at91_gpio->regbase; |
1448 | unsigned mask = 1 << offset; |
1449 | u32 pdsr; |
1450 | |
1451 | pdsr = readl_relaxed(pio + PIO_PDSR); |
1452 | return (pdsr & mask) != 0; |
1453 | } |
1454 | |
1455 | static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, |
1456 | int val) |
1457 | { |
1458 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gc: chip); |
1459 | void __iomem *pio = at91_gpio->regbase; |
1460 | unsigned mask = 1 << offset; |
1461 | |
1462 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); |
1463 | } |
1464 | |
1465 | static void at91_gpio_set_multiple(struct gpio_chip *chip, |
1466 | unsigned long *mask, unsigned long *bits) |
1467 | { |
1468 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gc: chip); |
1469 | void __iomem *pio = at91_gpio->regbase; |
1470 | |
1471 | #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) |
1472 | /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ |
1473 | uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); |
1474 | uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); |
1475 | |
1476 | writel_relaxed(set_mask, pio + PIO_SODR); |
1477 | writel_relaxed(clear_mask, pio + PIO_CODR); |
1478 | } |
1479 | |
1480 | static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
1481 | int val) |
1482 | { |
1483 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gc: chip); |
1484 | void __iomem *pio = at91_gpio->regbase; |
1485 | unsigned mask = 1 << offset; |
1486 | |
1487 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); |
1488 | writel_relaxed(mask, pio + PIO_OER); |
1489 | |
1490 | return 0; |
1491 | } |
1492 | |
1493 | #ifdef CONFIG_DEBUG_FS |
1494 | static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
1495 | { |
1496 | enum at91_mux mode; |
1497 | int i; |
1498 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gc: chip); |
1499 | void __iomem *pio = at91_gpio->regbase; |
1500 | const char *gpio_label; |
1501 | |
1502 | for_each_requested_gpio(chip, i, gpio_label) { |
1503 | unsigned mask = pin_to_mask(pin: i); |
1504 | |
1505 | mode = at91_gpio->ops->get_periph(pio, mask); |
1506 | seq_printf(m: s, fmt: "[%s] GPIO%s%d: " , |
1507 | gpio_label, chip->label, i); |
1508 | if (mode == AT91_MUX_GPIO) { |
1509 | seq_printf(m: s, fmt: "[gpio] " ); |
1510 | seq_printf(m: s, fmt: "%s " , |
1511 | readl_relaxed(pio + PIO_OSR) & mask ? |
1512 | "output" : "input" ); |
1513 | seq_printf(m: s, fmt: "%s\n" , |
1514 | readl_relaxed(pio + PIO_PDSR) & mask ? |
1515 | "set" : "clear" ); |
1516 | } else { |
1517 | seq_printf(m: s, fmt: "[periph %c]\n" , |
1518 | mode + 'A' - 1); |
1519 | } |
1520 | } |
1521 | } |
1522 | #else |
1523 | #define at91_gpio_dbg_show NULL |
1524 | #endif |
1525 | |
1526 | static int gpio_irq_request_resources(struct irq_data *d) |
1527 | { |
1528 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
1529 | |
1530 | return gpiochip_lock_as_irq(gc: &at91_gpio->chip, offset: irqd_to_hwirq(d)); |
1531 | } |
1532 | |
1533 | static void gpio_irq_release_resources(struct irq_data *d) |
1534 | { |
1535 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
1536 | |
1537 | gpiochip_unlock_as_irq(gc: &at91_gpio->chip, offset: irqd_to_hwirq(d)); |
1538 | } |
1539 | |
1540 | /* Several AIC controller irqs are dispatched through this GPIO handler. |
1541 | * To use any AT91_PIN_* as an externally triggered IRQ, first call |
1542 | * at91_set_gpio_input() then maybe enable its glitch filter. |
1543 | * Then just request_irq() with the pin ID; it works like any ARM IRQ |
1544 | * handler. |
1545 | * First implementation always triggers on rising and falling edges |
1546 | * whereas the newer PIO3 can be additionally configured to trigger on |
1547 | * level, edge with any polarity. |
1548 | * |
1549 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after |
1550 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). |
1551 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. |
1552 | */ |
1553 | |
1554 | static void gpio_irq_mask(struct irq_data *d) |
1555 | { |
1556 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
1557 | void __iomem *pio = at91_gpio->regbase; |
1558 | unsigned mask = 1 << d->hwirq; |
1559 | unsigned gpio = irqd_to_hwirq(d); |
1560 | |
1561 | gpiochip_disable_irq(gc: &at91_gpio->chip, offset: gpio); |
1562 | |
1563 | if (pio) |
1564 | writel_relaxed(mask, pio + PIO_IDR); |
1565 | } |
1566 | |
1567 | static void gpio_irq_unmask(struct irq_data *d) |
1568 | { |
1569 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
1570 | void __iomem *pio = at91_gpio->regbase; |
1571 | unsigned mask = 1 << d->hwirq; |
1572 | unsigned gpio = irqd_to_hwirq(d); |
1573 | |
1574 | gpiochip_enable_irq(gc: &at91_gpio->chip, offset: gpio); |
1575 | |
1576 | if (pio) |
1577 | writel_relaxed(mask, pio + PIO_IER); |
1578 | } |
1579 | |
1580 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
1581 | { |
1582 | switch (type) { |
1583 | case IRQ_TYPE_NONE: |
1584 | case IRQ_TYPE_EDGE_BOTH: |
1585 | return 0; |
1586 | default: |
1587 | return -EINVAL; |
1588 | } |
1589 | } |
1590 | |
1591 | /* Alternate irq type for PIO3 support */ |
1592 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type) |
1593 | { |
1594 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
1595 | void __iomem *pio = at91_gpio->regbase; |
1596 | unsigned mask = 1 << d->hwirq; |
1597 | |
1598 | switch (type) { |
1599 | case IRQ_TYPE_EDGE_RISING: |
1600 | irq_set_handler_locked(data: d, handler: handle_simple_irq); |
1601 | writel_relaxed(mask, pio + PIO_ESR); |
1602 | writel_relaxed(mask, pio + PIO_REHLSR); |
1603 | break; |
1604 | case IRQ_TYPE_EDGE_FALLING: |
1605 | irq_set_handler_locked(data: d, handler: handle_simple_irq); |
1606 | writel_relaxed(mask, pio + PIO_ESR); |
1607 | writel_relaxed(mask, pio + PIO_FELLSR); |
1608 | break; |
1609 | case IRQ_TYPE_LEVEL_LOW: |
1610 | irq_set_handler_locked(data: d, handler: handle_level_irq); |
1611 | writel_relaxed(mask, pio + PIO_LSR); |
1612 | writel_relaxed(mask, pio + PIO_FELLSR); |
1613 | break; |
1614 | case IRQ_TYPE_LEVEL_HIGH: |
1615 | irq_set_handler_locked(data: d, handler: handle_level_irq); |
1616 | writel_relaxed(mask, pio + PIO_LSR); |
1617 | writel_relaxed(mask, pio + PIO_REHLSR); |
1618 | break; |
1619 | case IRQ_TYPE_EDGE_BOTH: |
1620 | /* |
1621 | * disable additional interrupt modes: |
1622 | * fall back to default behavior |
1623 | */ |
1624 | irq_set_handler_locked(data: d, handler: handle_simple_irq); |
1625 | writel_relaxed(mask, pio + PIO_AIMDR); |
1626 | return 0; |
1627 | case IRQ_TYPE_NONE: |
1628 | default: |
1629 | pr_warn("AT91: No type for GPIO irq offset %d\n" , d->irq); |
1630 | return -EINVAL; |
1631 | } |
1632 | |
1633 | /* enable additional interrupt modes */ |
1634 | writel_relaxed(mask, pio + PIO_AIMER); |
1635 | |
1636 | return 0; |
1637 | } |
1638 | |
1639 | static void gpio_irq_ack(struct irq_data *d) |
1640 | { |
1641 | /* the interrupt is already cleared before by reading ISR */ |
1642 | } |
1643 | |
1644 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) |
1645 | { |
1646 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); |
1647 | unsigned mask = 1 << d->hwirq; |
1648 | |
1649 | if (state) |
1650 | at91_gpio->wakeups |= mask; |
1651 | else |
1652 | at91_gpio->wakeups &= ~mask; |
1653 | |
1654 | irq_set_irq_wake(irq: at91_gpio->pioc_virq, on: state); |
1655 | |
1656 | return 0; |
1657 | } |
1658 | |
1659 | static int at91_gpio_suspend(struct device *dev) |
1660 | { |
1661 | struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev); |
1662 | void __iomem *pio = at91_chip->regbase; |
1663 | |
1664 | at91_chip->backups = readl_relaxed(pio + PIO_IMR); |
1665 | writel_relaxed(at91_chip->backups, pio + PIO_IDR); |
1666 | writel_relaxed(at91_chip->wakeups, pio + PIO_IER); |
1667 | |
1668 | if (!at91_chip->wakeups) |
1669 | clk_disable_unprepare(clk: at91_chip->clock); |
1670 | else |
1671 | dev_dbg(dev, "GPIO-%c may wake for %08x\n" , |
1672 | 'A' + at91_chip->id, at91_chip->wakeups); |
1673 | |
1674 | return 0; |
1675 | } |
1676 | |
1677 | static int at91_gpio_resume(struct device *dev) |
1678 | { |
1679 | struct at91_gpio_chip *at91_chip = dev_get_drvdata(dev); |
1680 | void __iomem *pio = at91_chip->regbase; |
1681 | |
1682 | if (!at91_chip->wakeups) |
1683 | clk_prepare_enable(clk: at91_chip->clock); |
1684 | |
1685 | writel_relaxed(at91_chip->wakeups, pio + PIO_IDR); |
1686 | writel_relaxed(at91_chip->backups, pio + PIO_IER); |
1687 | |
1688 | return 0; |
1689 | } |
1690 | |
1691 | static void gpio_irq_handler(struct irq_desc *desc) |
1692 | { |
1693 | struct irq_chip *chip = irq_desc_get_chip(desc); |
1694 | struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); |
1695 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gc: gpio_chip); |
1696 | void __iomem *pio = at91_gpio->regbase; |
1697 | unsigned long isr; |
1698 | int n; |
1699 | |
1700 | chained_irq_enter(chip, desc); |
1701 | for (;;) { |
1702 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. |
1703 | * When there are none pending, we're finished unless we need |
1704 | * to process multiple banks (like ID_PIOCDE on sam9263). |
1705 | */ |
1706 | isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); |
1707 | if (!isr) { |
1708 | if (!at91_gpio->next) |
1709 | break; |
1710 | at91_gpio = at91_gpio->next; |
1711 | pio = at91_gpio->regbase; |
1712 | gpio_chip = &at91_gpio->chip; |
1713 | continue; |
1714 | } |
1715 | |
1716 | for_each_set_bit(n, &isr, BITS_PER_LONG) |
1717 | generic_handle_domain_irq(domain: gpio_chip->irq.domain, hwirq: n); |
1718 | } |
1719 | chained_irq_exit(chip, desc); |
1720 | /* now it may re-trigger */ |
1721 | } |
1722 | |
1723 | static int at91_gpio_of_irq_setup(struct platform_device *pdev, |
1724 | struct at91_gpio_chip *at91_gpio) |
1725 | { |
1726 | struct device *dev = &pdev->dev; |
1727 | struct gpio_chip *gpiochip_prev = NULL; |
1728 | struct at91_gpio_chip *prev = NULL; |
1729 | struct irq_data *d = irq_get_irq_data(irq: at91_gpio->pioc_virq); |
1730 | struct irq_chip *gpio_irqchip; |
1731 | struct gpio_irq_chip *girq; |
1732 | int i; |
1733 | |
1734 | gpio_irqchip = devm_kzalloc(dev, size: sizeof(*gpio_irqchip), GFP_KERNEL); |
1735 | if (!gpio_irqchip) |
1736 | return -ENOMEM; |
1737 | |
1738 | at91_gpio->pioc_hwirq = irqd_to_hwirq(d); |
1739 | |
1740 | gpio_irqchip->name = "GPIO" ; |
1741 | gpio_irqchip->irq_request_resources = gpio_irq_request_resources; |
1742 | gpio_irqchip->irq_release_resources = gpio_irq_release_resources; |
1743 | gpio_irqchip->irq_ack = gpio_irq_ack; |
1744 | gpio_irqchip->irq_disable = gpio_irq_mask; |
1745 | gpio_irqchip->irq_mask = gpio_irq_mask; |
1746 | gpio_irqchip->irq_unmask = gpio_irq_unmask; |
1747 | gpio_irqchip->irq_set_wake = pm_ptr(gpio_irq_set_wake); |
1748 | gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type; |
1749 | gpio_irqchip->flags = IRQCHIP_IMMUTABLE; |
1750 | |
1751 | /* Disable irqs of this PIO controller */ |
1752 | writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); |
1753 | |
1754 | /* |
1755 | * Let the generic code handle this edge IRQ, the chained |
1756 | * handler will perform the actual work of handling the parent |
1757 | * interrupt. |
1758 | */ |
1759 | girq = &at91_gpio->chip.irq; |
1760 | gpio_irq_chip_set_chip(girq, chip: gpio_irqchip); |
1761 | girq->default_type = IRQ_TYPE_NONE; |
1762 | girq->handler = handle_edge_irq; |
1763 | |
1764 | /* |
1765 | * The top level handler handles one bank of GPIOs, except |
1766 | * on some SoC it can handle up to three... |
1767 | * We only set up the handler for the first of the list. |
1768 | */ |
1769 | gpiochip_prev = irq_get_handler_data(irq: at91_gpio->pioc_virq); |
1770 | if (!gpiochip_prev) { |
1771 | girq->parent_handler = gpio_irq_handler; |
1772 | girq->num_parents = 1; |
1773 | girq->parents = devm_kcalloc(dev, n: girq->num_parents, |
1774 | size: sizeof(*girq->parents), |
1775 | GFP_KERNEL); |
1776 | if (!girq->parents) |
1777 | return -ENOMEM; |
1778 | girq->parents[0] = at91_gpio->pioc_virq; |
1779 | return 0; |
1780 | } |
1781 | |
1782 | prev = gpiochip_get_data(gc: gpiochip_prev); |
1783 | /* we can only have 2 banks before */ |
1784 | for (i = 0; i < 2; i++) { |
1785 | if (prev->next) { |
1786 | prev = prev->next; |
1787 | } else { |
1788 | prev->next = at91_gpio; |
1789 | return 0; |
1790 | } |
1791 | } |
1792 | |
1793 | return -EINVAL; |
1794 | } |
1795 | |
1796 | /* This structure is replicated for each GPIO block allocated at probe time */ |
1797 | static const struct gpio_chip at91_gpio_template = { |
1798 | .request = gpiochip_generic_request, |
1799 | .free = gpiochip_generic_free, |
1800 | .get_direction = at91_gpio_get_direction, |
1801 | .direction_input = at91_gpio_direction_input, |
1802 | .get = at91_gpio_get, |
1803 | .direction_output = at91_gpio_direction_output, |
1804 | .set = at91_gpio_set, |
1805 | .set_multiple = at91_gpio_set_multiple, |
1806 | .dbg_show = at91_gpio_dbg_show, |
1807 | .can_sleep = false, |
1808 | .ngpio = MAX_NB_GPIO_PER_BANK, |
1809 | }; |
1810 | |
1811 | static const struct of_device_id at91_gpio_of_match[] = { |
1812 | { .compatible = "atmel,at91sam9x5-gpio" , .data = &at91sam9x5_ops, }, |
1813 | { .compatible = "atmel,at91rm9200-gpio" , .data = &at91rm9200_ops }, |
1814 | { .compatible = "microchip,sam9x60-gpio" , .data = &sam9x60_ops }, |
1815 | { /* sentinel */ } |
1816 | }; |
1817 | |
1818 | static int at91_gpio_probe(struct platform_device *pdev) |
1819 | { |
1820 | struct device *dev = &pdev->dev; |
1821 | struct device_node *np = dev->of_node; |
1822 | struct at91_gpio_chip *at91_chip = NULL; |
1823 | struct gpio_chip *chip; |
1824 | struct pinctrl_gpio_range *range; |
1825 | int ret = 0; |
1826 | int irq, i; |
1827 | int alias_idx = of_alias_get_id(np, stem: "gpio" ); |
1828 | uint32_t ngpio; |
1829 | char **names; |
1830 | |
1831 | BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); |
1832 | if (gpio_chips[alias_idx]) |
1833 | return dev_err_probe(dev, err: -EBUSY, fmt: "%d slot is occupied.\n" , alias_idx); |
1834 | |
1835 | irq = platform_get_irq(pdev, 0); |
1836 | if (irq < 0) |
1837 | return irq; |
1838 | |
1839 | at91_chip = devm_kzalloc(dev, size: sizeof(*at91_chip), GFP_KERNEL); |
1840 | if (!at91_chip) |
1841 | return -ENOMEM; |
1842 | |
1843 | at91_chip->regbase = devm_platform_ioremap_resource(pdev, index: 0); |
1844 | if (IS_ERR(ptr: at91_chip->regbase)) |
1845 | return PTR_ERR(ptr: at91_chip->regbase); |
1846 | |
1847 | at91_chip->ops = device_get_match_data(dev); |
1848 | at91_chip->pioc_virq = irq; |
1849 | |
1850 | at91_chip->clock = devm_clk_get_enabled(dev, NULL); |
1851 | if (IS_ERR(ptr: at91_chip->clock)) |
1852 | return dev_err_probe(dev, err: PTR_ERR(ptr: at91_chip->clock), fmt: "failed to get clock, ignoring.\n" ); |
1853 | |
1854 | at91_chip->chip = at91_gpio_template; |
1855 | at91_chip->id = alias_idx; |
1856 | |
1857 | chip = &at91_chip->chip; |
1858 | chip->label = dev_name(dev); |
1859 | chip->parent = dev; |
1860 | chip->owner = THIS_MODULE; |
1861 | chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; |
1862 | |
1863 | if (!of_property_read_u32(np, propname: "#gpio-lines" , out_value: &ngpio)) { |
1864 | if (ngpio >= MAX_NB_GPIO_PER_BANK) |
1865 | dev_err(dev, "at91_gpio.%d, gpio-nb >= %d failback to %d\n" , |
1866 | alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); |
1867 | else |
1868 | chip->ngpio = ngpio; |
1869 | } |
1870 | |
1871 | names = devm_kasprintf_strarray(dev, prefix: "pio" , n: chip->ngpio); |
1872 | if (IS_ERR(ptr: names)) |
1873 | return PTR_ERR(ptr: names); |
1874 | |
1875 | for (i = 0; i < chip->ngpio; i++) |
1876 | strreplace(str: names[i], old: '-', new: alias_idx + 'A'); |
1877 | |
1878 | chip->names = (const char *const *)names; |
1879 | |
1880 | range = &at91_chip->range; |
1881 | range->name = chip->label; |
1882 | range->id = alias_idx; |
1883 | range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; |
1884 | |
1885 | range->npins = chip->ngpio; |
1886 | range->gc = chip; |
1887 | |
1888 | ret = at91_gpio_of_irq_setup(pdev, at91_gpio: at91_chip); |
1889 | if (ret) |
1890 | return ret; |
1891 | |
1892 | ret = gpiochip_add_data(chip, at91_chip); |
1893 | if (ret) |
1894 | return ret; |
1895 | |
1896 | gpio_chips[alias_idx] = at91_chip; |
1897 | platform_set_drvdata(pdev, data: at91_chip); |
1898 | gpio_banks = max(gpio_banks, alias_idx + 1); |
1899 | |
1900 | dev_info(dev, "at address %p\n" , at91_chip->regbase); |
1901 | |
1902 | return 0; |
1903 | } |
1904 | |
1905 | static DEFINE_NOIRQ_DEV_PM_OPS(at91_gpio_pm_ops, at91_gpio_suspend, at91_gpio_resume); |
1906 | |
1907 | static struct platform_driver at91_gpio_driver = { |
1908 | .driver = { |
1909 | .name = "gpio-at91" , |
1910 | .of_match_table = at91_gpio_of_match, |
1911 | .pm = pm_sleep_ptr(&at91_gpio_pm_ops), |
1912 | }, |
1913 | .probe = at91_gpio_probe, |
1914 | }; |
1915 | |
1916 | static struct platform_driver at91_pinctrl_driver = { |
1917 | .driver = { |
1918 | .name = "pinctrl-at91" , |
1919 | .of_match_table = at91_pinctrl_of_match, |
1920 | }, |
1921 | .probe = at91_pinctrl_probe, |
1922 | }; |
1923 | |
1924 | static struct platform_driver * const drivers[] = { |
1925 | &at91_gpio_driver, |
1926 | &at91_pinctrl_driver, |
1927 | }; |
1928 | |
1929 | static int __init at91_pinctrl_init(void) |
1930 | { |
1931 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
1932 | } |
1933 | arch_initcall(at91_pinctrl_init); |
1934 | |