1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support |
4 | * |
5 | * Copyright (C) 2022 9elements GmbH |
6 | * Authors: Patrick Rudolph <patrick.rudolph@9elements.com> |
7 | * Naresh Solanki <Naresh.Solanki@9elements.com> |
8 | */ |
9 | |
10 | #include <linux/acpi.h> |
11 | #include <linux/bitmap.h> |
12 | #include <linux/dmi.h> |
13 | #include <linux/gpio/driver.h> |
14 | #include <linux/gpio/consumer.h> |
15 | #include <linux/i2c.h> |
16 | #include <linux/init.h> |
17 | #include <linux/interrupt.h> |
18 | #include <linux/mod_devicetable.h> |
19 | #include <linux/module.h> |
20 | #include <linux/property.h> |
21 | #include <linux/regmap.h> |
22 | #include <linux/regulator/consumer.h> |
23 | #include <linux/seq_file.h> |
24 | |
25 | #include <linux/pinctrl/consumer.h> |
26 | #include <linux/pinctrl/pinconf.h> |
27 | #include <linux/pinctrl/pinconf-generic.h> |
28 | #include <linux/pinctrl/pinctrl.h> |
29 | #include <linux/pinctrl/pinmux.h> |
30 | |
31 | /* Fast access registers */ |
32 | #define CY8C95X0_INPUT 0x00 |
33 | #define CY8C95X0_OUTPUT 0x08 |
34 | #define CY8C95X0_INTSTATUS 0x10 |
35 | |
36 | #define CY8C95X0_INPUT_(x) (CY8C95X0_INPUT + (x)) |
37 | #define CY8C95X0_OUTPUT_(x) (CY8C95X0_OUTPUT + (x)) |
38 | #define CY8C95X0_INTSTATUS_(x) (CY8C95X0_INTSTATUS + (x)) |
39 | |
40 | /* Port Select configures the port */ |
41 | #define CY8C95X0_PORTSEL 0x18 |
42 | /* Port settings, write PORTSEL first */ |
43 | #define CY8C95X0_INTMASK 0x19 |
44 | #define CY8C95X0_PWMSEL 0x1A |
45 | #define CY8C95X0_INVERT 0x1B |
46 | #define CY8C95X0_DIRECTION 0x1C |
47 | /* Drive mode register change state on writing '1' */ |
48 | #define CY8C95X0_DRV_PU 0x1D |
49 | #define CY8C95X0_DRV_PD 0x1E |
50 | #define CY8C95X0_DRV_ODH 0x1F |
51 | #define CY8C95X0_DRV_ODL 0x20 |
52 | #define CY8C95X0_DRV_PP_FAST 0x21 |
53 | #define CY8C95X0_DRV_PP_SLOW 0x22 |
54 | #define CY8C95X0_DRV_HIZ 0x23 |
55 | #define CY8C95X0_DEVID 0x2E |
56 | #define CY8C95X0_WATCHDOG 0x2F |
57 | #define CY8C95X0_COMMAND 0x30 |
58 | |
59 | #define CY8C95X0_PIN_TO_OFFSET(x) (((x) >= 20) ? ((x) + 4) : (x)) |
60 | |
61 | #define CY8C95X0_MUX_REGMAP_TO_PORT(x) ((x) / MUXED_STRIDE) |
62 | #define CY8C95X0_MUX_REGMAP_TO_REG(x) (((x) % MUXED_STRIDE) + CY8C95X0_INTMASK) |
63 | #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) ((x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE) |
64 | |
65 | static const struct i2c_device_id cy8c95x0_id[] = { |
66 | { "cy8c9520" , 20, }, |
67 | { "cy8c9540" , 40, }, |
68 | { "cy8c9560" , 60, }, |
69 | { } |
70 | }; |
71 | MODULE_DEVICE_TABLE(i2c, cy8c95x0_id); |
72 | |
73 | #define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio)) |
74 | |
75 | static const struct of_device_id cy8c95x0_dt_ids[] = { |
76 | { .compatible = "cypress,cy8c9520" , .data = OF_CY8C95X(20), }, |
77 | { .compatible = "cypress,cy8c9540" , .data = OF_CY8C95X(40), }, |
78 | { .compatible = "cypress,cy8c9560" , .data = OF_CY8C95X(60), }, |
79 | { } |
80 | }; |
81 | MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids); |
82 | |
83 | static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true }; |
84 | |
85 | static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = { |
86 | { "irq-gpios" , &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, |
87 | { } |
88 | }; |
89 | |
90 | static int cy8c95x0_acpi_get_irq(struct device *dev) |
91 | { |
92 | int ret; |
93 | |
94 | ret = devm_acpi_dev_add_driver_gpios(dev, gpios: cy8c95x0_acpi_irq_gpios); |
95 | if (ret) |
96 | dev_warn(dev, "can't add GPIO ACPI mapping\n" ); |
97 | |
98 | ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), name: "irq-gpios" , index: 0); |
99 | if (ret < 0) |
100 | return ret; |
101 | |
102 | dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n" , ret); |
103 | return ret; |
104 | } |
105 | |
106 | static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = { |
107 | { |
108 | /* |
109 | * On Intel Galileo Gen 1 board the IRQ pin is provided |
110 | * as an absolute number instead of being relative. |
111 | * Since first controller (gpio-sch.c) and second |
112 | * (gpio-dwapb.c) are at the fixed bases, we may safely |
113 | * refer to the number in the global space to get an IRQ |
114 | * out of it. |
115 | */ |
116 | .matches = { |
117 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo" ), |
118 | }, |
119 | }, |
120 | {} |
121 | }; |
122 | |
123 | #define MAX_BANK 8 |
124 | #define BANK_SZ 8 |
125 | #define MAX_LINE (MAX_BANK * BANK_SZ) |
126 | #define MUXED_STRIDE 16 |
127 | #define CY8C95X0_GPIO_MASK GENMASK(7, 0) |
128 | |
129 | /** |
130 | * struct cy8c95x0_pinctrl - driver data |
131 | * @regmap: Device's regmap. Only direct access registers. |
132 | * @muxed_regmap: Regmap for all muxed registers. |
133 | * @irq_lock: IRQ bus lock |
134 | * @i2c_lock: Mutex for the device internal mux register |
135 | * @irq_mask: I/O bits affected by interrupts |
136 | * @irq_trig_raise: I/O bits affected by raising voltage level |
137 | * @irq_trig_fall: I/O bits affected by falling voltage level |
138 | * @irq_trig_low: I/O bits affected by a low voltage level |
139 | * @irq_trig_high: I/O bits affected by a high voltage level |
140 | * @push_pull: I/O bits configured as push pull driver |
141 | * @shiftmask: Mask used to compensate for Gport2 width |
142 | * @nport: Number of Gports in this chip |
143 | * @gpio_chip: gpiolib chip |
144 | * @driver_data: private driver data |
145 | * @regulator: Pointer to the regulator for the IC |
146 | * @dev: struct device |
147 | * @pctldev: pin controller device |
148 | * @pinctrl_desc: pin controller description |
149 | * @name: Chip controller name |
150 | * @tpin: Total number of pins |
151 | * @gpio_reset: GPIO line handler that can reset the IC |
152 | */ |
153 | struct cy8c95x0_pinctrl { |
154 | struct regmap *regmap; |
155 | struct regmap *muxed_regmap; |
156 | struct mutex irq_lock; |
157 | struct mutex i2c_lock; |
158 | DECLARE_BITMAP(irq_mask, MAX_LINE); |
159 | DECLARE_BITMAP(irq_trig_raise, MAX_LINE); |
160 | DECLARE_BITMAP(irq_trig_fall, MAX_LINE); |
161 | DECLARE_BITMAP(irq_trig_low, MAX_LINE); |
162 | DECLARE_BITMAP(irq_trig_high, MAX_LINE); |
163 | DECLARE_BITMAP(push_pull, MAX_LINE); |
164 | DECLARE_BITMAP(shiftmask, MAX_LINE); |
165 | int nport; |
166 | struct gpio_chip gpio_chip; |
167 | unsigned long driver_data; |
168 | struct regulator *regulator; |
169 | struct device *dev; |
170 | struct pinctrl_dev *pctldev; |
171 | struct pinctrl_desc pinctrl_desc; |
172 | char name[32]; |
173 | unsigned int tpin; |
174 | struct gpio_desc *gpio_reset; |
175 | }; |
176 | |
177 | static const struct pinctrl_pin_desc cy8c9560_pins[] = { |
178 | PINCTRL_PIN(0, "gp00" ), |
179 | PINCTRL_PIN(1, "gp01" ), |
180 | PINCTRL_PIN(2, "gp02" ), |
181 | PINCTRL_PIN(3, "gp03" ), |
182 | PINCTRL_PIN(4, "gp04" ), |
183 | PINCTRL_PIN(5, "gp05" ), |
184 | PINCTRL_PIN(6, "gp06" ), |
185 | PINCTRL_PIN(7, "gp07" ), |
186 | |
187 | PINCTRL_PIN(8, "gp10" ), |
188 | PINCTRL_PIN(9, "gp11" ), |
189 | PINCTRL_PIN(10, "gp12" ), |
190 | PINCTRL_PIN(11, "gp13" ), |
191 | PINCTRL_PIN(12, "gp14" ), |
192 | PINCTRL_PIN(13, "gp15" ), |
193 | PINCTRL_PIN(14, "gp16" ), |
194 | PINCTRL_PIN(15, "gp17" ), |
195 | |
196 | PINCTRL_PIN(16, "gp20" ), |
197 | PINCTRL_PIN(17, "gp21" ), |
198 | PINCTRL_PIN(18, "gp22" ), |
199 | PINCTRL_PIN(19, "gp23" ), |
200 | |
201 | PINCTRL_PIN(20, "gp30" ), |
202 | PINCTRL_PIN(21, "gp31" ), |
203 | PINCTRL_PIN(22, "gp32" ), |
204 | PINCTRL_PIN(23, "gp33" ), |
205 | PINCTRL_PIN(24, "gp34" ), |
206 | PINCTRL_PIN(25, "gp35" ), |
207 | PINCTRL_PIN(26, "gp36" ), |
208 | PINCTRL_PIN(27, "gp37" ), |
209 | |
210 | PINCTRL_PIN(28, "gp40" ), |
211 | PINCTRL_PIN(29, "gp41" ), |
212 | PINCTRL_PIN(30, "gp42" ), |
213 | PINCTRL_PIN(31, "gp43" ), |
214 | PINCTRL_PIN(32, "gp44" ), |
215 | PINCTRL_PIN(33, "gp45" ), |
216 | PINCTRL_PIN(34, "gp46" ), |
217 | PINCTRL_PIN(35, "gp47" ), |
218 | |
219 | PINCTRL_PIN(36, "gp50" ), |
220 | PINCTRL_PIN(37, "gp51" ), |
221 | PINCTRL_PIN(38, "gp52" ), |
222 | PINCTRL_PIN(39, "gp53" ), |
223 | PINCTRL_PIN(40, "gp54" ), |
224 | PINCTRL_PIN(41, "gp55" ), |
225 | PINCTRL_PIN(42, "gp56" ), |
226 | PINCTRL_PIN(43, "gp57" ), |
227 | |
228 | PINCTRL_PIN(44, "gp60" ), |
229 | PINCTRL_PIN(45, "gp61" ), |
230 | PINCTRL_PIN(46, "gp62" ), |
231 | PINCTRL_PIN(47, "gp63" ), |
232 | PINCTRL_PIN(48, "gp64" ), |
233 | PINCTRL_PIN(49, "gp65" ), |
234 | PINCTRL_PIN(50, "gp66" ), |
235 | PINCTRL_PIN(51, "gp67" ), |
236 | |
237 | PINCTRL_PIN(52, "gp70" ), |
238 | PINCTRL_PIN(53, "gp71" ), |
239 | PINCTRL_PIN(54, "gp72" ), |
240 | PINCTRL_PIN(55, "gp73" ), |
241 | PINCTRL_PIN(56, "gp74" ), |
242 | PINCTRL_PIN(57, "gp75" ), |
243 | PINCTRL_PIN(58, "gp76" ), |
244 | PINCTRL_PIN(59, "gp77" ), |
245 | }; |
246 | |
247 | static const char * const cy8c95x0_groups[] = { |
248 | "gp00" , |
249 | "gp01" , |
250 | "gp02" , |
251 | "gp03" , |
252 | "gp04" , |
253 | "gp05" , |
254 | "gp06" , |
255 | "gp07" , |
256 | |
257 | "gp10" , |
258 | "gp11" , |
259 | "gp12" , |
260 | "gp13" , |
261 | "gp14" , |
262 | "gp15" , |
263 | "gp16" , |
264 | "gp17" , |
265 | |
266 | "gp20" , |
267 | "gp21" , |
268 | "gp22" , |
269 | "gp23" , |
270 | |
271 | "gp30" , |
272 | "gp31" , |
273 | "gp32" , |
274 | "gp33" , |
275 | "gp34" , |
276 | "gp35" , |
277 | "gp36" , |
278 | "gp37" , |
279 | |
280 | "gp40" , |
281 | "gp41" , |
282 | "gp42" , |
283 | "gp43" , |
284 | "gp44" , |
285 | "gp45" , |
286 | "gp46" , |
287 | "gp47" , |
288 | |
289 | "gp50" , |
290 | "gp51" , |
291 | "gp52" , |
292 | "gp53" , |
293 | "gp54" , |
294 | "gp55" , |
295 | "gp56" , |
296 | "gp57" , |
297 | |
298 | "gp60" , |
299 | "gp61" , |
300 | "gp62" , |
301 | "gp63" , |
302 | "gp64" , |
303 | "gp65" , |
304 | "gp66" , |
305 | "gp67" , |
306 | |
307 | "gp70" , |
308 | "gp71" , |
309 | "gp72" , |
310 | "gp73" , |
311 | "gp74" , |
312 | "gp75" , |
313 | "gp76" , |
314 | "gp77" , |
315 | }; |
316 | |
317 | static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, |
318 | unsigned int pin, bool input); |
319 | |
320 | static inline u8 cypress_get_port(struct cy8c95x0_pinctrl *chip, unsigned int pin) |
321 | { |
322 | /* Account for GPORT2 which only has 4 bits */ |
323 | return CY8C95X0_PIN_TO_OFFSET(pin) / BANK_SZ; |
324 | } |
325 | |
326 | static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) |
327 | { |
328 | /* Account for GPORT2 which only has 4 bits */ |
329 | return BIT(CY8C95X0_PIN_TO_OFFSET(pin) % BANK_SZ); |
330 | } |
331 | |
332 | static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) |
333 | { |
334 | switch (reg) { |
335 | case 0x24 ... 0x27: |
336 | return false; |
337 | default: |
338 | return true; |
339 | } |
340 | } |
341 | |
342 | static bool cy8c95x0_writeable_register(struct device *dev, unsigned int reg) |
343 | { |
344 | switch (reg) { |
345 | case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): |
346 | return false; |
347 | case CY8C95X0_DEVID: |
348 | return false; |
349 | case 0x24 ... 0x27: |
350 | return false; |
351 | default: |
352 | return true; |
353 | } |
354 | } |
355 | |
356 | static bool cy8c95x0_volatile_register(struct device *dev, unsigned int reg) |
357 | { |
358 | switch (reg) { |
359 | case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): |
360 | case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): |
361 | case CY8C95X0_INTMASK: |
362 | case CY8C95X0_INVERT: |
363 | case CY8C95X0_PWMSEL: |
364 | case CY8C95X0_DIRECTION: |
365 | case CY8C95X0_DRV_PU: |
366 | case CY8C95X0_DRV_PD: |
367 | case CY8C95X0_DRV_ODH: |
368 | case CY8C95X0_DRV_ODL: |
369 | case CY8C95X0_DRV_PP_FAST: |
370 | case CY8C95X0_DRV_PP_SLOW: |
371 | case CY8C95X0_DRV_HIZ: |
372 | return true; |
373 | default: |
374 | return false; |
375 | } |
376 | } |
377 | |
378 | static bool cy8c95x0_precious_register(struct device *dev, unsigned int reg) |
379 | { |
380 | switch (reg) { |
381 | case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): |
382 | return true; |
383 | default: |
384 | return false; |
385 | } |
386 | } |
387 | |
388 | static bool cy8c95x0_muxed_register(unsigned int reg) |
389 | { |
390 | switch (reg) { |
391 | case CY8C95X0_INTMASK: |
392 | case CY8C95X0_PWMSEL: |
393 | case CY8C95X0_INVERT: |
394 | case CY8C95X0_DIRECTION: |
395 | case CY8C95X0_DRV_PU: |
396 | case CY8C95X0_DRV_PD: |
397 | case CY8C95X0_DRV_ODH: |
398 | case CY8C95X0_DRV_ODL: |
399 | case CY8C95X0_DRV_PP_FAST: |
400 | case CY8C95X0_DRV_PP_SLOW: |
401 | case CY8C95X0_DRV_HIZ: |
402 | return true; |
403 | default: |
404 | return false; |
405 | } |
406 | } |
407 | |
408 | static bool cy8c95x0_wc_register(unsigned int reg) |
409 | { |
410 | switch (reg) { |
411 | case CY8C95X0_DRV_PU: |
412 | case CY8C95X0_DRV_PD: |
413 | case CY8C95X0_DRV_ODH: |
414 | case CY8C95X0_DRV_ODL: |
415 | case CY8C95X0_DRV_PP_FAST: |
416 | case CY8C95X0_DRV_PP_SLOW: |
417 | case CY8C95X0_DRV_HIZ: |
418 | return true; |
419 | default: |
420 | return false; |
421 | } |
422 | } |
423 | |
424 | static bool cy8c95x0_quick_path_register(unsigned int reg) |
425 | { |
426 | switch (reg) { |
427 | case CY8C95X0_INPUT_(0) ... CY8C95X0_INPUT_(7): |
428 | case CY8C95X0_INTSTATUS_(0) ... CY8C95X0_INTSTATUS_(7): |
429 | case CY8C95X0_OUTPUT_(0) ... CY8C95X0_OUTPUT_(7): |
430 | return true; |
431 | default: |
432 | return false; |
433 | } |
434 | } |
435 | |
436 | static const struct reg_default cy8c95x0_reg_defaults[] = { |
437 | { CY8C95X0_OUTPUT_(0), GENMASK(7, 0) }, |
438 | { CY8C95X0_OUTPUT_(1), GENMASK(7, 0) }, |
439 | { CY8C95X0_OUTPUT_(2), GENMASK(7, 0) }, |
440 | { CY8C95X0_OUTPUT_(3), GENMASK(7, 0) }, |
441 | { CY8C95X0_OUTPUT_(4), GENMASK(7, 0) }, |
442 | { CY8C95X0_OUTPUT_(5), GENMASK(7, 0) }, |
443 | { CY8C95X0_OUTPUT_(6), GENMASK(7, 0) }, |
444 | { CY8C95X0_OUTPUT_(7), GENMASK(7, 0) }, |
445 | { CY8C95X0_PORTSEL, 0 }, |
446 | { CY8C95X0_PWMSEL, 0 }, |
447 | }; |
448 | |
449 | static int |
450 | cy8c95x0_mux_reg_read(void *context, unsigned int off, unsigned int *val) |
451 | { |
452 | struct cy8c95x0_pinctrl *chip = context; |
453 | u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off); |
454 | int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off); |
455 | |
456 | mutex_lock(&chip->i2c_lock); |
457 | /* Select the correct bank */ |
458 | ret = regmap_write(map: chip->regmap, CY8C95X0_PORTSEL, val: port); |
459 | if (ret < 0) |
460 | goto out; |
461 | |
462 | /* |
463 | * Read the register through direct access regmap. The target range |
464 | * is marked volatile. |
465 | */ |
466 | ret = regmap_read(map: chip->regmap, reg, val); |
467 | out: |
468 | mutex_unlock(lock: &chip->i2c_lock); |
469 | |
470 | return ret; |
471 | } |
472 | |
473 | static int |
474 | cy8c95x0_mux_reg_write(void *context, unsigned int off, unsigned int val) |
475 | { |
476 | struct cy8c95x0_pinctrl *chip = context; |
477 | u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off); |
478 | int ret, reg = CY8C95X0_MUX_REGMAP_TO_REG(off); |
479 | |
480 | mutex_lock(&chip->i2c_lock); |
481 | /* Select the correct bank */ |
482 | ret = regmap_write(map: chip->regmap, CY8C95X0_PORTSEL, val: port); |
483 | if (ret < 0) |
484 | goto out; |
485 | |
486 | /* |
487 | * Write the register through direct access regmap. The target range |
488 | * is marked volatile. |
489 | */ |
490 | ret = regmap_write(map: chip->regmap, reg, val); |
491 | out: |
492 | mutex_unlock(lock: &chip->i2c_lock); |
493 | |
494 | return ret; |
495 | } |
496 | |
497 | static bool cy8c95x0_mux_accessible_register(struct device *dev, unsigned int off) |
498 | { |
499 | struct i2c_client *i2c = to_i2c_client(dev); |
500 | struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client: i2c); |
501 | u8 port = CY8C95X0_MUX_REGMAP_TO_PORT(off); |
502 | u8 reg = CY8C95X0_MUX_REGMAP_TO_REG(off); |
503 | |
504 | if (port >= chip->nport) |
505 | return false; |
506 | |
507 | return cy8c95x0_muxed_register(reg); |
508 | } |
509 | |
510 | static struct regmap_bus cy8c95x0_regmap_bus = { |
511 | .reg_read = cy8c95x0_mux_reg_read, |
512 | .reg_write = cy8c95x0_mux_reg_write, |
513 | }; |
514 | |
515 | /* Regmap for muxed registers CY8C95X0_INTMASK - CY8C95X0_DRV_HIZ */ |
516 | static const struct regmap_config cy8c95x0_muxed_regmap = { |
517 | .name = "muxed" , |
518 | .reg_bits = 8, |
519 | .val_bits = 8, |
520 | .cache_type = REGCACHE_FLAT, |
521 | .use_single_read = true, |
522 | .use_single_write = true, |
523 | .max_register = MUXED_STRIDE * BANK_SZ, |
524 | .num_reg_defaults_raw = MUXED_STRIDE * BANK_SZ, |
525 | .readable_reg = cy8c95x0_mux_accessible_register, |
526 | .writeable_reg = cy8c95x0_mux_accessible_register, |
527 | }; |
528 | |
529 | /* Direct access regmap */ |
530 | static const struct regmap_config cy8c95x0_i2c_regmap = { |
531 | .name = "direct" , |
532 | .reg_bits = 8, |
533 | .val_bits = 8, |
534 | |
535 | .reg_defaults = cy8c95x0_reg_defaults, |
536 | .num_reg_defaults = ARRAY_SIZE(cy8c95x0_reg_defaults), |
537 | |
538 | .readable_reg = cy8c95x0_readable_register, |
539 | .writeable_reg = cy8c95x0_writeable_register, |
540 | .volatile_reg = cy8c95x0_volatile_register, |
541 | .precious_reg = cy8c95x0_precious_register, |
542 | |
543 | .cache_type = REGCACHE_FLAT, |
544 | .max_register = CY8C95X0_COMMAND, |
545 | }; |
546 | |
547 | static inline int cy8c95x0_regmap_update_bits_base(struct cy8c95x0_pinctrl *chip, |
548 | unsigned int reg, |
549 | unsigned int port, |
550 | unsigned int mask, |
551 | unsigned int val, |
552 | bool *change, bool async, |
553 | bool force) |
554 | { |
555 | struct regmap *regmap; |
556 | int ret, off, i, read_val; |
557 | |
558 | /* Caller should never modify PORTSEL directly */ |
559 | if (reg == CY8C95X0_PORTSEL) |
560 | return -EINVAL; |
561 | |
562 | /* Registers behind the PORTSEL mux have their own regmap */ |
563 | if (cy8c95x0_muxed_register(reg)) { |
564 | regmap = chip->muxed_regmap; |
565 | off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); |
566 | } else { |
567 | regmap = chip->regmap; |
568 | /* Quick path direct access registers honor the port argument */ |
569 | if (cy8c95x0_quick_path_register(reg)) |
570 | off = reg + port; |
571 | else |
572 | off = reg; |
573 | } |
574 | |
575 | ret = regmap_update_bits_base(map: regmap, reg: off, mask, val, change, async, force); |
576 | if (ret < 0) |
577 | return ret; |
578 | |
579 | /* Update the cache when a WC bit is written */ |
580 | if (cy8c95x0_wc_register(reg) && (mask & val)) { |
581 | for (i = CY8C95X0_DRV_PU; i <= CY8C95X0_DRV_HIZ; i++) { |
582 | if (i == reg) |
583 | continue; |
584 | off = CY8C95X0_MUX_REGMAP_TO_OFFSET(i, port); |
585 | |
586 | ret = regmap_read(map: regmap, reg: off, val: &read_val); |
587 | if (ret < 0) |
588 | continue; |
589 | |
590 | if (!(read_val & mask & val)) |
591 | continue; |
592 | |
593 | regcache_cache_only(map: regmap, enable: true); |
594 | regmap_update_bits(map: regmap, reg: off, mask: mask & val, val: 0); |
595 | regcache_cache_only(map: regmap, enable: false); |
596 | } |
597 | } |
598 | |
599 | return ret; |
600 | } |
601 | |
602 | /** |
603 | * cy8c95x0_regmap_write_bits() - writes a register using the regmap cache |
604 | * @chip: The pinctrl to work on |
605 | * @reg: The register to write to. Can be direct access or muxed register. |
606 | * MUST NOT be the PORTSEL register. |
607 | * @port: The port to be used for muxed registers or quick path direct access |
608 | * registers. Otherwise unused. |
609 | * @mask: Bitmask to change |
610 | * @val: New value for bitmask |
611 | * |
612 | * This function handles the register writes to the direct access registers and |
613 | * the muxed registers while caching all register accesses, internally handling |
614 | * the correct state of the PORTSEL register and protecting the access to muxed |
615 | * registers. |
616 | * The caller must only use this function to change registers behind the PORTSEL mux. |
617 | * |
618 | * Return: 0 for successful request, else a corresponding error value |
619 | */ |
620 | static int cy8c95x0_regmap_write_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, |
621 | unsigned int port, unsigned int mask, unsigned int val) |
622 | { |
623 | return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, async: false, force: true); |
624 | } |
625 | |
626 | /** |
627 | * cy8c95x0_regmap_update_bits() - updates a register using the regmap cache |
628 | * @chip: The pinctrl to work on |
629 | * @reg: The register to write to. Can be direct access or muxed register. |
630 | * MUST NOT be the PORTSEL register. |
631 | * @port: The port to be used for muxed registers or quick path direct access |
632 | * registers. Otherwise unused. |
633 | * @mask: Bitmask to change |
634 | * @val: New value for bitmask |
635 | * |
636 | * This function handles the register updates to the direct access registers and |
637 | * the muxed registers while caching all register accesses, internally handling |
638 | * the correct state of the PORTSEL register and protecting the access to muxed |
639 | * registers. |
640 | * The caller must only use this function to change registers behind the PORTSEL mux. |
641 | * |
642 | * Return: 0 for successful request, else a corresponding error value |
643 | */ |
644 | static int cy8c95x0_regmap_update_bits(struct cy8c95x0_pinctrl *chip, unsigned int reg, |
645 | unsigned int port, unsigned int mask, unsigned int val) |
646 | { |
647 | return cy8c95x0_regmap_update_bits_base(chip, reg, port, mask, val, NULL, async: false, force: false); |
648 | } |
649 | |
650 | /** |
651 | * cy8c95x0_regmap_read() - reads a register using the regmap cache |
652 | * @chip: The pinctrl to work on |
653 | * @reg: The register to read from. Can be direct access or muxed register. |
654 | * @port: The port to be used for muxed registers or quick path direct access |
655 | * registers. Otherwise unused. |
656 | * @read_val: Value read from hardware or cache |
657 | * |
658 | * This function handles the register reads from the direct access registers and |
659 | * the muxed registers while caching all register accesses, internally handling |
660 | * the correct state of the PORTSEL register and protecting the access to muxed |
661 | * registers. |
662 | * The caller must only use this function to read registers behind the PORTSEL mux. |
663 | * |
664 | * Return: 0 for successful request, else a corresponding error value |
665 | */ |
666 | static int cy8c95x0_regmap_read(struct cy8c95x0_pinctrl *chip, unsigned int reg, |
667 | unsigned int port, unsigned int *read_val) |
668 | { |
669 | struct regmap *regmap; |
670 | int off; |
671 | |
672 | /* Registers behind the PORTSEL mux have their own regmap */ |
673 | if (cy8c95x0_muxed_register(reg)) { |
674 | regmap = chip->muxed_regmap; |
675 | off = CY8C95X0_MUX_REGMAP_TO_OFFSET(reg, port); |
676 | } else { |
677 | regmap = chip->regmap; |
678 | /* Quick path direct access registers honor the port argument */ |
679 | if (cy8c95x0_quick_path_register(reg)) |
680 | off = reg + port; |
681 | else |
682 | off = reg; |
683 | } |
684 | |
685 | return regmap_read(map: regmap, reg: off, val: read_val); |
686 | } |
687 | |
688 | static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, |
689 | unsigned long *val, unsigned long *mask) |
690 | { |
691 | DECLARE_BITMAP(tmask, MAX_LINE); |
692 | DECLARE_BITMAP(tval, MAX_LINE); |
693 | int write_val; |
694 | int ret = 0; |
695 | int i; |
696 | u8 bits; |
697 | |
698 | /* Add the 4 bit gap of Gport2 */ |
699 | bitmap_andnot(dst: tmask, src1: mask, src2: chip->shiftmask, MAX_LINE); |
700 | bitmap_shift_left(dst: tmask, src: tmask, shift: 4, MAX_LINE); |
701 | bitmap_replace(dst: tmask, old: tmask, new: mask, mask: chip->shiftmask, BANK_SZ * 3); |
702 | |
703 | bitmap_andnot(dst: tval, src1: val, src2: chip->shiftmask, MAX_LINE); |
704 | bitmap_shift_left(dst: tval, src: tval, shift: 4, MAX_LINE); |
705 | bitmap_replace(dst: tval, old: tval, new: val, mask: chip->shiftmask, BANK_SZ * 3); |
706 | |
707 | for (i = 0; i < chip->nport; i++) { |
708 | /* Skip over unused banks */ |
709 | bits = bitmap_get_value8(map: tmask, start: i * BANK_SZ); |
710 | if (!bits) |
711 | continue; |
712 | |
713 | write_val = bitmap_get_value8(map: tval, start: i * BANK_SZ); |
714 | |
715 | ret = cy8c95x0_regmap_update_bits(chip, reg, port: i, mask: bits, val: write_val); |
716 | if (ret < 0) |
717 | goto out; |
718 | } |
719 | out: |
720 | |
721 | if (ret < 0) |
722 | dev_err(chip->dev, "failed writing register %d, port %d: err %d\n" , reg, i, ret); |
723 | |
724 | return ret; |
725 | } |
726 | |
727 | static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, |
728 | unsigned long *val, unsigned long *mask) |
729 | { |
730 | DECLARE_BITMAP(tmask, MAX_LINE); |
731 | DECLARE_BITMAP(tval, MAX_LINE); |
732 | DECLARE_BITMAP(tmp, MAX_LINE); |
733 | int read_val; |
734 | int ret = 0; |
735 | int i; |
736 | u8 bits; |
737 | |
738 | /* Add the 4 bit gap of Gport2 */ |
739 | bitmap_andnot(dst: tmask, src1: mask, src2: chip->shiftmask, MAX_LINE); |
740 | bitmap_shift_left(dst: tmask, src: tmask, shift: 4, MAX_LINE); |
741 | bitmap_replace(dst: tmask, old: tmask, new: mask, mask: chip->shiftmask, BANK_SZ * 3); |
742 | |
743 | bitmap_andnot(dst: tval, src1: val, src2: chip->shiftmask, MAX_LINE); |
744 | bitmap_shift_left(dst: tval, src: tval, shift: 4, MAX_LINE); |
745 | bitmap_replace(dst: tval, old: tval, new: val, mask: chip->shiftmask, BANK_SZ * 3); |
746 | |
747 | for (i = 0; i < chip->nport; i++) { |
748 | /* Skip over unused banks */ |
749 | bits = bitmap_get_value8(map: tmask, start: i * BANK_SZ); |
750 | if (!bits) |
751 | continue; |
752 | |
753 | ret = cy8c95x0_regmap_read(chip, reg, port: i, read_val: &read_val); |
754 | if (ret < 0) |
755 | goto out; |
756 | |
757 | read_val &= bits; |
758 | read_val |= bitmap_get_value8(map: tval, start: i * BANK_SZ) & ~bits; |
759 | bitmap_set_value8(map: tval, value: read_val, start: i * BANK_SZ); |
760 | } |
761 | |
762 | /* Fill the 4 bit gap of Gport2 */ |
763 | bitmap_shift_right(dst: tmp, src: tval, shift: 4, MAX_LINE); |
764 | bitmap_replace(dst: val, old: tmp, new: tval, mask: chip->shiftmask, MAX_LINE); |
765 | |
766 | out: |
767 | if (ret < 0) |
768 | dev_err(chip->dev, "failed reading register %d, port %d: err %d\n" , reg, i, ret); |
769 | |
770 | return ret; |
771 | } |
772 | |
773 | static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) |
774 | { |
775 | return pinctrl_gpio_direction_input(gc, offset: off); |
776 | } |
777 | |
778 | static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, |
779 | unsigned int off, int val) |
780 | { |
781 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
782 | u8 port = cypress_get_port(chip, pin: off); |
783 | u8 bit = cypress_get_pin_mask(chip, pin: off); |
784 | int ret; |
785 | |
786 | /* Set output level */ |
787 | ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, mask: bit, val: val ? bit : 0); |
788 | if (ret) |
789 | return ret; |
790 | |
791 | return pinctrl_gpio_direction_output(gc, offset: off); |
792 | } |
793 | |
794 | static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) |
795 | { |
796 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
797 | u8 port = cypress_get_port(chip, pin: off); |
798 | u8 bit = cypress_get_pin_mask(chip, pin: off); |
799 | u32 reg_val; |
800 | int ret; |
801 | |
802 | ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, read_val: ®_val); |
803 | if (ret < 0) { |
804 | /* |
805 | * NOTE: |
806 | * Diagnostic already emitted; that's all we should |
807 | * do unless gpio_*_value_cansleep() calls become different |
808 | * from their nonsleeping siblings (and report faults). |
809 | */ |
810 | return 0; |
811 | } |
812 | |
813 | return !!(reg_val & bit); |
814 | } |
815 | |
816 | static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off, |
817 | int val) |
818 | { |
819 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
820 | u8 port = cypress_get_port(chip, pin: off); |
821 | u8 bit = cypress_get_pin_mask(chip, pin: off); |
822 | |
823 | cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, mask: bit, val: val ? bit : 0); |
824 | } |
825 | |
826 | static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off) |
827 | { |
828 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
829 | u8 port = cypress_get_port(chip, pin: off); |
830 | u8 bit = cypress_get_pin_mask(chip, pin: off); |
831 | u32 reg_val; |
832 | int ret; |
833 | |
834 | ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, read_val: ®_val); |
835 | if (ret < 0) |
836 | goto out; |
837 | |
838 | if (reg_val & bit) |
839 | return GPIO_LINE_DIRECTION_IN; |
840 | |
841 | return GPIO_LINE_DIRECTION_OUT; |
842 | out: |
843 | return ret; |
844 | } |
845 | |
846 | static int cy8c95x0_gpio_get_pincfg(struct cy8c95x0_pinctrl *chip, |
847 | unsigned int off, |
848 | unsigned long *config) |
849 | { |
850 | enum pin_config_param param = pinconf_to_config_param(config: *config); |
851 | u8 port = cypress_get_port(chip, pin: off); |
852 | u8 bit = cypress_get_pin_mask(chip, pin: off); |
853 | unsigned int reg; |
854 | u32 reg_val; |
855 | u16 arg = 0; |
856 | int ret; |
857 | |
858 | switch (param) { |
859 | case PIN_CONFIG_BIAS_PULL_UP: |
860 | reg = CY8C95X0_DRV_PU; |
861 | break; |
862 | case PIN_CONFIG_BIAS_PULL_DOWN: |
863 | reg = CY8C95X0_DRV_PD; |
864 | break; |
865 | case PIN_CONFIG_BIAS_DISABLE: |
866 | reg = CY8C95X0_DRV_HIZ; |
867 | break; |
868 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
869 | reg = CY8C95X0_DRV_ODL; |
870 | break; |
871 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
872 | reg = CY8C95X0_DRV_ODH; |
873 | break; |
874 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
875 | reg = CY8C95X0_DRV_PP_FAST; |
876 | break; |
877 | case PIN_CONFIG_INPUT_ENABLE: |
878 | reg = CY8C95X0_DIRECTION; |
879 | break; |
880 | case PIN_CONFIG_MODE_PWM: |
881 | reg = CY8C95X0_PWMSEL; |
882 | break; |
883 | case PIN_CONFIG_OUTPUT: |
884 | reg = CY8C95X0_OUTPUT; |
885 | break; |
886 | case PIN_CONFIG_OUTPUT_ENABLE: |
887 | reg = CY8C95X0_DIRECTION; |
888 | break; |
889 | |
890 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
891 | case PIN_CONFIG_BIAS_BUS_HOLD: |
892 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: |
893 | case PIN_CONFIG_DRIVE_STRENGTH: |
894 | case PIN_CONFIG_DRIVE_STRENGTH_UA: |
895 | case PIN_CONFIG_INPUT_DEBOUNCE: |
896 | case PIN_CONFIG_INPUT_SCHMITT: |
897 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
898 | case PIN_CONFIG_MODE_LOW_POWER: |
899 | case PIN_CONFIG_PERSIST_STATE: |
900 | case PIN_CONFIG_POWER_SOURCE: |
901 | case PIN_CONFIG_SKEW_DELAY: |
902 | case PIN_CONFIG_SLEEP_HARDWARE_STATE: |
903 | case PIN_CONFIG_SLEW_RATE: |
904 | default: |
905 | ret = -ENOTSUPP; |
906 | goto out; |
907 | } |
908 | /* |
909 | * Writing 1 to one of the drive mode registers will automatically |
910 | * clear conflicting set bits in the other drive mode registers. |
911 | */ |
912 | ret = cy8c95x0_regmap_read(chip, reg, port, read_val: ®_val); |
913 | if (ret < 0) |
914 | goto out; |
915 | |
916 | if (reg_val & bit) |
917 | arg = 1; |
918 | if (param == PIN_CONFIG_OUTPUT_ENABLE) |
919 | arg = !arg; |
920 | |
921 | *config = pinconf_to_config_packed(param, argument: (u16)arg); |
922 | out: |
923 | return ret; |
924 | } |
925 | |
926 | static int cy8c95x0_gpio_set_pincfg(struct cy8c95x0_pinctrl *chip, |
927 | unsigned int off, |
928 | unsigned long config) |
929 | { |
930 | u8 port = cypress_get_port(chip, pin: off); |
931 | u8 bit = cypress_get_pin_mask(chip, pin: off); |
932 | unsigned long param = pinconf_to_config_param(config); |
933 | unsigned long arg = pinconf_to_config_argument(config); |
934 | unsigned int reg; |
935 | int ret; |
936 | |
937 | switch (param) { |
938 | case PIN_CONFIG_BIAS_PULL_UP: |
939 | __clear_bit(off, chip->push_pull); |
940 | reg = CY8C95X0_DRV_PU; |
941 | break; |
942 | case PIN_CONFIG_BIAS_PULL_DOWN: |
943 | __clear_bit(off, chip->push_pull); |
944 | reg = CY8C95X0_DRV_PD; |
945 | break; |
946 | case PIN_CONFIG_BIAS_DISABLE: |
947 | __clear_bit(off, chip->push_pull); |
948 | reg = CY8C95X0_DRV_HIZ; |
949 | break; |
950 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
951 | __clear_bit(off, chip->push_pull); |
952 | reg = CY8C95X0_DRV_ODL; |
953 | break; |
954 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
955 | __clear_bit(off, chip->push_pull); |
956 | reg = CY8C95X0_DRV_ODH; |
957 | break; |
958 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
959 | __set_bit(off, chip->push_pull); |
960 | reg = CY8C95X0_DRV_PP_FAST; |
961 | break; |
962 | case PIN_CONFIG_MODE_PWM: |
963 | reg = CY8C95X0_PWMSEL; |
964 | break; |
965 | case PIN_CONFIG_OUTPUT_ENABLE: |
966 | ret = cy8c95x0_pinmux_direction(chip, pin: off, input: !arg); |
967 | goto out; |
968 | case PIN_CONFIG_INPUT_ENABLE: |
969 | ret = cy8c95x0_pinmux_direction(chip, pin: off, input: arg); |
970 | goto out; |
971 | default: |
972 | ret = -ENOTSUPP; |
973 | goto out; |
974 | } |
975 | /* |
976 | * Writing 1 to one of the drive mode registers will automatically |
977 | * clear conflicting set bits in the other drive mode registers. |
978 | */ |
979 | ret = cy8c95x0_regmap_write_bits(chip, reg, port, mask: bit, val: bit); |
980 | out: |
981 | return ret; |
982 | } |
983 | |
984 | static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc, |
985 | unsigned long *mask, unsigned long *bits) |
986 | { |
987 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
988 | |
989 | return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, val: bits, mask); |
990 | } |
991 | |
992 | static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc, |
993 | unsigned long *mask, unsigned long *bits) |
994 | { |
995 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
996 | |
997 | cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, val: bits, mask); |
998 | } |
999 | |
1000 | static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc) |
1001 | { |
1002 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
1003 | struct device *dev = chip->dev; |
1004 | int ret; |
1005 | |
1006 | ret = gpiochip_add_pin_range(gc, pinctl_name: dev_name(dev), gpio_offset: 0, pin_offset: 0, npins: chip->tpin); |
1007 | if (ret) |
1008 | dev_err(dev, "failed to add GPIO pin range\n" ); |
1009 | |
1010 | return ret; |
1011 | } |
1012 | |
1013 | static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) |
1014 | { |
1015 | struct gpio_chip *gc = &chip->gpio_chip; |
1016 | |
1017 | gc->request = gpiochip_generic_request; |
1018 | gc->free = gpiochip_generic_free; |
1019 | gc->direction_input = cy8c95x0_gpio_direction_input; |
1020 | gc->direction_output = cy8c95x0_gpio_direction_output; |
1021 | gc->get = cy8c95x0_gpio_get_value; |
1022 | gc->set = cy8c95x0_gpio_set_value; |
1023 | gc->get_direction = cy8c95x0_gpio_get_direction; |
1024 | gc->get_multiple = cy8c95x0_gpio_get_multiple; |
1025 | gc->set_multiple = cy8c95x0_gpio_set_multiple; |
1026 | gc->set_config = gpiochip_generic_config; |
1027 | gc->can_sleep = true; |
1028 | gc->add_pin_ranges = cy8c95x0_add_pin_ranges; |
1029 | |
1030 | gc->base = -1; |
1031 | gc->ngpio = chip->tpin; |
1032 | |
1033 | gc->parent = chip->dev; |
1034 | gc->owner = THIS_MODULE; |
1035 | gc->names = NULL; |
1036 | |
1037 | gc->label = dev_name(dev: chip->dev); |
1038 | |
1039 | return devm_gpiochip_add_data(chip->dev, gc, chip); |
1040 | } |
1041 | |
1042 | static void cy8c95x0_irq_mask(struct irq_data *d) |
1043 | { |
1044 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
1045 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
1046 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
1047 | |
1048 | set_bit(nr: hwirq, addr: chip->irq_mask); |
1049 | gpiochip_disable_irq(gc, offset: hwirq); |
1050 | } |
1051 | |
1052 | static void cy8c95x0_irq_unmask(struct irq_data *d) |
1053 | { |
1054 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
1055 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
1056 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
1057 | |
1058 | gpiochip_enable_irq(gc, offset: hwirq); |
1059 | clear_bit(nr: hwirq, addr: chip->irq_mask); |
1060 | } |
1061 | |
1062 | static void cy8c95x0_irq_bus_lock(struct irq_data *d) |
1063 | { |
1064 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
1065 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
1066 | |
1067 | mutex_lock(&chip->irq_lock); |
1068 | } |
1069 | |
1070 | static void cy8c95x0_irq_bus_sync_unlock(struct irq_data *d) |
1071 | { |
1072 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
1073 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
1074 | DECLARE_BITMAP(ones, MAX_LINE); |
1075 | DECLARE_BITMAP(irq_mask, MAX_LINE); |
1076 | DECLARE_BITMAP(reg_direction, MAX_LINE); |
1077 | |
1078 | bitmap_fill(dst: ones, MAX_LINE); |
1079 | |
1080 | cy8c95x0_write_regs_mask(chip, CY8C95X0_INTMASK, val: chip->irq_mask, mask: ones); |
1081 | |
1082 | /* Switch direction to input if needed */ |
1083 | cy8c95x0_read_regs_mask(chip, CY8C95X0_DIRECTION, val: reg_direction, mask: chip->irq_mask); |
1084 | bitmap_or(dst: irq_mask, src1: chip->irq_mask, src2: reg_direction, MAX_LINE); |
1085 | bitmap_complement(dst: irq_mask, src: irq_mask, MAX_LINE); |
1086 | |
1087 | /* Look for any newly setup interrupt */ |
1088 | cy8c95x0_write_regs_mask(chip, CY8C95X0_DIRECTION, val: ones, mask: irq_mask); |
1089 | |
1090 | mutex_unlock(lock: &chip->irq_lock); |
1091 | } |
1092 | |
1093 | static int cy8c95x0_irq_set_type(struct irq_data *d, unsigned int type) |
1094 | { |
1095 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
1096 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
1097 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
1098 | unsigned int trig_type; |
1099 | |
1100 | switch (type) { |
1101 | case IRQ_TYPE_EDGE_RISING: |
1102 | case IRQ_TYPE_EDGE_FALLING: |
1103 | case IRQ_TYPE_EDGE_BOTH: |
1104 | trig_type = type; |
1105 | break; |
1106 | case IRQ_TYPE_LEVEL_HIGH: |
1107 | trig_type = IRQ_TYPE_EDGE_RISING; |
1108 | break; |
1109 | case IRQ_TYPE_LEVEL_LOW: |
1110 | trig_type = IRQ_TYPE_EDGE_FALLING; |
1111 | break; |
1112 | default: |
1113 | dev_err(chip->dev, "irq %d: unsupported type %d\n" , d->irq, type); |
1114 | return -EINVAL; |
1115 | } |
1116 | |
1117 | assign_bit(nr: hwirq, addr: chip->irq_trig_fall, value: trig_type & IRQ_TYPE_EDGE_FALLING); |
1118 | assign_bit(nr: hwirq, addr: chip->irq_trig_raise, value: trig_type & IRQ_TYPE_EDGE_RISING); |
1119 | assign_bit(nr: hwirq, addr: chip->irq_trig_low, value: type == IRQ_TYPE_LEVEL_LOW); |
1120 | assign_bit(nr: hwirq, addr: chip->irq_trig_high, value: type == IRQ_TYPE_LEVEL_HIGH); |
1121 | |
1122 | return 0; |
1123 | } |
1124 | |
1125 | static void cy8c95x0_irq_shutdown(struct irq_data *d) |
1126 | { |
1127 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
1128 | struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); |
1129 | irq_hw_number_t hwirq = irqd_to_hwirq(d); |
1130 | |
1131 | clear_bit(nr: hwirq, addr: chip->irq_trig_raise); |
1132 | clear_bit(nr: hwirq, addr: chip->irq_trig_fall); |
1133 | clear_bit(nr: hwirq, addr: chip->irq_trig_low); |
1134 | clear_bit(nr: hwirq, addr: chip->irq_trig_high); |
1135 | } |
1136 | |
1137 | static const struct irq_chip cy8c95x0_irqchip = { |
1138 | .name = "cy8c95x0-irq" , |
1139 | .irq_mask = cy8c95x0_irq_mask, |
1140 | .irq_unmask = cy8c95x0_irq_unmask, |
1141 | .irq_bus_lock = cy8c95x0_irq_bus_lock, |
1142 | .irq_bus_sync_unlock = cy8c95x0_irq_bus_sync_unlock, |
1143 | .irq_set_type = cy8c95x0_irq_set_type, |
1144 | .irq_shutdown = cy8c95x0_irq_shutdown, |
1145 | .flags = IRQCHIP_IMMUTABLE, |
1146 | GPIOCHIP_IRQ_RESOURCE_HELPERS, |
1147 | }; |
1148 | |
1149 | static bool cy8c95x0_irq_pending(struct cy8c95x0_pinctrl *chip, unsigned long *pending) |
1150 | { |
1151 | DECLARE_BITMAP(ones, MAX_LINE); |
1152 | DECLARE_BITMAP(cur_stat, MAX_LINE); |
1153 | DECLARE_BITMAP(new_stat, MAX_LINE); |
1154 | DECLARE_BITMAP(trigger, MAX_LINE); |
1155 | |
1156 | bitmap_fill(dst: ones, MAX_LINE); |
1157 | |
1158 | /* Read the current interrupt status from the device */ |
1159 | if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INTSTATUS, val: trigger, mask: ones)) |
1160 | return false; |
1161 | |
1162 | /* Check latched inputs */ |
1163 | if (cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, val: cur_stat, mask: trigger)) |
1164 | return false; |
1165 | |
1166 | /* Apply filter for rising/falling edge selection */ |
1167 | bitmap_replace(dst: new_stat, old: chip->irq_trig_fall, new: chip->irq_trig_raise, |
1168 | mask: cur_stat, MAX_LINE); |
1169 | |
1170 | bitmap_and(dst: pending, src1: new_stat, src2: trigger, MAX_LINE); |
1171 | |
1172 | return !bitmap_empty(src: pending, MAX_LINE); |
1173 | } |
1174 | |
1175 | static irqreturn_t cy8c95x0_irq_handler(int irq, void *devid) |
1176 | { |
1177 | struct cy8c95x0_pinctrl *chip = devid; |
1178 | struct gpio_chip *gc = &chip->gpio_chip; |
1179 | DECLARE_BITMAP(pending, MAX_LINE); |
1180 | int nested_irq, level; |
1181 | bool ret; |
1182 | |
1183 | ret = cy8c95x0_irq_pending(chip, pending); |
1184 | if (!ret) |
1185 | return IRQ_RETVAL(0); |
1186 | |
1187 | ret = 0; |
1188 | for_each_set_bit(level, pending, MAX_LINE) { |
1189 | /* Already accounted for 4bit gap in GPort2 */ |
1190 | nested_irq = irq_find_mapping(domain: gc->irq.domain, hwirq: level); |
1191 | |
1192 | if (unlikely(nested_irq <= 0)) { |
1193 | dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n" , level); |
1194 | continue; |
1195 | } |
1196 | |
1197 | if (test_bit(level, chip->irq_trig_low)) |
1198 | while (!cy8c95x0_gpio_get_value(gc, off: level)) |
1199 | handle_nested_irq(irq: nested_irq); |
1200 | else if (test_bit(level, chip->irq_trig_high)) |
1201 | while (cy8c95x0_gpio_get_value(gc, off: level)) |
1202 | handle_nested_irq(irq: nested_irq); |
1203 | else |
1204 | handle_nested_irq(irq: nested_irq); |
1205 | |
1206 | ret = 1; |
1207 | } |
1208 | |
1209 | return IRQ_RETVAL(ret); |
1210 | } |
1211 | |
1212 | static int cy8c95x0_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) |
1213 | { |
1214 | struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); |
1215 | |
1216 | return chip->tpin; |
1217 | } |
1218 | |
1219 | static const char *cy8c95x0_pinctrl_get_group_name(struct pinctrl_dev *pctldev, |
1220 | unsigned int group) |
1221 | { |
1222 | return cy8c95x0_groups[group]; |
1223 | } |
1224 | |
1225 | static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, |
1226 | unsigned int group, |
1227 | const unsigned int **pins, |
1228 | unsigned int *num_pins) |
1229 | { |
1230 | *pins = &cy8c9560_pins[group].number; |
1231 | *num_pins = 1; |
1232 | return 0; |
1233 | } |
1234 | |
1235 | static const char *cy8c95x0_get_fname(unsigned int selector) |
1236 | { |
1237 | if (selector == 0) |
1238 | return "gpio" ; |
1239 | else |
1240 | return "pwm" ; |
1241 | } |
1242 | |
1243 | static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1244 | unsigned int pin) |
1245 | { |
1246 | struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); |
1247 | DECLARE_BITMAP(mask, MAX_LINE); |
1248 | DECLARE_BITMAP(pwm, MAX_LINE); |
1249 | |
1250 | bitmap_zero(dst: mask, MAX_LINE); |
1251 | __set_bit(pin, mask); |
1252 | |
1253 | if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, val: pwm, mask)) { |
1254 | seq_puts(m: s, s: "not available" ); |
1255 | return; |
1256 | } |
1257 | |
1258 | seq_printf(m: s, fmt: "MODE:%s" , cy8c95x0_get_fname(test_bit(pin, pwm))); |
1259 | } |
1260 | |
1261 | static const struct pinctrl_ops cy8c95x0_pinctrl_ops = { |
1262 | .get_groups_count = cy8c95x0_pinctrl_get_groups_count, |
1263 | .get_group_name = cy8c95x0_pinctrl_get_group_name, |
1264 | .get_group_pins = cy8c95x0_pinctrl_get_group_pins, |
1265 | #ifdef CONFIG_OF |
1266 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, |
1267 | .dt_free_map = pinconf_generic_dt_free_map, |
1268 | #endif |
1269 | .pin_dbg_show = cy8c95x0_pin_dbg_show, |
1270 | }; |
1271 | |
1272 | static const char *cy8c95x0_get_function_name(struct pinctrl_dev *pctldev, unsigned int selector) |
1273 | { |
1274 | return cy8c95x0_get_fname(selector); |
1275 | } |
1276 | |
1277 | static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev) |
1278 | { |
1279 | return 2; |
1280 | } |
1281 | |
1282 | static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, |
1283 | const char * const **groups, |
1284 | unsigned int * const num_groups) |
1285 | { |
1286 | struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); |
1287 | |
1288 | *groups = cy8c95x0_groups; |
1289 | *num_groups = chip->tpin; |
1290 | return 0; |
1291 | } |
1292 | |
1293 | static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) |
1294 | { |
1295 | u8 port = cypress_get_port(chip, pin: off); |
1296 | u8 bit = cypress_get_pin_mask(chip, pin: off); |
1297 | |
1298 | return cy8c95x0_regmap_write_bits(chip, CY8C95X0_PWMSEL, port, mask: bit, val: mode ? bit : 0); |
1299 | } |
1300 | |
1301 | static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, |
1302 | unsigned int selector, unsigned int group) |
1303 | { |
1304 | u8 port = cypress_get_port(chip, pin: group); |
1305 | u8 bit = cypress_get_pin_mask(chip, pin: group); |
1306 | int ret; |
1307 | |
1308 | ret = cy8c95x0_set_mode(chip, off: group, mode: selector); |
1309 | if (ret < 0) |
1310 | return ret; |
1311 | |
1312 | if (selector == 0) |
1313 | return 0; |
1314 | |
1315 | /* Set direction to output & set output to 1 so that PWM can work */ |
1316 | ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, mask: bit, val: bit); |
1317 | if (ret < 0) |
1318 | return ret; |
1319 | |
1320 | return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, mask: bit, val: bit); |
1321 | } |
1322 | |
1323 | static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, |
1324 | unsigned int group) |
1325 | { |
1326 | struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); |
1327 | |
1328 | return cy8c95x0_pinmux_mode(chip, selector, group); |
1329 | } |
1330 | |
1331 | static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, |
1332 | struct pinctrl_gpio_range *range, |
1333 | unsigned int pin) |
1334 | { |
1335 | struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); |
1336 | |
1337 | return cy8c95x0_set_mode(chip, off: pin, mode: false); |
1338 | } |
1339 | |
1340 | static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, |
1341 | unsigned int pin, bool input) |
1342 | { |
1343 | u8 port = cypress_get_port(chip, pin); |
1344 | u8 bit = cypress_get_pin_mask(chip, pin); |
1345 | int ret; |
1346 | |
1347 | ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DIRECTION, port, mask: bit, val: input ? bit : 0); |
1348 | if (ret) |
1349 | return ret; |
1350 | |
1351 | /* |
1352 | * Disable driving the pin by forcing it to HighZ. Only setting |
1353 | * the direction register isn't sufficient in Push-Pull mode. |
1354 | */ |
1355 | if (input && test_bit(pin, chip->push_pull)) { |
1356 | ret = cy8c95x0_regmap_write_bits(chip, CY8C95X0_DRV_HIZ, port, mask: bit, val: bit); |
1357 | if (ret) |
1358 | return ret; |
1359 | |
1360 | __clear_bit(pin, chip->push_pull); |
1361 | } |
1362 | |
1363 | return 0; |
1364 | } |
1365 | |
1366 | static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, |
1367 | struct pinctrl_gpio_range *range, |
1368 | unsigned int pin, bool input) |
1369 | { |
1370 | struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); |
1371 | |
1372 | return cy8c95x0_pinmux_direction(chip, pin, input); |
1373 | } |
1374 | |
1375 | static const struct pinmux_ops cy8c95x0_pmxops = { |
1376 | .get_functions_count = cy8c95x0_get_functions_count, |
1377 | .get_function_name = cy8c95x0_get_function_name, |
1378 | .get_function_groups = cy8c95x0_get_function_groups, |
1379 | .set_mux = cy8c95x0_set_mux, |
1380 | .gpio_request_enable = cy8c95x0_gpio_request_enable, |
1381 | .gpio_set_direction = cy8c95x0_gpio_set_direction, |
1382 | .strict = true, |
1383 | }; |
1384 | |
1385 | static int cy8c95x0_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, |
1386 | unsigned long *config) |
1387 | { |
1388 | struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); |
1389 | |
1390 | return cy8c95x0_gpio_get_pincfg(chip, off: pin, config); |
1391 | } |
1392 | |
1393 | static int cy8c95x0_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, |
1394 | unsigned long *configs, unsigned int num_configs) |
1395 | { |
1396 | struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); |
1397 | int ret = 0; |
1398 | int i; |
1399 | |
1400 | for (i = 0; i < num_configs; i++) { |
1401 | ret = cy8c95x0_gpio_set_pincfg(chip, off: pin, config: configs[i]); |
1402 | if (ret) |
1403 | return ret; |
1404 | } |
1405 | |
1406 | return ret; |
1407 | } |
1408 | |
1409 | static const struct pinconf_ops cy8c95x0_pinconf_ops = { |
1410 | .pin_config_get = cy8c95x0_pinconf_get, |
1411 | .pin_config_set = cy8c95x0_pinconf_set, |
1412 | .is_generic = true, |
1413 | }; |
1414 | |
1415 | static int cy8c95x0_irq_setup(struct cy8c95x0_pinctrl *chip, int irq) |
1416 | { |
1417 | struct gpio_irq_chip *girq = &chip->gpio_chip.irq; |
1418 | DECLARE_BITMAP(pending_irqs, MAX_LINE); |
1419 | int ret; |
1420 | |
1421 | mutex_init(&chip->irq_lock); |
1422 | |
1423 | bitmap_zero(dst: pending_irqs, MAX_LINE); |
1424 | |
1425 | /* Read IRQ status register to clear all pending interrupts */ |
1426 | ret = cy8c95x0_irq_pending(chip, pending: pending_irqs); |
1427 | if (ret) { |
1428 | dev_err(chip->dev, "failed to clear irq status register\n" ); |
1429 | return ret; |
1430 | } |
1431 | |
1432 | /* Mask all interrupts */ |
1433 | bitmap_fill(dst: chip->irq_mask, MAX_LINE); |
1434 | |
1435 | gpio_irq_chip_set_chip(girq, chip: &cy8c95x0_irqchip); |
1436 | |
1437 | /* This will let us handle the parent IRQ in the driver */ |
1438 | girq->parent_handler = NULL; |
1439 | girq->num_parents = 0; |
1440 | girq->parents = NULL; |
1441 | girq->default_type = IRQ_TYPE_NONE; |
1442 | girq->handler = handle_simple_irq; |
1443 | girq->threaded = true; |
1444 | |
1445 | ret = devm_request_threaded_irq(dev: chip->dev, irq, |
1446 | NULL, thread_fn: cy8c95x0_irq_handler, |
1447 | IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_HIGH, |
1448 | devname: dev_name(dev: chip->dev), dev_id: chip); |
1449 | if (ret) { |
1450 | dev_err(chip->dev, "failed to request irq %d\n" , irq); |
1451 | return ret; |
1452 | } |
1453 | dev_info(chip->dev, "Registered threaded IRQ\n" ); |
1454 | |
1455 | return 0; |
1456 | } |
1457 | |
1458 | static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip) |
1459 | { |
1460 | struct pinctrl_desc *pd = &chip->pinctrl_desc; |
1461 | |
1462 | pd->pctlops = &cy8c95x0_pinctrl_ops; |
1463 | pd->confops = &cy8c95x0_pinconf_ops; |
1464 | pd->pmxops = &cy8c95x0_pmxops; |
1465 | pd->name = dev_name(dev: chip->dev); |
1466 | pd->pins = cy8c9560_pins; |
1467 | pd->npins = chip->tpin; |
1468 | pd->owner = THIS_MODULE; |
1469 | |
1470 | chip->pctldev = devm_pinctrl_register(dev: chip->dev, pctldesc: pd, driver_data: chip); |
1471 | if (IS_ERR(ptr: chip->pctldev)) |
1472 | return dev_err_probe(dev: chip->dev, err: PTR_ERR(ptr: chip->pctldev), |
1473 | fmt: "can't register controller\n" ); |
1474 | |
1475 | return 0; |
1476 | } |
1477 | |
1478 | static int cy8c95x0_detect(struct i2c_client *client, |
1479 | struct i2c_board_info *info) |
1480 | { |
1481 | struct i2c_adapter *adapter = client->adapter; |
1482 | int ret; |
1483 | const char *name; |
1484 | |
1485 | if (!i2c_check_functionality(adap: adapter, I2C_FUNC_SMBUS_BYTE_DATA)) |
1486 | return -ENODEV; |
1487 | |
1488 | ret = i2c_smbus_read_byte_data(client, CY8C95X0_DEVID); |
1489 | if (ret < 0) |
1490 | return ret; |
1491 | switch (ret & GENMASK(7, 4)) { |
1492 | case 0x20: |
1493 | name = cy8c95x0_id[0].name; |
1494 | break; |
1495 | case 0x40: |
1496 | name = cy8c95x0_id[1].name; |
1497 | break; |
1498 | case 0x60: |
1499 | name = cy8c95x0_id[2].name; |
1500 | break; |
1501 | default: |
1502 | return -ENODEV; |
1503 | } |
1504 | |
1505 | dev_info(&client->dev, "Found a %s chip at 0x%02x.\n" , name, client->addr); |
1506 | strscpy(info->type, name, I2C_NAME_SIZE); |
1507 | |
1508 | return 0; |
1509 | } |
1510 | |
1511 | static int cy8c95x0_probe(struct i2c_client *client) |
1512 | { |
1513 | struct cy8c95x0_pinctrl *chip; |
1514 | struct regulator *reg; |
1515 | int ret; |
1516 | |
1517 | chip = devm_kzalloc(dev: &client->dev, size: sizeof(*chip), GFP_KERNEL); |
1518 | if (!chip) |
1519 | return -ENOMEM; |
1520 | |
1521 | chip->dev = &client->dev; |
1522 | |
1523 | /* Set the device type */ |
1524 | chip->driver_data = (uintptr_t)i2c_get_match_data(client); |
1525 | if (!chip->driver_data) |
1526 | return -ENODEV; |
1527 | |
1528 | i2c_set_clientdata(client, data: chip); |
1529 | |
1530 | chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK; |
1531 | chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ); |
1532 | |
1533 | switch (chip->tpin) { |
1534 | case 20: |
1535 | strscpy(chip->name, cy8c95x0_id[0].name, I2C_NAME_SIZE); |
1536 | break; |
1537 | case 40: |
1538 | strscpy(chip->name, cy8c95x0_id[1].name, I2C_NAME_SIZE); |
1539 | break; |
1540 | case 60: |
1541 | strscpy(chip->name, cy8c95x0_id[2].name, I2C_NAME_SIZE); |
1542 | break; |
1543 | default: |
1544 | return -ENODEV; |
1545 | } |
1546 | |
1547 | reg = devm_regulator_get(dev: &client->dev, id: "vdd" ); |
1548 | if (IS_ERR(ptr: reg)) { |
1549 | if (PTR_ERR(ptr: reg) == -EPROBE_DEFER) |
1550 | return -EPROBE_DEFER; |
1551 | } else { |
1552 | ret = regulator_enable(regulator: reg); |
1553 | if (ret) { |
1554 | dev_err(&client->dev, "failed to enable regulator vdd: %d\n" , ret); |
1555 | return ret; |
1556 | } |
1557 | chip->regulator = reg; |
1558 | } |
1559 | |
1560 | /* bring the chip out of reset if reset pin is provided */ |
1561 | chip->gpio_reset = devm_gpiod_get_optional(dev: &client->dev, con_id: "reset" , flags: GPIOD_OUT_HIGH); |
1562 | if (IS_ERR(ptr: chip->gpio_reset)) { |
1563 | ret = dev_err_probe(dev: chip->dev, err: PTR_ERR(ptr: chip->gpio_reset), |
1564 | fmt: "Failed to get GPIO 'reset'\n" ); |
1565 | goto err_exit; |
1566 | } else if (chip->gpio_reset) { |
1567 | usleep_range(min: 1000, max: 2000); |
1568 | gpiod_set_value_cansleep(desc: chip->gpio_reset, value: 0); |
1569 | usleep_range(min: 250000, max: 300000); |
1570 | |
1571 | gpiod_set_consumer_name(desc: chip->gpio_reset, name: "CY8C95X0 RESET" ); |
1572 | } |
1573 | |
1574 | /* Generic regmap for direct access registers */ |
1575 | chip->regmap = devm_regmap_init_i2c(client, &cy8c95x0_i2c_regmap); |
1576 | if (IS_ERR(ptr: chip->regmap)) { |
1577 | ret = PTR_ERR(ptr: chip->regmap); |
1578 | goto err_exit; |
1579 | } |
1580 | |
1581 | /* Port specific regmap behind PORTSEL mux */ |
1582 | chip->muxed_regmap = devm_regmap_init(&client->dev, &cy8c95x0_regmap_bus, |
1583 | chip, &cy8c95x0_muxed_regmap); |
1584 | if (IS_ERR(ptr: chip->muxed_regmap)) { |
1585 | ret = dev_err_probe(dev: &client->dev, err: PTR_ERR(ptr: chip->muxed_regmap), |
1586 | fmt: "Failed to register muxed regmap\n" ); |
1587 | goto err_exit; |
1588 | } |
1589 | |
1590 | bitmap_zero(dst: chip->push_pull, MAX_LINE); |
1591 | bitmap_zero(dst: chip->shiftmask, MAX_LINE); |
1592 | bitmap_set(map: chip->shiftmask, start: 0, nbits: 20); |
1593 | mutex_init(&chip->i2c_lock); |
1594 | |
1595 | if (dmi_first_match(list: cy8c95x0_dmi_acpi_irq_info)) { |
1596 | ret = cy8c95x0_acpi_get_irq(dev: &client->dev); |
1597 | if (ret > 0) |
1598 | client->irq = ret; |
1599 | } |
1600 | |
1601 | if (client->irq) { |
1602 | ret = cy8c95x0_irq_setup(chip, irq: client->irq); |
1603 | if (ret) |
1604 | goto err_exit; |
1605 | } |
1606 | |
1607 | ret = cy8c95x0_setup_pinctrl(chip); |
1608 | if (ret) |
1609 | goto err_exit; |
1610 | |
1611 | ret = cy8c95x0_setup_gpiochip(chip); |
1612 | if (ret) |
1613 | goto err_exit; |
1614 | |
1615 | return 0; |
1616 | |
1617 | err_exit: |
1618 | if (!IS_ERR_OR_NULL(ptr: chip->regulator)) |
1619 | regulator_disable(regulator: chip->regulator); |
1620 | return ret; |
1621 | } |
1622 | |
1623 | static void cy8c95x0_remove(struct i2c_client *client) |
1624 | { |
1625 | struct cy8c95x0_pinctrl *chip = i2c_get_clientdata(client); |
1626 | |
1627 | if (!IS_ERR_OR_NULL(ptr: chip->regulator)) |
1628 | regulator_disable(regulator: chip->regulator); |
1629 | } |
1630 | |
1631 | static const struct acpi_device_id cy8c95x0_acpi_ids[] = { |
1632 | { "INT3490" , 40, }, |
1633 | { } |
1634 | }; |
1635 | MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids); |
1636 | |
1637 | static struct i2c_driver cy8c95x0_driver = { |
1638 | .driver = { |
1639 | .name = "cy8c95x0-pinctrl" , |
1640 | .of_match_table = cy8c95x0_dt_ids, |
1641 | .acpi_match_table = cy8c95x0_acpi_ids, |
1642 | }, |
1643 | .probe = cy8c95x0_probe, |
1644 | .remove = cy8c95x0_remove, |
1645 | .id_table = cy8c95x0_id, |
1646 | .detect = cy8c95x0_detect, |
1647 | }; |
1648 | module_i2c_driver(cy8c95x0_driver); |
1649 | |
1650 | MODULE_AUTHOR("Patrick Rudolph <patrick.rudolph@9elements.com>" ); |
1651 | MODULE_AUTHOR("Naresh Solanki <naresh.solanki@9elements.com>" ); |
1652 | MODULE_DESCRIPTION("Pinctrl driver for CY8C95X0" ); |
1653 | MODULE_LICENSE("GPL" ); |
1654 | |