| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * PIC32 pinctrl driver |
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| 4 | * |
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| 5 | * Joshua Henderson, <joshua.henderson@microchip.com> |
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| 6 | * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. |
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| 7 | */ |
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| 8 | #ifndef PINCTRL_PINCTRL_PIC32_H |
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| 9 | #define PINCTRL_PINCTRL_PIC32_H |
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| 10 | |
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| 11 | /* PORT Registers */ |
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| 12 | #define ANSEL_REG 0x00 |
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| 13 | #define TRIS_REG 0x10 |
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| 14 | #define PORT_REG 0x20 |
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| 15 | #define LAT_REG 0x30 |
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| 16 | #define ODCU_REG 0x40 |
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| 17 | #define CNPU_REG 0x50 |
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| 18 | #define CNPD_REG 0x60 |
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| 19 | #define CNCON_REG 0x70 |
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| 20 | #define CNEN_REG 0x80 |
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| 21 | #define CNSTAT_REG 0x90 |
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| 22 | #define CNNE_REG 0xA0 |
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| 23 | #define CNF_REG 0xB0 |
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| 24 | |
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| 25 | /* Input PPS Registers */ |
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| 26 | #define INT1R 0x04 |
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| 27 | #define INT2R 0x08 |
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| 28 | #define INT3R 0x0C |
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| 29 | #define INT4R 0x10 |
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| 30 | #define T2CKR 0x18 |
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| 31 | #define T3CKR 0x1C |
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| 32 | #define T4CKR 0x20 |
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| 33 | #define T5CKR 0x24 |
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| 34 | #define T6CKR 0x28 |
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| 35 | #define T7CKR 0x2C |
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| 36 | #define T8CKR 0x30 |
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| 37 | #define T9CKR 0x34 |
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| 38 | #define IC1R 0x38 |
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| 39 | #define IC2R 0x3C |
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| 40 | #define IC3R 0x40 |
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| 41 | #define IC4R 0x44 |
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| 42 | #define IC5R 0x48 |
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| 43 | #define IC6R 0x4C |
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| 44 | #define IC7R 0x50 |
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| 45 | #define IC8R 0x54 |
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| 46 | #define IC9R 0x58 |
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| 47 | #define OCFAR 0x60 |
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| 48 | #define U1RXR 0x68 |
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| 49 | #define U1CTSR 0x6C |
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| 50 | #define U2RXR 0x70 |
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| 51 | #define U2CTSR 0x74 |
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| 52 | #define U3RXR 0x78 |
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| 53 | #define U3CTSR 0x7C |
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| 54 | #define U4RXR 0x80 |
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| 55 | #define U4CTSR 0x84 |
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| 56 | #define U5RXR 0x88 |
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| 57 | #define U5CTSR 0x8C |
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| 58 | #define U6RXR 0x90 |
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| 59 | #define U6CTSR 0x94 |
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| 60 | #define SDI1R 0x9C |
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| 61 | #define SS1INR 0xA0 |
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| 62 | #define SDI2R 0xA8 |
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| 63 | #define SS2INR 0xAC |
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| 64 | #define SDI3R 0xB4 |
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| 65 | #define SS3INR 0xB8 |
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| 66 | #define SDI4R 0xC0 |
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| 67 | #define SS4INR 0xC4 |
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| 68 | #define SDI5R 0xCC |
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| 69 | #define SS5INR 0xD0 |
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| 70 | #define SDI6R 0xD8 |
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| 71 | #define SS6INR 0xDC |
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| 72 | #define C1RXR 0xE0 |
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| 73 | #define C2RXR 0xE4 |
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| 74 | #define REFCLKI1R 0xE8 |
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| 75 | #define REFCLKI3R 0xF0 |
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| 76 | #define REFCLKI4R 0xF4 |
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| 77 | |
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| 78 | /* Output PPS Registers */ |
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| 79 | #define RPA14R 0x138 |
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| 80 | #define RPA15R 0x13C |
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| 81 | #define RPB0R 0x140 |
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| 82 | #define RPB1R 0x144 |
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| 83 | #define RPB2R 0x148 |
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| 84 | #define RPB3R 0x14C |
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| 85 | #define RPB5R 0x154 |
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| 86 | #define RPB6R 0x158 |
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| 87 | #define RPB7R 0x15C |
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| 88 | #define RPB8R 0x160 |
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| 89 | #define RPB9R 0x164 |
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| 90 | #define RPB10R 0x168 |
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| 91 | #define RPB14R 0x178 |
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| 92 | #define RPB15R 0x17C |
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| 93 | #define RPC1R 0x184 |
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| 94 | #define RPC2R 0x188 |
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| 95 | #define RPC3R 0x18C |
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| 96 | #define RPC4R 0x190 |
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| 97 | #define RPC13R 0x1B4 |
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| 98 | #define RPC14R 0x1B8 |
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| 99 | #define RPD0R 0x1C0 |
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| 100 | #define RPD1R 0x1C4 |
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| 101 | #define RPD2R 0x1C8 |
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| 102 | #define RPD3R 0x1CC |
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| 103 | #define RPD4R 0x1D0 |
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| 104 | #define RPD5R 0x1D4 |
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| 105 | #define RPD6R 0x1D8 |
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| 106 | #define RPD7R 0x1DC |
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| 107 | #define RPD9R 0x1E4 |
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| 108 | #define RPD10R 0x1E8 |
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| 109 | #define RPD11R 0x1EC |
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| 110 | #define RPD12R 0x1F0 |
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| 111 | #define RPD14R 0x1F8 |
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| 112 | #define RPD15R 0x1FC |
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| 113 | #define RPE3R 0x20C |
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| 114 | #define RPE5R 0x214 |
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| 115 | #define RPE8R 0x220 |
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| 116 | #define RPE9R 0x224 |
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| 117 | #define RPF0R 0x240 |
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| 118 | #define RPF1R 0x244 |
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| 119 | #define RPF2R 0x248 |
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| 120 | #define RPF3R 0x24C |
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| 121 | #define RPF4R 0x250 |
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| 122 | #define RPF5R 0x254 |
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| 123 | #define RPF8R 0x260 |
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| 124 | #define RPF12R 0x270 |
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| 125 | #define RPF13R 0x274 |
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| 126 | #define RPG0R 0x280 |
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| 127 | #define RPG1R 0x284 |
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| 128 | #define RPG6R 0x298 |
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| 129 | #define RPG7R 0x29C |
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| 130 | #define RPG8R 0x2A0 |
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| 131 | #define RPG9R 0x2A4 |
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| 132 | |
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| 133 | #endif /* PINCTRL_PINCTRL_PIC32_H */ |
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| 134 | |
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