1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Pinctrl driver for Rockchip SoCs
4	*
5	* Copyright (c) 2013 MundoReader S.L.
6	* Author: Heiko Stuebner <heiko@sntech.de>
7	*
8	* With some ideas taken from pinctrl-samsung:
9	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
10	* http://www.samsung.com
11	* Copyright (c) 2012 Linaro Ltd
12	* https://www.linaro.org
13	*
14	* and pinctrl-at91:
15	* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16	*/
17
18	#include <linux/init.h>
19	#include <linux/module.h>
20	#include <linux/platform_device.h>
21	#include <linux/io.h>
22	#include <linux/bitops.h>
23	#include <linux/gpio/driver.h>
24	#include <linux/of.h>
25	#include <linux/of_platform.h>
26	#include <linux/pinctrl/machine.h>
27	#include <linux/pinctrl/pinconf.h>
28	#include <linux/pinctrl/pinctrl.h>
29	#include <linux/pinctrl/pinmux.h>
30	#include <linux/pinctrl/pinconf-generic.h>
31	#include <linux/irqchip/chained_irq.h>
32	#include <linux/clk.h>
33	#include <linux/regmap.h>
34	#include <linux/mfd/syscon.h>
35	#include <linux/string_helpers.h>
36
37	#include <dt-bindings/pinctrl/rockchip.h>
38
39	#include "core.h"
40	#include "pinconf.h"
41	#include "pinctrl-rockchip.h"
42
43	/*
44	* Generate a bitmask for setting a value (v) with a write mask bit in hiword
45	* register 31:16 area.
46	*/
47	#define WRITE_MASK_VAL(h, l, v) \
48	(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
49
50	/*
51	* Encode variants of iomux registers into a type variable
52	*/
53	#define IOMUX_GPIO_ONLY BIT(0)
54	#define IOMUX_WIDTH_4BIT BIT(1)
55	#define IOMUX_SOURCE_PMU BIT(2)
56	#define IOMUX_UNROUTED BIT(3)
57	#define IOMUX_WIDTH_3BIT BIT(4)
58	#define IOMUX_WIDTH_2BIT BIT(5)
59	#define IOMUX_L_SOURCE_PMU BIT(6)
60
61	#define PIN_BANK(id, pins, label) \
62	{ \
63	.bank_num = id, \
64	.nr_pins = pins, \
65	.name = label, \
66	.iomux = { \
67	{ .offset = -1 }, \
68	{ .offset = -1 }, \
69	{ .offset = -1 }, \
70	{ .offset = -1 }, \
71	}, \
72	}
73
74	#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
75	{ \
76	.bank_num = id, \
77	.nr_pins = pins, \
78	.name = label, \
79	.iomux = { \
80	{ .type = iom0, .offset = -1 }, \
81	{ .type = iom1, .offset = -1 }, \
82	{ .type = iom2, .offset = -1 }, \
83	{ .type = iom3, .offset = -1 }, \
84	}, \
85	}
86
87	#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
88	{ \
89	.bank_num = id, \
90	.nr_pins = pins, \
91	.name = label, \
92	.iomux = { \
93	{ .offset = -1 }, \
94	{ .offset = -1 }, \
95	{ .offset = -1 }, \
96	{ .offset = -1 }, \
97	}, \
98	.drv = { \
99	{ .drv_type = type0, .offset = -1 }, \
100	{ .drv_type = type1, .offset = -1 }, \
101	{ .drv_type = type2, .offset = -1 }, \
102	{ .drv_type = type3, .offset = -1 }, \
103	}, \
104	}
105
106	#define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
107	iom2, iom3, pull0, pull1, \
108	pull2, pull3) \
109	{ \
110	.bank_num = id, \
111	.nr_pins = pins, \
112	.name = label, \
113	.iomux = { \
114	{ .type = iom0, .offset = -1 }, \
115	{ .type = iom1, .offset = -1 }, \
116	{ .type = iom2, .offset = -1 }, \
117	{ .type = iom3, .offset = -1 }, \
118	}, \
119	.pull_type[0] = pull0, \
120	.pull_type[1] = pull1, \
121	.pull_type[2] = pull2, \
122	.pull_type[3] = pull3, \
123	}
124
125	#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
126	drv2, drv3, pull0, pull1, \
127	pull2, pull3) \
128	{ \
129	.bank_num = id, \
130	.nr_pins = pins, \
131	.name = label, \
132	.iomux = { \
133	{ .offset = -1 }, \
134	{ .offset = -1 }, \
135	{ .offset = -1 }, \
136	{ .offset = -1 }, \
137	}, \
138	.drv = { \
139	{ .drv_type = drv0, .offset = -1 }, \
140	{ .drv_type = drv1, .offset = -1 }, \
141	{ .drv_type = drv2, .offset = -1 }, \
142	{ .drv_type = drv3, .offset = -1 }, \
143	}, \
144	.pull_type[0] = pull0, \
145	.pull_type[1] = pull1, \
146	.pull_type[2] = pull2, \
147	.pull_type[3] = pull3, \
148	}
149
150	#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
151	iom3, offset0, offset1, offset2, \
152	offset3) \
153	{ \
154	.bank_num = id, \
155	.nr_pins = pins, \
156	.name = label, \
157	.iomux = { \
158	{ .type = iom0, .offset = offset0 }, \
159	{ .type = iom1, .offset = offset1 }, \
160	{ .type = iom2, .offset = offset2 }, \
161	{ .type = iom3, .offset = offset3 }, \
162	}, \
163	}
164
165	#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
166	iom2, iom3, drv0, drv1, drv2, \
167	drv3, offset0, offset1, \
168	offset2, offset3) \
169	{ \
170	.bank_num = id, \
171	.nr_pins = pins, \
172	.name = label, \
173	.iomux = { \
174	{ .type = iom0, .offset = -1 }, \
175	{ .type = iom1, .offset = -1 }, \
176	{ .type = iom2, .offset = -1 }, \
177	{ .type = iom3, .offset = -1 }, \
178	}, \
179	.drv = { \
180	{ .drv_type = drv0, .offset = offset0 }, \
181	{ .drv_type = drv1, .offset = offset1 }, \
182	{ .drv_type = drv2, .offset = offset2 }, \
183	{ .drv_type = drv3, .offset = offset3 }, \
184	}, \
185	}
186
187	#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
188	label, iom0, iom1, iom2, \
189	iom3, drv0, drv1, drv2, \
190	drv3, offset0, offset1, \
191	offset2, offset3, pull0, \
192	pull1, pull2, pull3) \
193	{ \
194	.bank_num = id, \
195	.nr_pins = pins, \
196	.name = label, \
197	.iomux = { \
198	{ .type = iom0, .offset = -1 }, \
199	{ .type = iom1, .offset = -1 }, \
200	{ .type = iom2, .offset = -1 }, \
201	{ .type = iom3, .offset = -1 }, \
202	}, \
203	.drv = { \
204	{ .drv_type = drv0, .offset = offset0 }, \
205	{ .drv_type = drv1, .offset = offset1 }, \
206	{ .drv_type = drv2, .offset = offset2 }, \
207	{ .drv_type = drv3, .offset = offset3 }, \
208	}, \
209	.pull_type[0] = pull0, \
210	.pull_type[1] = pull1, \
211	.pull_type[2] = pull2, \
212	.pull_type[3] = pull3, \
213	}
214
215	#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
216	{ \
217	.bank_num = ID, \
218	.pin = PIN, \
219	.func = FUNC, \
220	.route_offset = REG, \
221	.route_val = VAL, \
222	.route_location = FLAG, \
223	}
224
225	#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
226	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
227
228	#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
229	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
230
231	#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
232	PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
233
234	#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
235	PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
236
237	static struct regmap_config rockchip_regmap_config = {
238	.reg_bits = 32,
239	.val_bits = 32,
240	.reg_stride = 4,
241	};
242
243	static inline const struct rockchip_pin_group *pinctrl_name_to_group(
244	const struct rockchip_pinctrl *info,
245	const char *name)
246	{
247	int i;
248
249	for (i = 0; i < info->ngroups; i++) {
250	if (!strcmp(info->groups[i].name, name))
251	return &info->groups[i];
252	}
253
254	return NULL;
255	}
256
257	/*
258	* given a pin number that is local to a pin controller, find out the pin bank
259	* and the register base of the pin bank.
260	*/
261	static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
262	unsigned pin)
263	{
264	struct rockchip_pin_bank *b = info->ctrl->pin_banks;
265
266	while (pin >= (b->pin_base + b->nr_pins))
267	b++;
268
269	return b;
270	}
271
272	static struct rockchip_pin_bank *bank_num_to_bank(
273	struct rockchip_pinctrl *info,
274	unsigned num)
275	{
276	struct rockchip_pin_bank *b = info->ctrl->pin_banks;
277	int i;
278
279	for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
280	if (b->bank_num == num)
281	return b;
282	}
283
284	return ERR_PTR(error: -EINVAL);
285	}
286
287	/*
288	* Pinctrl_ops handling
289	*/
290
291	static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
292	{
293	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
294
295	return info->ngroups;
296	}
297
298	static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
299	unsigned selector)
300	{
301	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
302
303	return info->groups[selector].name;
304	}
305
306	static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
307	unsigned selector, const unsigned **pins,
308	unsigned *npins)
309	{
310	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
311
312	if (selector >= info->ngroups)
313	return -EINVAL;
314
315	*pins = info->groups[selector].pins;
316	*npins = info->groups[selector].npins;
317
318	return 0;
319	}
320
321	static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
322	struct device_node *np,
323	struct pinctrl_map **map, unsigned *num_maps)
324	{
325	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
326	const struct rockchip_pin_group *grp;
327	struct device *dev = info->dev;
328	struct pinctrl_map *new_map;
329	struct device_node *parent;
330	int map_num = 1;
331	int i;
332
333	/*
334	* first find the group of this node and check if we need to create
335	* config maps for pins
336	*/
337	grp = pinctrl_name_to_group(info, name: np->name);
338	if (!grp) {
339	dev_err(dev, "unable to find group for node %pOFn\n", np);
340	return -EINVAL;
341	}
342
343	map_num += grp->npins;
344
345	new_map = kcalloc(n: map_num, size: sizeof(*new_map), GFP_KERNEL);
346	if (!new_map)
347	return -ENOMEM;
348
349	*map = new_map;
350	*num_maps = map_num;
351
352	/* create mux map */
353	parent = of_get_parent(node: np);
354	if (!parent) {
355	kfree(objp: new_map);
356	return -EINVAL;
357	}
358	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
359	new_map[0].data.mux.function = parent->name;
360	new_map[0].data.mux.group = np->name;
361	of_node_put(node: parent);
362
363	/* create config map */
364	new_map++;
365	for (i = 0; i < grp->npins; i++) {
366	new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
367	new_map[i].data.configs.group_or_pin =
368	pin_get_name(pctldev, pin: grp->pins[i]);
369	new_map[i].data.configs.configs = grp->data[i].configs;
370	new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
371	}
372
373	dev_dbg(dev, "maps: function %s group %s num %d\n",
374	(*map)->data.mux.function, (*map)->data.mux.group, map_num);
375
376	return 0;
377	}
378
379	static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
380	struct pinctrl_map *map, unsigned num_maps)
381	{
382	kfree(objp: map);
383	}
384
385	static const struct pinctrl_ops rockchip_pctrl_ops = {
386	.get_groups_count = rockchip_get_groups_count,
387	.get_group_name = rockchip_get_group_name,
388	.get_group_pins = rockchip_get_group_pins,
389	.dt_node_to_map = rockchip_dt_node_to_map,
390	.dt_free_map = rockchip_dt_free_map,
391	};
392
393	/*
394	* Hardware access
395	*/
396
397	static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
398	{
399	.num = 1,
400	.pin = 0,
401	.reg = 0x418,
402	.bit = 0,
403	.mask = 0x3
404	}, {
405	.num = 1,
406	.pin = 1,
407	.reg = 0x418,
408	.bit = 2,
409	.mask = 0x3
410	}, {
411	.num = 1,
412	.pin = 2,
413	.reg = 0x418,
414	.bit = 4,
415	.mask = 0x3
416	}, {
417	.num = 1,
418	.pin = 3,
419	.reg = 0x418,
420	.bit = 6,
421	.mask = 0x3
422	}, {
423	.num = 1,
424	.pin = 4,
425	.reg = 0x418,
426	.bit = 8,
427	.mask = 0x3
428	}, {
429	.num = 1,
430	.pin = 5,
431	.reg = 0x418,
432	.bit = 10,
433	.mask = 0x3
434	}, {
435	.num = 1,
436	.pin = 6,
437	.reg = 0x418,
438	.bit = 12,
439	.mask = 0x3
440	}, {
441	.num = 1,
442	.pin = 7,
443	.reg = 0x418,
444	.bit = 14,
445	.mask = 0x3
446	}, {
447	.num = 1,
448	.pin = 8,
449	.reg = 0x41c,
450	.bit = 0,
451	.mask = 0x3
452	}, {
453	.num = 1,
454	.pin = 9,
455	.reg = 0x41c,
456	.bit = 2,
457	.mask = 0x3
458	},
459	};
460
461	static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
462	{
463	.num = 0,
464	.pin = 20,
465	.reg = 0x10000,
466	.bit = 0,
467	.mask = 0xf
468	},
469	{
470	.num = 0,
471	.pin = 21,
472	.reg = 0x10000,
473	.bit = 4,
474	.mask = 0xf
475	},
476	{
477	.num = 0,
478	.pin = 22,
479	.reg = 0x10000,
480	.bit = 8,
481	.mask = 0xf
482	},
483	{
484	.num = 0,
485	.pin = 23,
486	.reg = 0x10000,
487	.bit = 12,
488	.mask = 0xf
489	},
490	};
491
492	static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
493	{
494	.num = 2,
495	.pin = 20,
496	.reg = 0xe8,
497	.bit = 0,
498	.mask = 0x7
499	}, {
500	.num = 2,
501	.pin = 21,
502	.reg = 0xe8,
503	.bit = 4,
504	.mask = 0x7
505	}, {
506	.num = 2,
507	.pin = 22,
508	.reg = 0xe8,
509	.bit = 8,
510	.mask = 0x7
511	}, {
512	.num = 2,
513	.pin = 23,
514	.reg = 0xe8,
515	.bit = 12,
516	.mask = 0x7
517	}, {
518	.num = 2,
519	.pin = 24,
520	.reg = 0xd4,
521	.bit = 12,
522	.mask = 0x7
523	},
524	};
525
526	static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
527	{
528	/* gpio1b6_sel */
529	.num = 1,
530	.pin = 14,
531	.reg = 0x28,
532	.bit = 12,
533	.mask = 0xf
534	}, {
535	/* gpio1b7_sel */
536	.num = 1,
537	.pin = 15,
538	.reg = 0x2c,
539	.bit = 0,
540	.mask = 0x3
541	}, {
542	/* gpio1c2_sel */
543	.num = 1,
544	.pin = 18,
545	.reg = 0x30,
546	.bit = 4,
547	.mask = 0xf
548	}, {
549	/* gpio1c3_sel */
550	.num = 1,
551	.pin = 19,
552	.reg = 0x30,
553	.bit = 8,
554	.mask = 0xf
555	}, {
556	/* gpio1c4_sel */
557	.num = 1,
558	.pin = 20,
559	.reg = 0x30,
560	.bit = 12,
561	.mask = 0xf
562	}, {
563	/* gpio1c5_sel */
564	.num = 1,
565	.pin = 21,
566	.reg = 0x34,
567	.bit = 0,
568	.mask = 0xf
569	}, {
570	/* gpio1c6_sel */
571	.num = 1,
572	.pin = 22,
573	.reg = 0x34,
574	.bit = 4,
575	.mask = 0xf
576	}, {
577	/* gpio1c7_sel */
578	.num = 1,
579	.pin = 23,
580	.reg = 0x34,
581	.bit = 8,
582	.mask = 0xf
583	}, {
584	/* gpio2a2_sel */
585	.num = 2,
586	.pin = 2,
587	.reg = 0x40,
588	.bit = 4,
589	.mask = 0x3
590	}, {
591	/* gpio2a3_sel */
592	.num = 2,
593	.pin = 3,
594	.reg = 0x40,
595	.bit = 6,
596	.mask = 0x3
597	}, {
598	/* gpio2c0_sel */
599	.num = 2,
600	.pin = 16,
601	.reg = 0x50,
602	.bit = 0,
603	.mask = 0x3
604	}, {
605	/* gpio3b2_sel */
606	.num = 3,
607	.pin = 10,
608	.reg = 0x68,
609	.bit = 4,
610	.mask = 0x3
611	}, {
612	/* gpio3b3_sel */
613	.num = 3,
614	.pin = 11,
615	.reg = 0x68,
616	.bit = 6,
617	.mask = 0x3
618	}, {
619	/* gpio3b4_sel */
620	.num = 3,
621	.pin = 12,
622	.reg = 0x68,
623	.bit = 8,
624	.mask = 0xf
625	}, {
626	/* gpio3b5_sel */
627	.num = 3,
628	.pin = 13,
629	.reg = 0x68,
630	.bit = 12,
631	.mask = 0xf
632	},
633	};
634
635	static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
636	{
637	.num = 2,
638	.pin = 12,
639	.reg = 0x24,
640	.bit = 8,
641	.mask = 0x3
642	}, {
643	.num = 2,
644	.pin = 15,
645	.reg = 0x28,
646	.bit = 0,
647	.mask = 0x7
648	}, {
649	.num = 2,
650	.pin = 23,
651	.reg = 0x30,
652	.bit = 14,
653	.mask = 0x3
654	},
655	};
656
657	static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
658	int *reg, u8 *bit, int *mask)
659	{
660	struct rockchip_pinctrl *info = bank->drvdata;
661	struct rockchip_pin_ctrl *ctrl = info->ctrl;
662	struct rockchip_mux_recalced_data *data;
663	int i;
664
665	for (i = 0; i < ctrl->niomux_recalced; i++) {
666	data = &ctrl->iomux_recalced[i];
667	if (data->num == bank->bank_num &&
668	data->pin == pin)
669	break;
670	}
671
672	if (i >= ctrl->niomux_recalced)
673	return;
674
675	*reg = data->reg;
676	*mask = data->mask;
677	*bit = data->bit;
678	}
679
680	static struct rockchip_mux_route_data px30_mux_route_data[] = {
681	RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
682	RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
683	RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
684	RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
685	RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
686	RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
687	RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
688	RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
689	RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
690	RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
691	RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
692	RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
693	RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
694	RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
695	RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
696	RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
697	RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
698	RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
699	RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
700	RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
701	RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
702	RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
703	RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
704	RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
705	RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
706	RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
707	RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
708	RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
709	RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
710	RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
711	RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
712	RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
713	RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
714	RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
715	RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
716	RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
717	RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
718	RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
719	RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
720	RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
721	RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
722	RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
723	RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
724	RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
725	RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
726	RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
727	RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
728	RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
729	};
730
731	static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
732	RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
733	RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
734
735	RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
736	RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
737	RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
738
739	RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
740	RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
741
742	RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
743	RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
744
745	RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
746	RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
747
748	RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
749	RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
750	RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
751
752	RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
753	RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
754
755	RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
756	RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
757	RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
758
759	RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
760	RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
761	RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
762
763	RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
764	RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
765
766	RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
767	RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
768
769	RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
770	RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
771
772	RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
773	RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
774
775	RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
776	RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
777
778	RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
779	RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
780
781	RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
782	RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
783
784	RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
785	RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
786	RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
787
788	RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
789	RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
790	RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
791
792	RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
793	RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
794	RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
795
796	RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
797	RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
798
799	RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
800	RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
801
802	RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
803	RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
804
805	RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
806	RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
807
808	RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
809	RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
810
811	RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
812	RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
813
814	RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
815	RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
816
817	RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
818	RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
819
820	RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
821	RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
822	RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
823
824	RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
825	RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
826	};
827
828	static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
829	RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
830	RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
831	RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
832	RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
833	RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
834	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
835	RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
836	};
837
838	static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
839	RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
840	RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
841	};
842
843	static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
844	RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
845	RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
846	RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
847	RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
848	RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
849	RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
850	RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
851	RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
852	RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
853	RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
854	RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
855	RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
856	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
857	RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
858	RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
859	RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
860	RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
861	RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
862	};
863
864	static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
865	RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
866	RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
867	};
868
869	static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
870	RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
871	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
872	RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
873	RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
874	RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
875	RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
876	RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
877	RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
878	RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
879	RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
880	RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
881	RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
882	RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
883	RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
884	RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
885	RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
886	RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
887	RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
888	RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
889	RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
890	RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
891	RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
892	RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
893	RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
894	RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
895	RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
896	};
897
898	static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
899	RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
900	RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
901	RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
902	RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
903	RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
904	RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
905	RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
906	RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
907	RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
908	RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
909	RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
910	RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
911	};
912
913	static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
914	RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
915	RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
916	RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
917	RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
918	RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
919	};
920
921	static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
922	RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
923	RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
924	RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
925	RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
926	RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
927	RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
928	RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
929	RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
930	RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
931	RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
932	RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
933	RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
934	RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
935	RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
936	RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
937	RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
938	RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
939	RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
940	RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
941	RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
942	RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
943	RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
944	RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
945	RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
946	RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
947	RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
948	RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
949	RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
950	RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
951	RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
952	RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
953	RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
954	RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
955	RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
956	RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
957	RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
958	RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
959	RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
960	RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
961	RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
962	RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
963	RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
964	RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
965	RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
966	RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
967	RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
968	RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
969	RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
970	RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
971	RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
972	RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
973	RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
974	RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
975	RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
976	RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
977	RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
978	RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
979	RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
980	RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
981	RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
982	RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
983	RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
984	RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
985	RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
986	RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
987	RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
988	RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
989	RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
990	RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
991	RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
992	RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
993	RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
994	RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
995	RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
996	RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
997	RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
998	RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
999	RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1000	RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1001	RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1002	RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1003	RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1004	RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1005	RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1006	RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1007	RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1008	RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1009	RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1010	RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1011	RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1012	RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1013	RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1014	RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1015	};
1016
1017	static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1018	int mux, u32 *loc, u32 *reg, u32 *value)
1019	{
1020	struct rockchip_pinctrl *info = bank->drvdata;
1021	struct rockchip_pin_ctrl *ctrl = info->ctrl;
1022	struct rockchip_mux_route_data *data;
1023	int i;
1024
1025	for (i = 0; i < ctrl->niomux_routes; i++) {
1026	data = &ctrl->iomux_routes[i];
1027	if ((data->bank_num == bank->bank_num) &&
1028	(data->pin == pin) && (data->func == mux))
1029	break;
1030	}
1031
1032	if (i >= ctrl->niomux_routes)
1033	return false;
1034
1035	*loc = data->route_location;
1036	*reg = data->route_offset;
1037	*value = data->route_val;
1038
1039	return true;
1040	}
1041
1042	static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1043	{
1044	struct rockchip_pinctrl *info = bank->drvdata;
1045	struct rockchip_pin_ctrl *ctrl = info->ctrl;
1046	int iomux_num = (pin / 8);
1047	struct regmap *regmap;
1048	unsigned int val;
1049	int reg, ret, mask, mux_type;
1050	u8 bit;
1051
1052	if (iomux_num > 3)
1053	return -EINVAL;
1054
1055	if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1056	dev_err(info->dev, "pin %d is unrouted\n", pin);
1057	return -EINVAL;
1058	}
1059
1060	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1061	return RK_FUNC_GPIO;
1062
1063	if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1064	regmap = info->regmap_pmu;
1065	else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1066	regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1067	else
1068	regmap = info->regmap_base;
1069
1070	/* get basic quadrupel of mux registers and the correct reg inside */
1071	mux_type = bank->iomux[iomux_num].type;
1072	reg = bank->iomux[iomux_num].offset;
1073	if (mux_type & IOMUX_WIDTH_4BIT) {
1074	if ((pin % 8) >= 4)
1075	reg += 0x4;
1076	bit = (pin % 4) * 4;
1077	mask = 0xf;
1078	} else if (mux_type & IOMUX_WIDTH_3BIT) {
1079	if ((pin % 8) >= 5)
1080	reg += 0x4;
1081	bit = (pin % 8 % 5) * 3;
1082	mask = 0x7;
1083	} else {
1084	bit = (pin % 8) * 2;
1085	mask = 0x3;
1086	}
1087
1088	if (bank->recalced_mask & BIT(pin))
1089	rockchip_get_recalced_mux(bank, pin, reg: &reg, bit: &bit, mask: &mask);
1090
1091	if (ctrl->type == RK3588) {
1092	if (bank->bank_num == 0) {
1093	if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1094	u32 reg0 = 0;
1095
1096	reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1097	ret = regmap_read(map: regmap, reg: reg0, val: &val);
1098	if (ret)
1099	return ret;
1100
1101	if (!(val & BIT(8)))
1102	return ((val >> bit) & mask);
1103
1104	reg = reg + 0x8000; /* BUS_IOC_BASE */
1105	regmap = info->regmap_base;
1106	}
1107	} else if (bank->bank_num > 0) {
1108	reg += 0x8000; /* BUS_IOC_BASE */
1109	}
1110	}
1111
1112	ret = regmap_read(map: regmap, reg, val: &val);
1113	if (ret)
1114	return ret;
1115
1116	return ((val >> bit) & mask);
1117	}
1118
1119	static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1120	int pin, int mux)
1121	{
1122	struct rockchip_pinctrl *info = bank->drvdata;
1123	struct device *dev = info->dev;
1124	int iomux_num = (pin / 8);
1125
1126	if (iomux_num > 3)
1127	return -EINVAL;
1128
1129	if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1130	dev_err(dev, "pin %d is unrouted\n", pin);
1131	return -EINVAL;
1132	}
1133
1134	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1135	if (mux != RK_FUNC_GPIO) {
1136	dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1137	return -ENOTSUPP;
1138	}
1139	}
1140
1141	return 0;
1142	}
1143
1144	/*
1145	* Set a new mux function for a pin.
1146	*
1147	* The register is divided into the upper and lower 16 bit. When changing
1148	* a value, the previous register value is not read and changed. Instead
1149	* it seems the changed bits are marked in the upper 16 bit, while the
1150	* changed value gets set in the same offset in the lower 16 bit.
1151	* All pin settings seem to be 2 bit wide in both the upper and lower
1152	* parts.
1153	* @bank: pin bank to change
1154	* @pin: pin to change
1155	* @mux: new mux function to set
1156	*/
1157	static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1158	{
1159	struct rockchip_pinctrl *info = bank->drvdata;
1160	struct rockchip_pin_ctrl *ctrl = info->ctrl;
1161	struct device *dev = info->dev;
1162	int iomux_num = (pin / 8);
1163	struct regmap *regmap;
1164	int reg, ret, mask, mux_type;
1165	u8 bit;
1166	u32 data, rmask, route_location, route_reg, route_val;
1167
1168	ret = rockchip_verify_mux(bank, pin, mux);
1169	if (ret < 0)
1170	return ret;
1171
1172	if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1173	return 0;
1174
1175	dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1176
1177	if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1178	regmap = info->regmap_pmu;
1179	else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1180	regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1181	else
1182	regmap = info->regmap_base;
1183
1184	/* get basic quadrupel of mux registers and the correct reg inside */
1185	mux_type = bank->iomux[iomux_num].type;
1186	reg = bank->iomux[iomux_num].offset;
1187	if (mux_type & IOMUX_WIDTH_4BIT) {
1188	if ((pin % 8) >= 4)
1189	reg += 0x4;
1190	bit = (pin % 4) * 4;
1191	mask = 0xf;
1192	} else if (mux_type & IOMUX_WIDTH_3BIT) {
1193	if ((pin % 8) >= 5)
1194	reg += 0x4;
1195	bit = (pin % 8 % 5) * 3;
1196	mask = 0x7;
1197	} else {
1198	bit = (pin % 8) * 2;
1199	mask = 0x3;
1200	}
1201
1202	if (bank->recalced_mask & BIT(pin))
1203	rockchip_get_recalced_mux(bank, pin, reg: &reg, bit: &bit, mask: &mask);
1204
1205	if (ctrl->type == RK3588) {
1206	if (bank->bank_num == 0) {
1207	if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1208	if (mux < 8) {
1209	reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
1210	data = (mask << (bit + 16));
1211	rmask = data | (data >> 16);
1212	data |= (mux & mask) << bit;
1213	ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
1214	} else {
1215	u32 reg0 = 0;
1216
1217	reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1218	data = (mask << (bit + 16));
1219	rmask = data | (data >> 16);
1220	data |= 8 << bit;
1221	ret = regmap_update_bits(map: regmap, reg: reg0, mask: rmask, val: data);
1222
1223	reg0 = reg + 0x8000; /* BUS_IOC_BASE */
1224	data = (mask << (bit + 16));
1225	rmask = data | (data >> 16);
1226	data |= mux << bit;
1227	regmap = info->regmap_base;
1228	ret |= regmap_update_bits(map: regmap, reg: reg0, mask: rmask, val: data);
1229	}
1230	} else {
1231	data = (mask << (bit + 16));
1232	rmask = data | (data >> 16);
1233	data |= (mux & mask) << bit;
1234	ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
1235	}
1236	return ret;
1237	} else if (bank->bank_num > 0) {
1238	reg += 0x8000; /* BUS_IOC_BASE */
1239	}
1240	}
1241
1242	if (mux > mask)
1243	return -EINVAL;
1244
1245	if (bank->route_mask & BIT(pin)) {
1246	if (rockchip_get_mux_route(bank, pin, mux, loc: &route_location,
1247	reg: &route_reg, value: &route_val)) {
1248	struct regmap *route_regmap = regmap;
1249
1250	/* handle special locations */
1251	switch (route_location) {
1252	case ROCKCHIP_ROUTE_PMU:
1253	route_regmap = info->regmap_pmu;
1254	break;
1255	case ROCKCHIP_ROUTE_GRF:
1256	route_regmap = info->regmap_base;
1257	break;
1258	}
1259
1260	ret = regmap_write(map: route_regmap, reg: route_reg, val: route_val);
1261	if (ret)
1262	return ret;
1263	}
1264	}
1265
1266	data = (mask << (bit + 16));
1267	rmask = data | (data >> 16);
1268	data |= (mux & mask) << bit;
1269	ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
1270
1271	return ret;
1272	}
1273
1274	#define PX30_PULL_PMU_OFFSET 0x10
1275	#define PX30_PULL_GRF_OFFSET 0x60
1276	#define PX30_PULL_BITS_PER_PIN 2
1277	#define PX30_PULL_PINS_PER_REG 8
1278	#define PX30_PULL_BANK_STRIDE 16
1279
1280	static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1281	int pin_num, struct regmap **regmap,
1282	int *reg, u8 *bit)
1283	{
1284	struct rockchip_pinctrl *info = bank->drvdata;
1285
1286	/* The first 32 pins of the first bank are located in PMU */
1287	if (bank->bank_num == 0) {
1288	*regmap = info->regmap_pmu;
1289	*reg = PX30_PULL_PMU_OFFSET;
1290	} else {
1291	*regmap = info->regmap_base;
1292	*reg = PX30_PULL_GRF_OFFSET;
1293
1294	/* correct the offset, as we're starting with the 2nd bank */
1295	*reg -= 0x10;
1296	*reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1297	}
1298
1299	*reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1300	*bit = (pin_num % PX30_PULL_PINS_PER_REG);
1301	*bit *= PX30_PULL_BITS_PER_PIN;
1302
1303	return 0;
1304	}
1305
1306	#define PX30_DRV_PMU_OFFSET 0x20
1307	#define PX30_DRV_GRF_OFFSET 0xf0
1308	#define PX30_DRV_BITS_PER_PIN 2
1309	#define PX30_DRV_PINS_PER_REG 8
1310	#define PX30_DRV_BANK_STRIDE 16
1311
1312	static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1313	int pin_num, struct regmap **regmap,
1314	int *reg, u8 *bit)
1315	{
1316	struct rockchip_pinctrl *info = bank->drvdata;
1317
1318	/* The first 32 pins of the first bank are located in PMU */
1319	if (bank->bank_num == 0) {
1320	*regmap = info->regmap_pmu;
1321	*reg = PX30_DRV_PMU_OFFSET;
1322	} else {
1323	*regmap = info->regmap_base;
1324	*reg = PX30_DRV_GRF_OFFSET;
1325
1326	/* correct the offset, as we're starting with the 2nd bank */
1327	*reg -= 0x10;
1328	*reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1329	}
1330
1331	*reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1332	*bit = (pin_num % PX30_DRV_PINS_PER_REG);
1333	*bit *= PX30_DRV_BITS_PER_PIN;
1334
1335	return 0;
1336	}
1337
1338	#define PX30_SCHMITT_PMU_OFFSET 0x38
1339	#define PX30_SCHMITT_GRF_OFFSET 0xc0
1340	#define PX30_SCHMITT_PINS_PER_PMU_REG 16
1341	#define PX30_SCHMITT_BANK_STRIDE 16
1342	#define PX30_SCHMITT_PINS_PER_GRF_REG 8
1343
1344	static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1345	int pin_num,
1346	struct regmap **regmap,
1347	int *reg, u8 *bit)
1348	{
1349	struct rockchip_pinctrl *info = bank->drvdata;
1350	int pins_per_reg;
1351
1352	if (bank->bank_num == 0) {
1353	*regmap = info->regmap_pmu;
1354	*reg = PX30_SCHMITT_PMU_OFFSET;
1355	pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1356	} else {
1357	*regmap = info->regmap_base;
1358	*reg = PX30_SCHMITT_GRF_OFFSET;
1359	pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1360	*reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1361	}
1362
1363	*reg += ((pin_num / pins_per_reg) * 4);
1364	*bit = pin_num % pins_per_reg;
1365
1366	return 0;
1367	}
1368
1369	#define RV1108_PULL_PMU_OFFSET 0x10
1370	#define RV1108_PULL_OFFSET 0x110
1371	#define RV1108_PULL_PINS_PER_REG 8
1372	#define RV1108_PULL_BITS_PER_PIN 2
1373	#define RV1108_PULL_BANK_STRIDE 16
1374
1375	static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1376	int pin_num, struct regmap **regmap,
1377	int *reg, u8 *bit)
1378	{
1379	struct rockchip_pinctrl *info = bank->drvdata;
1380
1381	/* The first 24 pins of the first bank are located in PMU */
1382	if (bank->bank_num == 0) {
1383	*regmap = info->regmap_pmu;
1384	*reg = RV1108_PULL_PMU_OFFSET;
1385	} else {
1386	*reg = RV1108_PULL_OFFSET;
1387	*regmap = info->regmap_base;
1388	/* correct the offset, as we're starting with the 2nd bank */
1389	*reg -= 0x10;
1390	*reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1391	}
1392
1393	*reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1394	*bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1395	*bit *= RV1108_PULL_BITS_PER_PIN;
1396
1397	return 0;
1398	}
1399
1400	#define RV1108_DRV_PMU_OFFSET 0x20
1401	#define RV1108_DRV_GRF_OFFSET 0x210
1402	#define RV1108_DRV_BITS_PER_PIN 2
1403	#define RV1108_DRV_PINS_PER_REG 8
1404	#define RV1108_DRV_BANK_STRIDE 16
1405
1406	static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1407	int pin_num, struct regmap **regmap,
1408	int *reg, u8 *bit)
1409	{
1410	struct rockchip_pinctrl *info = bank->drvdata;
1411
1412	/* The first 24 pins of the first bank are located in PMU */
1413	if (bank->bank_num == 0) {
1414	*regmap = info->regmap_pmu;
1415	*reg = RV1108_DRV_PMU_OFFSET;
1416	} else {
1417	*regmap = info->regmap_base;
1418	*reg = RV1108_DRV_GRF_OFFSET;
1419
1420	/* correct the offset, as we're starting with the 2nd bank */
1421	*reg -= 0x10;
1422	*reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1423	}
1424
1425	*reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1426	*bit = pin_num % RV1108_DRV_PINS_PER_REG;
1427	*bit *= RV1108_DRV_BITS_PER_PIN;
1428
1429	return 0;
1430	}
1431
1432	#define RV1108_SCHMITT_PMU_OFFSET 0x30
1433	#define RV1108_SCHMITT_GRF_OFFSET 0x388
1434	#define RV1108_SCHMITT_BANK_STRIDE 8
1435	#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1436	#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1437
1438	static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1439	int pin_num,
1440	struct regmap **regmap,
1441	int *reg, u8 *bit)
1442	{
1443	struct rockchip_pinctrl *info = bank->drvdata;
1444	int pins_per_reg;
1445
1446	if (bank->bank_num == 0) {
1447	*regmap = info->regmap_pmu;
1448	*reg = RV1108_SCHMITT_PMU_OFFSET;
1449	pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1450	} else {
1451	*regmap = info->regmap_base;
1452	*reg = RV1108_SCHMITT_GRF_OFFSET;
1453	pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1454	*reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1455	}
1456	*reg += ((pin_num / pins_per_reg) * 4);
1457	*bit = pin_num % pins_per_reg;
1458
1459	return 0;
1460	}
1461
1462	#define RV1126_PULL_PMU_OFFSET 0x40
1463	#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
1464	#define RV1126_PULL_PINS_PER_REG 8
1465	#define RV1126_PULL_BITS_PER_PIN 2
1466	#define RV1126_PULL_BANK_STRIDE 16
1467	#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1468
1469	static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1470	int pin_num, struct regmap **regmap,
1471	int *reg, u8 *bit)
1472	{
1473	struct rockchip_pinctrl *info = bank->drvdata;
1474
1475	/* The first 24 pins of the first bank are located in PMU */
1476	if (bank->bank_num == 0) {
1477	if (RV1126_GPIO_C4_D7(pin_num)) {
1478	*regmap = info->regmap_base;
1479	*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1480	*reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
1481	*bit = pin_num % RV1126_PULL_PINS_PER_REG;
1482	*bit *= RV1126_PULL_BITS_PER_PIN;
1483	return 0;
1484	}
1485	*regmap = info->regmap_pmu;
1486	*reg = RV1126_PULL_PMU_OFFSET;
1487	} else {
1488	*reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1489	*regmap = info->regmap_base;
1490	*reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
1491	}
1492
1493	*reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
1494	*bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1495	*bit *= RV1126_PULL_BITS_PER_PIN;
1496
1497	return 0;
1498	}
1499
1500	#define RV1126_DRV_PMU_OFFSET 0x20
1501	#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
1502	#define RV1126_DRV_BITS_PER_PIN 4
1503	#define RV1126_DRV_PINS_PER_REG 4
1504	#define RV1126_DRV_BANK_STRIDE 32
1505
1506	static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1507	int pin_num, struct regmap **regmap,
1508	int *reg, u8 *bit)
1509	{
1510	struct rockchip_pinctrl *info = bank->drvdata;
1511
1512	/* The first 24 pins of the first bank are located in PMU */
1513	if (bank->bank_num == 0) {
1514	if (RV1126_GPIO_C4_D7(pin_num)) {
1515	*regmap = info->regmap_base;
1516	*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1517	*reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
1518	*reg -= 0x4;
1519	*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1520	*bit *= RV1126_DRV_BITS_PER_PIN;
1521	return 0;
1522	}
1523	*regmap = info->regmap_pmu;
1524	*reg = RV1126_DRV_PMU_OFFSET;
1525	} else {
1526	*regmap = info->regmap_base;
1527	*reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1528	*reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
1529	}
1530
1531	*reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
1532	*bit = pin_num % RV1126_DRV_PINS_PER_REG;
1533	*bit *= RV1126_DRV_BITS_PER_PIN;
1534
1535	return 0;
1536	}
1537
1538	#define RV1126_SCHMITT_PMU_OFFSET 0x60
1539	#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
1540	#define RV1126_SCHMITT_BANK_STRIDE 16
1541	#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
1542	#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
1543
1544	static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1545	int pin_num,
1546	struct regmap **regmap,
1547	int *reg, u8 *bit)
1548	{
1549	struct rockchip_pinctrl *info = bank->drvdata;
1550	int pins_per_reg;
1551
1552	if (bank->bank_num == 0) {
1553	if (RV1126_GPIO_C4_D7(pin_num)) {
1554	*regmap = info->regmap_base;
1555	*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1556	*reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
1557	*bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
1558	return 0;
1559	}
1560	*regmap = info->regmap_pmu;
1561	*reg = RV1126_SCHMITT_PMU_OFFSET;
1562	pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
1563	} else {
1564	*regmap = info->regmap_base;
1565	*reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1566	pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
1567	*reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
1568	}
1569	*reg += ((pin_num / pins_per_reg) * 4);
1570	*bit = pin_num % pins_per_reg;
1571
1572	return 0;
1573	}
1574
1575	#define RK3308_SCHMITT_PINS_PER_REG 8
1576	#define RK3308_SCHMITT_BANK_STRIDE 16
1577	#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1578
1579	static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1580	int pin_num, struct regmap **regmap,
1581	int *reg, u8 *bit)
1582	{
1583	struct rockchip_pinctrl *info = bank->drvdata;
1584
1585	*regmap = info->regmap_base;
1586	*reg = RK3308_SCHMITT_GRF_OFFSET;
1587
1588	*reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1589	*reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1590	*bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1591
1592	return 0;
1593	}
1594
1595	#define RK2928_PULL_OFFSET 0x118
1596	#define RK2928_PULL_PINS_PER_REG 16
1597	#define RK2928_PULL_BANK_STRIDE 8
1598
1599	static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1600	int pin_num, struct regmap **regmap,
1601	int *reg, u8 *bit)
1602	{
1603	struct rockchip_pinctrl *info = bank->drvdata;
1604
1605	*regmap = info->regmap_base;
1606	*reg = RK2928_PULL_OFFSET;
1607	*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1608	*reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1609
1610	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
1611
1612	return 0;
1613	};
1614
1615	#define RK3128_PULL_OFFSET 0x118
1616
1617	static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1618	int pin_num, struct regmap **regmap,
1619	int *reg, u8 *bit)
1620	{
1621	struct rockchip_pinctrl *info = bank->drvdata;
1622
1623	*regmap = info->regmap_base;
1624	*reg = RK3128_PULL_OFFSET;
1625	*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1626	*reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1627
1628	*bit = pin_num % RK2928_PULL_PINS_PER_REG;
1629
1630	return 0;
1631	}
1632
1633	#define RK3188_PULL_OFFSET 0x164
1634	#define RK3188_PULL_BITS_PER_PIN 2
1635	#define RK3188_PULL_PINS_PER_REG 8
1636	#define RK3188_PULL_BANK_STRIDE 16
1637	#define RK3188_PULL_PMU_OFFSET 0x64
1638
1639	static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1640	int pin_num, struct regmap **regmap,
1641	int *reg, u8 *bit)
1642	{
1643	struct rockchip_pinctrl *info = bank->drvdata;
1644
1645	/* The first 12 pins of the first bank are located elsewhere */
1646	if (bank->bank_num == 0 && pin_num < 12) {
1647	*regmap = info->regmap_pmu ? info->regmap_pmu
1648	: bank->regmap_pull;
1649	*reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1650	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1651	*bit = pin_num % RK3188_PULL_PINS_PER_REG;
1652	*bit *= RK3188_PULL_BITS_PER_PIN;
1653	} else {
1654	*regmap = info->regmap_pull ? info->regmap_pull
1655	: info->regmap_base;
1656	*reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1657
1658	/* correct the offset, as it is the 2nd pull register */
1659	*reg -= 4;
1660	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1661	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1662
1663	/*
1664	* The bits in these registers have an inverse ordering
1665	* with the lowest pin being in bits 15:14 and the highest
1666	* pin in bits 1:0
1667	*/
1668	*bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1669	*bit *= RK3188_PULL_BITS_PER_PIN;
1670	}
1671
1672	return 0;
1673	}
1674
1675	#define RK3288_PULL_OFFSET 0x140
1676	static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1677	int pin_num, struct regmap **regmap,
1678	int *reg, u8 *bit)
1679	{
1680	struct rockchip_pinctrl *info = bank->drvdata;
1681
1682	/* The first 24 pins of the first bank are located in PMU */
1683	if (bank->bank_num == 0) {
1684	*regmap = info->regmap_pmu;
1685	*reg = RK3188_PULL_PMU_OFFSET;
1686
1687	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1688	*bit = pin_num % RK3188_PULL_PINS_PER_REG;
1689	*bit *= RK3188_PULL_BITS_PER_PIN;
1690	} else {
1691	*regmap = info->regmap_base;
1692	*reg = RK3288_PULL_OFFSET;
1693
1694	/* correct the offset, as we're starting with the 2nd bank */
1695	*reg -= 0x10;
1696	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1697	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1698
1699	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1700	*bit *= RK3188_PULL_BITS_PER_PIN;
1701	}
1702
1703	return 0;
1704	}
1705
1706	#define RK3288_DRV_PMU_OFFSET 0x70
1707	#define RK3288_DRV_GRF_OFFSET 0x1c0
1708	#define RK3288_DRV_BITS_PER_PIN 2
1709	#define RK3288_DRV_PINS_PER_REG 8
1710	#define RK3288_DRV_BANK_STRIDE 16
1711
1712	static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1713	int pin_num, struct regmap **regmap,
1714	int *reg, u8 *bit)
1715	{
1716	struct rockchip_pinctrl *info = bank->drvdata;
1717
1718	/* The first 24 pins of the first bank are located in PMU */
1719	if (bank->bank_num == 0) {
1720	*regmap = info->regmap_pmu;
1721	*reg = RK3288_DRV_PMU_OFFSET;
1722
1723	*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1724	*bit = pin_num % RK3288_DRV_PINS_PER_REG;
1725	*bit *= RK3288_DRV_BITS_PER_PIN;
1726	} else {
1727	*regmap = info->regmap_base;
1728	*reg = RK3288_DRV_GRF_OFFSET;
1729
1730	/* correct the offset, as we're starting with the 2nd bank */
1731	*reg -= 0x10;
1732	*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1733	*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1734
1735	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1736	*bit *= RK3288_DRV_BITS_PER_PIN;
1737	}
1738
1739	return 0;
1740	}
1741
1742	#define RK3228_PULL_OFFSET 0x100
1743
1744	static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1745	int pin_num, struct regmap **regmap,
1746	int *reg, u8 *bit)
1747	{
1748	struct rockchip_pinctrl *info = bank->drvdata;
1749
1750	*regmap = info->regmap_base;
1751	*reg = RK3228_PULL_OFFSET;
1752	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1753	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1754
1755	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1756	*bit *= RK3188_PULL_BITS_PER_PIN;
1757
1758	return 0;
1759	}
1760
1761	#define RK3228_DRV_GRF_OFFSET 0x200
1762
1763	static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1764	int pin_num, struct regmap **regmap,
1765	int *reg, u8 *bit)
1766	{
1767	struct rockchip_pinctrl *info = bank->drvdata;
1768
1769	*regmap = info->regmap_base;
1770	*reg = RK3228_DRV_GRF_OFFSET;
1771	*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1772	*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1773
1774	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1775	*bit *= RK3288_DRV_BITS_PER_PIN;
1776
1777	return 0;
1778	}
1779
1780	#define RK3308_PULL_OFFSET 0xa0
1781
1782	static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1783	int pin_num, struct regmap **regmap,
1784	int *reg, u8 *bit)
1785	{
1786	struct rockchip_pinctrl *info = bank->drvdata;
1787
1788	*regmap = info->regmap_base;
1789	*reg = RK3308_PULL_OFFSET;
1790	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1791	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1792
1793	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1794	*bit *= RK3188_PULL_BITS_PER_PIN;
1795
1796	return 0;
1797	}
1798
1799	#define RK3308_DRV_GRF_OFFSET 0x100
1800
1801	static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1802	int pin_num, struct regmap **regmap,
1803	int *reg, u8 *bit)
1804	{
1805	struct rockchip_pinctrl *info = bank->drvdata;
1806
1807	*regmap = info->regmap_base;
1808	*reg = RK3308_DRV_GRF_OFFSET;
1809	*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1810	*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1811
1812	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1813	*bit *= RK3288_DRV_BITS_PER_PIN;
1814
1815	return 0;
1816	}
1817
1818	#define RK3368_PULL_GRF_OFFSET 0x100
1819	#define RK3368_PULL_PMU_OFFSET 0x10
1820
1821	static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1822	int pin_num, struct regmap **regmap,
1823	int *reg, u8 *bit)
1824	{
1825	struct rockchip_pinctrl *info = bank->drvdata;
1826
1827	/* The first 32 pins of the first bank are located in PMU */
1828	if (bank->bank_num == 0) {
1829	*regmap = info->regmap_pmu;
1830	*reg = RK3368_PULL_PMU_OFFSET;
1831
1832	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1833	*bit = pin_num % RK3188_PULL_PINS_PER_REG;
1834	*bit *= RK3188_PULL_BITS_PER_PIN;
1835	} else {
1836	*regmap = info->regmap_base;
1837	*reg = RK3368_PULL_GRF_OFFSET;
1838
1839	/* correct the offset, as we're starting with the 2nd bank */
1840	*reg -= 0x10;
1841	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1842	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1843
1844	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1845	*bit *= RK3188_PULL_BITS_PER_PIN;
1846	}
1847
1848	return 0;
1849	}
1850
1851	#define RK3368_DRV_PMU_OFFSET 0x20
1852	#define RK3368_DRV_GRF_OFFSET 0x200
1853
1854	static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1855	int pin_num, struct regmap **regmap,
1856	int *reg, u8 *bit)
1857	{
1858	struct rockchip_pinctrl *info = bank->drvdata;
1859
1860	/* The first 32 pins of the first bank are located in PMU */
1861	if (bank->bank_num == 0) {
1862	*regmap = info->regmap_pmu;
1863	*reg = RK3368_DRV_PMU_OFFSET;
1864
1865	*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1866	*bit = pin_num % RK3288_DRV_PINS_PER_REG;
1867	*bit *= RK3288_DRV_BITS_PER_PIN;
1868	} else {
1869	*regmap = info->regmap_base;
1870	*reg = RK3368_DRV_GRF_OFFSET;
1871
1872	/* correct the offset, as we're starting with the 2nd bank */
1873	*reg -= 0x10;
1874	*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1875	*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1876
1877	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1878	*bit *= RK3288_DRV_BITS_PER_PIN;
1879	}
1880
1881	return 0;
1882	}
1883
1884	#define RK3399_PULL_GRF_OFFSET 0xe040
1885	#define RK3399_PULL_PMU_OFFSET 0x40
1886	#define RK3399_DRV_3BITS_PER_PIN 3
1887
1888	static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1889	int pin_num, struct regmap **regmap,
1890	int *reg, u8 *bit)
1891	{
1892	struct rockchip_pinctrl *info = bank->drvdata;
1893
1894	/* The bank0:16 and bank1:32 pins are located in PMU */
1895	if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1896	*regmap = info->regmap_pmu;
1897	*reg = RK3399_PULL_PMU_OFFSET;
1898
1899	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1900
1901	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1902	*bit = pin_num % RK3188_PULL_PINS_PER_REG;
1903	*bit *= RK3188_PULL_BITS_PER_PIN;
1904	} else {
1905	*regmap = info->regmap_base;
1906	*reg = RK3399_PULL_GRF_OFFSET;
1907
1908	/* correct the offset, as we're starting with the 3rd bank */
1909	*reg -= 0x20;
1910	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1911	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1912
1913	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1914	*bit *= RK3188_PULL_BITS_PER_PIN;
1915	}
1916
1917	return 0;
1918	}
1919
1920	static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1921	int pin_num, struct regmap **regmap,
1922	int *reg, u8 *bit)
1923	{
1924	struct rockchip_pinctrl *info = bank->drvdata;
1925	int drv_num = (pin_num / 8);
1926
1927	/* The bank0:16 and bank1:32 pins are located in PMU */
1928	if ((bank->bank_num == 0) || (bank->bank_num == 1))
1929	*regmap = info->regmap_pmu;
1930	else
1931	*regmap = info->regmap_base;
1932
1933	*reg = bank->drv[drv_num].offset;
1934	if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1935	(bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1936	*bit = (pin_num % 8) * 3;
1937	else
1938	*bit = (pin_num % 8) * 2;
1939
1940	return 0;
1941	}
1942
1943	#define RK3568_PULL_PMU_OFFSET 0x20
1944	#define RK3568_PULL_GRF_OFFSET 0x80
1945	#define RK3568_PULL_BITS_PER_PIN 2
1946	#define RK3568_PULL_PINS_PER_REG 8
1947	#define RK3568_PULL_BANK_STRIDE 0x10
1948
1949	static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1950	int pin_num, struct regmap **regmap,
1951	int *reg, u8 *bit)
1952	{
1953	struct rockchip_pinctrl *info = bank->drvdata;
1954
1955	if (bank->bank_num == 0) {
1956	*regmap = info->regmap_pmu;
1957	*reg = RK3568_PULL_PMU_OFFSET;
1958	*reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
1959	*reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1960
1961	*bit = pin_num % RK3568_PULL_PINS_PER_REG;
1962	*bit *= RK3568_PULL_BITS_PER_PIN;
1963	} else {
1964	*regmap = info->regmap_base;
1965	*reg = RK3568_PULL_GRF_OFFSET;
1966	*reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
1967	*reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
1968
1969	*bit = (pin_num % RK3568_PULL_PINS_PER_REG);
1970	*bit *= RK3568_PULL_BITS_PER_PIN;
1971	}
1972
1973	return 0;
1974	}
1975
1976	#define RK3568_DRV_PMU_OFFSET 0x70
1977	#define RK3568_DRV_GRF_OFFSET 0x200
1978	#define RK3568_DRV_BITS_PER_PIN 8
1979	#define RK3568_DRV_PINS_PER_REG 2
1980	#define RK3568_DRV_BANK_STRIDE 0x40
1981
1982	static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1983	int pin_num, struct regmap **regmap,
1984	int *reg, u8 *bit)
1985	{
1986	struct rockchip_pinctrl *info = bank->drvdata;
1987
1988	/* The first 32 pins of the first bank are located in PMU */
1989	if (bank->bank_num == 0) {
1990	*regmap = info->regmap_pmu;
1991	*reg = RK3568_DRV_PMU_OFFSET;
1992	*reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
1993
1994	*bit = pin_num % RK3568_DRV_PINS_PER_REG;
1995	*bit *= RK3568_DRV_BITS_PER_PIN;
1996	} else {
1997	*regmap = info->regmap_base;
1998	*reg = RK3568_DRV_GRF_OFFSET;
1999	*reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
2000	*reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2001
2002	*bit = (pin_num % RK3568_DRV_PINS_PER_REG);
2003	*bit *= RK3568_DRV_BITS_PER_PIN;
2004	}
2005
2006	return 0;
2007	}
2008
2009	#define RK3588_PMU1_IOC_REG (0x0000)
2010	#define RK3588_PMU2_IOC_REG (0x4000)
2011	#define RK3588_BUS_IOC_REG (0x8000)
2012	#define RK3588_VCCIO1_4_IOC_REG (0x9000)
2013	#define RK3588_VCCIO3_5_IOC_REG (0xA000)
2014	#define RK3588_VCCIO2_IOC_REG (0xB000)
2015	#define RK3588_VCCIO6_IOC_REG (0xC000)
2016	#define RK3588_EMMC_IOC_REG (0xD000)
2017
2018	static const u32 rk3588_ds_regs[][2] = {
2019	{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
2020	{RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
2021	{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
2022	{RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
2023	{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
2024	{RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
2025	{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
2026	{RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
2027	{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
2028	{RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
2029	{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
2030	{RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
2031	{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
2032	{RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
2033	{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
2034	{RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
2035	{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
2036	{RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
2037	{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
2038	{RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
2039	{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
2040	{RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
2041	{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
2042	{RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
2043	{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
2044	{RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
2045	{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
2046	{RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
2047	{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
2048	{RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
2049	{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
2050	{RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
2051	{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
2052	{RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
2053	{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
2054	{RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
2055	{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
2056	{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
2057	{RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
2058	{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
2059	{RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
2060	};
2061
2062	static const u32 rk3588_p_regs[][2] = {
2063	{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
2064	{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
2065	{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
2066	{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
2067	{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
2068	{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
2069	{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
2070	{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
2071	{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
2072	{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
2073	{RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
2074	{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
2075	{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
2076	{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
2077	{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
2078	{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
2079	{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
2080	{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
2081	{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
2082	{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
2083	{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
2084	{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
2085	{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
2086	};
2087
2088	static const u32 rk3588_smt_regs[][2] = {
2089	{RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
2090	{RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
2091	{RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
2092	{RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
2093	{RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
2094	{RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
2095	{RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
2096	{RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
2097	{RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
2098	{RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
2099	{RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
2100	{RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
2101	{RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
2102	{RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
2103	{RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
2104	{RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
2105	{RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
2106	{RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
2107	{RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
2108	{RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
2109	{RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
2110	{RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
2111	{RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
2112	};
2113
2114	#define RK3588_PULL_BITS_PER_PIN 2
2115	#define RK3588_PULL_PINS_PER_REG 8
2116
2117	static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2118	int pin_num, struct regmap **regmap,
2119	int *reg, u8 *bit)
2120	{
2121	struct rockchip_pinctrl *info = bank->drvdata;
2122	u8 bank_num = bank->bank_num;
2123	u32 pin = bank_num * 32 + pin_num;
2124	int i;
2125
2126	for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
2127	if (pin >= rk3588_p_regs[i][0]) {
2128	*reg = rk3588_p_regs[i][1];
2129	*regmap = info->regmap_base;
2130	*bit = pin_num % RK3588_PULL_PINS_PER_REG;
2131	*bit *= RK3588_PULL_BITS_PER_PIN;
2132	return 0;
2133	}
2134	}
2135
2136	return -EINVAL;
2137	}
2138
2139	#define RK3588_DRV_BITS_PER_PIN 4
2140	#define RK3588_DRV_PINS_PER_REG 4
2141
2142	static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2143	int pin_num, struct regmap **regmap,
2144	int *reg, u8 *bit)
2145	{
2146	struct rockchip_pinctrl *info = bank->drvdata;
2147	u8 bank_num = bank->bank_num;
2148	u32 pin = bank_num * 32 + pin_num;
2149	int i;
2150
2151	for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
2152	if (pin >= rk3588_ds_regs[i][0]) {
2153	*reg = rk3588_ds_regs[i][1];
2154	*regmap = info->regmap_base;
2155	*bit = pin_num % RK3588_DRV_PINS_PER_REG;
2156	*bit *= RK3588_DRV_BITS_PER_PIN;
2157	return 0;
2158	}
2159	}
2160
2161	return -EINVAL;
2162	}
2163
2164	#define RK3588_SMT_BITS_PER_PIN 1
2165	#define RK3588_SMT_PINS_PER_REG 8
2166
2167	static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2168	int pin_num,
2169	struct regmap **regmap,
2170	int *reg, u8 *bit)
2171	{
2172	struct rockchip_pinctrl *info = bank->drvdata;
2173	u8 bank_num = bank->bank_num;
2174	u32 pin = bank_num * 32 + pin_num;
2175	int i;
2176
2177	for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
2178	if (pin >= rk3588_smt_regs[i][0]) {
2179	*reg = rk3588_smt_regs[i][1];
2180	*regmap = info->regmap_base;
2181	*bit = pin_num % RK3588_SMT_PINS_PER_REG;
2182	*bit *= RK3588_SMT_BITS_PER_PIN;
2183	return 0;
2184	}
2185	}
2186
2187	return -EINVAL;
2188	}
2189
2190	static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2191	{ 2, 4, 8, 12, -1, -1, -1, -1 },
2192	{ 3, 6, 9, 12, -1, -1, -1, -1 },
2193	{ 5, 10, 15, 20, -1, -1, -1, -1 },
2194	{ 4, 6, 8, 10, 12, 14, 16, 18 },
2195	{ 4, 7, 10, 13, 16, 19, 22, 26 }
2196	};
2197
2198	static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2199	int pin_num)
2200	{
2201	struct rockchip_pinctrl *info = bank->drvdata;
2202	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2203	struct device *dev = info->dev;
2204	struct regmap *regmap;
2205	int reg, ret;
2206	u32 data, temp, rmask_bits;
2207	u8 bit;
2208	int drv_type = bank->drv[pin_num / 8].drv_type;
2209
2210	ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2211	if (ret)
2212	return ret;
2213
2214	switch (drv_type) {
2215	case DRV_TYPE_IO_1V8_3V0_AUTO:
2216	case DRV_TYPE_IO_3V3_ONLY:
2217	rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2218	switch (bit) {
2219	case 0 ... 12:
2220	/* regular case, nothing to do */
2221	break;
2222	case 15:
2223	/*
2224	* drive-strength offset is special, as it is
2225	* spread over 2 registers
2226	*/
2227	ret = regmap_read(map: regmap, reg, val: &data);
2228	if (ret)
2229	return ret;
2230
2231	ret = regmap_read(map: regmap, reg: reg + 0x4, val: &temp);
2232	if (ret)
2233	return ret;
2234
2235	/*
2236	* the bit data[15] contains bit 0 of the value
2237	* while temp[1:0] contains bits 2 and 1
2238	*/
2239	data >>= 15;
2240	temp &= 0x3;
2241	temp <<= 1;
2242	data |= temp;
2243
2244	return rockchip_perpin_drv_list[drv_type][data];
2245	case 18 ... 21:
2246	/* setting fully enclosed in the second register */
2247	reg += 4;
2248	bit -= 16;
2249	break;
2250	default:
2251	dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2252	bit, drv_type);
2253	return -EINVAL;
2254	}
2255
2256	break;
2257	case DRV_TYPE_IO_DEFAULT:
2258	case DRV_TYPE_IO_1V8_OR_3V0:
2259	case DRV_TYPE_IO_1V8_ONLY:
2260	rmask_bits = RK3288_DRV_BITS_PER_PIN;
2261	break;
2262	default:
2263	dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2264	return -EINVAL;
2265	}
2266
2267	ret = regmap_read(map: regmap, reg, val: &data);
2268	if (ret)
2269	return ret;
2270
2271	data >>= bit;
2272	data &= (1 << rmask_bits) - 1;
2273
2274	return rockchip_perpin_drv_list[drv_type][data];
2275	}
2276
2277	static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2278	int pin_num, int strength)
2279	{
2280	struct rockchip_pinctrl *info = bank->drvdata;
2281	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2282	struct device *dev = info->dev;
2283	struct regmap *regmap;
2284	int reg, ret, i;
2285	u32 data, rmask, rmask_bits, temp;
2286	u8 bit;
2287	int drv_type = bank->drv[pin_num / 8].drv_type;
2288
2289	dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
2290	bank->bank_num, pin_num, strength);
2291
2292	ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2293	if (ret)
2294	return ret;
2295	if (ctrl->type == RK3588) {
2296	rmask_bits = RK3588_DRV_BITS_PER_PIN;
2297	ret = strength;
2298	goto config;
2299	} else if (ctrl->type == RK3568) {
2300	rmask_bits = RK3568_DRV_BITS_PER_PIN;
2301	ret = (1 << (strength + 1)) - 1;
2302	goto config;
2303	}
2304
2305	if (ctrl->type == RV1126) {
2306	rmask_bits = RV1126_DRV_BITS_PER_PIN;
2307	ret = strength;
2308	goto config;
2309	}
2310
2311	ret = -EINVAL;
2312	for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2313	if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2314	ret = i;
2315	break;
2316	} else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2317	ret = rockchip_perpin_drv_list[drv_type][i];
2318	break;
2319	}
2320	}
2321
2322	if (ret < 0) {
2323	dev_err(dev, "unsupported driver strength %d\n", strength);
2324	return ret;
2325	}
2326
2327	switch (drv_type) {
2328	case DRV_TYPE_IO_1V8_3V0_AUTO:
2329	case DRV_TYPE_IO_3V3_ONLY:
2330	rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2331	switch (bit) {
2332	case 0 ... 12:
2333	/* regular case, nothing to do */
2334	break;
2335	case 15:
2336	/*
2337	* drive-strength offset is special, as it is spread
2338	* over 2 registers, the bit data[15] contains bit 0
2339	* of the value while temp[1:0] contains bits 2 and 1
2340	*/
2341	data = (ret & 0x1) << 15;
2342	temp = (ret >> 0x1) & 0x3;
2343
2344	rmask = BIT(15) | BIT(31);
2345	data |= BIT(31);
2346	ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
2347	if (ret)
2348	return ret;
2349
2350	rmask = 0x3 | (0x3 << 16);
2351	temp |= (0x3 << 16);
2352	reg += 0x4;
2353	ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: temp);
2354
2355	return ret;
2356	case 18 ... 21:
2357	/* setting fully enclosed in the second register */
2358	reg += 4;
2359	bit -= 16;
2360	break;
2361	default:
2362	dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2363	bit, drv_type);
2364	return -EINVAL;
2365	}
2366	break;
2367	case DRV_TYPE_IO_DEFAULT:
2368	case DRV_TYPE_IO_1V8_OR_3V0:
2369	case DRV_TYPE_IO_1V8_ONLY:
2370	rmask_bits = RK3288_DRV_BITS_PER_PIN;
2371	break;
2372	default:
2373	dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2374	return -EINVAL;
2375	}
2376
2377	config:
2378	/* enable the write to the equivalent lower bits */
2379	data = ((1 << rmask_bits) - 1) << (bit + 16);
2380	rmask = data | (data >> 16);
2381	data |= (ret << bit);
2382
2383	ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
2384
2385	return ret;
2386	}
2387
2388	static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2389	{
2390	PIN_CONFIG_BIAS_DISABLE,
2391	PIN_CONFIG_BIAS_PULL_UP,
2392	PIN_CONFIG_BIAS_PULL_DOWN,
2393	PIN_CONFIG_BIAS_BUS_HOLD
2394	},
2395	{
2396	PIN_CONFIG_BIAS_DISABLE,
2397	PIN_CONFIG_BIAS_PULL_DOWN,
2398	PIN_CONFIG_BIAS_DISABLE,
2399	PIN_CONFIG_BIAS_PULL_UP
2400	},
2401	};
2402
2403	static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2404	{
2405	struct rockchip_pinctrl *info = bank->drvdata;
2406	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2407	struct device *dev = info->dev;
2408	struct regmap *regmap;
2409	int reg, ret, pull_type;
2410	u8 bit;
2411	u32 data;
2412
2413	/* rk3066b does support any pulls */
2414	if (ctrl->type == RK3066B)
2415	return PIN_CONFIG_BIAS_DISABLE;
2416
2417	ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2418	if (ret)
2419	return ret;
2420
2421	ret = regmap_read(map: regmap, reg, val: &data);
2422	if (ret)
2423	return ret;
2424
2425	switch (ctrl->type) {
2426	case RK2928:
2427	case RK3128:
2428	return !(data & BIT(bit))
2429	? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2430	: PIN_CONFIG_BIAS_DISABLE;
2431	case PX30:
2432	case RV1108:
2433	case RK3188:
2434	case RK3288:
2435	case RK3308:
2436	case RK3368:
2437	case RK3399:
2438	case RK3568:
2439	case RK3588:
2440	pull_type = bank->pull_type[pin_num / 8];
2441	data >>= bit;
2442	data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2443	/*
2444	* In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2445	* where that pull up value becomes 3.
2446	*/
2447	if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2448	if (data == 3)
2449	data = 1;
2450	}
2451
2452	return rockchip_pull_list[pull_type][data];
2453	default:
2454	dev_err(dev, "unsupported pinctrl type\n");
2455	return -EINVAL;
2456	};
2457	}
2458
2459	static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2460	int pin_num, int pull)
2461	{
2462	struct rockchip_pinctrl *info = bank->drvdata;
2463	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2464	struct device *dev = info->dev;
2465	struct regmap *regmap;
2466	int reg, ret, i, pull_type;
2467	u8 bit;
2468	u32 data, rmask;
2469
2470	dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
2471
2472	/* rk3066b does support any pulls */
2473	if (ctrl->type == RK3066B)
2474	return pull ? -EINVAL : 0;
2475
2476	ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2477	if (ret)
2478	return ret;
2479
2480	switch (ctrl->type) {
2481	case RK2928:
2482	case RK3128:
2483	data = BIT(bit + 16);
2484	if (pull == PIN_CONFIG_BIAS_DISABLE)
2485	data |= BIT(bit);
2486	ret = regmap_write(map: regmap, reg, val: data);
2487	break;
2488	case PX30:
2489	case RV1108:
2490	case RV1126:
2491	case RK3188:
2492	case RK3288:
2493	case RK3308:
2494	case RK3368:
2495	case RK3399:
2496	case RK3568:
2497	case RK3588:
2498	pull_type = bank->pull_type[pin_num / 8];
2499	ret = -EINVAL;
2500	for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2501	i++) {
2502	if (rockchip_pull_list[pull_type][i] == pull) {
2503	ret = i;
2504	break;
2505	}
2506	}
2507	/*
2508	* In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2509	* where that pull up value becomes 3.
2510	*/
2511	if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2512	if (ret == 1)
2513	ret = 3;
2514	}
2515
2516	if (ret < 0) {
2517	dev_err(dev, "unsupported pull setting %d\n", pull);
2518	return ret;
2519	}
2520
2521	/* enable the write to the equivalent lower bits */
2522	data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2523	rmask = data | (data >> 16);
2524	data |= (ret << bit);
2525
2526	ret = regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
2527	break;
2528	default:
2529	dev_err(dev, "unsupported pinctrl type\n");
2530	return -EINVAL;
2531	}
2532
2533	return ret;
2534	}
2535
2536	#define RK3328_SCHMITT_BITS_PER_PIN 1
2537	#define RK3328_SCHMITT_PINS_PER_REG 16
2538	#define RK3328_SCHMITT_BANK_STRIDE 8
2539	#define RK3328_SCHMITT_GRF_OFFSET 0x380
2540
2541	static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2542	int pin_num,
2543	struct regmap **regmap,
2544	int *reg, u8 *bit)
2545	{
2546	struct rockchip_pinctrl *info = bank->drvdata;
2547
2548	*regmap = info->regmap_base;
2549	*reg = RK3328_SCHMITT_GRF_OFFSET;
2550
2551	*reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2552	*reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2553	*bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2554
2555	return 0;
2556	}
2557
2558	#define RK3568_SCHMITT_BITS_PER_PIN 2
2559	#define RK3568_SCHMITT_PINS_PER_REG 8
2560	#define RK3568_SCHMITT_BANK_STRIDE 0x10
2561	#define RK3568_SCHMITT_GRF_OFFSET 0xc0
2562	#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
2563
2564	static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2565	int pin_num,
2566	struct regmap **regmap,
2567	int *reg, u8 *bit)
2568	{
2569	struct rockchip_pinctrl *info = bank->drvdata;
2570
2571	if (bank->bank_num == 0) {
2572	*regmap = info->regmap_pmu;
2573	*reg = RK3568_SCHMITT_PMUGRF_OFFSET;
2574	} else {
2575	*regmap = info->regmap_base;
2576	*reg = RK3568_SCHMITT_GRF_OFFSET;
2577	*reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
2578	}
2579
2580	*reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
2581	*bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
2582	*bit *= RK3568_SCHMITT_BITS_PER_PIN;
2583
2584	return 0;
2585	}
2586
2587	static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2588	{
2589	struct rockchip_pinctrl *info = bank->drvdata;
2590	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2591	struct regmap *regmap;
2592	int reg, ret;
2593	u8 bit;
2594	u32 data;
2595
2596	ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2597	if (ret)
2598	return ret;
2599
2600	ret = regmap_read(map: regmap, reg, val: &data);
2601	if (ret)
2602	return ret;
2603
2604	data >>= bit;
2605	switch (ctrl->type) {
2606	case RK3568:
2607	return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2608	default:
2609	break;
2610	}
2611
2612	return data & 0x1;
2613	}
2614
2615	static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2616	int pin_num, int enable)
2617	{
2618	struct rockchip_pinctrl *info = bank->drvdata;
2619	struct rockchip_pin_ctrl *ctrl = info->ctrl;
2620	struct device *dev = info->dev;
2621	struct regmap *regmap;
2622	int reg, ret;
2623	u8 bit;
2624	u32 data, rmask;
2625
2626	dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
2627	bank->bank_num, pin_num, enable);
2628
2629	ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2630	if (ret)
2631	return ret;
2632
2633	/* enable the write to the equivalent lower bits */
2634	switch (ctrl->type) {
2635	case RK3568:
2636	data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2637	rmask = data | (data >> 16);
2638	data |= ((enable ? 0x2 : 0x1) << bit);
2639	break;
2640	default:
2641	data = BIT(bit + 16) | (enable << bit);
2642	rmask = BIT(bit + 16) | BIT(bit);
2643	break;
2644	}
2645
2646	return regmap_update_bits(map: regmap, reg, mask: rmask, val: data);
2647	}
2648
2649	/*
2650	* Pinmux_ops handling
2651	*/
2652
2653	static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2654	{
2655	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2656
2657	return info->nfunctions;
2658	}
2659
2660	static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2661	unsigned selector)
2662	{
2663	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2664
2665	return info->functions[selector].name;
2666	}
2667
2668	static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2669	unsigned selector, const char * const **groups,
2670	unsigned * const num_groups)
2671	{
2672	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2673
2674	*groups = info->functions[selector].groups;
2675	*num_groups = info->functions[selector].ngroups;
2676
2677	return 0;
2678	}
2679
2680	static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2681	unsigned group)
2682	{
2683	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2684	const unsigned int *pins = info->groups[group].pins;
2685	const struct rockchip_pin_config *data = info->groups[group].data;
2686	struct device *dev = info->dev;
2687	struct rockchip_pin_bank *bank;
2688	int cnt, ret = 0;
2689
2690	dev_dbg(dev, "enable function %s group %s\n",
2691	info->functions[selector].name, info->groups[group].name);
2692
2693	/*
2694	* for each pin in the pin group selected, program the corresponding
2695	* pin function number in the config register.
2696	*/
2697	for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2698	bank = pin_to_bank(info, pin: pins[cnt]);
2699	ret = rockchip_set_mux(bank, pin: pins[cnt] - bank->pin_base,
2700	mux: data[cnt].func);
2701	if (ret)
2702	break;
2703	}
2704
2705	if (ret) {
2706	/* revert the already done pin settings */
2707	for (cnt--; cnt >= 0; cnt--)
2708	rockchip_set_mux(bank, pin: pins[cnt] - bank->pin_base, mux: 0);
2709
2710	return ret;
2711	}
2712
2713	return 0;
2714	}
2715
2716	static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2717	struct pinctrl_gpio_range *range,
2718	unsigned offset,
2719	bool input)
2720	{
2721	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2722	struct rockchip_pin_bank *bank;
2723
2724	bank = pin_to_bank(info, pin: offset);
2725	return rockchip_set_mux(bank, pin: offset - bank->pin_base, RK_FUNC_GPIO);
2726	}
2727
2728	static const struct pinmux_ops rockchip_pmx_ops = {
2729	.get_functions_count = rockchip_pmx_get_funcs_count,
2730	.get_function_name = rockchip_pmx_get_func_name,
2731	.get_function_groups = rockchip_pmx_get_groups,
2732	.set_mux = rockchip_pmx_set,
2733	.gpio_set_direction = rockchip_pmx_gpio_set_direction,
2734	};
2735
2736	/*
2737	* Pinconf_ops handling
2738	*/
2739
2740	static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2741	enum pin_config_param pull)
2742	{
2743	switch (ctrl->type) {
2744	case RK2928:
2745	case RK3128:
2746	return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2747	pull == PIN_CONFIG_BIAS_DISABLE);
2748	case RK3066B:
2749	return pull ? false : true;
2750	case PX30:
2751	case RV1108:
2752	case RV1126:
2753	case RK3188:
2754	case RK3288:
2755	case RK3308:
2756	case RK3368:
2757	case RK3399:
2758	case RK3568:
2759	case RK3588:
2760	return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2761	}
2762
2763	return false;
2764	}
2765
2766	static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
2767	unsigned int pin, u32 param, u32 arg)
2768	{
2769	struct rockchip_pin_deferred *cfg;
2770
2771	cfg = kzalloc(size: sizeof(*cfg), GFP_KERNEL);
2772	if (!cfg)
2773	return -ENOMEM;
2774
2775	cfg->pin = pin;
2776	cfg->param = param;
2777	cfg->arg = arg;
2778
2779	list_add_tail(new: &cfg->head, head: &bank->deferred_pins);
2780
2781	return 0;
2782	}
2783
2784	/* set the pin config settings for a specified pin */
2785	static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2786	unsigned long *configs, unsigned num_configs)
2787	{
2788	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2789	struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2790	struct gpio_chip *gpio = &bank->gpio_chip;
2791	enum pin_config_param param;
2792	u32 arg;
2793	int i;
2794	int rc;
2795
2796	for (i = 0; i < num_configs; i++) {
2797	param = pinconf_to_config_param(config: configs[i]);
2798	arg = pinconf_to_config_argument(config: configs[i]);
2799
2800	if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
2801	/*
2802	* Check for gpio driver not being probed yet.
2803	* The lock makes sure that either gpio-probe has completed
2804	* or the gpio driver hasn't probed yet.
2805	*/
2806	mutex_lock(&bank->deferred_lock);
2807	if (!gpio || !gpio->direction_output) {
2808	rc = rockchip_pinconf_defer_pin(bank, pin: pin - bank->pin_base, param,
2809	arg);
2810	mutex_unlock(lock: &bank->deferred_lock);
2811	if (rc)
2812	return rc;
2813
2814	break;
2815	}
2816	mutex_unlock(lock: &bank->deferred_lock);
2817	}
2818
2819	switch (param) {
2820	case PIN_CONFIG_BIAS_DISABLE:
2821	rc = rockchip_set_pull(bank, pin_num: pin - bank->pin_base,
2822	pull: param);
2823	if (rc)
2824	return rc;
2825	break;
2826	case PIN_CONFIG_BIAS_PULL_UP:
2827	case PIN_CONFIG_BIAS_PULL_DOWN:
2828	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2829	case PIN_CONFIG_BIAS_BUS_HOLD:
2830	if (!rockchip_pinconf_pull_valid(ctrl: info->ctrl, pull: param))
2831	return -ENOTSUPP;
2832
2833	if (!arg)
2834	return -EINVAL;
2835
2836	rc = rockchip_set_pull(bank, pin_num: pin - bank->pin_base,
2837	pull: param);
2838	if (rc)
2839	return rc;
2840	break;
2841	case PIN_CONFIG_OUTPUT:
2842	rc = rockchip_set_mux(bank, pin: pin - bank->pin_base,
2843	RK_FUNC_GPIO);
2844	if (rc != RK_FUNC_GPIO)
2845	return -EINVAL;
2846
2847	rc = gpio->direction_output(gpio, pin - bank->pin_base,
2848	arg);
2849	if (rc)
2850	return rc;
2851	break;
2852	case PIN_CONFIG_INPUT_ENABLE:
2853	rc = rockchip_set_mux(bank, pin: pin - bank->pin_base,
2854	RK_FUNC_GPIO);
2855	if (rc != RK_FUNC_GPIO)
2856	return -EINVAL;
2857
2858	rc = gpio->direction_input(gpio, pin - bank->pin_base);
2859	if (rc)
2860	return rc;
2861	break;
2862	case PIN_CONFIG_DRIVE_STRENGTH:
2863	/* rk3288 is the first with per-pin drive-strength */
2864	if (!info->ctrl->drv_calc_reg)
2865	return -ENOTSUPP;
2866
2867	rc = rockchip_set_drive_perpin(bank,
2868	pin_num: pin - bank->pin_base, strength: arg);
2869	if (rc < 0)
2870	return rc;
2871	break;
2872	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2873	if (!info->ctrl->schmitt_calc_reg)
2874	return -ENOTSUPP;
2875
2876	rc = rockchip_set_schmitt(bank,
2877	pin_num: pin - bank->pin_base, enable: arg);
2878	if (rc < 0)
2879	return rc;
2880	break;
2881	default:
2882	return -ENOTSUPP;
2883	break;
2884	}
2885	} /* for each config */
2886
2887	return 0;
2888	}
2889
2890	/* get the pin config settings for a specified pin */
2891	static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2892	unsigned long *config)
2893	{
2894	struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2895	struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2896	struct gpio_chip *gpio = &bank->gpio_chip;
2897	enum pin_config_param param = pinconf_to_config_param(config: *config);
2898	u16 arg;
2899	int rc;
2900
2901	switch (param) {
2902	case PIN_CONFIG_BIAS_DISABLE:
2903	if (rockchip_get_pull(bank, pin_num: pin - bank->pin_base) != param)
2904	return -EINVAL;
2905
2906	arg = 0;
2907	break;
2908	case PIN_CONFIG_BIAS_PULL_UP:
2909	case PIN_CONFIG_BIAS_PULL_DOWN:
2910	case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
2911	case PIN_CONFIG_BIAS_BUS_HOLD:
2912	if (!rockchip_pinconf_pull_valid(ctrl: info->ctrl, pull: param))
2913	return -ENOTSUPP;
2914
2915	if (rockchip_get_pull(bank, pin_num: pin - bank->pin_base) != param)
2916	return -EINVAL;
2917
2918	arg = 1;
2919	break;
2920	case PIN_CONFIG_OUTPUT:
2921	rc = rockchip_get_mux(bank, pin: pin - bank->pin_base);
2922	if (rc != RK_FUNC_GPIO)
2923	return -EINVAL;
2924
2925	if (!gpio || !gpio->get) {
2926	arg = 0;
2927	break;
2928	}
2929
2930	rc = gpio->get(gpio, pin - bank->pin_base);
2931	if (rc < 0)
2932	return rc;
2933
2934	arg = rc ? 1 : 0;
2935	break;
2936	case PIN_CONFIG_DRIVE_STRENGTH:
2937	/* rk3288 is the first with per-pin drive-strength */
2938	if (!info->ctrl->drv_calc_reg)
2939	return -ENOTSUPP;
2940
2941	rc = rockchip_get_drive_perpin(bank, pin_num: pin - bank->pin_base);
2942	if (rc < 0)
2943	return rc;
2944
2945	arg = rc;
2946	break;
2947	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2948	if (!info->ctrl->schmitt_calc_reg)
2949	return -ENOTSUPP;
2950
2951	rc = rockchip_get_schmitt(bank, pin_num: pin - bank->pin_base);
2952	if (rc < 0)
2953	return rc;
2954
2955	arg = rc;
2956	break;
2957	default:
2958	return -ENOTSUPP;
2959	break;
2960	}
2961
2962	*config = pinconf_to_config_packed(param, argument: arg);
2963
2964	return 0;
2965	}
2966
2967	static const struct pinconf_ops rockchip_pinconf_ops = {
2968	.pin_config_get = rockchip_pinconf_get,
2969	.pin_config_set = rockchip_pinconf_set,
2970	.is_generic = true,
2971	};
2972
2973	static const struct of_device_id rockchip_bank_match[] = {
2974	{ .compatible = "rockchip,gpio-bank" },
2975	{ .compatible = "rockchip,rk3188-gpio-bank0" },
2976	{},
2977	};
2978
2979	static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2980	struct device_node *np)
2981	{
2982	struct device_node *child;
2983
2984	for_each_child_of_node(np, child) {
2985	if (of_match_node(matches: rockchip_bank_match, node: child))
2986	continue;
2987
2988	info->nfunctions++;
2989	info->ngroups += of_get_child_count(np: child);
2990	}
2991	}
2992
2993	static int rockchip_pinctrl_parse_groups(struct device_node *np,
2994	struct rockchip_pin_group *grp,
2995	struct rockchip_pinctrl *info,
2996	u32 index)
2997	{
2998	struct device *dev = info->dev;
2999	struct rockchip_pin_bank *bank;
3000	int size;
3001	const __be32 *list;
3002	int num;
3003	int i, j;
3004	int ret;
3005
3006	dev_dbg(dev, "group(%d): %pOFn\n", index, np);
3007
3008	/* Initialise group */
3009	grp->name = np->name;
3010
3011	/*
3012	* the binding format is rockchip,pins = <bank pin mux CONFIG>,
3013	* do sanity check and calculate pins number
3014	*/
3015	list = of_get_property(node: np, name: "rockchip,pins", lenp: &size);
3016	/* we do not check return since it's safe node passed down */
3017	size /= sizeof(*list);
3018	if (!size || size % 4)
3019	return dev_err_probe(dev, err: -EINVAL, fmt: "wrong pins number or pins and configs should be by 4\n");
3020
3021	grp->npins = size / 4;
3022
3023	grp->pins = devm_kcalloc(dev, n: grp->npins, size: sizeof(*grp->pins), GFP_KERNEL);
3024	grp->data = devm_kcalloc(dev, n: grp->npins, size: sizeof(*grp->data), GFP_KERNEL);
3025	if (!grp->pins || !grp->data)
3026	return -ENOMEM;
3027
3028	for (i = 0, j = 0; i < size; i += 4, j++) {
3029	const __be32 *phandle;
3030	struct device_node *np_config;
3031
3032	num = be32_to_cpu(*list++);
3033	bank = bank_num_to_bank(info, num);
3034	if (IS_ERR(ptr: bank))
3035	return PTR_ERR(ptr: bank);
3036
3037	grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
3038	grp->data[j].func = be32_to_cpu(*list++);
3039
3040	phandle = list++;
3041	if (!phandle)
3042	return -EINVAL;
3043
3044	np_config = of_find_node_by_phandle(be32_to_cpup(p: phandle));
3045	ret = pinconf_generic_parse_dt_config(np: np_config, NULL,
3046	configs: &grp->data[j].configs, nconfigs: &grp->data[j].nconfigs);
3047	of_node_put(node: np_config);
3048	if (ret)
3049	return ret;
3050	}
3051
3052	return 0;
3053	}
3054
3055	static int rockchip_pinctrl_parse_functions(struct device_node *np,
3056	struct rockchip_pinctrl *info,
3057	u32 index)
3058	{
3059	struct device *dev = info->dev;
3060	struct device_node *child;
3061	struct rockchip_pmx_func *func;
3062	struct rockchip_pin_group *grp;
3063	int ret;
3064	static u32 grp_index;
3065	u32 i = 0;
3066
3067	dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
3068
3069	func = &info->functions[index];
3070
3071	/* Initialise function */
3072	func->name = np->name;
3073	func->ngroups = of_get_child_count(np);
3074	if (func->ngroups <= 0)
3075	return 0;
3076
3077	func->groups = devm_kcalloc(dev, n: func->ngroups, size: sizeof(*func->groups), GFP_KERNEL);
3078	if (!func->groups)
3079	return -ENOMEM;
3080
3081	for_each_child_of_node(np, child) {
3082	func->groups[i] = child->name;
3083	grp = &info->groups[grp_index++];
3084	ret = rockchip_pinctrl_parse_groups(np: child, grp, info, index: i++);
3085	if (ret) {
3086	of_node_put(node: child);
3087	return ret;
3088	}
3089	}
3090
3091	return 0;
3092	}
3093
3094	static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
3095	struct rockchip_pinctrl *info)
3096	{
3097	struct device *dev = &pdev->dev;
3098	struct device_node *np = dev->of_node;
3099	struct device_node *child;
3100	int ret;
3101	int i;
3102
3103	rockchip_pinctrl_child_count(info, np);
3104
3105	dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
3106	dev_dbg(dev, "ngroups = %d\n", info->ngroups);
3107
3108	info->functions = devm_kcalloc(dev, n: info->nfunctions, size: sizeof(*info->functions), GFP_KERNEL);
3109	if (!info->functions)
3110	return -ENOMEM;
3111
3112	info->groups = devm_kcalloc(dev, n: info->ngroups, size: sizeof(*info->groups), GFP_KERNEL);
3113	if (!info->groups)
3114	return -ENOMEM;
3115
3116	i = 0;
3117
3118	for_each_child_of_node(np, child) {
3119	if (of_match_node(matches: rockchip_bank_match, node: child))
3120	continue;
3121
3122	ret = rockchip_pinctrl_parse_functions(np: child, info, index: i++);
3123	if (ret) {
3124	dev_err(dev, "failed to parse function\n");
3125	of_node_put(node: child);
3126	return ret;
3127	}
3128	}
3129
3130	return 0;
3131	}
3132
3133	static int rockchip_pinctrl_register(struct platform_device *pdev,
3134	struct rockchip_pinctrl *info)
3135	{
3136	struct pinctrl_desc *ctrldesc = &info->pctl;
3137	struct pinctrl_pin_desc *pindesc, *pdesc;
3138	struct rockchip_pin_bank *pin_bank;
3139	struct device *dev = &pdev->dev;
3140	char **pin_names;
3141	int pin, bank, ret;
3142	int k;
3143
3144	ctrldesc->name = "rockchip-pinctrl";
3145	ctrldesc->owner = THIS_MODULE;
3146	ctrldesc->pctlops = &rockchip_pctrl_ops;
3147	ctrldesc->pmxops = &rockchip_pmx_ops;
3148	ctrldesc->confops = &rockchip_pinconf_ops;
3149
3150	pindesc = devm_kcalloc(dev, n: info->ctrl->nr_pins, size: sizeof(*pindesc), GFP_KERNEL);
3151	if (!pindesc)
3152	return -ENOMEM;
3153
3154	ctrldesc->pins = pindesc;
3155	ctrldesc->npins = info->ctrl->nr_pins;
3156
3157	pdesc = pindesc;
3158	for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
3159	pin_bank = &info->ctrl->pin_banks[bank];
3160
3161	pin_names = devm_kasprintf_strarray(dev, prefix: pin_bank->name, n: pin_bank->nr_pins);
3162	if (IS_ERR(ptr: pin_names))
3163	return PTR_ERR(ptr: pin_names);
3164
3165	for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3166	pdesc->number = k;
3167	pdesc->name = pin_names[pin];
3168	pdesc++;
3169	}
3170
3171	INIT_LIST_HEAD(list: &pin_bank->deferred_pins);
3172	mutex_init(&pin_bank->deferred_lock);
3173	}
3174
3175	ret = rockchip_pinctrl_parse_dt(pdev, info);
3176	if (ret)
3177	return ret;
3178
3179	info->pctl_dev = devm_pinctrl_register(dev, pctldesc: ctrldesc, driver_data: info);
3180	if (IS_ERR(ptr: info->pctl_dev))
3181	return dev_err_probe(dev, err: PTR_ERR(ptr: info->pctl_dev), fmt: "could not register pinctrl driver\n");
3182
3183	return 0;
3184	}
3185
3186	static const struct of_device_id rockchip_pinctrl_dt_match[];
3187
3188	/* retrieve the soc specific data */
3189	static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3190	struct rockchip_pinctrl *d,
3191	struct platform_device *pdev)
3192	{
3193	struct device *dev = &pdev->dev;
3194	struct device_node *node = dev->of_node;
3195	const struct of_device_id *match;
3196	struct rockchip_pin_ctrl *ctrl;
3197	struct rockchip_pin_bank *bank;
3198	int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3199
3200	match = of_match_node(matches: rockchip_pinctrl_dt_match, node);
3201	ctrl = (struct rockchip_pin_ctrl *)match->data;
3202
3203	grf_offs = ctrl->grf_mux_offset;
3204	pmu_offs = ctrl->pmu_mux_offset;
3205	drv_pmu_offs = ctrl->pmu_drv_offset;
3206	drv_grf_offs = ctrl->grf_drv_offset;
3207	bank = ctrl->pin_banks;
3208	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3209	int bank_pins = 0;
3210
3211	raw_spin_lock_init(&bank->slock);
3212	bank->drvdata = d;
3213	bank->pin_base = ctrl->nr_pins;
3214	ctrl->nr_pins += bank->nr_pins;
3215
3216	/* calculate iomux and drv offsets */
3217	for (j = 0; j < 4; j++) {
3218	struct rockchip_iomux *iom = &bank->iomux[j];
3219	struct rockchip_drv *drv = &bank->drv[j];
3220	int inc;
3221
3222	if (bank_pins >= bank->nr_pins)
3223	break;
3224
3225	/* preset iomux offset value, set new start value */
3226	if (iom->offset >= 0) {
3227	if ((iom->type & IOMUX_SOURCE_PMU) ||
3228	(iom->type & IOMUX_L_SOURCE_PMU))
3229	pmu_offs = iom->offset;
3230	else
3231	grf_offs = iom->offset;
3232	} else { /* set current iomux offset */
3233	iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
3234	(iom->type & IOMUX_L_SOURCE_PMU)) ?
3235	pmu_offs : grf_offs;
3236	}
3237
3238	/* preset drv offset value, set new start value */
3239	if (drv->offset >= 0) {
3240	if (iom->type & IOMUX_SOURCE_PMU)
3241	drv_pmu_offs = drv->offset;
3242	else
3243	drv_grf_offs = drv->offset;
3244	} else { /* set current drv offset */
3245	drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3246	drv_pmu_offs : drv_grf_offs;
3247	}
3248
3249	dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3250	i, j, iom->offset, drv->offset);
3251
3252	/*
3253	* Increase offset according to iomux width.
3254	* 4bit iomux'es are spread over two registers.
3255	*/
3256	inc = (iom->type & (IOMUX_WIDTH_4BIT |
3257	IOMUX_WIDTH_3BIT |
3258	IOMUX_WIDTH_2BIT)) ? 8 : 4;
3259	if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3260	pmu_offs += inc;
3261	else
3262	grf_offs += inc;
3263
3264	/*
3265	* Increase offset according to drv width.
3266	* 3bit drive-strenth'es are spread over two registers.
3267	*/
3268	if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3269	(drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3270	inc = 8;
3271	else
3272	inc = 4;
3273
3274	if (iom->type & IOMUX_SOURCE_PMU)
3275	drv_pmu_offs += inc;
3276	else
3277	drv_grf_offs += inc;
3278
3279	bank_pins += 8;
3280	}
3281
3282	/* calculate the per-bank recalced_mask */
3283	for (j = 0; j < ctrl->niomux_recalced; j++) {
3284	int pin = 0;
3285
3286	if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3287	pin = ctrl->iomux_recalced[j].pin;
3288	bank->recalced_mask |= BIT(pin);
3289	}
3290	}
3291
3292	/* calculate the per-bank route_mask */
3293	for (j = 0; j < ctrl->niomux_routes; j++) {
3294	int pin = 0;
3295
3296	if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3297	pin = ctrl->iomux_routes[j].pin;
3298	bank->route_mask |= BIT(pin);
3299	}
3300	}
3301	}
3302
3303	return ctrl;
3304	}
3305
3306	#define RK3288_GRF_GPIO6C_IOMUX 0x64
3307	#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3308
3309	static u32 rk3288_grf_gpio6c_iomux;
3310
3311	static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3312	{
3313	struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3314	int ret = pinctrl_force_sleep(pctldev: info->pctl_dev);
3315
3316	if (ret)
3317	return ret;
3318
3319	/*
3320	* RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3321	* the setting here, and restore it at resume.
3322	*/
3323	if (info->ctrl->type == RK3288) {
3324	ret = regmap_read(map: info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3325	val: &rk3288_grf_gpio6c_iomux);
3326	if (ret) {
3327	pinctrl_force_default(pctldev: info->pctl_dev);
3328	return ret;
3329	}
3330	}
3331
3332	return 0;
3333	}
3334
3335	static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3336	{
3337	struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3338	int ret;
3339
3340	if (info->ctrl->type == RK3288) {
3341	ret = regmap_write(map: info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3342	val: rk3288_grf_gpio6c_iomux |
3343	GPIO6C6_SEL_WRITE_ENABLE);
3344	if (ret)
3345	return ret;
3346	}
3347
3348	return pinctrl_force_default(pctldev: info->pctl_dev);
3349	}
3350
3351	static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3352	rockchip_pinctrl_resume);
3353
3354	static int rockchip_pinctrl_probe(struct platform_device *pdev)
3355	{
3356	struct rockchip_pinctrl *info;
3357	struct device *dev = &pdev->dev;
3358	struct device_node *np = dev->of_node, *node;
3359	struct rockchip_pin_ctrl *ctrl;
3360	struct resource *res;
3361	void __iomem *base;
3362	int ret;
3363
3364	if (!dev->of_node)
3365	return dev_err_probe(dev, err: -ENODEV, fmt: "device tree node not found\n");
3366
3367	info = devm_kzalloc(dev, size: sizeof(*info), GFP_KERNEL);
3368	if (!info)
3369	return -ENOMEM;
3370
3371	info->dev = dev;
3372
3373	ctrl = rockchip_pinctrl_get_soc_data(d: info, pdev);
3374	if (!ctrl)
3375	return dev_err_probe(dev, err: -EINVAL, fmt: "driver data not available\n");
3376	info->ctrl = ctrl;
3377
3378	node = of_parse_phandle(np, phandle_name: "rockchip,grf", index: 0);
3379	if (node) {
3380	info->regmap_base = syscon_node_to_regmap(np: node);
3381	of_node_put(node);
3382	if (IS_ERR(ptr: info->regmap_base))
3383	return PTR_ERR(ptr: info->regmap_base);
3384	} else {
3385	base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res);
3386	if (IS_ERR(ptr: base))
3387	return PTR_ERR(ptr: base);
3388
3389	rockchip_regmap_config.max_register = resource_size(res) - 4;
3390	rockchip_regmap_config.name = "rockchip,pinctrl";
3391	info->regmap_base =
3392	devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3393
3394	/* to check for the old dt-bindings */
3395	info->reg_size = resource_size(res);
3396
3397	/* Honor the old binding, with pull registers as 2nd resource */
3398	if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3399	base = devm_platform_get_and_ioremap_resource(pdev, index: 1, res: &res);
3400	if (IS_ERR(ptr: base))
3401	return PTR_ERR(ptr: base);
3402
3403	rockchip_regmap_config.max_register = resource_size(res) - 4;
3404	rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3405	info->regmap_pull =
3406	devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3407	}
3408	}
3409
3410	/* try to find the optional reference to the pmu syscon */
3411	node = of_parse_phandle(np, phandle_name: "rockchip,pmu", index: 0);
3412	if (node) {
3413	info->regmap_pmu = syscon_node_to_regmap(np: node);
3414	of_node_put(node);
3415	if (IS_ERR(ptr: info->regmap_pmu))
3416	return PTR_ERR(ptr: info->regmap_pmu);
3417	}
3418
3419	ret = rockchip_pinctrl_register(pdev, info);
3420	if (ret)
3421	return ret;
3422
3423	platform_set_drvdata(pdev, data: info);
3424
3425	ret = of_platform_populate(root: np, NULL, NULL, parent: &pdev->dev);
3426	if (ret)
3427	return dev_err_probe(dev, err: ret, fmt: "failed to register gpio device\n");
3428
3429	return 0;
3430	}
3431
3432	static void rockchip_pinctrl_remove(struct platform_device *pdev)
3433	{
3434	struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
3435	struct rockchip_pin_bank *bank;
3436	struct rockchip_pin_deferred *cfg;
3437	int i;
3438
3439	of_platform_depopulate(parent: &pdev->dev);
3440
3441	for (i = 0; i < info->ctrl->nr_banks; i++) {
3442	bank = &info->ctrl->pin_banks[i];
3443
3444	mutex_lock(&bank->deferred_lock);
3445	while (!list_empty(head: &bank->deferred_pins)) {
3446	cfg = list_first_entry(&bank->deferred_pins,
3447	struct rockchip_pin_deferred, head);
3448	list_del(entry: &cfg->head);
3449	kfree(objp: cfg);
3450	}
3451	mutex_unlock(lock: &bank->deferred_lock);
3452	}
3453	}
3454
3455	static struct rockchip_pin_bank px30_pin_banks[] = {
3456	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3457	IOMUX_SOURCE_PMU,
3458	IOMUX_SOURCE_PMU,
3459	IOMUX_SOURCE_PMU
3460	),
3461	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3462	IOMUX_WIDTH_4BIT,
3463	IOMUX_WIDTH_4BIT,
3464	IOMUX_WIDTH_4BIT
3465	),
3466	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3467	IOMUX_WIDTH_4BIT,
3468	IOMUX_WIDTH_4BIT,
3469	IOMUX_WIDTH_4BIT
3470	),
3471	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3472	IOMUX_WIDTH_4BIT,
3473	IOMUX_WIDTH_4BIT,
3474	IOMUX_WIDTH_4BIT
3475	),
3476	};
3477
3478	static struct rockchip_pin_ctrl px30_pin_ctrl = {
3479	.pin_banks = px30_pin_banks,
3480	.nr_banks = ARRAY_SIZE(px30_pin_banks),
3481	.label = "PX30-GPIO",
3482	.type = PX30,
3483	.grf_mux_offset = 0x0,
3484	.pmu_mux_offset = 0x0,
3485	.iomux_routes = px30_mux_route_data,
3486	.niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3487	.pull_calc_reg = px30_calc_pull_reg_and_bit,
3488	.drv_calc_reg = px30_calc_drv_reg_and_bit,
3489	.schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3490	};
3491
3492	static struct rockchip_pin_bank rv1108_pin_banks[] = {
3493	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3494	IOMUX_SOURCE_PMU,
3495	IOMUX_SOURCE_PMU,
3496	IOMUX_SOURCE_PMU),
3497	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3498	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3499	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3500	};
3501
3502	static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3503	.pin_banks = rv1108_pin_banks,
3504	.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3505	.label = "RV1108-GPIO",
3506	.type = RV1108,
3507	.grf_mux_offset = 0x10,
3508	.pmu_mux_offset = 0x0,
3509	.iomux_recalced = rv1108_mux_recalced_data,
3510	.niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3511	.pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3512	.drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3513	.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3514	};
3515
3516	static struct rockchip_pin_bank rv1126_pin_banks[] = {
3517	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3518	IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3519	IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3520	IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
3521	IOMUX_WIDTH_4BIT),
3522	PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
3523	IOMUX_WIDTH_4BIT,
3524	IOMUX_WIDTH_4BIT,
3525	IOMUX_WIDTH_4BIT,
3526	IOMUX_WIDTH_4BIT,
3527	0x10010, 0x10018, 0x10020, 0x10028),
3528	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
3529	IOMUX_WIDTH_4BIT,
3530	IOMUX_WIDTH_4BIT,
3531	IOMUX_WIDTH_4BIT,
3532	IOMUX_WIDTH_4BIT),
3533	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3534	IOMUX_WIDTH_4BIT,
3535	IOMUX_WIDTH_4BIT,
3536	IOMUX_WIDTH_4BIT,
3537	IOMUX_WIDTH_4BIT),
3538	PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
3539	IOMUX_WIDTH_4BIT, 0, 0, 0),
3540	};
3541
3542	static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
3543	.pin_banks = rv1126_pin_banks,
3544	.nr_banks = ARRAY_SIZE(rv1126_pin_banks),
3545	.label = "RV1126-GPIO",
3546	.type = RV1126,
3547	.grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
3548	.pmu_mux_offset = 0x0,
3549	.iomux_routes = rv1126_mux_route_data,
3550	.niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
3551	.iomux_recalced = rv1126_mux_recalced_data,
3552	.niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
3553	.pull_calc_reg = rv1126_calc_pull_reg_and_bit,
3554	.drv_calc_reg = rv1126_calc_drv_reg_and_bit,
3555	.schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
3556	};
3557
3558	static struct rockchip_pin_bank rk2928_pin_banks[] = {
3559	PIN_BANK(0, 32, "gpio0"),
3560	PIN_BANK(1, 32, "gpio1"),
3561	PIN_BANK(2, 32, "gpio2"),
3562	PIN_BANK(3, 32, "gpio3"),
3563	};
3564
3565	static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3566	.pin_banks = rk2928_pin_banks,
3567	.nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3568	.label = "RK2928-GPIO",
3569	.type = RK2928,
3570	.grf_mux_offset = 0xa8,
3571	.pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3572	};
3573
3574	static struct rockchip_pin_bank rk3036_pin_banks[] = {
3575	PIN_BANK(0, 32, "gpio0"),
3576	PIN_BANK(1, 32, "gpio1"),
3577	PIN_BANK(2, 32, "gpio2"),
3578	};
3579
3580	static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3581	.pin_banks = rk3036_pin_banks,
3582	.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3583	.label = "RK3036-GPIO",
3584	.type = RK2928,
3585	.grf_mux_offset = 0xa8,
3586	.pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3587	};
3588
3589	static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3590	PIN_BANK(0, 32, "gpio0"),
3591	PIN_BANK(1, 32, "gpio1"),
3592	PIN_BANK(2, 32, "gpio2"),
3593	PIN_BANK(3, 32, "gpio3"),
3594	PIN_BANK(4, 32, "gpio4"),
3595	PIN_BANK(6, 16, "gpio6"),
3596	};
3597
3598	static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3599	.pin_banks = rk3066a_pin_banks,
3600	.nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3601	.label = "RK3066a-GPIO",
3602	.type = RK2928,
3603	.grf_mux_offset = 0xa8,
3604	.pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3605	};
3606
3607	static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3608	PIN_BANK(0, 32, "gpio0"),
3609	PIN_BANK(1, 32, "gpio1"),
3610	PIN_BANK(2, 32, "gpio2"),
3611	PIN_BANK(3, 32, "gpio3"),
3612	};
3613
3614	static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3615	.pin_banks = rk3066b_pin_banks,
3616	.nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3617	.label = "RK3066b-GPIO",
3618	.type = RK3066B,
3619	.grf_mux_offset = 0x60,
3620	};
3621
3622	static struct rockchip_pin_bank rk3128_pin_banks[] = {
3623	PIN_BANK(0, 32, "gpio0"),
3624	PIN_BANK(1, 32, "gpio1"),
3625	PIN_BANK(2, 32, "gpio2"),
3626	PIN_BANK(3, 32, "gpio3"),
3627	};
3628
3629	static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3630	.pin_banks = rk3128_pin_banks,
3631	.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3632	.label = "RK3128-GPIO",
3633	.type = RK3128,
3634	.grf_mux_offset = 0xa8,
3635	.iomux_recalced = rk3128_mux_recalced_data,
3636	.niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3637	.iomux_routes = rk3128_mux_route_data,
3638	.niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3639	.pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3640	};
3641
3642	static struct rockchip_pin_bank rk3188_pin_banks[] = {
3643	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3644	PIN_BANK(1, 32, "gpio1"),
3645	PIN_BANK(2, 32, "gpio2"),
3646	PIN_BANK(3, 32, "gpio3"),
3647	};
3648
3649	static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3650	.pin_banks = rk3188_pin_banks,
3651	.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3652	.label = "RK3188-GPIO",
3653	.type = RK3188,
3654	.grf_mux_offset = 0x60,
3655	.iomux_routes = rk3188_mux_route_data,
3656	.niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
3657	.pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3658	};
3659
3660	static struct rockchip_pin_bank rk3228_pin_banks[] = {
3661	PIN_BANK(0, 32, "gpio0"),
3662	PIN_BANK(1, 32, "gpio1"),
3663	PIN_BANK(2, 32, "gpio2"),
3664	PIN_BANK(3, 32, "gpio3"),
3665	};
3666
3667	static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3668	.pin_banks = rk3228_pin_banks,
3669	.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3670	.label = "RK3228-GPIO",
3671	.type = RK3288,
3672	.grf_mux_offset = 0x0,
3673	.iomux_routes = rk3228_mux_route_data,
3674	.niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3675	.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3676	.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3677	};
3678
3679	static struct rockchip_pin_bank rk3288_pin_banks[] = {
3680	PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3681	IOMUX_SOURCE_PMU,
3682	IOMUX_SOURCE_PMU,
3683	IOMUX_UNROUTED
3684	),
3685	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3686	IOMUX_UNROUTED,
3687	IOMUX_UNROUTED,
3688	0
3689	),
3690	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3691	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3692	PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3693	IOMUX_WIDTH_4BIT,
3694	0,
3695	0
3696	),
3697	PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3698	0,
3699	0,
3700	IOMUX_UNROUTED
3701	),
3702	PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3703	PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3704	0,
3705	IOMUX_WIDTH_4BIT,
3706	IOMUX_UNROUTED
3707	),
3708	PIN_BANK(8, 16, "gpio8"),
3709	};
3710
3711	static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3712	.pin_banks = rk3288_pin_banks,
3713	.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3714	.label = "RK3288-GPIO",
3715	.type = RK3288,
3716	.grf_mux_offset = 0x0,
3717	.pmu_mux_offset = 0x84,
3718	.iomux_routes = rk3288_mux_route_data,
3719	.niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3720	.pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3721	.drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3722	};
3723
3724	static struct rockchip_pin_bank rk3308_pin_banks[] = {
3725	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3726	IOMUX_WIDTH_2BIT,
3727	IOMUX_WIDTH_2BIT,
3728	IOMUX_WIDTH_2BIT),
3729	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3730	IOMUX_WIDTH_2BIT,
3731	IOMUX_WIDTH_2BIT,
3732	IOMUX_WIDTH_2BIT),
3733	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3734	IOMUX_WIDTH_2BIT,
3735	IOMUX_WIDTH_2BIT,
3736	IOMUX_WIDTH_2BIT),
3737	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3738	IOMUX_WIDTH_2BIT,
3739	IOMUX_WIDTH_2BIT,
3740	IOMUX_WIDTH_2BIT),
3741	PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3742	IOMUX_WIDTH_2BIT,
3743	IOMUX_WIDTH_2BIT,
3744	IOMUX_WIDTH_2BIT),
3745	};
3746
3747	static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3748	.pin_banks = rk3308_pin_banks,
3749	.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
3750	.label = "RK3308-GPIO",
3751	.type = RK3308,
3752	.grf_mux_offset = 0x0,
3753	.iomux_recalced = rk3308_mux_recalced_data,
3754	.niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
3755	.iomux_routes = rk3308_mux_route_data,
3756	.niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
3757	.pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3758	.drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3759	.schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
3760	};
3761
3762	static struct rockchip_pin_bank rk3328_pin_banks[] = {
3763	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3764	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3765	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3766	IOMUX_WIDTH_3BIT,
3767	IOMUX_WIDTH_3BIT,
3768	0),
3769	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3770	IOMUX_WIDTH_3BIT,
3771	IOMUX_WIDTH_3BIT,
3772	0,
3773	0),
3774	};
3775
3776	static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3777	.pin_banks = rk3328_pin_banks,
3778	.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3779	.label = "RK3328-GPIO",
3780	.type = RK3288,
3781	.grf_mux_offset = 0x0,
3782	.iomux_recalced = rk3328_mux_recalced_data,
3783	.niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
3784	.iomux_routes = rk3328_mux_route_data,
3785	.niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3786	.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3787	.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3788	.schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3789	};
3790
3791	static struct rockchip_pin_bank rk3368_pin_banks[] = {
3792	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3793	IOMUX_SOURCE_PMU,
3794	IOMUX_SOURCE_PMU,
3795	IOMUX_SOURCE_PMU
3796	),
3797	PIN_BANK(1, 32, "gpio1"),
3798	PIN_BANK(2, 32, "gpio2"),
3799	PIN_BANK(3, 32, "gpio3"),
3800	};
3801
3802	static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3803	.pin_banks = rk3368_pin_banks,
3804	.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3805	.label = "RK3368-GPIO",
3806	.type = RK3368,
3807	.grf_mux_offset = 0x0,
3808	.pmu_mux_offset = 0x0,
3809	.pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3810	.drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3811	};
3812
3813	static struct rockchip_pin_bank rk3399_pin_banks[] = {
3814	PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3815	IOMUX_SOURCE_PMU,
3816	IOMUX_SOURCE_PMU,
3817	IOMUX_SOURCE_PMU,
3818	IOMUX_SOURCE_PMU,
3819	DRV_TYPE_IO_1V8_ONLY,
3820	DRV_TYPE_IO_1V8_ONLY,
3821	DRV_TYPE_IO_DEFAULT,
3822	DRV_TYPE_IO_DEFAULT,
3823	0x80,
3824	0x88,
3825	-1,
3826	-1,
3827	PULL_TYPE_IO_1V8_ONLY,
3828	PULL_TYPE_IO_1V8_ONLY,
3829	PULL_TYPE_IO_DEFAULT,
3830	PULL_TYPE_IO_DEFAULT
3831	),
3832	PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3833	IOMUX_SOURCE_PMU,
3834	IOMUX_SOURCE_PMU,
3835	IOMUX_SOURCE_PMU,
3836	DRV_TYPE_IO_1V8_OR_3V0,
3837	DRV_TYPE_IO_1V8_OR_3V0,
3838	DRV_TYPE_IO_1V8_OR_3V0,
3839	DRV_TYPE_IO_1V8_OR_3V0,
3840	0xa0,
3841	0xa8,
3842	0xb0,
3843	0xb8
3844	),
3845	PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3846	DRV_TYPE_IO_1V8_OR_3V0,
3847	DRV_TYPE_IO_1V8_ONLY,
3848	DRV_TYPE_IO_1V8_ONLY,
3849	PULL_TYPE_IO_DEFAULT,
3850	PULL_TYPE_IO_DEFAULT,
3851	PULL_TYPE_IO_1V8_ONLY,
3852	PULL_TYPE_IO_1V8_ONLY
3853	),
3854	PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3855	DRV_TYPE_IO_3V3_ONLY,
3856	DRV_TYPE_IO_3V3_ONLY,
3857	DRV_TYPE_IO_1V8_OR_3V0
3858	),
3859	PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3860	DRV_TYPE_IO_1V8_3V0_AUTO,
3861	DRV_TYPE_IO_1V8_OR_3V0,
3862	DRV_TYPE_IO_1V8_OR_3V0
3863	),
3864	};
3865
3866	static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3867	.pin_banks = rk3399_pin_banks,
3868	.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3869	.label = "RK3399-GPIO",
3870	.type = RK3399,
3871	.grf_mux_offset = 0xe000,
3872	.pmu_mux_offset = 0x0,
3873	.grf_drv_offset = 0xe100,
3874	.pmu_drv_offset = 0x80,
3875	.iomux_routes = rk3399_mux_route_data,
3876	.niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
3877	.pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3878	.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3879	};
3880
3881	static struct rockchip_pin_bank rk3568_pin_banks[] = {
3882	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3883	IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3884	IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
3885	IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
3886	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3887	IOMUX_WIDTH_4BIT,
3888	IOMUX_WIDTH_4BIT,
3889	IOMUX_WIDTH_4BIT),
3890	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3891	IOMUX_WIDTH_4BIT,
3892	IOMUX_WIDTH_4BIT,
3893	IOMUX_WIDTH_4BIT),
3894	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3895	IOMUX_WIDTH_4BIT,
3896	IOMUX_WIDTH_4BIT,
3897	IOMUX_WIDTH_4BIT),
3898	PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3899	IOMUX_WIDTH_4BIT,
3900	IOMUX_WIDTH_4BIT,
3901	IOMUX_WIDTH_4BIT),
3902	};
3903
3904	static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
3905	.pin_banks = rk3568_pin_banks,
3906	.nr_banks = ARRAY_SIZE(rk3568_pin_banks),
3907	.label = "RK3568-GPIO",
3908	.type = RK3568,
3909	.grf_mux_offset = 0x0,
3910	.pmu_mux_offset = 0x0,
3911	.grf_drv_offset = 0x0200,
3912	.pmu_drv_offset = 0x0070,
3913	.iomux_routes = rk3568_mux_route_data,
3914	.niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
3915	.pull_calc_reg = rk3568_calc_pull_reg_and_bit,
3916	.drv_calc_reg = rk3568_calc_drv_reg_and_bit,
3917	.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
3918	};
3919
3920	static struct rockchip_pin_bank rk3588_pin_banks[] = {
3921	RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
3922	IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3923	RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
3924	IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3925	RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
3926	IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3927	RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
3928	IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3929	RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
3930	IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
3931	};
3932
3933	static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
3934	.pin_banks = rk3588_pin_banks,
3935	.nr_banks = ARRAY_SIZE(rk3588_pin_banks),
3936	.label = "RK3588-GPIO",
3937	.type = RK3588,
3938	.pull_calc_reg = rk3588_calc_pull_reg_and_bit,
3939	.drv_calc_reg = rk3588_calc_drv_reg_and_bit,
3940	.schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
3941	};
3942
3943	static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3944	{ .compatible = "rockchip,px30-pinctrl",
3945	.data = &px30_pin_ctrl },
3946	{ .compatible = "rockchip,rv1108-pinctrl",
3947	.data = &rv1108_pin_ctrl },
3948	{ .compatible = "rockchip,rv1126-pinctrl",
3949	.data = &rv1126_pin_ctrl },
3950	{ .compatible = "rockchip,rk2928-pinctrl",
3951	.data = &rk2928_pin_ctrl },
3952	{ .compatible = "rockchip,rk3036-pinctrl",
3953	.data = &rk3036_pin_ctrl },
3954	{ .compatible = "rockchip,rk3066a-pinctrl",
3955	.data = &rk3066a_pin_ctrl },
3956	{ .compatible = "rockchip,rk3066b-pinctrl",
3957	.data = &rk3066b_pin_ctrl },
3958	{ .compatible = "rockchip,rk3128-pinctrl",
3959	.data = (void *)&rk3128_pin_ctrl },
3960	{ .compatible = "rockchip,rk3188-pinctrl",
3961	.data = &rk3188_pin_ctrl },
3962	{ .compatible = "rockchip,rk3228-pinctrl",
3963	.data = &rk3228_pin_ctrl },
3964	{ .compatible = "rockchip,rk3288-pinctrl",
3965	.data = &rk3288_pin_ctrl },
3966	{ .compatible = "rockchip,rk3308-pinctrl",
3967	.data = &rk3308_pin_ctrl },
3968	{ .compatible = "rockchip,rk3328-pinctrl",
3969	.data = &rk3328_pin_ctrl },
3970	{ .compatible = "rockchip,rk3368-pinctrl",
3971	.data = &rk3368_pin_ctrl },
3972	{ .compatible = "rockchip,rk3399-pinctrl",
3973	.data = &rk3399_pin_ctrl },
3974	{ .compatible = "rockchip,rk3568-pinctrl",
3975	.data = &rk3568_pin_ctrl },
3976	{ .compatible = "rockchip,rk3588-pinctrl",
3977	.data = &rk3588_pin_ctrl },
3978	{},
3979	};
3980
3981	static struct platform_driver rockchip_pinctrl_driver = {
3982	.probe = rockchip_pinctrl_probe,
3983	.remove_new = rockchip_pinctrl_remove,
3984	.driver = {
3985	.name = "rockchip-pinctrl",
3986	.pm = &rockchip_pinctrl_dev_pm_ops,
3987	.of_match_table = rockchip_pinctrl_dt_match,
3988	},
3989	};
3990
3991	static int __init rockchip_pinctrl_drv_register(void)
3992	{
3993	return platform_driver_register(&rockchip_pinctrl_driver);
3994	}
3995	postcore_initcall(rockchip_pinctrl_drv_register);
3996
3997	static void __exit rockchip_pinctrl_drv_unregister(void)
3998	{
3999	platform_driver_unregister(&rockchip_pinctrl_driver);
4000	}
4001	module_exit(rockchip_pinctrl_drv_unregister);
4002
4003	MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
4004	MODULE_LICENSE("GPL");
4005	MODULE_ALIAS("platform:pinctrl-rockchip");
4006	MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
4007