1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Marvell PXA2xx family pin control |
4 | * |
5 | * Copyright (C) 2015 Robert Jarzmik |
6 | */ |
7 | |
8 | #include <linux/bitops.h> |
9 | #include <linux/io.h> |
10 | #include <linux/of.h> |
11 | #include <linux/of_address.h> |
12 | #include <linux/module.h> |
13 | #include <linux/pinctrl/machine.h> |
14 | #include <linux/pinctrl/pinconf.h> |
15 | #include <linux/pinctrl/pinconf-generic.h> |
16 | #include <linux/pinctrl/pinmux.h> |
17 | #include <linux/pinctrl/pinctrl.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/slab.h> |
20 | |
21 | #include "../pinctrl-utils.h" |
22 | #include "pinctrl-pxa2xx.h" |
23 | |
24 | static int pxa2xx_pctrl_get_groups_count(struct pinctrl_dev *pctldev) |
25 | { |
26 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
27 | |
28 | return pctl->ngroups; |
29 | } |
30 | |
31 | static const char *pxa2xx_pctrl_get_group_name(struct pinctrl_dev *pctldev, |
32 | unsigned tgroup) |
33 | { |
34 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
35 | struct pxa_pinctrl_group *group = pctl->groups + tgroup; |
36 | |
37 | return group->name; |
38 | } |
39 | |
40 | static int pxa2xx_pctrl_get_group_pins(struct pinctrl_dev *pctldev, |
41 | unsigned tgroup, |
42 | const unsigned **pins, |
43 | unsigned *num_pins) |
44 | { |
45 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
46 | struct pxa_pinctrl_group *group = pctl->groups + tgroup; |
47 | |
48 | *pins = (unsigned *)&group->pin; |
49 | *num_pins = 1; |
50 | |
51 | return 0; |
52 | } |
53 | |
54 | static const struct pinctrl_ops pxa2xx_pctl_ops = { |
55 | #ifdef CONFIG_OF |
56 | .dt_node_to_map = pinconf_generic_dt_node_to_map_all, |
57 | .dt_free_map = pinctrl_utils_free_map, |
58 | #endif |
59 | .get_groups_count = pxa2xx_pctrl_get_groups_count, |
60 | .get_group_name = pxa2xx_pctrl_get_group_name, |
61 | .get_group_pins = pxa2xx_pctrl_get_group_pins, |
62 | }; |
63 | |
64 | static struct pxa_desc_function * |
65 | pxa_desc_by_func_group(struct pxa_pinctrl *pctl, const char *pin_name, |
66 | const char *func_name) |
67 | { |
68 | int i; |
69 | struct pxa_desc_function *df; |
70 | |
71 | for (i = 0; i < pctl->npins; i++) { |
72 | const struct pxa_desc_pin *pin = pctl->ppins + i; |
73 | |
74 | if (!strcmp(pin->pin.name, pin_name)) |
75 | for (df = pin->functions; df->name; df++) |
76 | if (!strcmp(df->name, func_name)) |
77 | return df; |
78 | } |
79 | |
80 | return NULL; |
81 | } |
82 | |
83 | static int pxa2xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
84 | struct pinctrl_gpio_range *range, |
85 | unsigned pin, |
86 | bool input) |
87 | { |
88 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
89 | unsigned long flags; |
90 | uint32_t val; |
91 | void __iomem *gpdr; |
92 | |
93 | gpdr = pctl->base_gpdr[pin / 32]; |
94 | dev_dbg(pctl->dev, "set_direction(pin=%d): dir=%d\n" , |
95 | pin, !input); |
96 | |
97 | spin_lock_irqsave(&pctl->lock, flags); |
98 | |
99 | val = readl_relaxed(gpdr); |
100 | val = (val & ~BIT(pin % 32)) | (input ? 0 : BIT(pin % 32)); |
101 | writel_relaxed(val, gpdr); |
102 | |
103 | spin_unlock_irqrestore(lock: &pctl->lock, flags); |
104 | |
105 | return 0; |
106 | } |
107 | |
108 | static const char *pxa2xx_pmx_get_func_name(struct pinctrl_dev *pctldev, |
109 | unsigned function) |
110 | { |
111 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
112 | struct pxa_pinctrl_function *pf = pctl->functions + function; |
113 | |
114 | return pf->name; |
115 | } |
116 | |
117 | static int pxa2xx_get_functions_count(struct pinctrl_dev *pctldev) |
118 | { |
119 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
120 | |
121 | return pctl->nfuncs; |
122 | } |
123 | |
124 | static int pxa2xx_pmx_get_func_groups(struct pinctrl_dev *pctldev, |
125 | unsigned function, |
126 | const char * const **groups, |
127 | unsigned * const num_groups) |
128 | { |
129 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
130 | struct pxa_pinctrl_function *pf = pctl->functions + function; |
131 | |
132 | *groups = pf->groups; |
133 | *num_groups = pf->ngroups; |
134 | |
135 | return 0; |
136 | } |
137 | |
138 | static int pxa2xx_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned function, |
139 | unsigned tgroup) |
140 | { |
141 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
142 | struct pxa_pinctrl_group *group = pctl->groups + tgroup; |
143 | struct pxa_desc_function *df; |
144 | int pin, shift; |
145 | unsigned long flags; |
146 | void __iomem *gafr, *gpdr; |
147 | u32 val; |
148 | |
149 | |
150 | df = pxa_desc_by_func_group(pctl, pin_name: group->name, |
151 | func_name: (pctl->functions + function)->name); |
152 | if (!df) |
153 | return -EINVAL; |
154 | |
155 | pin = group->pin; |
156 | gafr = pctl->base_gafr[pin / 16]; |
157 | gpdr = pctl->base_gpdr[pin / 32]; |
158 | shift = (pin % 16) << 1; |
159 | dev_dbg(pctl->dev, "set_mux(pin=%d): af=%d dir=%d\n" , |
160 | pin, df->muxval >> 1, df->muxval & 0x1); |
161 | |
162 | spin_lock_irqsave(&pctl->lock, flags); |
163 | |
164 | val = readl_relaxed(gafr); |
165 | val = (val & ~(0x3 << shift)) | ((df->muxval >> 1) << shift); |
166 | writel_relaxed(val, gafr); |
167 | |
168 | val = readl_relaxed(gpdr); |
169 | val = (val & ~BIT(pin % 32)) | ((df->muxval & 1) ? BIT(pin % 32) : 0); |
170 | writel_relaxed(val, gpdr); |
171 | |
172 | spin_unlock_irqrestore(lock: &pctl->lock, flags); |
173 | |
174 | return 0; |
175 | } |
176 | static const struct pinmux_ops pxa2xx_pinmux_ops = { |
177 | .get_functions_count = pxa2xx_get_functions_count, |
178 | .get_function_name = pxa2xx_pmx_get_func_name, |
179 | .get_function_groups = pxa2xx_pmx_get_func_groups, |
180 | .set_mux = pxa2xx_pmx_set_mux, |
181 | .gpio_set_direction = pxa2xx_pmx_gpio_set_direction, |
182 | }; |
183 | |
184 | static int pxa2xx_pconf_group_get(struct pinctrl_dev *pctldev, |
185 | unsigned group, |
186 | unsigned long *config) |
187 | { |
188 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
189 | struct pxa_pinctrl_group *g = pctl->groups + group; |
190 | unsigned long flags; |
191 | unsigned pin = g->pin; |
192 | void __iomem *pgsr = pctl->base_pgsr[pin / 32]; |
193 | u32 val; |
194 | |
195 | spin_lock_irqsave(&pctl->lock, flags); |
196 | val = readl_relaxed(pgsr) & BIT(pin % 32); |
197 | *config = val ? PIN_CONFIG_MODE_LOW_POWER : 0; |
198 | spin_unlock_irqrestore(lock: &pctl->lock, flags); |
199 | |
200 | dev_dbg(pctl->dev, "get sleep gpio state(pin=%d) %d\n" , |
201 | pin, !!val); |
202 | return 0; |
203 | } |
204 | |
205 | static int pxa2xx_pconf_group_set(struct pinctrl_dev *pctldev, |
206 | unsigned group, |
207 | unsigned long *configs, |
208 | unsigned num_configs) |
209 | { |
210 | struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
211 | struct pxa_pinctrl_group *g = pctl->groups + group; |
212 | unsigned long flags; |
213 | unsigned pin = g->pin; |
214 | void __iomem *pgsr = pctl->base_pgsr[pin / 32]; |
215 | int i, is_set = 0; |
216 | u32 val; |
217 | |
218 | for (i = 0; i < num_configs; i++) { |
219 | switch (pinconf_to_config_param(config: configs[i])) { |
220 | case PIN_CONFIG_MODE_LOW_POWER: |
221 | is_set = pinconf_to_config_argument(config: configs[i]); |
222 | break; |
223 | default: |
224 | return -EINVAL; |
225 | } |
226 | } |
227 | |
228 | dev_dbg(pctl->dev, "set sleep gpio state(pin=%d) %d\n" , |
229 | pin, is_set); |
230 | |
231 | spin_lock_irqsave(&pctl->lock, flags); |
232 | val = readl_relaxed(pgsr); |
233 | val = (val & ~BIT(pin % 32)) | (is_set ? BIT(pin % 32) : 0); |
234 | writel_relaxed(val, pgsr); |
235 | spin_unlock_irqrestore(lock: &pctl->lock, flags); |
236 | |
237 | return 0; |
238 | } |
239 | |
240 | static const struct pinconf_ops pxa2xx_pconf_ops = { |
241 | .pin_config_group_get = pxa2xx_pconf_group_get, |
242 | .pin_config_group_set = pxa2xx_pconf_group_set, |
243 | .is_generic = true, |
244 | }; |
245 | |
246 | static struct pinctrl_desc pxa2xx_pinctrl_desc = { |
247 | .confops = &pxa2xx_pconf_ops, |
248 | .pctlops = &pxa2xx_pctl_ops, |
249 | .pmxops = &pxa2xx_pinmux_ops, |
250 | }; |
251 | |
252 | static const struct pxa_pinctrl_function * |
253 | pxa2xx_find_function(struct pxa_pinctrl *pctl, const char *fname, |
254 | const struct pxa_pinctrl_function *functions) |
255 | { |
256 | const struct pxa_pinctrl_function *func; |
257 | |
258 | for (func = functions; func->name; func++) |
259 | if (!strcmp(fname, func->name)) |
260 | return func; |
261 | |
262 | return NULL; |
263 | } |
264 | |
265 | static int pxa2xx_build_functions(struct pxa_pinctrl *pctl) |
266 | { |
267 | int i; |
268 | struct pxa_pinctrl_function *functions; |
269 | struct pxa_desc_function *df; |
270 | |
271 | /* |
272 | * Each pin can have at most 6 alternate functions, and 2 gpio functions |
273 | * which are common to each pin. As there are more than 2 pins without |
274 | * alternate function, 6 * npins is an absolute high limit of the number |
275 | * of functions. |
276 | */ |
277 | functions = devm_kcalloc(dev: pctl->dev, n: pctl->npins * 6, |
278 | size: sizeof(*functions), GFP_KERNEL); |
279 | if (!functions) |
280 | return -ENOMEM; |
281 | |
282 | for (i = 0; i < pctl->npins; i++) |
283 | for (df = pctl->ppins[i].functions; df->name; df++) |
284 | if (!pxa2xx_find_function(pctl, fname: df->name, functions)) |
285 | (functions + pctl->nfuncs++)->name = df->name; |
286 | pctl->functions = devm_kmemdup(dev: pctl->dev, src: functions, |
287 | len: pctl->nfuncs * sizeof(*functions), |
288 | GFP_KERNEL); |
289 | if (!pctl->functions) |
290 | return -ENOMEM; |
291 | |
292 | devm_kfree(dev: pctl->dev, p: functions); |
293 | return 0; |
294 | } |
295 | |
296 | static int pxa2xx_build_groups(struct pxa_pinctrl *pctl) |
297 | { |
298 | int i, j, ngroups; |
299 | struct pxa_pinctrl_function *func; |
300 | struct pxa_desc_function *df; |
301 | char **gtmp; |
302 | |
303 | gtmp = devm_kmalloc_array(dev: pctl->dev, n: pctl->npins, size: sizeof(*gtmp), |
304 | GFP_KERNEL); |
305 | if (!gtmp) |
306 | return -ENOMEM; |
307 | |
308 | for (i = 0; i < pctl->nfuncs; i++) { |
309 | ngroups = 0; |
310 | for (j = 0; j < pctl->npins; j++) |
311 | for (df = pctl->ppins[j].functions; df->name; |
312 | df++) |
313 | if (!strcmp(pctl->functions[i].name, |
314 | df->name)) |
315 | gtmp[ngroups++] = (char *) |
316 | pctl->ppins[j].pin.name; |
317 | func = pctl->functions + i; |
318 | func->ngroups = ngroups; |
319 | func->groups = |
320 | devm_kmalloc_array(dev: pctl->dev, n: ngroups, |
321 | size: sizeof(char *), GFP_KERNEL); |
322 | if (!func->groups) |
323 | return -ENOMEM; |
324 | |
325 | memcpy(func->groups, gtmp, ngroups * sizeof(*gtmp)); |
326 | } |
327 | |
328 | devm_kfree(dev: pctl->dev, p: gtmp); |
329 | return 0; |
330 | } |
331 | |
332 | static int pxa2xx_build_state(struct pxa_pinctrl *pctl, |
333 | const struct pxa_desc_pin *ppins, int npins) |
334 | { |
335 | struct pxa_pinctrl_group *group; |
336 | struct pinctrl_pin_desc *pins; |
337 | int ret, i; |
338 | |
339 | pctl->npins = npins; |
340 | pctl->ppins = ppins; |
341 | pctl->ngroups = npins; |
342 | |
343 | pctl->desc.npins = npins; |
344 | pins = devm_kcalloc(dev: pctl->dev, n: npins, size: sizeof(*pins), GFP_KERNEL); |
345 | if (!pins) |
346 | return -ENOMEM; |
347 | |
348 | pctl->desc.pins = pins; |
349 | for (i = 0; i < npins; i++) |
350 | pins[i] = ppins[i].pin; |
351 | |
352 | pctl->groups = devm_kmalloc_array(dev: pctl->dev, n: pctl->ngroups, |
353 | size: sizeof(*pctl->groups), GFP_KERNEL); |
354 | if (!pctl->groups) |
355 | return -ENOMEM; |
356 | |
357 | for (i = 0; i < npins; i++) { |
358 | group = pctl->groups + i; |
359 | group->name = ppins[i].pin.name; |
360 | group->pin = ppins[i].pin.number; |
361 | } |
362 | |
363 | ret = pxa2xx_build_functions(pctl); |
364 | if (ret) |
365 | return ret; |
366 | |
367 | ret = pxa2xx_build_groups(pctl); |
368 | if (ret) |
369 | return ret; |
370 | |
371 | return 0; |
372 | } |
373 | |
374 | int pxa2xx_pinctrl_init(struct platform_device *pdev, |
375 | const struct pxa_desc_pin *ppins, int npins, |
376 | void __iomem *base_gafr[], void __iomem *base_gpdr[], |
377 | void __iomem *base_pgsr[]) |
378 | { |
379 | struct pxa_pinctrl *pctl; |
380 | int ret, i, maxpin = 0; |
381 | |
382 | for (i = 0; i < npins; i++) |
383 | maxpin = max_t(int, ppins[i].pin.number, maxpin); |
384 | |
385 | pctl = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pctl), GFP_KERNEL); |
386 | if (!pctl) |
387 | return -ENOMEM; |
388 | pctl->base_gafr = devm_kcalloc(dev: &pdev->dev, roundup(maxpin, 16), |
389 | size: sizeof(*pctl->base_gafr), GFP_KERNEL); |
390 | pctl->base_gpdr = devm_kcalloc(dev: &pdev->dev, roundup(maxpin, 32), |
391 | size: sizeof(*pctl->base_gpdr), GFP_KERNEL); |
392 | pctl->base_pgsr = devm_kcalloc(dev: &pdev->dev, roundup(maxpin, 32), |
393 | size: sizeof(*pctl->base_pgsr), GFP_KERNEL); |
394 | if (!pctl->base_gafr || !pctl->base_gpdr || !pctl->base_pgsr) |
395 | return -ENOMEM; |
396 | |
397 | platform_set_drvdata(pdev, data: pctl); |
398 | spin_lock_init(&pctl->lock); |
399 | |
400 | pctl->dev = &pdev->dev; |
401 | pctl->desc = pxa2xx_pinctrl_desc; |
402 | pctl->desc.name = dev_name(dev: &pdev->dev); |
403 | pctl->desc.owner = THIS_MODULE; |
404 | |
405 | for (i = 0; i < roundup(maxpin, 16); i += 16) |
406 | pctl->base_gafr[i / 16] = base_gafr[i / 16]; |
407 | for (i = 0; i < roundup(maxpin, 32); i += 32) { |
408 | pctl->base_gpdr[i / 32] = base_gpdr[i / 32]; |
409 | pctl->base_pgsr[i / 32] = base_pgsr[i / 32]; |
410 | } |
411 | |
412 | ret = pxa2xx_build_state(pctl, ppins, npins); |
413 | if (ret) |
414 | return ret; |
415 | |
416 | pctl->pctl_dev = devm_pinctrl_register(dev: &pdev->dev, pctldesc: &pctl->desc, driver_data: pctl); |
417 | if (IS_ERR(ptr: pctl->pctl_dev)) { |
418 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n" ); |
419 | return PTR_ERR(ptr: pctl->pctl_dev); |
420 | } |
421 | |
422 | dev_info(&pdev->dev, "initialized pxa2xx pinctrl driver\n" ); |
423 | |
424 | return 0; |
425 | } |
426 | EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_init); |
427 | |
428 | MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>" ); |
429 | MODULE_DESCRIPTION("Marvell PXA2xx pinctrl driver" ); |
430 | MODULE_LICENSE("GPL v2" ); |
431 | |