1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2021, The Linux Foundation. All rights reserved. |
4 | * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. |
5 | */ |
6 | |
7 | #include <linux/module.h> |
8 | #include <linux/of.h> |
9 | #include <linux/platform_device.h> |
10 | |
11 | #include "pinctrl-msm.h" |
12 | |
13 | #define REG_BASE 0x100000 |
14 | #define REG_SIZE 0x1000 |
15 | |
16 | #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ |
17 | { \ |
18 | .grp = PINCTRL_PINGROUP("gpio" #id, \ |
19 | gpio##id##_pins, \ |
20 | ARRAY_SIZE(gpio##id##_pins)), \ |
21 | .funcs = (int[]){ \ |
22 | msm_mux_gpio, /* gpio mode */ \ |
23 | msm_mux_##f1, \ |
24 | msm_mux_##f2, \ |
25 | msm_mux_##f3, \ |
26 | msm_mux_##f4, \ |
27 | msm_mux_##f5, \ |
28 | msm_mux_##f6, \ |
29 | msm_mux_##f7, \ |
30 | msm_mux_##f8, \ |
31 | msm_mux_##f9 \ |
32 | }, \ |
33 | .nfuncs = 10, \ |
34 | .ctl_reg = REG_BASE + REG_SIZE * id, \ |
35 | .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ |
36 | .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ |
37 | .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ |
38 | .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ |
39 | .mux_bit = 2, \ |
40 | .pull_bit = 0, \ |
41 | .drv_bit = 6, \ |
42 | .oe_bit = 9, \ |
43 | .in_bit = 0, \ |
44 | .out_bit = 1, \ |
45 | .intr_enable_bit = 0, \ |
46 | .intr_status_bit = 0, \ |
47 | .intr_target_bit = 5, \ |
48 | .intr_target_kpss_val = 3, \ |
49 | .intr_raw_status_bit = 4, \ |
50 | .intr_polarity_bit = 1, \ |
51 | .intr_detection_bit = 2, \ |
52 | .intr_detection_width = 2, \ |
53 | } |
54 | |
55 | #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ |
56 | { \ |
57 | .grp = PINCTRL_PINGROUP(#pg_name, \ |
58 | pg_name##_pins, \ |
59 | ARRAY_SIZE(pg_name##_pins)), \ |
60 | .ctl_reg = REG_BASE + ctl, \ |
61 | .io_reg = 0, \ |
62 | .intr_cfg_reg = 0, \ |
63 | .intr_status_reg = 0, \ |
64 | .intr_target_reg = 0, \ |
65 | .mux_bit = -1, \ |
66 | .pull_bit = pull, \ |
67 | .drv_bit = drv, \ |
68 | .oe_bit = -1, \ |
69 | .in_bit = -1, \ |
70 | .out_bit = -1, \ |
71 | .intr_enable_bit = -1, \ |
72 | .intr_status_bit = -1, \ |
73 | .intr_target_bit = -1, \ |
74 | .intr_raw_status_bit = -1, \ |
75 | .intr_polarity_bit = -1, \ |
76 | .intr_detection_bit = -1, \ |
77 | .intr_detection_width = -1, \ |
78 | } |
79 | |
80 | #define UFS_RESET(pg_name, offset) \ |
81 | { \ |
82 | .grp = PINCTRL_PINGROUP(#pg_name, \ |
83 | pg_name##_pins, \ |
84 | ARRAY_SIZE(pg_name##_pins)), \ |
85 | .ctl_reg = offset, \ |
86 | .io_reg = offset + 0x4, \ |
87 | .intr_cfg_reg = 0, \ |
88 | .intr_status_reg = 0, \ |
89 | .intr_target_reg = 0, \ |
90 | .mux_bit = -1, \ |
91 | .pull_bit = 3, \ |
92 | .drv_bit = 0, \ |
93 | .oe_bit = -1, \ |
94 | .in_bit = -1, \ |
95 | .out_bit = 0, \ |
96 | .intr_enable_bit = -1, \ |
97 | .intr_status_bit = -1, \ |
98 | .intr_target_bit = -1, \ |
99 | .intr_raw_status_bit = -1, \ |
100 | .intr_polarity_bit = -1, \ |
101 | .intr_detection_bit = -1, \ |
102 | .intr_detection_width = -1, \ |
103 | } |
104 | |
105 | #define QUP_I3C(qup_mode, qup_offset) \ |
106 | { \ |
107 | .mode = qup_mode, \ |
108 | .offset = qup_offset, \ |
109 | } |
110 | |
111 | static const struct pinctrl_pin_desc qdu1000_pins[] = { |
112 | PINCTRL_PIN(0, "GPIO_0" ), |
113 | PINCTRL_PIN(1, "GPIO_1" ), |
114 | PINCTRL_PIN(2, "GPIO_2" ), |
115 | PINCTRL_PIN(3, "GPIO_3" ), |
116 | PINCTRL_PIN(4, "GPIO_4" ), |
117 | PINCTRL_PIN(5, "GPIO_5" ), |
118 | PINCTRL_PIN(6, "GPIO_6" ), |
119 | PINCTRL_PIN(7, "GPIO_7" ), |
120 | PINCTRL_PIN(8, "GPIO_8" ), |
121 | PINCTRL_PIN(9, "GPIO_9" ), |
122 | PINCTRL_PIN(10, "GPIO_10" ), |
123 | PINCTRL_PIN(11, "GPIO_11" ), |
124 | PINCTRL_PIN(12, "GPIO_12" ), |
125 | PINCTRL_PIN(13, "GPIO_13" ), |
126 | PINCTRL_PIN(14, "GPIO_14" ), |
127 | PINCTRL_PIN(15, "GPIO_15" ), |
128 | PINCTRL_PIN(16, "GPIO_16" ), |
129 | PINCTRL_PIN(17, "GPIO_17" ), |
130 | PINCTRL_PIN(18, "GPIO_18" ), |
131 | PINCTRL_PIN(19, "GPIO_19" ), |
132 | PINCTRL_PIN(20, "GPIO_20" ), |
133 | PINCTRL_PIN(21, "GPIO_21" ), |
134 | PINCTRL_PIN(22, "GPIO_22" ), |
135 | PINCTRL_PIN(23, "GPIO_23" ), |
136 | PINCTRL_PIN(24, "GPIO_24" ), |
137 | PINCTRL_PIN(25, "GPIO_25" ), |
138 | PINCTRL_PIN(26, "GPIO_26" ), |
139 | PINCTRL_PIN(27, "GPIO_27" ), |
140 | PINCTRL_PIN(28, "GPIO_28" ), |
141 | PINCTRL_PIN(29, "GPIO_29" ), |
142 | PINCTRL_PIN(30, "GPIO_30" ), |
143 | PINCTRL_PIN(31, "GPIO_31" ), |
144 | PINCTRL_PIN(32, "GPIO_32" ), |
145 | PINCTRL_PIN(33, "GPIO_33" ), |
146 | PINCTRL_PIN(34, "GPIO_34" ), |
147 | PINCTRL_PIN(35, "GPIO_35" ), |
148 | PINCTRL_PIN(36, "GPIO_36" ), |
149 | PINCTRL_PIN(37, "GPIO_37" ), |
150 | PINCTRL_PIN(38, "GPIO_38" ), |
151 | PINCTRL_PIN(39, "GPIO_39" ), |
152 | PINCTRL_PIN(40, "GPIO_40" ), |
153 | PINCTRL_PIN(41, "GPIO_41" ), |
154 | PINCTRL_PIN(42, "GPIO_42" ), |
155 | PINCTRL_PIN(43, "GPIO_43" ), |
156 | PINCTRL_PIN(44, "GPIO_44" ), |
157 | PINCTRL_PIN(45, "GPIO_45" ), |
158 | PINCTRL_PIN(46, "GPIO_46" ), |
159 | PINCTRL_PIN(47, "GPIO_47" ), |
160 | PINCTRL_PIN(48, "GPIO_48" ), |
161 | PINCTRL_PIN(49, "GPIO_49" ), |
162 | PINCTRL_PIN(50, "GPIO_50" ), |
163 | PINCTRL_PIN(51, "GPIO_51" ), |
164 | PINCTRL_PIN(52, "GPIO_52" ), |
165 | PINCTRL_PIN(53, "GPIO_53" ), |
166 | PINCTRL_PIN(54, "GPIO_54" ), |
167 | PINCTRL_PIN(55, "GPIO_55" ), |
168 | PINCTRL_PIN(56, "GPIO_56" ), |
169 | PINCTRL_PIN(57, "GPIO_57" ), |
170 | PINCTRL_PIN(58, "GPIO_58" ), |
171 | PINCTRL_PIN(59, "GPIO_59" ), |
172 | PINCTRL_PIN(60, "GPIO_60" ), |
173 | PINCTRL_PIN(61, "GPIO_61" ), |
174 | PINCTRL_PIN(62, "GPIO_62" ), |
175 | PINCTRL_PIN(63, "GPIO_63" ), |
176 | PINCTRL_PIN(64, "GPIO_64" ), |
177 | PINCTRL_PIN(65, "GPIO_65" ), |
178 | PINCTRL_PIN(66, "GPIO_66" ), |
179 | PINCTRL_PIN(67, "GPIO_67" ), |
180 | PINCTRL_PIN(68, "GPIO_68" ), |
181 | PINCTRL_PIN(69, "GPIO_69" ), |
182 | PINCTRL_PIN(70, "GPIO_70" ), |
183 | PINCTRL_PIN(71, "GPIO_71" ), |
184 | PINCTRL_PIN(72, "GPIO_72" ), |
185 | PINCTRL_PIN(73, "GPIO_73" ), |
186 | PINCTRL_PIN(74, "GPIO_74" ), |
187 | PINCTRL_PIN(75, "GPIO_75" ), |
188 | PINCTRL_PIN(76, "GPIO_76" ), |
189 | PINCTRL_PIN(77, "GPIO_77" ), |
190 | PINCTRL_PIN(78, "GPIO_78" ), |
191 | PINCTRL_PIN(79, "GPIO_79" ), |
192 | PINCTRL_PIN(80, "GPIO_80" ), |
193 | PINCTRL_PIN(81, "GPIO_81" ), |
194 | PINCTRL_PIN(82, "GPIO_82" ), |
195 | PINCTRL_PIN(83, "GPIO_83" ), |
196 | PINCTRL_PIN(84, "GPIO_84" ), |
197 | PINCTRL_PIN(85, "GPIO_85" ), |
198 | PINCTRL_PIN(86, "GPIO_86" ), |
199 | PINCTRL_PIN(87, "GPIO_87" ), |
200 | PINCTRL_PIN(88, "GPIO_88" ), |
201 | PINCTRL_PIN(89, "GPIO_89" ), |
202 | PINCTRL_PIN(90, "GPIO_90" ), |
203 | PINCTRL_PIN(91, "GPIO_91" ), |
204 | PINCTRL_PIN(92, "GPIO_92" ), |
205 | PINCTRL_PIN(93, "GPIO_93" ), |
206 | PINCTRL_PIN(94, "GPIO_94" ), |
207 | PINCTRL_PIN(95, "GPIO_95" ), |
208 | PINCTRL_PIN(96, "GPIO_96" ), |
209 | PINCTRL_PIN(97, "GPIO_97" ), |
210 | PINCTRL_PIN(98, "GPIO_98" ), |
211 | PINCTRL_PIN(99, "GPIO_99" ), |
212 | PINCTRL_PIN(100, "GPIO_100" ), |
213 | PINCTRL_PIN(101, "GPIO_101" ), |
214 | PINCTRL_PIN(102, "GPIO_102" ), |
215 | PINCTRL_PIN(103, "GPIO_103" ), |
216 | PINCTRL_PIN(104, "GPIO_104" ), |
217 | PINCTRL_PIN(105, "GPIO_105" ), |
218 | PINCTRL_PIN(106, "GPIO_106" ), |
219 | PINCTRL_PIN(107, "GPIO_107" ), |
220 | PINCTRL_PIN(108, "GPIO_108" ), |
221 | PINCTRL_PIN(109, "GPIO_109" ), |
222 | PINCTRL_PIN(110, "GPIO_110" ), |
223 | PINCTRL_PIN(111, "GPIO_111" ), |
224 | PINCTRL_PIN(112, "GPIO_112" ), |
225 | PINCTRL_PIN(113, "GPIO_113" ), |
226 | PINCTRL_PIN(114, "GPIO_114" ), |
227 | PINCTRL_PIN(115, "GPIO_115" ), |
228 | PINCTRL_PIN(116, "GPIO_116" ), |
229 | PINCTRL_PIN(117, "GPIO_117" ), |
230 | PINCTRL_PIN(118, "GPIO_118" ), |
231 | PINCTRL_PIN(119, "GPIO_119" ), |
232 | PINCTRL_PIN(120, "GPIO_120" ), |
233 | PINCTRL_PIN(121, "GPIO_121" ), |
234 | PINCTRL_PIN(122, "GPIO_122" ), |
235 | PINCTRL_PIN(123, "GPIO_123" ), |
236 | PINCTRL_PIN(124, "GPIO_124" ), |
237 | PINCTRL_PIN(125, "GPIO_125" ), |
238 | PINCTRL_PIN(126, "GPIO_126" ), |
239 | PINCTRL_PIN(127, "GPIO_127" ), |
240 | PINCTRL_PIN(128, "GPIO_128" ), |
241 | PINCTRL_PIN(129, "GPIO_129" ), |
242 | PINCTRL_PIN(130, "GPIO_130" ), |
243 | PINCTRL_PIN(131, "GPIO_131" ), |
244 | PINCTRL_PIN(132, "GPIO_132" ), |
245 | PINCTRL_PIN(133, "GPIO_133" ), |
246 | PINCTRL_PIN(134, "GPIO_134" ), |
247 | PINCTRL_PIN(135, "GPIO_135" ), |
248 | PINCTRL_PIN(136, "GPIO_136" ), |
249 | PINCTRL_PIN(137, "GPIO_137" ), |
250 | PINCTRL_PIN(138, "GPIO_138" ), |
251 | PINCTRL_PIN(139, "GPIO_139" ), |
252 | PINCTRL_PIN(140, "GPIO_140" ), |
253 | PINCTRL_PIN(141, "GPIO_141" ), |
254 | PINCTRL_PIN(142, "GPIO_142" ), |
255 | PINCTRL_PIN(143, "GPIO_143" ), |
256 | PINCTRL_PIN(144, "GPIO_144" ), |
257 | PINCTRL_PIN(145, "GPIO_145" ), |
258 | PINCTRL_PIN(146, "GPIO_146" ), |
259 | PINCTRL_PIN(147, "GPIO_147" ), |
260 | PINCTRL_PIN(148, "GPIO_148" ), |
261 | PINCTRL_PIN(149, "GPIO_149" ), |
262 | PINCTRL_PIN(150, "GPIO_150" ), |
263 | PINCTRL_PIN(151, "SDC1_RCLK" ), |
264 | PINCTRL_PIN(152, "SDC1_CLK" ), |
265 | PINCTRL_PIN(153, "SDC1_CMD" ), |
266 | PINCTRL_PIN(154, "SDC1_DATA" ), |
267 | }; |
268 | |
269 | #define DECLARE_MSM_GPIO_PINS(pin) \ |
270 | static const unsigned int gpio##pin##_pins[] = { pin } |
271 | DECLARE_MSM_GPIO_PINS(0); |
272 | DECLARE_MSM_GPIO_PINS(1); |
273 | DECLARE_MSM_GPIO_PINS(2); |
274 | DECLARE_MSM_GPIO_PINS(3); |
275 | DECLARE_MSM_GPIO_PINS(4); |
276 | DECLARE_MSM_GPIO_PINS(5); |
277 | DECLARE_MSM_GPIO_PINS(6); |
278 | DECLARE_MSM_GPIO_PINS(7); |
279 | DECLARE_MSM_GPIO_PINS(8); |
280 | DECLARE_MSM_GPIO_PINS(9); |
281 | DECLARE_MSM_GPIO_PINS(10); |
282 | DECLARE_MSM_GPIO_PINS(11); |
283 | DECLARE_MSM_GPIO_PINS(12); |
284 | DECLARE_MSM_GPIO_PINS(13); |
285 | DECLARE_MSM_GPIO_PINS(14); |
286 | DECLARE_MSM_GPIO_PINS(15); |
287 | DECLARE_MSM_GPIO_PINS(16); |
288 | DECLARE_MSM_GPIO_PINS(17); |
289 | DECLARE_MSM_GPIO_PINS(18); |
290 | DECLARE_MSM_GPIO_PINS(19); |
291 | DECLARE_MSM_GPIO_PINS(20); |
292 | DECLARE_MSM_GPIO_PINS(21); |
293 | DECLARE_MSM_GPIO_PINS(22); |
294 | DECLARE_MSM_GPIO_PINS(23); |
295 | DECLARE_MSM_GPIO_PINS(24); |
296 | DECLARE_MSM_GPIO_PINS(25); |
297 | DECLARE_MSM_GPIO_PINS(26); |
298 | DECLARE_MSM_GPIO_PINS(27); |
299 | DECLARE_MSM_GPIO_PINS(28); |
300 | DECLARE_MSM_GPIO_PINS(29); |
301 | DECLARE_MSM_GPIO_PINS(30); |
302 | DECLARE_MSM_GPIO_PINS(31); |
303 | DECLARE_MSM_GPIO_PINS(32); |
304 | DECLARE_MSM_GPIO_PINS(33); |
305 | DECLARE_MSM_GPIO_PINS(34); |
306 | DECLARE_MSM_GPIO_PINS(35); |
307 | DECLARE_MSM_GPIO_PINS(36); |
308 | DECLARE_MSM_GPIO_PINS(37); |
309 | DECLARE_MSM_GPIO_PINS(38); |
310 | DECLARE_MSM_GPIO_PINS(39); |
311 | DECLARE_MSM_GPIO_PINS(40); |
312 | DECLARE_MSM_GPIO_PINS(41); |
313 | DECLARE_MSM_GPIO_PINS(42); |
314 | DECLARE_MSM_GPIO_PINS(43); |
315 | DECLARE_MSM_GPIO_PINS(44); |
316 | DECLARE_MSM_GPIO_PINS(45); |
317 | DECLARE_MSM_GPIO_PINS(46); |
318 | DECLARE_MSM_GPIO_PINS(47); |
319 | DECLARE_MSM_GPIO_PINS(48); |
320 | DECLARE_MSM_GPIO_PINS(49); |
321 | DECLARE_MSM_GPIO_PINS(50); |
322 | DECLARE_MSM_GPIO_PINS(51); |
323 | DECLARE_MSM_GPIO_PINS(52); |
324 | DECLARE_MSM_GPIO_PINS(53); |
325 | DECLARE_MSM_GPIO_PINS(54); |
326 | DECLARE_MSM_GPIO_PINS(55); |
327 | DECLARE_MSM_GPIO_PINS(56); |
328 | DECLARE_MSM_GPIO_PINS(57); |
329 | DECLARE_MSM_GPIO_PINS(58); |
330 | DECLARE_MSM_GPIO_PINS(59); |
331 | DECLARE_MSM_GPIO_PINS(60); |
332 | DECLARE_MSM_GPIO_PINS(61); |
333 | DECLARE_MSM_GPIO_PINS(62); |
334 | DECLARE_MSM_GPIO_PINS(63); |
335 | DECLARE_MSM_GPIO_PINS(64); |
336 | DECLARE_MSM_GPIO_PINS(65); |
337 | DECLARE_MSM_GPIO_PINS(66); |
338 | DECLARE_MSM_GPIO_PINS(67); |
339 | DECLARE_MSM_GPIO_PINS(68); |
340 | DECLARE_MSM_GPIO_PINS(69); |
341 | DECLARE_MSM_GPIO_PINS(70); |
342 | DECLARE_MSM_GPIO_PINS(71); |
343 | DECLARE_MSM_GPIO_PINS(72); |
344 | DECLARE_MSM_GPIO_PINS(73); |
345 | DECLARE_MSM_GPIO_PINS(74); |
346 | DECLARE_MSM_GPIO_PINS(75); |
347 | DECLARE_MSM_GPIO_PINS(76); |
348 | DECLARE_MSM_GPIO_PINS(77); |
349 | DECLARE_MSM_GPIO_PINS(78); |
350 | DECLARE_MSM_GPIO_PINS(79); |
351 | DECLARE_MSM_GPIO_PINS(80); |
352 | DECLARE_MSM_GPIO_PINS(81); |
353 | DECLARE_MSM_GPIO_PINS(82); |
354 | DECLARE_MSM_GPIO_PINS(83); |
355 | DECLARE_MSM_GPIO_PINS(84); |
356 | DECLARE_MSM_GPIO_PINS(85); |
357 | DECLARE_MSM_GPIO_PINS(86); |
358 | DECLARE_MSM_GPIO_PINS(87); |
359 | DECLARE_MSM_GPIO_PINS(88); |
360 | DECLARE_MSM_GPIO_PINS(89); |
361 | DECLARE_MSM_GPIO_PINS(90); |
362 | DECLARE_MSM_GPIO_PINS(91); |
363 | DECLARE_MSM_GPIO_PINS(92); |
364 | DECLARE_MSM_GPIO_PINS(93); |
365 | DECLARE_MSM_GPIO_PINS(94); |
366 | DECLARE_MSM_GPIO_PINS(95); |
367 | DECLARE_MSM_GPIO_PINS(96); |
368 | DECLARE_MSM_GPIO_PINS(97); |
369 | DECLARE_MSM_GPIO_PINS(98); |
370 | DECLARE_MSM_GPIO_PINS(99); |
371 | DECLARE_MSM_GPIO_PINS(100); |
372 | DECLARE_MSM_GPIO_PINS(101); |
373 | DECLARE_MSM_GPIO_PINS(102); |
374 | DECLARE_MSM_GPIO_PINS(103); |
375 | DECLARE_MSM_GPIO_PINS(104); |
376 | DECLARE_MSM_GPIO_PINS(105); |
377 | DECLARE_MSM_GPIO_PINS(106); |
378 | DECLARE_MSM_GPIO_PINS(107); |
379 | DECLARE_MSM_GPIO_PINS(108); |
380 | DECLARE_MSM_GPIO_PINS(109); |
381 | DECLARE_MSM_GPIO_PINS(110); |
382 | DECLARE_MSM_GPIO_PINS(111); |
383 | DECLARE_MSM_GPIO_PINS(112); |
384 | DECLARE_MSM_GPIO_PINS(113); |
385 | DECLARE_MSM_GPIO_PINS(114); |
386 | DECLARE_MSM_GPIO_PINS(115); |
387 | DECLARE_MSM_GPIO_PINS(116); |
388 | DECLARE_MSM_GPIO_PINS(117); |
389 | DECLARE_MSM_GPIO_PINS(118); |
390 | DECLARE_MSM_GPIO_PINS(119); |
391 | DECLARE_MSM_GPIO_PINS(120); |
392 | DECLARE_MSM_GPIO_PINS(121); |
393 | DECLARE_MSM_GPIO_PINS(122); |
394 | DECLARE_MSM_GPIO_PINS(123); |
395 | DECLARE_MSM_GPIO_PINS(124); |
396 | DECLARE_MSM_GPIO_PINS(125); |
397 | DECLARE_MSM_GPIO_PINS(126); |
398 | DECLARE_MSM_GPIO_PINS(127); |
399 | DECLARE_MSM_GPIO_PINS(128); |
400 | DECLARE_MSM_GPIO_PINS(129); |
401 | DECLARE_MSM_GPIO_PINS(130); |
402 | DECLARE_MSM_GPIO_PINS(131); |
403 | DECLARE_MSM_GPIO_PINS(132); |
404 | DECLARE_MSM_GPIO_PINS(133); |
405 | DECLARE_MSM_GPIO_PINS(134); |
406 | DECLARE_MSM_GPIO_PINS(135); |
407 | DECLARE_MSM_GPIO_PINS(136); |
408 | DECLARE_MSM_GPIO_PINS(137); |
409 | DECLARE_MSM_GPIO_PINS(138); |
410 | DECLARE_MSM_GPIO_PINS(139); |
411 | DECLARE_MSM_GPIO_PINS(140); |
412 | DECLARE_MSM_GPIO_PINS(141); |
413 | DECLARE_MSM_GPIO_PINS(142); |
414 | DECLARE_MSM_GPIO_PINS(143); |
415 | DECLARE_MSM_GPIO_PINS(144); |
416 | DECLARE_MSM_GPIO_PINS(145); |
417 | DECLARE_MSM_GPIO_PINS(146); |
418 | DECLARE_MSM_GPIO_PINS(147); |
419 | DECLARE_MSM_GPIO_PINS(148); |
420 | DECLARE_MSM_GPIO_PINS(149); |
421 | DECLARE_MSM_GPIO_PINS(150); |
422 | |
423 | static const unsigned int sdc1_rclk_pins[] = { 151 }; |
424 | static const unsigned int sdc1_clk_pins[] = { 152 }; |
425 | static const unsigned int sdc1_cmd_pins[] = { 153 }; |
426 | static const unsigned int sdc1_data_pins[] = { 154 }; |
427 | |
428 | enum qdu1000_functions { |
429 | msm_mux_gpio, |
430 | msm_mux_cmo_pri, |
431 | msm_mux_si5518_int, |
432 | msm_mux_atest_char, |
433 | msm_mux_atest_usb, |
434 | msm_mux_char_exec, |
435 | msm_mux_cmu_rng, |
436 | msm_mux_dbg_out_clk, |
437 | msm_mux_ddr_bist, |
438 | msm_mux_ddr_pxi0, |
439 | msm_mux_ddr_pxi1, |
440 | msm_mux_ddr_pxi2, |
441 | msm_mux_ddr_pxi3, |
442 | msm_mux_ddr_pxi4, |
443 | msm_mux_ddr_pxi5, |
444 | msm_mux_ddr_pxi6, |
445 | msm_mux_ddr_pxi7, |
446 | msm_mux_eth012_int_n, |
447 | msm_mux_eth345_int_n, |
448 | msm_mux_eth6_int_n, |
449 | msm_mux_gcc_gp1, |
450 | msm_mux_gcc_gp2, |
451 | msm_mux_gcc_gp3, |
452 | msm_mux_gps_pps_in, |
453 | msm_mux_hardsync_pps_in, |
454 | msm_mux_intr_c, |
455 | msm_mux_jitter_bist_ref, |
456 | msm_mux_pcie_clkreqn, |
457 | msm_mux_phase_flag, |
458 | msm_mux_pll_bist, |
459 | msm_mux_pll_clk, |
460 | msm_mux_prng_rosc, |
461 | msm_mux_qdss_cti, |
462 | msm_mux_qdss_gpio, |
463 | msm_mux_qlink0_enable, |
464 | msm_mux_qlink0_request, |
465 | msm_mux_qlink0_wmss, |
466 | msm_mux_qlink1_enable, |
467 | msm_mux_qlink1_request, |
468 | msm_mux_qlink1_wmss, |
469 | msm_mux_qlink2_enable, |
470 | msm_mux_qlink2_request, |
471 | msm_mux_qlink2_wmss, |
472 | msm_mux_qlink3_enable, |
473 | msm_mux_qlink3_request, |
474 | msm_mux_qlink3_wmss, |
475 | msm_mux_qlink4_enable, |
476 | msm_mux_qlink4_request, |
477 | msm_mux_qlink4_wmss, |
478 | msm_mux_qlink5_enable, |
479 | msm_mux_qlink5_request, |
480 | msm_mux_qlink5_wmss, |
481 | msm_mux_qlink6_enable, |
482 | msm_mux_qlink6_request, |
483 | msm_mux_qlink6_wmss, |
484 | msm_mux_qlink7_enable, |
485 | msm_mux_qlink7_request, |
486 | msm_mux_qlink7_wmss, |
487 | msm_mux_qspi_clk, |
488 | msm_mux_qspi_cs, |
489 | msm_mux_qspi0, |
490 | msm_mux_qspi1, |
491 | msm_mux_qspi2, |
492 | msm_mux_qspi3, |
493 | msm_mux_qup00, |
494 | msm_mux_qup01, |
495 | msm_mux_qup02, |
496 | msm_mux_qup03, |
497 | msm_mux_qup04, |
498 | msm_mux_qup05, |
499 | msm_mux_qup06, |
500 | msm_mux_qup07, |
501 | msm_mux_qup08, |
502 | msm_mux_qup10, |
503 | msm_mux_qup11, |
504 | msm_mux_qup12, |
505 | msm_mux_qup13, |
506 | msm_mux_qup14, |
507 | msm_mux_qup15, |
508 | msm_mux_qup16, |
509 | msm_mux_qup17, |
510 | msm_mux_qup20, |
511 | msm_mux_qup21, |
512 | msm_mux_qup22, |
513 | msm_mux_smb_alert, |
514 | msm_mux_smb_clk, |
515 | msm_mux_smb_dat, |
516 | msm_mux_tb_trig, |
517 | msm_mux_tgu_ch0, |
518 | msm_mux_tgu_ch1, |
519 | msm_mux_tgu_ch2, |
520 | msm_mux_tgu_ch3, |
521 | msm_mux_tgu_ch4, |
522 | msm_mux_tgu_ch5, |
523 | msm_mux_tgu_ch6, |
524 | msm_mux_tgu_ch7, |
525 | msm_mux_tmess_prng0, |
526 | msm_mux_tmess_prng1, |
527 | msm_mux_tmess_prng2, |
528 | msm_mux_tmess_prng3, |
529 | msm_mux_tod_pps_in, |
530 | msm_mux_tsense_pwm1, |
531 | msm_mux_tsense_pwm2, |
532 | msm_mux_usb2phy_ac, |
533 | msm_mux_usb_con_det, |
534 | msm_mux_usb_dfp_en, |
535 | msm_mux_usb_phy, |
536 | msm_mux_vfr_0, |
537 | msm_mux_vfr_1, |
538 | msm_mux_vsense_trigger, |
539 | msm_mux__, |
540 | }; |
541 | |
542 | static const char * const gpio_groups[] = { |
543 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio4" , "gpio5" , "gpio6" , "gpio7" , |
544 | "gpio8" , "gpio9" , "gpio10" , "gpio11" , "gpio12" , "gpio13" , "gpio14" , |
545 | "gpio15" , "gpio16" , "gpio17" , "gpio18" , "gpio19" , "gpio20" , "gpio21" , |
546 | "gpio22" , "gpio23" , "gpio24" , "gpio25" , "gpio26" , "gpio27" , "gpio28" , |
547 | "gpio29" , "gpio30" , "gpio31" , "gpio32" , "gpio33" , "gpio34" , "gpio35" , |
548 | "gpio36" , "gpio37" , "gpio38" , "gpio39" , "gpio40" , "gpio41" , "gpio42" , |
549 | "gpio43" , "gpio44" , "gpio45" , "gpio46" , "gpio47" , "gpio48" , "gpio49" , |
550 | "gpio50" , "gpio51" , "gpio52" , "gpio53" , "gpio54" , "gpio55" , "gpio56" , |
551 | "gpio57" , "gpio58" , "gpio59" , "gpio60" , "gpio61" , "gpio62" , "gpio63" , |
552 | "gpio64" , "gpio65" , "gpio66" , "gpio67" , "gpio68" , "gpio69" , "gpio70" , |
553 | "gpio71" , "gpio72" , "gpio73" , "gpio74" , "gpio75" , "gpio76" , "gpio77" , |
554 | "gpio78" , "gpio79" , "gpio80" , "gpio81" , "gpio82" , "gpio83" , "gpio84" , |
555 | "gpio85" , "gpio86" , "gpio87" , "gpio88" , "gpio89" , "gpio90" , "gpio91" , |
556 | "gpio92" , "gpio93" , "gpio94" , "gpio95" , "gpio96" , "gpio97" , "gpio98" , |
557 | "gpio99" , "gpio100" , "gpio101" , "gpio102" , "gpio103" , "gpio104" , |
558 | "gpio105" , "gpio106" , "gpio107" , "gpio108" , "gpio109" , "gpio110" , |
559 | "gpio111" , "gpio112" , "gpio113" , "gpio114" , "gpio115" , "gpio116" , |
560 | "gpio117" , "gpio118" , "gpio119" , "gpio120" , "gpio121" , "gpio122" , |
561 | "gpio123" , "gpio124" , "gpio125" , "gpio126" , "gpio127" , "gpio128" , |
562 | "gpio129" , "gpio130" , "gpio131" , "gpio132" , "gpio133" , "gpio134" , |
563 | "gpio135" , "gpio136" , "gpio137" , "gpio138" , "gpio139" , "gpio140" , |
564 | "gpio141" , "gpio142" , "gpio143" , "gpio144" , "gpio145" , "gpio146" , |
565 | "gpio147" , "gpio148" , "gpio149" , "gpio150" , |
566 | }; |
567 | static const char * const cmo_pri_groups[] = { |
568 | "gpio103" , |
569 | }; |
570 | static const char * const si5518_int_groups[] = { |
571 | "gpio44" , |
572 | }; |
573 | static const char * const atest_char_groups[] = { |
574 | "gpio89" , "gpio90" , "gpio91" , "gpio92" , "gpio95" , |
575 | }; |
576 | static const char * const atest_usb_groups[] = { |
577 | "gpio114" , "gpio115" , "gpio116" , "gpio117" , "gpio118" , |
578 | }; |
579 | static const char * const char_exec_groups[] = { |
580 | "gpio99" , "gpio100" , |
581 | }; |
582 | static const char * const cmu_rng_groups[] = { |
583 | "gpio89" , "gpio90" , "gpio91" , "gpio92" , |
584 | }; |
585 | static const char * const dbg_out_clk_groups[] = { |
586 | "gpio136" , |
587 | }; |
588 | static const char * const ddr_bist_groups[] = { |
589 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , |
590 | }; |
591 | static const char * const ddr_pxi0_groups[] = { |
592 | "gpio114" , "gpio115" , |
593 | }; |
594 | static const char * const ddr_pxi1_groups[] = { |
595 | "gpio116" , "gpio117" , |
596 | }; |
597 | static const char * const ddr_pxi2_groups[] = { |
598 | "gpio118" , "gpio119" , |
599 | }; |
600 | static const char * const ddr_pxi3_groups[] = { |
601 | "gpio120" , "gpio121" , |
602 | }; |
603 | static const char * const ddr_pxi4_groups[] = { |
604 | "gpio122" , "gpio123" , |
605 | }; |
606 | static const char * const ddr_pxi5_groups[] = { |
607 | "gpio124" , "gpio125" , |
608 | }; |
609 | static const char * const ddr_pxi6_groups[] = { |
610 | "gpio126" , "gpio127" , |
611 | }; |
612 | static const char * const ddr_pxi7_groups[] = { |
613 | "gpio128" , "gpio129" , |
614 | }; |
615 | static const char * const eth012_int_n_groups[] = { |
616 | "gpio86" , |
617 | }; |
618 | static const char * const eth345_int_n_groups[] = { |
619 | "gpio87" , |
620 | }; |
621 | static const char * const eth6_int_n_groups[] = { |
622 | "gpio88" , |
623 | }; |
624 | static const char * const gcc_gp1_groups[] = { |
625 | "gpio86" , "gpio134" , |
626 | }; |
627 | static const char * const gcc_gp2_groups[] = { |
628 | "gpio87" , "gpio135" , |
629 | }; |
630 | static const char * const gcc_gp3_groups[] = { |
631 | "gpio88" , "gpio136" , |
632 | }; |
633 | static const char * const gps_pps_in_groups[] = { |
634 | "gpio49" , |
635 | }; |
636 | static const char * const hardsync_pps_in_groups[] = { |
637 | "gpio47" , |
638 | }; |
639 | static const char * const intr_c_groups[] = { |
640 | "gpio26" , "gpio27" , "gpio28" , "gpio141" , "gpio142" , "gpio143" , |
641 | }; |
642 | static const char * const jitter_bist_ref_groups[] = { |
643 | "gpio130" , |
644 | }; |
645 | static const char * const pcie_clkreqn_groups[] = { |
646 | "gpio98" , "gpio99" , "gpio100" , |
647 | }; |
648 | static const char * const phase_flag_groups[] = { |
649 | "gpio6" , "gpio7" , "gpio8" , "gpio9" , "gpio16" , "gpio17" , "gpio18" , |
650 | "gpio19" , "gpio20" , "gpio22" , "gpio21" , "gpio23" , "gpio24" , "gpio25" , |
651 | "gpio26" , "gpio27" , "gpio28" , "gpio29" , "gpio30" , "gpio31" , "gpio32" , |
652 | "gpio33" , "gpio42" , "gpio43" , "gpio89" , "gpio90" , "gpio91" , "gpio92" , |
653 | "gpio95" , "gpio96" , "gpio97" , "gpio102" , |
654 | }; |
655 | static const char * const pll_bist_groups[] = { |
656 | "gpio20" , |
657 | }; |
658 | static const char * const pll_clk_groups[] = { |
659 | "gpio98" , |
660 | }; |
661 | static const char * const prng_rosc_groups[] = { |
662 | "gpio18" , "gpio19" , "gpio20" , "gpio21" , |
663 | }; |
664 | static const char * const qdss_cti_groups[] = { |
665 | "gpio36" , "gpio37" , "gpio38" , "gpio39" , "gpio40" , "gpio41" , "gpio48" , |
666 | "gpio49" , "gpio86" , "gpio87" , "gpio93" , "gpio94" , "gpio130" , "gpio131" , |
667 | "gpio132" , "gpio133" , "gpio134" , "gpio135" , "gpio144" , "gpio145" , |
668 | }; |
669 | static const char * const qdss_gpio_groups[] = { |
670 | "gpio6" , "gpio7" , "gpio8" , "gpio9" , "gpio16" , "gpio17" , "gpio18" , |
671 | "gpio19" , "gpio20" , "gpio21" , "gpio22" , "gpio23" , "gpio25" , "gpio26" , |
672 | "gpio27" , "gpio28" , "gpio24" , "gpio29" , "gpio30" , "gpio31" , "gpio32" , |
673 | "gpio33" , "gpio34" , "gpio35" , "gpio42" , "gpio43" , "gpio88" , "gpio89" , |
674 | "gpio90" , "gpio91" , "gpio92" , "gpio95" , "gpio96" , "gpio97" , "gpio102" , |
675 | "gpio103" , |
676 | }; |
677 | static const char * const qlink0_enable_groups[] = { |
678 | "gpio67" , |
679 | }; |
680 | static const char * const qlink0_request_groups[] = { |
681 | "gpio66" , |
682 | }; |
683 | static const char * const qlink0_wmss_groups[] = { |
684 | "gpio82" , |
685 | }; |
686 | static const char * const qlink1_enable_groups[] = { |
687 | "gpio69" , |
688 | }; |
689 | static const char * const qlink1_request_groups[] = { |
690 | "gpio68" , |
691 | }; |
692 | static const char * const qlink1_wmss_groups[] = { |
693 | "gpio83" , |
694 | }; |
695 | static const char * const qlink2_enable_groups[] = { |
696 | "gpio71" , |
697 | }; |
698 | static const char * const qlink2_request_groups[] = { |
699 | "gpio70" , |
700 | }; |
701 | static const char * const qlink2_wmss_groups[] = { |
702 | "gpio138" , |
703 | }; |
704 | static const char * const qlink3_enable_groups[] = { |
705 | "gpio73" , |
706 | }; |
707 | static const char * const qlink3_request_groups[] = { |
708 | "gpio72" , |
709 | }; |
710 | static const char * const qlink3_wmss_groups[] = { |
711 | "gpio139" , |
712 | }; |
713 | static const char * const qlink4_enable_groups[] = { |
714 | "gpio75" , |
715 | }; |
716 | static const char * const qlink4_request_groups[] = { |
717 | "gpio74" , |
718 | }; |
719 | static const char * const qlink4_wmss_groups[] = { |
720 | "gpio84" , |
721 | }; |
722 | static const char * const qlink5_enable_groups[] = { |
723 | "gpio77" , |
724 | }; |
725 | static const char * const qlink5_request_groups[] = { |
726 | "gpio76" , |
727 | }; |
728 | static const char * const qlink5_wmss_groups[] = { |
729 | "gpio85" , |
730 | }; |
731 | static const char * const qlink6_enable_groups[] = { |
732 | "gpio79" , |
733 | }; |
734 | static const char * const qlink6_request_groups[] = { |
735 | "gpio78" , |
736 | }; |
737 | static const char * const qlink6_wmss_groups[] = { |
738 | "gpio56" , |
739 | }; |
740 | static const char * const qlink7_enable_groups[] = { |
741 | "gpio81" , |
742 | }; |
743 | static const char * const qlink7_request_groups[] = { |
744 | "gpio80" , |
745 | }; |
746 | static const char * const qlink7_wmss_groups[] = { |
747 | "gpio57" , |
748 | }; |
749 | static const char * const qspi0_groups[] = { |
750 | "gpio114" , |
751 | }; |
752 | static const char * const qspi1_groups[] = { |
753 | "gpio115" , |
754 | }; |
755 | static const char * const qspi2_groups[] = { |
756 | "gpio116" , |
757 | }; |
758 | static const char * const qspi3_groups[] = { |
759 | "gpio117" , |
760 | }; |
761 | static const char * const qspi_clk_groups[] = { |
762 | "gpio126" , |
763 | }; |
764 | static const char * const qspi_cs_groups[] = { |
765 | "gpio125" , |
766 | }; |
767 | static const char * const qup00_groups[] = { |
768 | "gpio6" , "gpio7" , "gpio8" , "gpio9" , |
769 | }; |
770 | static const char * const qup01_groups[] = { |
771 | "gpio10" , "gpio11" , "gpio12" , "gpio13" , |
772 | }; |
773 | static const char * const qup02_groups[] = { |
774 | "gpio10" , "gpio11" , "gpio12" , "gpio13" , |
775 | }; |
776 | static const char * const qup03_groups[] = { |
777 | "gpio14" , "gpio15" , "gpio16" , "gpio17" , |
778 | }; |
779 | static const char * const qup04_groups[] = { |
780 | "gpio14" , "gpio15" , "gpio16" , "gpio17" , |
781 | }; |
782 | static const char * const qup05_groups[] = { |
783 | "gpio130" , "gpio131" , "gpio132" , "gpio133" , |
784 | }; |
785 | static const char * const qup06_groups[] = { |
786 | "gpio130" , "gpio131" , "gpio132" , "gpio133" , |
787 | }; |
788 | static const char * const qup07_groups[] = { |
789 | "gpio134" , "gpio135" , |
790 | }; |
791 | static const char * const qup08_groups[] = { |
792 | "gpio134" , "gpio135" , |
793 | }; |
794 | static const char * const qup10_groups[] = { |
795 | "gpio18" , "gpio19" , "gpio20" , "gpio21" , |
796 | }; |
797 | static const char * const qup11_groups[] = { |
798 | "gpio22" , "gpio23" , "gpio24" , "gpio25" , |
799 | }; |
800 | static const char * const qup12_groups[] = { |
801 | "gpio22" , "gpio23" , "gpio24" , "gpio25" , |
802 | }; |
803 | static const char * const qup13_groups[] = { |
804 | "gpio26" , "gpio27" , "gpio28" , "gpio29" , |
805 | }; |
806 | static const char * const qup14_groups[] = { |
807 | "gpio26" , "gpio27" , "gpio28" , "gpio29" , |
808 | }; |
809 | static const char * const qup15_groups[] = { |
810 | "gpio30" , "gpio31" , "gpio32" , "gpio33" , |
811 | }; |
812 | static const char * const qup16_groups[] = { |
813 | "gpio29" , "gpio34" , "gpio35" , "gpio36" , "gpio37" , "gpio38" , "gpio39" , |
814 | }; |
815 | static const char * const qup17_groups[] = { |
816 | "gpio12" , "gpio13" , "gpio14" , "gpio30" , "gpio31" , "gpio40" , "gpio41" , |
817 | }; |
818 | static const char * const qup20_groups[] = { |
819 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , |
820 | }; |
821 | static const char * const qup21_groups[] = { |
822 | "gpio0" , "gpio1" , "gpio2" , "gpio3" , |
823 | }; |
824 | static const char * const qup22_groups[] = { |
825 | "gpio4" , "gpio5" , "gpio128" , "gpio129" , |
826 | }; |
827 | static const char * const smb_alert_groups[] = { |
828 | "gpio88" , "gpio101" , |
829 | }; |
830 | static const char * const smb_clk_groups[] = { |
831 | "gpio133" , |
832 | }; |
833 | static const char * const smb_dat_groups[] = { |
834 | "gpio132" , |
835 | }; |
836 | static const char * const tb_trig_groups[] = { |
837 | "gpio114" , |
838 | }; |
839 | static const char * const tgu_ch0_groups[] = { |
840 | "gpio6" , |
841 | }; |
842 | static const char * const tgu_ch1_groups[] = { |
843 | "gpio7" , |
844 | }; |
845 | static const char * const tgu_ch2_groups[] = { |
846 | "gpio8" , |
847 | }; |
848 | static const char * const tgu_ch3_groups[] = { |
849 | "gpio9" , |
850 | }; |
851 | static const char * const tgu_ch4_groups[] = { |
852 | "gpio44" , |
853 | }; |
854 | static const char * const tgu_ch5_groups[] = { |
855 | "gpio45" , |
856 | }; |
857 | static const char * const tgu_ch6_groups[] = { |
858 | "gpio46" , |
859 | }; |
860 | static const char * const tgu_ch7_groups[] = { |
861 | "gpio47" , |
862 | }; |
863 | static const char * const tmess_prng0_groups[] = { |
864 | "gpio33" , |
865 | }; |
866 | static const char * const tmess_prng1_groups[] = { |
867 | "gpio32" , |
868 | }; |
869 | static const char * const tmess_prng2_groups[] = { |
870 | "gpio31" , |
871 | }; |
872 | static const char * const tmess_prng3_groups[] = { |
873 | "gpio30" , |
874 | }; |
875 | static const char * const tod_pps_in_groups[] = { |
876 | "gpio48" , |
877 | }; |
878 | static const char * const tsense_pwm1_groups[] = { |
879 | "gpio2" , |
880 | }; |
881 | static const char * const tsense_pwm2_groups[] = { |
882 | "gpio3" , |
883 | }; |
884 | static const char * const usb2phy_ac_groups[] = { |
885 | "gpio90" , |
886 | }; |
887 | static const char * const usb_con_det_groups[] = { |
888 | "gpio42" , |
889 | }; |
890 | static const char * const usb_dfp_en_groups[] = { |
891 | "gpio43" , |
892 | }; |
893 | static const char * const usb_phy_groups[] = { |
894 | "gpio91" , |
895 | }; |
896 | static const char * const vfr_0_groups[] = { |
897 | "gpio93" , |
898 | }; |
899 | static const char * const vfr_1_groups[] = { |
900 | "gpio94" , |
901 | }; |
902 | static const char * const vsense_trigger_groups[] = { |
903 | "gpio135" , |
904 | }; |
905 | |
906 | static const struct pinfunction qdu1000_functions[] = { |
907 | MSM_PIN_FUNCTION(gpio), |
908 | MSM_PIN_FUNCTION(cmo_pri), |
909 | MSM_PIN_FUNCTION(si5518_int), |
910 | MSM_PIN_FUNCTION(atest_char), |
911 | MSM_PIN_FUNCTION(atest_usb), |
912 | MSM_PIN_FUNCTION(char_exec), |
913 | MSM_PIN_FUNCTION(cmu_rng), |
914 | MSM_PIN_FUNCTION(dbg_out_clk), |
915 | MSM_PIN_FUNCTION(ddr_bist), |
916 | MSM_PIN_FUNCTION(ddr_pxi0), |
917 | MSM_PIN_FUNCTION(ddr_pxi1), |
918 | MSM_PIN_FUNCTION(ddr_pxi2), |
919 | MSM_PIN_FUNCTION(ddr_pxi3), |
920 | MSM_PIN_FUNCTION(ddr_pxi4), |
921 | MSM_PIN_FUNCTION(ddr_pxi5), |
922 | MSM_PIN_FUNCTION(ddr_pxi6), |
923 | MSM_PIN_FUNCTION(ddr_pxi7), |
924 | MSM_PIN_FUNCTION(eth012_int_n), |
925 | MSM_PIN_FUNCTION(eth345_int_n), |
926 | MSM_PIN_FUNCTION(eth6_int_n), |
927 | MSM_PIN_FUNCTION(gcc_gp1), |
928 | MSM_PIN_FUNCTION(gcc_gp2), |
929 | MSM_PIN_FUNCTION(gcc_gp3), |
930 | MSM_PIN_FUNCTION(gps_pps_in), |
931 | MSM_PIN_FUNCTION(hardsync_pps_in), |
932 | MSM_PIN_FUNCTION(intr_c), |
933 | MSM_PIN_FUNCTION(jitter_bist_ref), |
934 | MSM_PIN_FUNCTION(pcie_clkreqn), |
935 | MSM_PIN_FUNCTION(phase_flag), |
936 | MSM_PIN_FUNCTION(pll_bist), |
937 | MSM_PIN_FUNCTION(pll_clk), |
938 | MSM_PIN_FUNCTION(prng_rosc), |
939 | MSM_PIN_FUNCTION(qdss_cti), |
940 | MSM_PIN_FUNCTION(qdss_gpio), |
941 | MSM_PIN_FUNCTION(qlink0_enable), |
942 | MSM_PIN_FUNCTION(qlink0_request), |
943 | MSM_PIN_FUNCTION(qlink0_wmss), |
944 | MSM_PIN_FUNCTION(qlink1_enable), |
945 | MSM_PIN_FUNCTION(qlink1_request), |
946 | MSM_PIN_FUNCTION(qlink1_wmss), |
947 | MSM_PIN_FUNCTION(qlink2_enable), |
948 | MSM_PIN_FUNCTION(qlink2_request), |
949 | MSM_PIN_FUNCTION(qlink2_wmss), |
950 | MSM_PIN_FUNCTION(qlink3_enable), |
951 | MSM_PIN_FUNCTION(qlink3_request), |
952 | MSM_PIN_FUNCTION(qlink3_wmss), |
953 | MSM_PIN_FUNCTION(qlink4_enable), |
954 | MSM_PIN_FUNCTION(qlink4_request), |
955 | MSM_PIN_FUNCTION(qlink4_wmss), |
956 | MSM_PIN_FUNCTION(qlink5_enable), |
957 | MSM_PIN_FUNCTION(qlink5_request), |
958 | MSM_PIN_FUNCTION(qlink5_wmss), |
959 | MSM_PIN_FUNCTION(qlink6_enable), |
960 | MSM_PIN_FUNCTION(qlink6_request), |
961 | MSM_PIN_FUNCTION(qlink6_wmss), |
962 | MSM_PIN_FUNCTION(qlink7_enable), |
963 | MSM_PIN_FUNCTION(qlink7_request), |
964 | MSM_PIN_FUNCTION(qlink7_wmss), |
965 | MSM_PIN_FUNCTION(qspi0), |
966 | MSM_PIN_FUNCTION(qspi1), |
967 | MSM_PIN_FUNCTION(qspi2), |
968 | MSM_PIN_FUNCTION(qspi3), |
969 | MSM_PIN_FUNCTION(qspi_clk), |
970 | MSM_PIN_FUNCTION(qspi_cs), |
971 | MSM_PIN_FUNCTION(qup00), |
972 | MSM_PIN_FUNCTION(qup01), |
973 | MSM_PIN_FUNCTION(qup02), |
974 | MSM_PIN_FUNCTION(qup03), |
975 | MSM_PIN_FUNCTION(qup04), |
976 | MSM_PIN_FUNCTION(qup05), |
977 | MSM_PIN_FUNCTION(qup06), |
978 | MSM_PIN_FUNCTION(qup07), |
979 | MSM_PIN_FUNCTION(qup08), |
980 | MSM_PIN_FUNCTION(qup10), |
981 | MSM_PIN_FUNCTION(qup11), |
982 | MSM_PIN_FUNCTION(qup12), |
983 | MSM_PIN_FUNCTION(qup13), |
984 | MSM_PIN_FUNCTION(qup14), |
985 | MSM_PIN_FUNCTION(qup15), |
986 | MSM_PIN_FUNCTION(qup16), |
987 | MSM_PIN_FUNCTION(qup17), |
988 | MSM_PIN_FUNCTION(qup20), |
989 | MSM_PIN_FUNCTION(qup21), |
990 | MSM_PIN_FUNCTION(qup22), |
991 | MSM_PIN_FUNCTION(smb_alert), |
992 | MSM_PIN_FUNCTION(smb_clk), |
993 | MSM_PIN_FUNCTION(smb_dat), |
994 | MSM_PIN_FUNCTION(tb_trig), |
995 | MSM_PIN_FUNCTION(tgu_ch0), |
996 | MSM_PIN_FUNCTION(tgu_ch1), |
997 | MSM_PIN_FUNCTION(tgu_ch2), |
998 | MSM_PIN_FUNCTION(tgu_ch3), |
999 | MSM_PIN_FUNCTION(tgu_ch4), |
1000 | MSM_PIN_FUNCTION(tgu_ch5), |
1001 | MSM_PIN_FUNCTION(tgu_ch6), |
1002 | MSM_PIN_FUNCTION(tgu_ch7), |
1003 | MSM_PIN_FUNCTION(tmess_prng0), |
1004 | MSM_PIN_FUNCTION(tmess_prng1), |
1005 | MSM_PIN_FUNCTION(tmess_prng2), |
1006 | MSM_PIN_FUNCTION(tmess_prng3), |
1007 | MSM_PIN_FUNCTION(tod_pps_in), |
1008 | MSM_PIN_FUNCTION(tsense_pwm1), |
1009 | MSM_PIN_FUNCTION(tsense_pwm2), |
1010 | MSM_PIN_FUNCTION(usb2phy_ac), |
1011 | MSM_PIN_FUNCTION(usb_con_det), |
1012 | MSM_PIN_FUNCTION(usb_dfp_en), |
1013 | MSM_PIN_FUNCTION(usb_phy), |
1014 | MSM_PIN_FUNCTION(vfr_0), |
1015 | MSM_PIN_FUNCTION(vfr_1), |
1016 | MSM_PIN_FUNCTION(vsense_trigger), |
1017 | }; |
1018 | |
1019 | /* |
1020 | * Every pin is maintained as a single group, and missing or non-existing pin |
1021 | * would be maintained as dummy group to synchronize pin group index with |
1022 | * pin descriptor registered with pinctrl core. |
1023 | * Clients would not be able to request these dummy pin groups. |
1024 | */ |
1025 | static const struct msm_pingroup qdu1000_groups[] = { |
1026 | [0] = PINGROUP(0, qup20, qup21, ddr_bist, _, _, _, _, _, _), |
1027 | [1] = PINGROUP(1, qup20, qup21, ddr_bist, _, _, _, _, _, _), |
1028 | [2] = PINGROUP(2, qup21, qup20, ddr_bist, _, |
1029 | tsense_pwm1, _, _, _, _), |
1030 | [3] = PINGROUP(3, qup21, qup20, ddr_bist, _, |
1031 | tsense_pwm2, _, _, _, _), |
1032 | [4] = PINGROUP(4, qup22, _, _, _, _, _, _, _, _), |
1033 | [5] = PINGROUP(5, qup22, _, _, _, _, _, _, _, _), |
1034 | [6] = PINGROUP(6, qup00, tgu_ch0, phase_flag, _, |
1035 | qdss_gpio, _, _, _, _), |
1036 | [7] = PINGROUP(7, qup00, tgu_ch1, phase_flag, _, |
1037 | qdss_gpio, _, _, _, _), |
1038 | [8] = PINGROUP(8, qup00, tgu_ch2, phase_flag, _, |
1039 | qdss_gpio, _, _, _, _), |
1040 | [9] = PINGROUP(9, qup00, tgu_ch3, phase_flag, _, |
1041 | qdss_gpio, _, _, _, _), |
1042 | [10] = PINGROUP(10, qup01, qup02, _, _, _, _, _, _, _), |
1043 | [11] = PINGROUP(11, qup01, qup02, _, _, _, _, _, _, _), |
1044 | [12] = PINGROUP(12, qup02, qup01, qup17, _, _, _, _, _, _), |
1045 | [13] = PINGROUP(13, qup02, qup01, qup17, _, _, _, _, _, _), |
1046 | [14] = PINGROUP(14, qup03, qup04, qup17, _, _, _, _, _, _), |
1047 | [15] = PINGROUP(15, qup03, qup04, _, _, _, _, _, _, _), |
1048 | [16] = PINGROUP(16, qup04, qup03, phase_flag, _, |
1049 | qdss_gpio, _, _, _, _), |
1050 | [17] = PINGROUP(17, qup04, qup03, phase_flag, _, |
1051 | qdss_gpio, _, _, _, _), |
1052 | [18] = PINGROUP(18, qup10, prng_rosc, phase_flag, |
1053 | _, qdss_gpio, _, _, _, _), |
1054 | [19] = PINGROUP(19, qup10, prng_rosc, phase_flag, |
1055 | _, qdss_gpio, _, _, _, _), |
1056 | [20] = PINGROUP(20, qup10, prng_rosc, pll_bist, |
1057 | phase_flag, _, qdss_gpio, _, _, _), |
1058 | [21] = PINGROUP(21, qup10, prng_rosc, phase_flag, |
1059 | _, qdss_gpio, _, _, _, _), |
1060 | [22] = PINGROUP(22, qup11, qup12, phase_flag, _, |
1061 | qdss_gpio, _, _, _, _), |
1062 | [23] = PINGROUP(23, qup11, qup12, phase_flag, _, |
1063 | qdss_gpio, _, _, _, _), |
1064 | [24] = PINGROUP(24, qup12, qup11, phase_flag, _, |
1065 | qdss_gpio, _, _, _, _), |
1066 | [25] = PINGROUP(25, qup12, qup11, phase_flag, _, |
1067 | qdss_gpio, _, _, _, _), |
1068 | [26] = PINGROUP(26, qup13, qup14, intr_c, |
1069 | phase_flag, _, qdss_gpio, _, _, _), |
1070 | [27] = PINGROUP(27, qup13, qup14, intr_c, |
1071 | phase_flag, _, qdss_gpio, _, _, _), |
1072 | [28] = PINGROUP(28, qup14, qup13, intr_c, |
1073 | phase_flag, _, qdss_gpio, _, _, _), |
1074 | [29] = PINGROUP(29, qup14, qup13, qup16, |
1075 | phase_flag, _, qdss_gpio, _, _, _), |
1076 | [30] = PINGROUP(30, qup17, qup15, tmess_prng3, |
1077 | phase_flag, _, qdss_gpio, _, _, _), |
1078 | [31] = PINGROUP(31, qup17, qup15, tmess_prng2, |
1079 | phase_flag, _, qdss_gpio, _, _, _), |
1080 | [32] = PINGROUP(32, qup15, tmess_prng1, phase_flag, |
1081 | _, qdss_gpio, _, _, _, _), |
1082 | [33] = PINGROUP(33, qup15, tmess_prng0, phase_flag, |
1083 | _, qdss_gpio, _, _, _, _), |
1084 | [34] = PINGROUP(34, qup16, qdss_gpio, _, _, _, _, _, _, _), |
1085 | [35] = PINGROUP(35, qup16, qdss_gpio, _, _, _, _, _, _, _), |
1086 | [36] = PINGROUP(36, qup16, qdss_cti, _, _, _, _, _, _, _), |
1087 | [37] = PINGROUP(37, qup16, qdss_cti, _, _, _, _, _, _, _), |
1088 | [38] = PINGROUP(38, qup16, qdss_cti, _, _, _, _, _, _, _), |
1089 | [39] = PINGROUP(39, qup16, qdss_cti, _, _, _, _, _, _, _), |
1090 | [40] = PINGROUP(40, qup17, qdss_cti, _, _, _, _, _, _, _), |
1091 | [41] = PINGROUP(41, qup17, qdss_cti, _, _, _, _, _, _, _), |
1092 | [42] = PINGROUP(42, usb_con_det, phase_flag, _, |
1093 | qdss_gpio, _, _, _, _, _), |
1094 | [43] = PINGROUP(43, usb_dfp_en, phase_flag, _, |
1095 | qdss_gpio, _, _, _, _, _), |
1096 | [44] = PINGROUP(44, si5518_int, tgu_ch4, _, _, _, _, _, _, _), |
1097 | [45] = PINGROUP(45, tgu_ch5, _, _, _, _, _, _, _, _), |
1098 | [46] = PINGROUP(46, tgu_ch6, _, _, _, _, _, _, _, _), |
1099 | [47] = PINGROUP(47, hardsync_pps_in, tgu_ch7, _, _, _, _, _, _, _), |
1100 | [48] = PINGROUP(48, tod_pps_in, qdss_cti, _, _, _, _, _, _, _), |
1101 | [49] = PINGROUP(49, gps_pps_in, qdss_cti, _, _, _, _, _, _, _), |
1102 | [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), |
1103 | [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), |
1104 | [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), |
1105 | [53] = PINGROUP(53, _, _, _, _, _, _, _, _, _), |
1106 | [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _), |
1107 | [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _), |
1108 | [56] = PINGROUP(56, _, qlink6_wmss, _, _, _, _, _, _, _), |
1109 | [57] = PINGROUP(57, _, qlink7_wmss, _, _, _, _, _, _, _), |
1110 | [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), |
1111 | [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _), |
1112 | [60] = PINGROUP(60, _, _, _, _, _, _, _, _, _), |
1113 | [61] = PINGROUP(61, _, _, _, _, _, _, _, _, _), |
1114 | [62] = PINGROUP(62, _, _, _, _, _, _, _, _, _), |
1115 | [63] = PINGROUP(63, _, _, _, _, _, _, _, _, _), |
1116 | [64] = PINGROUP(64, _, _, _, _, _, _, _, _, _), |
1117 | [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _), |
1118 | [66] = PINGROUP(66, qlink0_request, _, _, _, _, _, _, _, _), |
1119 | [67] = PINGROUP(67, qlink0_enable, _, _, _, _, _, _, _, _), |
1120 | [68] = PINGROUP(68, qlink1_request, _, _, _, _, _, _, _, _), |
1121 | [69] = PINGROUP(69, qlink1_enable, _, _, _, _, _, _, _, _), |
1122 | [70] = PINGROUP(70, qlink2_request, _, _, _, _, _, _, _, _), |
1123 | [71] = PINGROUP(71, qlink2_enable, _, _, _, _, _, _, _, _), |
1124 | [72] = PINGROUP(72, qlink3_request, _, _, _, _, _, _, _, _), |
1125 | [73] = PINGROUP(73, qlink3_enable, _, _, _, _, _, _, _, _), |
1126 | [74] = PINGROUP(74, qlink4_request, _, _, _, _, _, _, _, _), |
1127 | [75] = PINGROUP(75, qlink4_enable, _, _, _, _, _, _, _, _), |
1128 | [76] = PINGROUP(76, qlink5_request, _, _, _, _, _, _, _, _), |
1129 | [77] = PINGROUP(77, qlink5_enable, _, _, _, _, _, _, _, _), |
1130 | [78] = PINGROUP(78, qlink6_request, _, _, _, _, _, _, _, _), |
1131 | [79] = PINGROUP(79, qlink6_enable, _, _, _, _, _, _, _, _), |
1132 | [80] = PINGROUP(80, qlink7_request, _, _, _, _, _, _, _, _), |
1133 | [81] = PINGROUP(81, qlink7_enable, _, _, _, _, _, _, _, _), |
1134 | [82] = PINGROUP(82, qlink0_wmss, _, _, _, _, _, _, _, _), |
1135 | [83] = PINGROUP(83, qlink1_wmss, _, _, _, _, _, _, _, _), |
1136 | [84] = PINGROUP(84, qlink4_wmss, _, _, _, _, _, _, _, _), |
1137 | [85] = PINGROUP(85, qlink5_wmss, _, _, _, _, _, _, _, _), |
1138 | [86] = PINGROUP(86, eth012_int_n, gcc_gp1, _, qdss_cti, _, _, _, _, _), |
1139 | [87] = PINGROUP(87, eth345_int_n, gcc_gp2, _, qdss_cti, _, _, _, _, _), |
1140 | [88] = PINGROUP(88, eth6_int_n, smb_alert, gcc_gp3, _, |
1141 | qdss_gpio, _, _, _, _), |
1142 | [89] = PINGROUP(89, phase_flag, cmu_rng, _, |
1143 | qdss_gpio, atest_char, _, _, _, _), |
1144 | [90] = PINGROUP(90, usb2phy_ac, phase_flag, |
1145 | cmu_rng, _, qdss_gpio, |
1146 | atest_char, _, _, _), |
1147 | [91] = PINGROUP(91, usb_phy, phase_flag, cmu_rng, |
1148 | _, qdss_gpio, atest_char, _, _, _), |
1149 | [92] = PINGROUP(92, phase_flag, cmu_rng, _, |
1150 | qdss_gpio, atest_char, _, _, _, _), |
1151 | [93] = PINGROUP(93, vfr_0, qdss_cti, _, _, _, _, _, _, _), |
1152 | [94] = PINGROUP(94, vfr_1, qdss_cti, _, _, _, _, _, _, _), |
1153 | [95] = PINGROUP(95, phase_flag, _, qdss_gpio, |
1154 | atest_char, _, _, _, _, _), |
1155 | [96] = PINGROUP(96, phase_flag, _, qdss_gpio, _, _, _, _, _, _), |
1156 | [97] = PINGROUP(97, phase_flag, _, qdss_gpio, _, _, _, _, _, _), |
1157 | [98] = PINGROUP(98, pll_clk, _, _, _, _, _, _, _, _), |
1158 | [99] = PINGROUP(99, pcie_clkreqn, char_exec, _, _, _, _, _, _, _), |
1159 | [100] = PINGROUP(100, char_exec, _, _, _, _, _, _, _, _), |
1160 | [101] = PINGROUP(101, smb_alert, _, _, _, _, _, _, _, _), |
1161 | [102] = PINGROUP(102, phase_flag, _, qdss_gpio, _, _, _, _, _, _), |
1162 | [103] = PINGROUP(103, cmo_pri, qdss_gpio, _, _, _, _, _, _, _), |
1163 | [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), |
1164 | [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), |
1165 | [106] = PINGROUP(106, _, _, _, _, _, _, _, _, _), |
1166 | [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), |
1167 | [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _), |
1168 | [109] = PINGROUP(109, _, _, _, _, _, _, _, _, _), |
1169 | [110] = PINGROUP(110, _, _, _, _, _, _, _, _, _), |
1170 | [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _), |
1171 | [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), |
1172 | [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), |
1173 | [114] = PINGROUP(114, qspi0, tb_trig, _, |
1174 | atest_usb, ddr_pxi0, _, _, _, _), |
1175 | [115] = PINGROUP(115, qspi1, _, atest_usb, |
1176 | ddr_pxi0, _, _, _, _, _), |
1177 | [116] = PINGROUP(116, qspi2, _, atest_usb, |
1178 | ddr_pxi1, _, _, _, _, _), |
1179 | [117] = PINGROUP(117, qspi3, _, atest_usb, |
1180 | ddr_pxi1, _, _, _, _, _), |
1181 | [118] = PINGROUP(118, _, atest_usb, ddr_pxi2, _, _, _, _, _, _), |
1182 | [119] = PINGROUP(119, _, _, ddr_pxi2, _, _, _, _, _, _), |
1183 | [120] = PINGROUP(120, _, _, ddr_pxi3, _, _, _, _, _, _), |
1184 | [121] = PINGROUP(121, _, ddr_pxi3, _, _, _, _, _, _, _), |
1185 | [122] = PINGROUP(122, _, ddr_pxi4, _, _, _, _, _, _, _), |
1186 | [123] = PINGROUP(123, _, ddr_pxi4, _, _, _, _, _, _, _), |
1187 | [124] = PINGROUP(124, _, ddr_pxi5, _, _, _, _, _, _, _), |
1188 | [125] = PINGROUP(125, qspi_cs, _, ddr_pxi5, _, _, _, _, _, _), |
1189 | [126] = PINGROUP(126, qspi_clk, _, ddr_pxi6, _, _, _, _, _, _), |
1190 | [127] = PINGROUP(127, _, ddr_pxi6, _, _, _, _, _, _, _), |
1191 | [128] = PINGROUP(128, qup22, _, ddr_pxi7, _, _, _, _, _, _), |
1192 | [129] = PINGROUP(129, qup22, ddr_pxi7, _, _, _, _, _, _, _), |
1193 | [130] = PINGROUP(130, qup05, qup06, jitter_bist_ref, |
1194 | qdss_cti, _, _, _, _, _), |
1195 | [131] = PINGROUP(131, qup05, qup06, qdss_cti, _, _, _, _, _, _), |
1196 | [132] = PINGROUP(132, qup06, qup05, smb_dat, |
1197 | qdss_cti, _, _, _, _, _), |
1198 | [133] = PINGROUP(133, qup06, qup05, smb_clk, |
1199 | qdss_cti, _, _, _, _, _), |
1200 | [134] = PINGROUP(134, qup08, qup07, gcc_gp1, _, |
1201 | qdss_cti, _, _, _, _), |
1202 | [135] = PINGROUP(135, qup08, qup07, gcc_gp2, _, |
1203 | qdss_cti, vsense_trigger, _, _, _), |
1204 | [136] = PINGROUP(136, gcc_gp3, dbg_out_clk, _, _, _, _, _, _, _), |
1205 | [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), |
1206 | [138] = PINGROUP(138, qlink2_wmss, _, _, _, _, _, _, _, _), |
1207 | [139] = PINGROUP(139, qlink3_wmss, _, _, _, _, _, _, _, _), |
1208 | [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), |
1209 | [141] = PINGROUP(141, intr_c, _, _, _, _, _, _, _, _), |
1210 | [142] = PINGROUP(142, intr_c, _, _, _, _, _, _, _, _), |
1211 | [143] = PINGROUP(143, intr_c, _, _, _, _, _, _, _, _), |
1212 | [144] = PINGROUP(144, qdss_cti, _, _, _, _, _, _, _, _), |
1213 | [145] = PINGROUP(145, qdss_cti, _, _, _, _, _, _, _, _), |
1214 | [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), |
1215 | [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), |
1216 | [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), |
1217 | [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _), |
1218 | [150] = PINGROUP(150, _, _, _, _, _, _, _, _, _), |
1219 | [151] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9e000, 0, 0), |
1220 | [152] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9d000, 13, 6), |
1221 | [153] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9d000, 11, 3), |
1222 | [154] = SDC_QDSD_PINGROUP(sdc1_data, 0x9d000, 9, 0), |
1223 | }; |
1224 | static const struct msm_pinctrl_soc_data qdu1000_tlmm = { |
1225 | .pins = qdu1000_pins, |
1226 | .npins = ARRAY_SIZE(qdu1000_pins), |
1227 | .functions = qdu1000_functions, |
1228 | .nfunctions = ARRAY_SIZE(qdu1000_functions), |
1229 | .groups = qdu1000_groups, |
1230 | .ngroups = ARRAY_SIZE(qdu1000_groups), |
1231 | .ngpios = 151, |
1232 | }; |
1233 | |
1234 | static int qdu1000_tlmm_probe(struct platform_device *pdev) |
1235 | { |
1236 | return msm_pinctrl_probe(pdev, soc_data: &qdu1000_tlmm); |
1237 | } |
1238 | |
1239 | static const struct of_device_id qdu1000_tlmm_of_match[] = { |
1240 | { .compatible = "qcom,qdu1000-tlmm" , }, |
1241 | { }, |
1242 | }; |
1243 | MODULE_DEVICE_TABLE(of, qdu1000_tlmm_of_match); |
1244 | |
1245 | static struct platform_driver qdu1000_tlmm_driver = { |
1246 | .driver = { |
1247 | .name = "qdu1000-tlmm" , |
1248 | .of_match_table = qdu1000_tlmm_of_match, |
1249 | }, |
1250 | .probe = qdu1000_tlmm_probe, |
1251 | .remove_new = msm_pinctrl_remove, |
1252 | }; |
1253 | |
1254 | static int __init qdu1000_tlmm_init(void) |
1255 | { |
1256 | return platform_driver_register(&qdu1000_tlmm_driver); |
1257 | } |
1258 | arch_initcall(qdu1000_tlmm_init); |
1259 | |
1260 | static void __exit qdu1000_tlmm_exit(void) |
1261 | { |
1262 | platform_driver_unregister(&qdu1000_tlmm_driver); |
1263 | } |
1264 | module_exit(qdu1000_tlmm_exit); |
1265 | |
1266 | MODULE_DESCRIPTION("QTI QDU1000 TLMM driver" ); |
1267 | MODULE_LICENSE("GPL" ); |
1268 | |