1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A779H0 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c
8 */
9
10#include <linux/errno.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13
14#include "sh_pfc.h"
15
16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
17
18#define CPU_ALL_GP(fn, sfx) \
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(1, 29, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_16(2, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 16, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 17, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 18, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 19, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 20, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 21, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 22, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_1(3, 23, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(3, 24, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_1(3, 25, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(3, 26, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(3, 27, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(3, 28, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(3, 29, fn, sfx, CFG_FLAGS), \
43 PORT_GP_CFG_1(3, 30, fn, sfx, CFG_FLAGS), \
44 PORT_GP_CFG_1(3, 31, fn, sfx, CFG_FLAGS), \
45 PORT_GP_CFG_14(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
46 PORT_GP_CFG_1(4, 14, fn, sfx, CFG_FLAGS), \
47 PORT_GP_CFG_1(4, 15, fn, sfx, CFG_FLAGS), \
48 PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS), \
49 PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS), \
50 PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS), \
51 PORT_GP_CFG_21(5, fn, sfx, CFG_FLAGS), \
52 PORT_GP_CFG_21(6, fn, sfx, CFG_FLAGS), \
53 PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS)
54
55#define CPU_ALL_NOGP(fn) \
56 PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
57 PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
58 PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
59
60/*
61 * F_() : just information
62 * FM() : macro for FN_xxx / xxx_MARK
63 */
64
65/* GPSR0 */
66#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
67#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
68#define GPSR0_16 F_(MSIOF2_TXD, IP2SR0_3_0)
69#define GPSR0_15 F_(MSIOF2_SYNC, IP1SR0_31_28)
70#define GPSR0_14 F_(MSIOF2_SS1, IP1SR0_27_24)
71#define GPSR0_13 F_(MSIOF2_SS2, IP1SR0_23_20)
72#define GPSR0_12 F_(MSIOF5_RXD, IP1SR0_19_16)
73#define GPSR0_11 F_(MSIOF5_SCK, IP1SR0_15_12)
74#define GPSR0_10 F_(MSIOF5_TXD, IP1SR0_11_8)
75#define GPSR0_9 F_(MSIOF5_SYNC, IP1SR0_7_4)
76#define GPSR0_8 F_(MSIOF5_SS1, IP1SR0_3_0)
77#define GPSR0_7 F_(MSIOF5_SS2, IP0SR0_31_28)
78#define GPSR0_6 F_(IRQ0, IP0SR0_27_24)
79#define GPSR0_5 F_(IRQ1, IP0SR0_23_20)
80#define GPSR0_4 F_(IRQ2, IP0SR0_19_16)
81#define GPSR0_3 F_(IRQ3, IP0SR0_15_12)
82#define GPSR0_2 F_(GP0_02, IP0SR0_11_8)
83#define GPSR0_1 F_(GP0_01, IP0SR0_7_4)
84#define GPSR0_0 F_(GP0_00, IP0SR0_3_0)
85
86/* GPSR1 */
87#define GPSR1_29 F_(ERROROUTC_N_A, IP3SR1_23_20)
88#define GPSR1_28 F_(HTX3, IP3SR1_19_16)
89#define GPSR1_27 F_(HCTS3_N, IP3SR1_15_12)
90#define GPSR1_26 F_(HRTS3_N, IP3SR1_11_8)
91#define GPSR1_25 F_(HSCK3, IP3SR1_7_4)
92#define GPSR1_24 F_(HRX3, IP3SR1_3_0)
93#define GPSR1_23 F_(GP1_23, IP2SR1_31_28)
94#define GPSR1_22 F_(AUDIO_CLKIN, IP2SR1_27_24)
95#define GPSR1_21 F_(AUDIO_CLKOUT, IP2SR1_23_20)
96#define GPSR1_20 F_(SSI_SD, IP2SR1_19_16)
97#define GPSR1_19 F_(SSI_WS, IP2SR1_15_12)
98#define GPSR1_18 F_(SSI_SCK, IP2SR1_11_8)
99#define GPSR1_17 F_(SCIF_CLK, IP2SR1_7_4)
100#define GPSR1_16 F_(HRX0, IP2SR1_3_0)
101#define GPSR1_15 F_(HSCK0, IP1SR1_31_28)
102#define GPSR1_14 F_(HRTS0_N, IP1SR1_27_24)
103#define GPSR1_13 F_(HCTS0_N, IP1SR1_23_20)
104#define GPSR1_12 F_(HTX0, IP1SR1_19_16)
105#define GPSR1_11 F_(MSIOF0_RXD, IP1SR1_15_12)
106#define GPSR1_10 F_(MSIOF0_SCK, IP1SR1_11_8)
107#define GPSR1_9 F_(MSIOF0_TXD, IP1SR1_7_4)
108#define GPSR1_8 F_(MSIOF0_SYNC, IP1SR1_3_0)
109#define GPSR1_7 F_(MSIOF0_SS1, IP0SR1_31_28)
110#define GPSR1_6 F_(MSIOF0_SS2, IP0SR1_27_24)
111#define GPSR1_5 F_(MSIOF1_RXD, IP0SR1_23_20)
112#define GPSR1_4 F_(MSIOF1_TXD, IP0SR1_19_16)
113#define GPSR1_3 F_(MSIOF1_SCK, IP0SR1_15_12)
114#define GPSR1_2 F_(MSIOF1_SYNC, IP0SR1_11_8)
115#define GPSR1_1 F_(MSIOF1_SS1, IP0SR1_7_4)
116#define GPSR1_0 F_(MSIOF1_SS2, IP0SR1_3_0)
117
118/* GPSR2 */
119#define GPSR2_19 F_(CANFD1_RX, IP2SR2_15_12)
120#define GPSR2_17 F_(CANFD1_TX, IP2SR2_7_4)
121#define GPSR2_15 F_(CANFD3_RX, IP1SR2_31_28)
122#define GPSR2_14 F_(CANFD3_TX, IP1SR2_27_24)
123#define GPSR2_13 F_(CANFD2_RX, IP1SR2_23_20)
124#define GPSR2_12 F_(CANFD2_TX, IP1SR2_19_16)
125#define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
126#define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
127#define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
128#define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
129#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
130#define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
131#define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)
132#define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
133#define GPSR2_3 F_(CLK_EXTFXR, IP0SR2_15_12)
134#define GPSR2_2 F_(RXDA_EXTFXR, IP0SR2_11_8)
135#define GPSR2_1 F_(FXR_TXENA_N_A, IP0SR2_7_4)
136#define GPSR2_0 F_(FXR_TXDA, IP0SR2_3_0)
137
138/* GPSR3 */
139#define GPSR3_31 F_(TCLK4, IP3SR3_31_28)
140#define GPSR3_30 F_(TCLK3, IP3SR3_27_24)
141#define GPSR3_29 F_(RPC_INT_N, IP3SR3_23_20)
142#define GPSR3_28 F_(RPC_WP_N, IP3SR3_19_16)
143#define GPSR3_27 F_(RPC_RESET_N, IP3SR3_15_12)
144#define GPSR3_26 F_(QSPI1_IO3, IP3SR3_11_8)
145#define GPSR3_25 F_(QSPI1_SSL, IP3SR3_7_4)
146#define GPSR3_24 F_(QSPI1_IO2, IP3SR3_3_0)
147#define GPSR3_23 F_(QSPI1_MISO_IO1, IP2SR3_31_28)
148#define GPSR3_22 F_(QSPI1_SPCLK, IP2SR3_27_24)
149#define GPSR3_21 F_(QSPI1_MOSI_IO0, IP2SR3_23_20)
150#define GPSR3_20 F_(QSPI0_SPCLK, IP2SR3_19_16)
151#define GPSR3_19 F_(QSPI0_MOSI_IO0, IP2SR3_15_12)
152#define GPSR3_18 F_(QSPI0_MISO_IO1, IP2SR3_11_8)
153#define GPSR3_17 F_(QSPI0_IO2, IP2SR3_7_4)
154#define GPSR3_16 F_(QSPI0_IO3, IP2SR3_3_0)
155#define GPSR3_15 F_(QSPI0_SSL, IP1SR3_31_28)
156#define GPSR3_14 F_(PWM2, IP1SR3_27_24)
157#define GPSR3_13 F_(PWM1, IP1SR3_23_20)
158#define GPSR3_12 F_(SD_WP, IP1SR3_19_16)
159#define GPSR3_11 F_(SD_CD, IP1SR3_15_12)
160#define GPSR3_10 F_(MMC_SD_CMD, IP1SR3_11_8)
161#define GPSR3_9 F_(MMC_D6, IP1SR3_7_4)
162#define GPSR3_8 F_(MMC_D7, IP1SR3_3_0)
163#define GPSR3_7 F_(MMC_D4, IP0SR3_31_28)
164#define GPSR3_6 F_(MMC_D5, IP0SR3_27_24)
165#define GPSR3_5 F_(MMC_SD_D3, IP0SR3_23_20)
166#define GPSR3_4 F_(MMC_DS, IP0SR3_19_16)
167#define GPSR3_3 F_(MMC_SD_CLK, IP0SR3_15_12)
168#define GPSR3_2 F_(MMC_SD_D2, IP0SR3_11_8)
169#define GPSR3_1 F_(MMC_SD_D0, IP0SR3_7_4)
170#define GPSR3_0 F_(MMC_SD_D1, IP0SR3_3_0)
171
172/* GPSR4 */
173#define GPSR4_24 F_(AVS1, IP3SR4_3_0)
174#define GPSR4_23 F_(AVS0, IP2SR4_31_28)
175#define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20)
176#define GPSR4_15 F_(PWM4, IP1SR4_31_28)
177#define GPSR4_14 F_(PWM3, IP1SR4_27_24)
178#define GPSR4_13 F_(HSCK2, IP1SR4_23_20)
179#define GPSR4_12 F_(HCTS2_N, IP1SR4_19_16)
180#define GPSR4_11 F_(SCIF_CLK2, IP1SR4_15_12)
181#define GPSR4_10 F_(HRTS2_N, IP1SR4_11_8)
182#define GPSR4_9 F_(HTX2, IP1SR4_7_4)
183#define GPSR4_8 F_(HRX2, IP1SR4_3_0)
184#define GPSR4_7 F_(SDA3, IP0SR4_31_28)
185#define GPSR4_6 F_(SCL3, IP0SR4_27_24)
186#define GPSR4_5 F_(SDA2, IP0SR4_23_20)
187#define GPSR4_4 F_(SCL2, IP0SR4_19_16)
188#define GPSR4_3 F_(SDA1, IP0SR4_15_12)
189#define GPSR4_2 F_(SCL1, IP0SR4_11_8)
190#define GPSR4_1 F_(SDA0, IP0SR4_7_4)
191#define GPSR4_0 F_(SCL0, IP0SR4_3_0)
192
193/* GPSR 5 */
194#define GPSR5_20 F_(AVB2_RX_CTL, IP2SR5_19_16)
195#define GPSR5_19 F_(AVB2_TX_CTL, IP2SR5_15_12)
196#define GPSR5_18 F_(AVB2_RXC, IP2SR5_11_8)
197#define GPSR5_17 F_(AVB2_RD0, IP2SR5_7_4)
198#define GPSR5_16 F_(AVB2_TXC, IP2SR5_3_0)
199#define GPSR5_15 F_(AVB2_TD0, IP1SR5_31_28)
200#define GPSR5_14 F_(AVB2_RD1, IP1SR5_27_24)
201#define GPSR5_13 F_(AVB2_RD2, IP1SR5_23_20)
202#define GPSR5_12 F_(AVB2_TD1, IP1SR5_19_16)
203#define GPSR5_11 F_(AVB2_TD2, IP1SR5_15_12)
204#define GPSR5_10 F_(AVB2_MDIO, IP1SR5_11_8)
205#define GPSR5_9 F_(AVB2_RD3, IP1SR5_7_4)
206#define GPSR5_8 F_(AVB2_TD3, IP1SR5_3_0)
207#define GPSR5_7 F_(AVB2_TXCREFCLK, IP0SR5_31_28)
208#define GPSR5_6 F_(AVB2_MDC, IP0SR5_27_24)
209#define GPSR5_5 F_(AVB2_MAGIC, IP0SR5_23_20)
210#define GPSR5_4 F_(AVB2_PHY_INT, IP0SR5_19_16)
211#define GPSR5_3 F_(AVB2_LINK, IP0SR5_15_12)
212#define GPSR5_2 F_(AVB2_AVTP_MATCH, IP0SR5_11_8)
213#define GPSR5_1 F_(AVB2_AVTP_CAPTURE, IP0SR5_7_4)
214#define GPSR5_0 F_(AVB2_AVTP_PPS, IP0SR5_3_0)
215
216/* GPSR 6 */
217#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
218#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
219#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
220#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
221#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
222#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
223#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
224#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
225#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
226#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
227#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
228#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
229#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
230#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
231#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
232#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
233#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
234#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
235#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
236#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
237#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
238
239/* GPSR7 */
240#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
241#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
242#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
243#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
244#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
245#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
246#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
247#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
248#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
249#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
250#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
251#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
252#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
253#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
254#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
255#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
256#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
257#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
258#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
259#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
260#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
261
262
263/* SR0 */
264/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
265#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_N_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP0SR0_19_16 FM(IRQ2) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP0SR0_23_20 FM(IRQ1) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP0SR0_27_24 FM(IRQ0) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP0SR0_31_28 FM(MSIOF5_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273
274/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
275#define IP1SR0_3_0 FM(MSIOF5_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP1SR0_7_4 FM(MSIOF5_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1_A) FM(IRQ2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1_A) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1_A) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283
284/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
285#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N_A) FM(CTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N_A) FM(RTS1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1_A) FM(SCK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288
289/* SR1 */
290/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
291#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_B) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_N_B) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_N_B) FM(RTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_B) FM(CTS3_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_B) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299
300/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
301#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_B) FM(CTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_B) FM(RTS1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309
310/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
311#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP2SR1_31_28 F_(0, 0) FM(TCLK2_A) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319
320/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
321#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP3SR1_23_20 FM(ERROROUTC_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327
328/* SR2 */
329/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
330#define IP0SR2_3_0 FM(FXR_TXDA) F_(0, 0) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP0SR2_7_4 FM(FXR_TXENA_N_A) F_(0, 0) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP0SR2_11_8 FM(RXDA_EXTFXR) F_(0, 0) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP0SR2_15_12 FM(CLK_EXTFXR) F_(0, 0) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP0SR2_31_28 FM(TPU0TO1_A) F_(0, 0) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338
339/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
340#define IP1SR2_3_0 FM(TPU0TO0_A) F_(0, 0) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348
349/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
350#define IP2SR2_7_4 FM(CANFD1_TX) F_(0, 0) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP2SR2_15_12 FM(CANFD1_RX) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352
353/* SR3 */
354/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
355#define IP0SR3_3_0 FM(MMC_SD_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP0SR3_7_4 FM(MMC_SD_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP0SR3_11_8 FM(MMC_SD_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP0SR3_15_12 FM(MMC_SD_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP0SR3_19_16 FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP0SR3_23_20 FM(MMC_SD_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP0SR3_27_24 FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP0SR3_31_28 FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363
364/* IP1SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
365#define IP1SR3_3_0 FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP1SR3_7_4 FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP1SR3_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP1SR3_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373
374/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
375#define IP2SR3_3_0 FM(QSPI0_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP2SR3_7_4 FM(QSPI0_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377#define IP2SR3_11_8 FM(QSPI0_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP2SR3_15_12 FM(QSPI0_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379#define IP2SR3_19_16 FM(QSPI0_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380#define IP2SR3_23_20 FM(QSPI1_MOSI_IO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP2SR3_27_24 FM(QSPI1_SPCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP2SR3_31_28 FM(QSPI1_MISO_IO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383
384/* IP3SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
385#define IP3SR3_3_0 FM(QSPI1_IO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386#define IP3SR3_7_4 FM(QSPI1_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387#define IP3SR3_11_8 FM(QSPI1_IO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP3SR3_27_24 FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP3SR3_31_28 FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393
394/* SR4 */
395/* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
396#define IP0SR4_3_0 FM(SCL0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP0SR4_7_4 FM(SDA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP0SR4_11_8 FM(SCL1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP0SR4_15_12 FM(SDA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP0SR4_19_16 FM(SCL2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP0SR4_23_20 FM(SDA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402#define IP0SR4_27_24 FM(SCL3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403#define IP0SR4_31_28 FM(SDA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404
405/* IP1SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
406#define IP1SR4_3_0 FM(HRX2) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407#define IP1SR4_7_4 FM(HTX2) FM(CTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
408#define IP1SR4_11_8 FM(HRTS2_N) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409#define IP1SR4_15_12 FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410#define IP1SR4_19_16 FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411#define IP1SR4_23_20 FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
412#define IP1SR4_27_24 FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413#define IP1SR4_31_28 FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414
415/* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
416#define IP2SR4_23_20 FM(PCIE0_CLKREQ_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
417#define IP2SR4_31_28 FM(AVS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
418
419/* IP3SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
420#define IP3SR4_3_0 FM(AVS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
421
422/* SR5 */
423/* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
424#define IP0SR5_3_0 FM(AVB2_AVTP_PPS) FM(Ether_GPTP_PPS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425#define IP0SR5_7_4 FM(AVB2_AVTP_CAPTURE) FM(Ether_GPTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
426#define IP0SR5_11_8 FM(AVB2_AVTP_MATCH) FM(Ether_GPTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
427#define IP0SR5_15_12 FM(AVB2_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
428#define IP0SR5_19_16 FM(AVB2_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429#define IP0SR5_23_20 FM(AVB2_MAGIC) FM(Ether_GPTP_PPS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
430#define IP0SR5_27_24 FM(AVB2_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431#define IP0SR5_31_28 FM(AVB2_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
432
433/* IP1SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
434#define IP1SR5_3_0 FM(AVB2_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
435#define IP1SR5_7_4 FM(AVB2_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
436#define IP1SR5_11_8 FM(AVB2_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
437#define IP1SR5_15_12 FM(AVB2_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
438#define IP1SR5_19_16 FM(AVB2_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
439#define IP1SR5_23_20 FM(AVB2_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
440#define IP1SR5_27_24 FM(AVB2_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
441#define IP1SR5_31_28 FM(AVB2_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
442
443/* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
444#define IP2SR5_3_0 FM(AVB2_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
445#define IP2SR5_7_4 FM(AVB2_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
446#define IP2SR5_11_8 FM(AVB2_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447#define IP2SR5_15_12 FM(AVB2_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448#define IP2SR5_19_16 FM(AVB2_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449
450/* SR6 */
451/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
452#define IP0SR6_3_0 FM(AVB1_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453#define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
454#define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
455#define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
456#define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
457#define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
458#define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
459#define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
460
461/* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
462#define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463#define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464#define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465#define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466#define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
467#define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
468#define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
469#define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
470
471/* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
472#define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473#define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
474#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
475#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
476#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
477
478/* SR7 */
479/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
480#define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
481#define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
482#define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
483#define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
484#define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
485#define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
486#define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
487#define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
488
489/* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
490#define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
491#define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
492#define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
493#define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
494#define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
495#define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
496#define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
497#define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
498
499/* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
500#define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
501#define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
502#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
504#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
505
506#define PINMUX_GPSR \
507 GPSR3_31 \
508 GPSR3_30 \
509 GPSR1_29 GPSR3_29 \
510 GPSR1_28 GPSR3_28 \
511 GPSR1_27 GPSR3_27 \
512 GPSR1_26 GPSR3_26 \
513 GPSR1_25 GPSR3_25 \
514 GPSR1_24 GPSR3_24 GPSR4_24 \
515 GPSR1_23 GPSR3_23 GPSR4_23 \
516 GPSR1_22 GPSR3_22 \
517 GPSR1_21 GPSR3_21 GPSR4_21 \
518 GPSR1_20 GPSR3_20 GPSR5_20 GPSR6_20 GPSR7_20 \
519 GPSR1_19 GPSR2_19 GPSR3_19 GPSR5_19 GPSR6_19 GPSR7_19 \
520GPSR0_18 GPSR1_18 GPSR3_18 GPSR5_18 GPSR6_18 GPSR7_18 \
521GPSR0_17 GPSR1_17 GPSR2_17 GPSR3_17 GPSR5_17 GPSR6_17 GPSR7_17 \
522GPSR0_16 GPSR1_16 GPSR3_16 GPSR5_16 GPSR6_16 GPSR7_16 \
523GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 GPSR7_15 \
524GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 GPSR7_14 \
525GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 GPSR7_13 \
526GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 GPSR7_12 \
527GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 GPSR7_11 \
528GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 GPSR7_10 \
529GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 GPSR7_9 \
530GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 GPSR7_8 \
531GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 GPSR7_7 \
532GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 GPSR7_6 \
533GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 GPSR7_5 \
534GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 GPSR7_4 \
535GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
536GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
537GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
538GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
539
540#define PINMUX_IPSR \
541\
542FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
543FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
544FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
545FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \
546FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \
547FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
548FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
549FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
550\
551FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
552FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
553FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
554FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
555FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
556FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
557FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \
558FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
559\
560FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 \
561FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
562FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 \
563FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
564FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \
565FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \
566FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \
567FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \
568\
569FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \
570FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \
571FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR3_11_8 FM(IP3SR3_11_8) IP3SR3_11_8 \
572FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \
573FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \
574FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \
575FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 FM(IP3SR3_27_24) IP3SR3_27_24 \
576FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 FM(IP3SR3_31_28) IP3SR3_31_28 \
577\
578FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP3SR4_3_0) IP3SR4_3_0 \
579FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 \
580FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 \
581FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 \
582FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 \
583FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \
584FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \
585FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \
586\
587FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \
588FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \
589FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \
590FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \
591FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \
592FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \
593FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \
594FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 \
595\
596FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \
597FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \
598FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \
599FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \
600FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \
601FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \
602FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \
603FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \
604\
605FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \
606FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \
607FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \
608FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \
609FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \
610FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \
611FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \
612FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \
613
614/* MOD_SEL4 */ /* 0 */ /* 1 */
615#define MOD_SEL4_7 FM(SEL_SDA3_0) FM(SEL_SDA3_1)
616#define MOD_SEL4_6 FM(SEL_SCL3_0) FM(SEL_SCL3_1)
617#define MOD_SEL4_5 FM(SEL_SDA2_0) FM(SEL_SDA2_1)
618#define MOD_SEL4_4 FM(SEL_SCL2_0) FM(SEL_SCL2_1)
619#define MOD_SEL4_3 FM(SEL_SDA1_0) FM(SEL_SDA1_1)
620#define MOD_SEL4_2 FM(SEL_SCL1_0) FM(SEL_SCL1_1)
621#define MOD_SEL4_1 FM(SEL_SDA0_0) FM(SEL_SDA0_1)
622#define MOD_SEL4_0 FM(SEL_SCL0_0) FM(SEL_SCL0_1)
623
624#define PINMUX_MOD_SELS \
625\
626MOD_SEL4_7 \
627MOD_SEL4_6 \
628MOD_SEL4_5 \
629MOD_SEL4_4 \
630MOD_SEL4_3 \
631MOD_SEL4_2 \
632MOD_SEL4_1 \
633MOD_SEL4_0
634
635enum {
636 PINMUX_RESERVED = 0,
637
638 PINMUX_DATA_BEGIN,
639 GP_ALL(DATA),
640 PINMUX_DATA_END,
641
642#define F_(x, y)
643#define FM(x) FN_##x,
644 PINMUX_FUNCTION_BEGIN,
645 GP_ALL(FN),
646 PINMUX_GPSR
647 PINMUX_IPSR
648 PINMUX_MOD_SELS
649 PINMUX_FUNCTION_END,
650#undef F_
651#undef FM
652
653#define F_(x, y)
654#define FM(x) x##_MARK,
655 PINMUX_MARK_BEGIN,
656 PINMUX_GPSR
657 PINMUX_IPSR
658 PINMUX_MOD_SELS
659 PINMUX_MARK_END,
660#undef F_
661#undef FM
662};
663
664static const u16 pinmux_data[] = {
665 PINMUX_DATA_GP_ALL(),
666
667 /* IP0SR0 */
668 PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_N_B),
669 PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_B),
670
671 PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
672
673 PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_SS2),
674
675 PINMUX_IPSR_GPSR(IP0SR0_15_12, IRQ3),
676 PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_SCK),
677
678 PINMUX_IPSR_GPSR(IP0SR0_19_16, IRQ2),
679 PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_TXD),
680
681 PINMUX_IPSR_GPSR(IP0SR0_23_20, IRQ1),
682 PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_RXD),
683
684 PINMUX_IPSR_GPSR(IP0SR0_27_24, IRQ0),
685 PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF3_SYNC),
686
687 PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF5_SS2),
688
689 /* IP1SR0 */
690 PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF5_SS1),
691
692 PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF5_SYNC),
693
694 PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF5_TXD),
695
696 PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF5_SCK),
697
698 PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF5_RXD),
699
700 PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
701 PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1_A),
702 PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_B),
703
704 PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
705 PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1_A),
706 PINMUX_IPSR_GPSR(IP1SR0_27_24, TX1_A),
707
708 PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF2_SYNC),
709 PINMUX_IPSR_GPSR(IP1SR0_31_28, HRX1_A),
710 PINMUX_IPSR_GPSR(IP1SR0_31_28, RX1_A),
711
712 /* IP2SR0 */
713 PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF2_TXD),
714 PINMUX_IPSR_GPSR(IP2SR0_3_0, HCTS1_N_A),
715 PINMUX_IPSR_GPSR(IP2SR0_3_0, CTS1_N_A),
716
717 PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF2_SCK),
718 PINMUX_IPSR_GPSR(IP2SR0_7_4, HRTS1_N_A),
719 PINMUX_IPSR_GPSR(IP2SR0_7_4, RTS1_N_A),
720
721 PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF2_RXD),
722 PINMUX_IPSR_GPSR(IP2SR0_11_8, HSCK1_A),
723 PINMUX_IPSR_GPSR(IP2SR0_11_8, SCK1_A),
724
725 /* IP0SR1 */
726 PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
727 PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_B),
728 PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3_B),
729
730 PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
731 PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_N_B),
732 PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3_B),
733
734 PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
735 PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_N_B),
736 PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N_B),
737
738 PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
739 PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_B),
740 PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N_B),
741
742 PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
743 PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_B),
744 PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3_B),
745
746 PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
747
748 PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
749 PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_B),
750 PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_B),
751
752 PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
753 PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_B),
754 PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_B),
755
756 /* IP1SR1 */
757 PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
758 PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_B),
759 PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_N_B),
760
761 PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
762 PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_B),
763 PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_N_B),
764
765 PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
766 PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_B),
767 PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_B),
768
769 PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
770
771 PINMUX_IPSR_GPSR(IP1SR1_19_16, HTX0),
772 PINMUX_IPSR_GPSR(IP1SR1_19_16, TX0),
773
774 PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
775 PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
776
777 PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
778 PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
779 PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM0_B),
780
781 PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
782 PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
783 PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),
784
785 /* IP2SR1 */
786 PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
787 PINMUX_IPSR_GPSR(IP2SR1_3_0, RX0),
788
789 PINMUX_IPSR_GPSR(IP2SR1_7_4, SCIF_CLK),
790 PINMUX_IPSR_GPSR(IP2SR1_7_4, IRQ4_A),
791
792 PINMUX_IPSR_GPSR(IP2SR1_11_8, SSI_SCK),
793 PINMUX_IPSR_GPSR(IP2SR1_11_8, TCLK3_B),
794
795 PINMUX_IPSR_GPSR(IP2SR1_15_12, SSI_WS),
796 PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4_B),
797
798 PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
799 PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_B),
800
801 PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
802 PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_B),
803
804 PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
805 PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_C),
806
807 PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2_A),
808 PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
809 PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
810
811 /* IP3SR1 */
812 PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3_A),
813 PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
814 PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
815
816 PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),
817 PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
818 PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
819 PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B),
820
821 PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),
822 PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
823 PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
824 PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B),
825
826 PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),
827 PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
828 PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
829
830 PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3_A),
831 PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
832 PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
833
834 PINMUX_IPSR_GPSR(IP3SR1_23_20, ERROROUTC_N_A),
835
836 /* IP0SR2 */
837 PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
838 PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B),
839
840 PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A),
841 PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B),
842
843 PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
844 PINMUX_IPSR_GPSR(IP0SR2_11_8, IRQ5),
845
846 PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
847 PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),
848
849 PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
850
851 PINMUX_IPSR_GPSR(IP0SR2_23_20, FXR_TXENB_N_A),
852
853 PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
854
855 PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),
856 PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),
857
858 /* IP1SR2 */
859 PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A),
860 PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B),
861
862 PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
863 PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_N_B),
864
865 PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
866 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B),
867
868 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
869 PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
870
871 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
872 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),
873 PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C),
874
875 PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
876 PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A),
877 PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
878 PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C),
879
880 PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
881 PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),
882
883 PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
884 PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
885
886 /* IP2SR2 */
887 PINMUX_IPSR_GPSR(IP2SR2_7_4, CANFD1_TX),
888 PINMUX_IPSR_GPSR(IP2SR2_7_4, PWM1_C),
889
890 PINMUX_IPSR_GPSR(IP2SR2_15_12, CANFD1_RX),
891 PINMUX_IPSR_GPSR(IP2SR2_15_12, PWM2_C),
892
893 /* IP0SR3 */
894 PINMUX_IPSR_GPSR(IP0SR3_3_0, MMC_SD_D1),
895
896 PINMUX_IPSR_GPSR(IP0SR3_7_4, MMC_SD_D0),
897
898 PINMUX_IPSR_GPSR(IP0SR3_11_8, MMC_SD_D2),
899
900 PINMUX_IPSR_GPSR(IP0SR3_15_12, MMC_SD_CLK),
901
902 PINMUX_IPSR_GPSR(IP0SR3_19_16, MMC_DS),
903
904 PINMUX_IPSR_GPSR(IP0SR3_23_20, MMC_SD_D3),
905
906 PINMUX_IPSR_GPSR(IP0SR3_27_24, MMC_D5),
907
908 PINMUX_IPSR_GPSR(IP0SR3_31_28, MMC_D4),
909
910 /* IP1SR3 */
911 PINMUX_IPSR_GPSR(IP1SR3_3_0, MMC_D7),
912
913 PINMUX_IPSR_GPSR(IP1SR3_7_4, MMC_D6),
914
915 PINMUX_IPSR_GPSR(IP1SR3_11_8, MMC_SD_CMD),
916
917 PINMUX_IPSR_GPSR(IP1SR3_15_12, SD_CD),
918
919 PINMUX_IPSR_GPSR(IP1SR3_19_16, SD_WP),
920
921 PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),
922
923 PINMUX_IPSR_GPSR(IP1SR3_27_24, PWM2_A),
924
925 PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
926
927 /* IP2SR3 */
928 PINMUX_IPSR_GPSR(IP2SR3_3_0, QSPI0_IO3),
929
930 PINMUX_IPSR_GPSR(IP2SR3_7_4, QSPI0_IO2),
931
932 PINMUX_IPSR_GPSR(IP2SR3_11_8, QSPI0_MISO_IO1),
933
934 PINMUX_IPSR_GPSR(IP2SR3_15_12, QSPI0_MOSI_IO0),
935
936 PINMUX_IPSR_GPSR(IP2SR3_19_16, QSPI0_SPCLK),
937
938 PINMUX_IPSR_GPSR(IP2SR3_23_20, QSPI1_MOSI_IO0),
939
940 PINMUX_IPSR_GPSR(IP2SR3_27_24, QSPI1_SPCLK),
941
942 PINMUX_IPSR_GPSR(IP2SR3_31_28, QSPI1_MISO_IO1),
943
944 /* IP3SR3 */
945 PINMUX_IPSR_GPSR(IP3SR3_3_0, QSPI1_IO2),
946
947 PINMUX_IPSR_GPSR(IP3SR3_7_4, QSPI1_SSL),
948
949 PINMUX_IPSR_GPSR(IP3SR3_11_8, QSPI1_IO3),
950
951 PINMUX_IPSR_GPSR(IP3SR3_15_12, RPC_RESET_N),
952
953 PINMUX_IPSR_GPSR(IP3SR3_19_16, RPC_WP_N),
954
955 PINMUX_IPSR_GPSR(IP3SR3_23_20, RPC_INT_N),
956
957 PINMUX_IPSR_GPSR(IP3SR3_27_24, TCLK3_A),
958
959 PINMUX_IPSR_GPSR(IP3SR3_31_28, TCLK4_A),
960
961 /* IP0SR4 */
962 PINMUX_IPSR_MSEL(IP0SR4_3_0, SCL0, SEL_SCL0_0),
963
964 PINMUX_IPSR_MSEL(IP0SR4_7_4, SDA0, SEL_SDA0_0),
965
966 PINMUX_IPSR_MSEL(IP0SR4_11_8, SCL1, SEL_SCL1_0),
967
968 PINMUX_IPSR_MSEL(IP0SR4_15_12, SDA1, SEL_SDA1_0),
969
970 PINMUX_IPSR_MSEL(IP0SR4_19_16, SCL2, SEL_SCL2_0),
971
972 PINMUX_IPSR_MSEL(IP0SR4_23_20, SDA2, SEL_SDA2_0),
973
974 PINMUX_IPSR_MSEL(IP0SR4_27_24, SCL3, SEL_SCL3_0),
975
976 PINMUX_IPSR_MSEL(IP0SR4_31_28, SDA3, SEL_SDA3_0),
977
978 /* IP1SR4 */
979 PINMUX_IPSR_GPSR(IP1SR4_3_0, HRX2),
980 PINMUX_IPSR_GPSR(IP1SR4_3_0, SCK4),
981
982 PINMUX_IPSR_GPSR(IP1SR4_7_4, HTX2),
983 PINMUX_IPSR_GPSR(IP1SR4_7_4, CTS4_N),
984
985 PINMUX_IPSR_GPSR(IP1SR4_11_8, HRTS2_N),
986 PINMUX_IPSR_GPSR(IP1SR4_11_8, RTS4_N),
987
988 PINMUX_IPSR_GPSR(IP1SR4_15_12, SCIF_CLK2),
989
990 PINMUX_IPSR_GPSR(IP1SR4_19_16, HCTS2_N),
991 PINMUX_IPSR_GPSR(IP1SR4_19_16, TX4),
992
993 PINMUX_IPSR_GPSR(IP1SR4_23_20, HSCK2),
994 PINMUX_IPSR_GPSR(IP1SR4_23_20, RX4),
995
996 PINMUX_IPSR_GPSR(IP1SR4_27_24, PWM3_A),
997
998 PINMUX_IPSR_GPSR(IP1SR4_31_28, PWM4),
999
1000 /* IP2SR4 */
1001 PINMUX_IPSR_GPSR(IP2SR4_23_20, PCIE0_CLKREQ_N),
1002
1003 PINMUX_IPSR_GPSR(IP2SR4_31_28, AVS0),
1004
1005 /* IP3SR4 */
1006 PINMUX_IPSR_GPSR(IP3SR4_3_0, AVS1),
1007
1008 /* IP0SR5 */
1009 PINMUX_IPSR_GPSR(IP0SR5_3_0, AVB2_AVTP_PPS),
1010 PINMUX_IPSR_GPSR(IP0SR5_3_0, Ether_GPTP_PPS0),
1011
1012 PINMUX_IPSR_GPSR(IP0SR5_7_4, AVB2_AVTP_CAPTURE),
1013 PINMUX_IPSR_GPSR(IP0SR5_7_4, Ether_GPTP_CAPTURE),
1014
1015 PINMUX_IPSR_GPSR(IP0SR5_11_8, AVB2_AVTP_MATCH),
1016 PINMUX_IPSR_GPSR(IP0SR5_11_8, Ether_GPTP_MATCH),
1017
1018 PINMUX_IPSR_GPSR(IP0SR5_15_12, AVB2_LINK),
1019
1020 PINMUX_IPSR_GPSR(IP0SR5_19_16, AVB2_PHY_INT),
1021
1022 PINMUX_IPSR_GPSR(IP0SR5_23_20, AVB2_MAGIC),
1023 PINMUX_IPSR_GPSR(IP0SR5_23_20, Ether_GPTP_PPS1),
1024
1025 PINMUX_IPSR_GPSR(IP0SR5_27_24, AVB2_MDC),
1026
1027 PINMUX_IPSR_GPSR(IP0SR5_31_28, AVB2_TXCREFCLK),
1028
1029 /* IP1SR5 */
1030 PINMUX_IPSR_GPSR(IP1SR5_3_0, AVB2_TD3),
1031
1032 PINMUX_IPSR_GPSR(IP1SR5_7_4, AVB2_RD3),
1033
1034 PINMUX_IPSR_GPSR(IP1SR5_11_8, AVB2_MDIO),
1035
1036 PINMUX_IPSR_GPSR(IP1SR5_15_12, AVB2_TD2),
1037
1038 PINMUX_IPSR_GPSR(IP1SR5_19_16, AVB2_TD1),
1039
1040 PINMUX_IPSR_GPSR(IP1SR5_23_20, AVB2_RD2),
1041
1042 PINMUX_IPSR_GPSR(IP1SR5_27_24, AVB2_RD1),
1043
1044 PINMUX_IPSR_GPSR(IP1SR5_31_28, AVB2_TD0),
1045
1046 /* IP2SR5 */
1047 PINMUX_IPSR_GPSR(IP2SR5_3_0, AVB2_TXC),
1048
1049 PINMUX_IPSR_GPSR(IP2SR5_7_4, AVB2_RD0),
1050
1051 PINMUX_IPSR_GPSR(IP2SR5_11_8, AVB2_RXC),
1052
1053 PINMUX_IPSR_GPSR(IP2SR5_15_12, AVB2_TX_CTL),
1054
1055 PINMUX_IPSR_GPSR(IP2SR5_19_16, AVB2_RX_CTL),
1056
1057 /* IP0SR6 */
1058 PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
1059
1060 PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
1061
1062 PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
1063
1064 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
1065
1066 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
1067 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
1068
1069 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
1070 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
1071
1072 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
1073 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
1074
1075 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
1076 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
1077
1078 /* IP1SR6 */
1079 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
1080 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC),
1081
1082 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
1083 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
1084
1085 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
1086 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
1087
1088 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
1089 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
1090
1091 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
1092 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
1093
1094 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
1095 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
1096
1097 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
1098 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
1099
1100 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0),
1101 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
1102
1103 /* IP2SR6 */
1104 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
1105 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
1106
1107 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
1108 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
1109
1110 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
1111 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
1112
1113 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
1114 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
1115
1116 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
1117
1118 /* IP0SR7 */
1119 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),
1120 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),
1121
1122 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
1123 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
1124
1125 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
1126 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
1127 PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
1128
1129 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
1130 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
1131
1132 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
1133 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
1134
1135 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
1136
1137 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),
1138 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),
1139
1140 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),
1141 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),
1142
1143 /* IP1SR7 */
1144 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
1145 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),
1146
1147 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
1148
1149 PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),
1150
1151 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),
1152 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),
1153
1154 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
1155 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
1156
1157 PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),
1158
1159 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
1160
1161 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),
1162 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),
1163
1164 /* IP2SR7 */
1165 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),
1166 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),
1167
1168 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
1169 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
1170
1171 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0),
1172 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0),
1173
1174 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC),
1175 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC),
1176
1177 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL),
1178 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV),
1179};
1180
1181/*
1182 * Pins not associated with a GPIO port.
1183 */
1184enum {
1185 GP_ASSIGN_LAST(),
1186 NOGP_ALL(),
1187};
1188
1189static const struct sh_pfc_pin pinmux_pins[] = {
1190 PINMUX_GPIO_GP_ALL(),
1191 PINMUX_NOGP_ALL(),
1192};
1193
1194/* - AUDIO CLOCK ----------------------------------------- */
1195static const unsigned int audio_clkin_pins[] = {
1196 /* CLK IN */
1197 RCAR_GP_PIN(1, 22),
1198};
1199static const unsigned int audio_clkin_mux[] = {
1200 AUDIO_CLKIN_MARK,
1201};
1202static const unsigned int audio_clkout_pins[] = {
1203 /* CLK OUT */
1204 RCAR_GP_PIN(1, 21),
1205};
1206static const unsigned int audio_clkout_mux[] = {
1207 AUDIO_CLKOUT_MARK,
1208};
1209
1210/* - AVB0 ------------------------------------------------ */
1211static const unsigned int avb0_link_pins[] = {
1212 /* AVB0_LINK */
1213 RCAR_GP_PIN(7, 4),
1214};
1215static const unsigned int avb0_link_mux[] = {
1216 AVB0_LINK_MARK,
1217};
1218static const unsigned int avb0_magic_pins[] = {
1219 /* AVB0_MAGIC */
1220 RCAR_GP_PIN(7, 10),
1221};
1222static const unsigned int avb0_magic_mux[] = {
1223 AVB0_MAGIC_MARK,
1224};
1225static const unsigned int avb0_phy_int_pins[] = {
1226 /* AVB0_PHY_INT */
1227 RCAR_GP_PIN(7, 5),
1228};
1229static const unsigned int avb0_phy_int_mux[] = {
1230 AVB0_PHY_INT_MARK,
1231};
1232static const unsigned int avb0_mdio_pins[] = {
1233 /* AVB0_MDC, AVB0_MDIO */
1234 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1235};
1236static const unsigned int avb0_mdio_mux[] = {
1237 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1238};
1239static const unsigned int avb0_rgmii_pins[] = {
1240 /*
1241 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1242 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1243 */
1244 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1245 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
1246 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
1247 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1248 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1249 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
1250};
1251static const unsigned int avb0_rgmii_mux[] = {
1252 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
1253 AVB0_TD0_MARK, AVB0_TD1_MARK,
1254 AVB0_TD2_MARK, AVB0_TD3_MARK,
1255 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
1256 AVB0_RD0_MARK, AVB0_RD1_MARK,
1257 AVB0_RD2_MARK, AVB0_RD3_MARK,
1258};
1259static const unsigned int avb0_txcrefclk_pins[] = {
1260 /* AVB0_TXCREFCLK */
1261 RCAR_GP_PIN(7, 9),
1262};
1263static const unsigned int avb0_txcrefclk_mux[] = {
1264 AVB0_TXCREFCLK_MARK,
1265};
1266static const unsigned int avb0_avtp_pps_pins[] = {
1267 /* AVB0_AVTP_PPS */
1268 RCAR_GP_PIN(7, 0),
1269};
1270static const unsigned int avb0_avtp_pps_mux[] = {
1271 AVB0_AVTP_PPS_MARK,
1272};
1273static const unsigned int avb0_avtp_capture_pins[] = {
1274 /* AVB0_AVTP_CAPTURE */
1275 RCAR_GP_PIN(7, 1),
1276};
1277static const unsigned int avb0_avtp_capture_mux[] = {
1278 AVB0_AVTP_CAPTURE_MARK,
1279};
1280static const unsigned int avb0_avtp_match_pins[] = {
1281 /* AVB0_AVTP_MATCH */
1282 RCAR_GP_PIN(7, 2),
1283};
1284static const unsigned int avb0_avtp_match_mux[] = {
1285 AVB0_AVTP_MATCH_MARK,
1286};
1287
1288/* - AVB1 ------------------------------------------------ */
1289static const unsigned int avb1_link_pins[] = {
1290 /* AVB1_LINK */
1291 RCAR_GP_PIN(6, 4),
1292};
1293static const unsigned int avb1_link_mux[] = {
1294 AVB1_LINK_MARK,
1295};
1296static const unsigned int avb1_magic_pins[] = {
1297 /* AVB1_MAGIC */
1298 RCAR_GP_PIN(6, 1),
1299};
1300static const unsigned int avb1_magic_mux[] = {
1301 AVB1_MAGIC_MARK,
1302};
1303static const unsigned int avb1_phy_int_pins[] = {
1304 /* AVB1_PHY_INT */
1305 RCAR_GP_PIN(6, 3),
1306};
1307static const unsigned int avb1_phy_int_mux[] = {
1308 AVB1_PHY_INT_MARK,
1309};
1310static const unsigned int avb1_mdio_pins[] = {
1311 /* AVB1_MDC, AVB1_MDIO */
1312 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1313};
1314static const unsigned int avb1_mdio_mux[] = {
1315 AVB1_MDC_MARK, AVB1_MDIO_MARK,
1316};
1317static const unsigned int avb1_rgmii_pins[] = {
1318 /*
1319 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1320 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1321 */
1322 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1323 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1324 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1325 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1326 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1327 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1328};
1329static const unsigned int avb1_rgmii_mux[] = {
1330 AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
1331 AVB1_TD0_MARK, AVB1_TD1_MARK,
1332 AVB1_TD2_MARK, AVB1_TD3_MARK,
1333 AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
1334 AVB1_RD0_MARK, AVB1_RD1_MARK,
1335 AVB1_RD2_MARK, AVB1_RD3_MARK,
1336};
1337static const unsigned int avb1_txcrefclk_pins[] = {
1338 /* AVB1_TXCREFCLK */
1339 RCAR_GP_PIN(6, 20),
1340};
1341static const unsigned int avb1_txcrefclk_mux[] = {
1342 AVB1_TXCREFCLK_MARK,
1343};
1344static const unsigned int avb1_avtp_pps_pins[] = {
1345 /* AVB1_AVTP_PPS */
1346 RCAR_GP_PIN(6, 10),
1347};
1348static const unsigned int avb1_avtp_pps_mux[] = {
1349 AVB1_AVTP_PPS_MARK,
1350};
1351static const unsigned int avb1_avtp_capture_pins[] = {
1352 /* AVB1_AVTP_CAPTURE */
1353 RCAR_GP_PIN(6, 11),
1354};
1355static const unsigned int avb1_avtp_capture_mux[] = {
1356 AVB1_AVTP_CAPTURE_MARK,
1357};
1358static const unsigned int avb1_avtp_match_pins[] = {
1359 /* AVB1_AVTP_MATCH */
1360 RCAR_GP_PIN(6, 5),
1361};
1362static const unsigned int avb1_avtp_match_mux[] = {
1363 AVB1_AVTP_MATCH_MARK,
1364};
1365
1366/* - AVB2 ------------------------------------------------ */
1367static const unsigned int avb2_link_pins[] = {
1368 /* AVB2_LINK */
1369 RCAR_GP_PIN(5, 3),
1370};
1371static const unsigned int avb2_link_mux[] = {
1372 AVB2_LINK_MARK,
1373};
1374static const unsigned int avb2_magic_pins[] = {
1375 /* AVB2_MAGIC */
1376 RCAR_GP_PIN(5, 5),
1377};
1378static const unsigned int avb2_magic_mux[] = {
1379 AVB2_MAGIC_MARK,
1380};
1381static const unsigned int avb2_phy_int_pins[] = {
1382 /* AVB2_PHY_INT */
1383 RCAR_GP_PIN(5, 4),
1384};
1385static const unsigned int avb2_phy_int_mux[] = {
1386 AVB2_PHY_INT_MARK,
1387};
1388static const unsigned int avb2_mdio_pins[] = {
1389 /* AVB2_MDC, AVB2_MDIO */
1390 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1391};
1392static const unsigned int avb2_mdio_mux[] = {
1393 AVB2_MDC_MARK, AVB2_MDIO_MARK,
1394};
1395static const unsigned int avb2_rgmii_pins[] = {
1396 /*
1397 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1398 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1399 */
1400 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1401 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1402 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
1403 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1404 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1405 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1406};
1407static const unsigned int avb2_rgmii_mux[] = {
1408 AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
1409 AVB2_TD0_MARK, AVB2_TD1_MARK,
1410 AVB2_TD2_MARK, AVB2_TD3_MARK,
1411 AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
1412 AVB2_RD0_MARK, AVB2_RD1_MARK,
1413 AVB2_RD2_MARK, AVB2_RD3_MARK,
1414};
1415static const unsigned int avb2_txcrefclk_pins[] = {
1416 /* AVB2_TXCREFCLK */
1417 RCAR_GP_PIN(5, 7),
1418};
1419static const unsigned int avb2_txcrefclk_mux[] = {
1420 AVB2_TXCREFCLK_MARK,
1421};
1422static const unsigned int avb2_avtp_pps_pins[] = {
1423 /* AVB2_AVTP_PPS */
1424 RCAR_GP_PIN(5, 0),
1425};
1426static const unsigned int avb2_avtp_pps_mux[] = {
1427 AVB2_AVTP_PPS_MARK,
1428};
1429static const unsigned int avb2_avtp_capture_pins[] = {
1430 /* AVB2_AVTP_CAPTURE */
1431 RCAR_GP_PIN(5, 1),
1432};
1433static const unsigned int avb2_avtp_capture_mux[] = {
1434 AVB2_AVTP_CAPTURE_MARK,
1435};
1436static const unsigned int avb2_avtp_match_pins[] = {
1437 /* AVB2_AVTP_MATCH */
1438 RCAR_GP_PIN(5, 2),
1439};
1440static const unsigned int avb2_avtp_match_mux[] = {
1441 AVB2_AVTP_MATCH_MARK,
1442};
1443
1444/* - CANFD0 ----------------------------------------------------------------- */
1445static const unsigned int canfd0_data_pins[] = {
1446 /* CANFD0_TX, CANFD0_RX */
1447 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1448};
1449static const unsigned int canfd0_data_mux[] = {
1450 CANFD0_TX_MARK, CANFD0_RX_MARK,
1451};
1452
1453/* - CANFD1 ----------------------------------------------------------------- */
1454static const unsigned int canfd1_data_pins[] = {
1455 /* CANFD1_TX, CANFD1_RX */
1456 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 19),
1457};
1458static const unsigned int canfd1_data_mux[] = {
1459 CANFD1_TX_MARK, CANFD1_RX_MARK,
1460};
1461
1462/* - CANFD2 ----------------------------------------------------------------- */
1463static const unsigned int canfd2_data_pins[] = {
1464 /* CANFD2_TX, CANFD2_RX */
1465 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1466};
1467static const unsigned int canfd2_data_mux[] = {
1468 CANFD2_TX_MARK, CANFD2_RX_MARK,
1469};
1470
1471/* - CANFD3 ----------------------------------------------------------------- */
1472static const unsigned int canfd3_data_pins[] = {
1473 /* CANFD3_TX, CANFD3_RX */
1474 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1475};
1476static const unsigned int canfd3_data_mux[] = {
1477 CANFD3_TX_MARK, CANFD3_RX_MARK,
1478};
1479
1480/* - CANFD Clock ------------------------------------------------------------ */
1481static const unsigned int can_clk_pins[] = {
1482 /* CAN_CLK */
1483 RCAR_GP_PIN(2, 9),
1484};
1485static const unsigned int can_clk_mux[] = {
1486 CAN_CLK_MARK,
1487};
1488
1489/* - HSCIF0 ----------------------------------------------------------------- */
1490static const unsigned int hscif0_data_pins[] = {
1491 /* HRX0, HTX0 */
1492 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1493};
1494static const unsigned int hscif0_data_mux[] = {
1495 HRX0_MARK, HTX0_MARK,
1496};
1497static const unsigned int hscif0_clk_pins[] = {
1498 /* HSCK0 */
1499 RCAR_GP_PIN(1, 15),
1500};
1501static const unsigned int hscif0_clk_mux[] = {
1502 HSCK0_MARK,
1503};
1504static const unsigned int hscif0_ctrl_pins[] = {
1505 /* HRTS0_N, HCTS0_N */
1506 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1507};
1508static const unsigned int hscif0_ctrl_mux[] = {
1509 HRTS0_N_MARK, HCTS0_N_MARK,
1510};
1511
1512/* - HSCIF1_A ----------------------------------------------------------------- */
1513static const unsigned int hscif1_data_a_pins[] = {
1514 /* HRX1_A, HTX1_A */
1515 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1516};
1517static const unsigned int hscif1_data_a_mux[] = {
1518 HRX1_A_MARK, HTX1_A_MARK,
1519};
1520static const unsigned int hscif1_clk_a_pins[] = {
1521 /* HSCK1_A */
1522 RCAR_GP_PIN(0, 18),
1523};
1524static const unsigned int hscif1_clk_a_mux[] = {
1525 HSCK1_A_MARK,
1526};
1527static const unsigned int hscif1_ctrl_a_pins[] = {
1528 /* HRTS1_N_A, HCTS1_N_A */
1529 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1530};
1531static const unsigned int hscif1_ctrl_a_mux[] = {
1532 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1533};
1534
1535/* - HSCIF1_B ---------------------------------------------------------------- */
1536static const unsigned int hscif1_data_b_pins[] = {
1537 /* HRX1_B, HTX1_B */
1538 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1539};
1540static const unsigned int hscif1_data_b_mux[] = {
1541 HRX1_B_MARK, HTX1_B_MARK,
1542};
1543static const unsigned int hscif1_clk_b_pins[] = {
1544 /* HSCK1_B */
1545 RCAR_GP_PIN(1, 10),
1546};
1547static const unsigned int hscif1_clk_b_mux[] = {
1548 HSCK1_B_MARK,
1549};
1550static const unsigned int hscif1_ctrl_b_pins[] = {
1551 /* HRTS1_N_B, HCTS1_N_B */
1552 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1553};
1554static const unsigned int hscif1_ctrl_b_mux[] = {
1555 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1556};
1557
1558/* - HSCIF2 ----------------------------------------------------------------- */
1559static const unsigned int hscif2_data_pins[] = {
1560 /* HRX2, HTX2 */
1561 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1562};
1563static const unsigned int hscif2_data_mux[] = {
1564 HRX2_MARK, HTX2_MARK,
1565};
1566static const unsigned int hscif2_clk_pins[] = {
1567 /* HSCK2 */
1568 RCAR_GP_PIN(4, 13),
1569};
1570static const unsigned int hscif2_clk_mux[] = {
1571 HSCK2_MARK,
1572};
1573static const unsigned int hscif2_ctrl_pins[] = {
1574 /* HRTS2_N, HCTS2_N */
1575 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 12),
1576};
1577static const unsigned int hscif2_ctrl_mux[] = {
1578 HRTS2_N_MARK, HCTS2_N_MARK,
1579};
1580
1581/* - HSCIF3_A ----------------------------------------------------------------- */
1582static const unsigned int hscif3_data_a_pins[] = {
1583 /* HRX3_A, HTX3_A */
1584 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1585};
1586static const unsigned int hscif3_data_a_mux[] = {
1587 HRX3_A_MARK, HTX3_A_MARK,
1588};
1589static const unsigned int hscif3_clk_a_pins[] = {
1590 /* HSCK3_A */
1591 RCAR_GP_PIN(1, 25),
1592};
1593static const unsigned int hscif3_clk_a_mux[] = {
1594 HSCK3_A_MARK,
1595};
1596static const unsigned int hscif3_ctrl_a_pins[] = {
1597 /* HRTS3_N_A, HCTS3_N_A */
1598 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1599};
1600static const unsigned int hscif3_ctrl_a_mux[] = {
1601 HRTS3_N_A_MARK, HCTS3_N_A_MARK,
1602};
1603
1604/* - HSCIF3_B ----------------------------------------------------------------- */
1605static const unsigned int hscif3_data_b_pins[] = {
1606 /* HRX3_B, HTX3_B */
1607 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1608};
1609static const unsigned int hscif3_data_b_mux[] = {
1610 HRX3_B_MARK, HTX3_B_MARK,
1611};
1612static const unsigned int hscif3_clk_b_pins[] = {
1613 /* HSCK3_B */
1614 RCAR_GP_PIN(1, 3),
1615};
1616static const unsigned int hscif3_clk_b_mux[] = {
1617 HSCK3_B_MARK,
1618};
1619static const unsigned int hscif3_ctrl_b_pins[] = {
1620 /* HRTS3_N_B, HCTS3_N_B */
1621 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1622};
1623static const unsigned int hscif3_ctrl_b_mux[] = {
1624 HRTS3_N_B_MARK, HCTS3_N_B_MARK,
1625};
1626
1627/* - I2C0 ------------------------------------------------------------------- */
1628static const unsigned int i2c0_pins[] = {
1629 /* SDA0, SCL0 */
1630 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1631};
1632static const unsigned int i2c0_mux[] = {
1633 SDA0_MARK, SCL0_MARK,
1634};
1635
1636/* - I2C1 ------------------------------------------------------------------- */
1637static const unsigned int i2c1_pins[] = {
1638 /* SDA1, SCL1 */
1639 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1640};
1641static const unsigned int i2c1_mux[] = {
1642 SDA1_MARK, SCL1_MARK,
1643};
1644
1645/* - I2C2 ------------------------------------------------------------------- */
1646static const unsigned int i2c2_pins[] = {
1647 /* SDA2, SCL2 */
1648 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1649};
1650static const unsigned int i2c2_mux[] = {
1651 SDA2_MARK, SCL2_MARK,
1652};
1653
1654/* - I2C3 ------------------------------------------------------------------- */
1655static const unsigned int i2c3_pins[] = {
1656 /* SDA3, SCL3 */
1657 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
1658};
1659static const unsigned int i2c3_mux[] = {
1660 SDA3_MARK, SCL3_MARK,
1661};
1662
1663/* - MMC -------------------------------------------------------------------- */
1664static const unsigned int mmc_data_pins[] = {
1665 /* MMC_SD_D[0:3], MMC_D[4:7] */
1666 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1667 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1668 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1669 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1670};
1671static const unsigned int mmc_data_mux[] = {
1672 MMC_SD_D0_MARK, MMC_SD_D1_MARK,
1673 MMC_SD_D2_MARK, MMC_SD_D3_MARK,
1674 MMC_D4_MARK, MMC_D5_MARK,
1675 MMC_D6_MARK, MMC_D7_MARK,
1676};
1677static const unsigned int mmc_ctrl_pins[] = {
1678 /* MMC_SD_CLK, MMC_SD_CMD */
1679 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1680};
1681static const unsigned int mmc_ctrl_mux[] = {
1682 MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
1683};
1684static const unsigned int mmc_cd_pins[] = {
1685 /* SD_CD */
1686 RCAR_GP_PIN(3, 11),
1687};
1688static const unsigned int mmc_cd_mux[] = {
1689 SD_CD_MARK,
1690};
1691static const unsigned int mmc_wp_pins[] = {
1692 /* SD_WP */
1693 RCAR_GP_PIN(3, 12),
1694};
1695static const unsigned int mmc_wp_mux[] = {
1696 SD_WP_MARK,
1697};
1698static const unsigned int mmc_ds_pins[] = {
1699 /* MMC_DS */
1700 RCAR_GP_PIN(3, 4),
1701};
1702static const unsigned int mmc_ds_mux[] = {
1703 MMC_DS_MARK,
1704};
1705
1706/* - MSIOF0 ----------------------------------------------------------------- */
1707static const unsigned int msiof0_clk_pins[] = {
1708 /* MSIOF0_SCK */
1709 RCAR_GP_PIN(1, 10),
1710};
1711static const unsigned int msiof0_clk_mux[] = {
1712 MSIOF0_SCK_MARK,
1713};
1714static const unsigned int msiof0_sync_pins[] = {
1715 /* MSIOF0_SYNC */
1716 RCAR_GP_PIN(1, 8),
1717};
1718static const unsigned int msiof0_sync_mux[] = {
1719 MSIOF0_SYNC_MARK,
1720};
1721static const unsigned int msiof0_ss1_pins[] = {
1722 /* MSIOF0_SS1 */
1723 RCAR_GP_PIN(1, 7),
1724};
1725static const unsigned int msiof0_ss1_mux[] = {
1726 MSIOF0_SS1_MARK,
1727};
1728static const unsigned int msiof0_ss2_pins[] = {
1729 /* MSIOF0_SS2 */
1730 RCAR_GP_PIN(1, 6),
1731};
1732static const unsigned int msiof0_ss2_mux[] = {
1733 MSIOF0_SS2_MARK,
1734};
1735static const unsigned int msiof0_txd_pins[] = {
1736 /* MSIOF0_TXD */
1737 RCAR_GP_PIN(1, 9),
1738};
1739static const unsigned int msiof0_txd_mux[] = {
1740 MSIOF0_TXD_MARK,
1741};
1742static const unsigned int msiof0_rxd_pins[] = {
1743 /* MSIOF0_RXD */
1744 RCAR_GP_PIN(1, 11),
1745};
1746static const unsigned int msiof0_rxd_mux[] = {
1747 MSIOF0_RXD_MARK,
1748};
1749
1750/* - MSIOF1 ----------------------------------------------------------------- */
1751static const unsigned int msiof1_clk_pins[] = {
1752 /* MSIOF1_SCK */
1753 RCAR_GP_PIN(1, 3),
1754};
1755static const unsigned int msiof1_clk_mux[] = {
1756 MSIOF1_SCK_MARK,
1757};
1758static const unsigned int msiof1_sync_pins[] = {
1759 /* MSIOF1_SYNC */
1760 RCAR_GP_PIN(1, 2),
1761};
1762static const unsigned int msiof1_sync_mux[] = {
1763 MSIOF1_SYNC_MARK,
1764};
1765static const unsigned int msiof1_ss1_pins[] = {
1766 /* MSIOF1_SS1 */
1767 RCAR_GP_PIN(1, 1),
1768};
1769static const unsigned int msiof1_ss1_mux[] = {
1770 MSIOF1_SS1_MARK,
1771};
1772static const unsigned int msiof1_ss2_pins[] = {
1773 /* MSIOF1_SS2 */
1774 RCAR_GP_PIN(1, 0),
1775};
1776static const unsigned int msiof1_ss2_mux[] = {
1777 MSIOF1_SS2_MARK,
1778};
1779static const unsigned int msiof1_txd_pins[] = {
1780 /* MSIOF1_TXD */
1781 RCAR_GP_PIN(1, 4),
1782};
1783static const unsigned int msiof1_txd_mux[] = {
1784 MSIOF1_TXD_MARK,
1785};
1786static const unsigned int msiof1_rxd_pins[] = {
1787 /* MSIOF1_RXD */
1788 RCAR_GP_PIN(1, 5),
1789};
1790static const unsigned int msiof1_rxd_mux[] = {
1791 MSIOF1_RXD_MARK,
1792};
1793
1794/* - MSIOF2 ----------------------------------------------------------------- */
1795static const unsigned int msiof2_clk_pins[] = {
1796 /* MSIOF2_SCK */
1797 RCAR_GP_PIN(0, 17),
1798};
1799static const unsigned int msiof2_clk_mux[] = {
1800 MSIOF2_SCK_MARK,
1801};
1802static const unsigned int msiof2_sync_pins[] = {
1803 /* MSIOF2_SYNC */
1804 RCAR_GP_PIN(0, 15),
1805};
1806static const unsigned int msiof2_sync_mux[] = {
1807 MSIOF2_SYNC_MARK,
1808};
1809static const unsigned int msiof2_ss1_pins[] = {
1810 /* MSIOF2_SS1 */
1811 RCAR_GP_PIN(0, 14),
1812};
1813static const unsigned int msiof2_ss1_mux[] = {
1814 MSIOF2_SS1_MARK,
1815};
1816static const unsigned int msiof2_ss2_pins[] = {
1817 /* MSIOF2_SS2 */
1818 RCAR_GP_PIN(0, 13),
1819};
1820static const unsigned int msiof2_ss2_mux[] = {
1821 MSIOF2_SS2_MARK,
1822};
1823static const unsigned int msiof2_txd_pins[] = {
1824 /* MSIOF2_TXD */
1825 RCAR_GP_PIN(0, 16),
1826};
1827static const unsigned int msiof2_txd_mux[] = {
1828 MSIOF2_TXD_MARK,
1829};
1830static const unsigned int msiof2_rxd_pins[] = {
1831 /* MSIOF2_RXD */
1832 RCAR_GP_PIN(0, 18),
1833};
1834static const unsigned int msiof2_rxd_mux[] = {
1835 MSIOF2_RXD_MARK,
1836};
1837
1838/* - MSIOF3 ----------------------------------------------------------------- */
1839static const unsigned int msiof3_clk_pins[] = {
1840 /* MSIOF3_SCK */
1841 RCAR_GP_PIN(0, 3),
1842};
1843static const unsigned int msiof3_clk_mux[] = {
1844 MSIOF3_SCK_MARK,
1845};
1846static const unsigned int msiof3_sync_pins[] = {
1847 /* MSIOF3_SYNC */
1848 RCAR_GP_PIN(0, 6),
1849};
1850static const unsigned int msiof3_sync_mux[] = {
1851 MSIOF3_SYNC_MARK,
1852};
1853static const unsigned int msiof3_ss1_pins[] = {
1854 /* MSIOF3_SS1 */
1855 RCAR_GP_PIN(0, 1),
1856};
1857static const unsigned int msiof3_ss1_mux[] = {
1858 MSIOF3_SS1_MARK,
1859};
1860static const unsigned int msiof3_ss2_pins[] = {
1861 /* MSIOF3_SS2 */
1862 RCAR_GP_PIN(0, 2),
1863};
1864static const unsigned int msiof3_ss2_mux[] = {
1865 MSIOF3_SS2_MARK,
1866};
1867static const unsigned int msiof3_txd_pins[] = {
1868 /* MSIOF3_TXD */
1869 RCAR_GP_PIN(0, 4),
1870};
1871static const unsigned int msiof3_txd_mux[] = {
1872 MSIOF3_TXD_MARK,
1873};
1874static const unsigned int msiof3_rxd_pins[] = {
1875 /* MSIOF3_RXD */
1876 RCAR_GP_PIN(0, 5),
1877};
1878static const unsigned int msiof3_rxd_mux[] = {
1879 MSIOF3_RXD_MARK,
1880};
1881
1882/* - MSIOF4 ----------------------------------------------------------------- */
1883static const unsigned int msiof4_clk_pins[] = {
1884 /* MSIOF4_SCK */
1885 RCAR_GP_PIN(1, 25),
1886};
1887static const unsigned int msiof4_clk_mux[] = {
1888 MSIOF4_SCK_MARK,
1889};
1890static const unsigned int msiof4_sync_pins[] = {
1891 /* MSIOF4_SYNC */
1892 RCAR_GP_PIN(1, 28),
1893};
1894static const unsigned int msiof4_sync_mux[] = {
1895 MSIOF4_SYNC_MARK,
1896};
1897static const unsigned int msiof4_ss1_pins[] = {
1898 /* MSIOF4_SS1 */
1899 RCAR_GP_PIN(1, 23),
1900};
1901static const unsigned int msiof4_ss1_mux[] = {
1902 MSIOF4_SS1_MARK,
1903};
1904static const unsigned int msiof4_ss2_pins[] = {
1905 /* MSIOF4_SS2 */
1906 RCAR_GP_PIN(1, 24),
1907};
1908static const unsigned int msiof4_ss2_mux[] = {
1909 MSIOF4_SS2_MARK,
1910};
1911static const unsigned int msiof4_txd_pins[] = {
1912 /* MSIOF4_TXD */
1913 RCAR_GP_PIN(1, 26),
1914};
1915static const unsigned int msiof4_txd_mux[] = {
1916 MSIOF4_TXD_MARK,
1917};
1918static const unsigned int msiof4_rxd_pins[] = {
1919 /* MSIOF4_RXD */
1920 RCAR_GP_PIN(1, 27),
1921};
1922static const unsigned int msiof4_rxd_mux[] = {
1923 MSIOF4_RXD_MARK,
1924};
1925
1926/* - MSIOF5 ----------------------------------------------------------------- */
1927static const unsigned int msiof5_clk_pins[] = {
1928 /* MSIOF5_SCK */
1929 RCAR_GP_PIN(0, 11),
1930};
1931static const unsigned int msiof5_clk_mux[] = {
1932 MSIOF5_SCK_MARK,
1933};
1934static const unsigned int msiof5_sync_pins[] = {
1935 /* MSIOF5_SYNC */
1936 RCAR_GP_PIN(0, 9),
1937};
1938static const unsigned int msiof5_sync_mux[] = {
1939 MSIOF5_SYNC_MARK,
1940};
1941static const unsigned int msiof5_ss1_pins[] = {
1942 /* MSIOF5_SS1 */
1943 RCAR_GP_PIN(0, 8),
1944};
1945static const unsigned int msiof5_ss1_mux[] = {
1946 MSIOF5_SS1_MARK,
1947};
1948static const unsigned int msiof5_ss2_pins[] = {
1949 /* MSIOF5_SS2 */
1950 RCAR_GP_PIN(0, 7),
1951};
1952static const unsigned int msiof5_ss2_mux[] = {
1953 MSIOF5_SS2_MARK,
1954};
1955static const unsigned int msiof5_txd_pins[] = {
1956 /* MSIOF5_TXD */
1957 RCAR_GP_PIN(0, 10),
1958};
1959static const unsigned int msiof5_txd_mux[] = {
1960 MSIOF5_TXD_MARK,
1961};
1962static const unsigned int msiof5_rxd_pins[] = {
1963 /* MSIOF5_RXD */
1964 RCAR_GP_PIN(0, 12),
1965};
1966static const unsigned int msiof5_rxd_mux[] = {
1967 MSIOF5_RXD_MARK,
1968};
1969
1970/* - PCIE ------------------------------------------------------------------- */
1971static const unsigned int pcie0_clkreq_n_pins[] = {
1972 /* PCIE0_CLKREQ_N */
1973 RCAR_GP_PIN(4, 21),
1974};
1975
1976static const unsigned int pcie0_clkreq_n_mux[] = {
1977 PCIE0_CLKREQ_N_MARK,
1978};
1979
1980/* - PWM0_A ------------------------------------------------------------------- */
1981static const unsigned int pwm0_a_pins[] = {
1982 /* PWM0_A */
1983 RCAR_GP_PIN(1, 15),
1984};
1985static const unsigned int pwm0_a_mux[] = {
1986 PWM0_A_MARK,
1987};
1988
1989/* - PWM0_B ------------------------------------------------------------------- */
1990static const unsigned int pwm0_b_pins[] = {
1991 /* PWM0_B */
1992 RCAR_GP_PIN(1, 14),
1993};
1994static const unsigned int pwm0_b_mux[] = {
1995 PWM0_B_MARK,
1996};
1997
1998/* - PWM1_A ------------------------------------------------------------------- */
1999static const unsigned int pwm1_a_pins[] = {
2000 /* PWM1_A */
2001 RCAR_GP_PIN(3, 13),
2002};
2003static const unsigned int pwm1_a_mux[] = {
2004 PWM1_A_MARK,
2005};
2006
2007/* - PWM1_B ------------------------------------------------------------------- */
2008static const unsigned int pwm1_b_pins[] = {
2009 /* PWM1_B */
2010 RCAR_GP_PIN(2, 13),
2011};
2012static const unsigned int pwm1_b_mux[] = {
2013 PWM1_B_MARK,
2014};
2015
2016/* - PWM1_C ------------------------------------------------------------------- */
2017static const unsigned int pwm1_c_pins[] = {
2018 /* PWM1_C */
2019 RCAR_GP_PIN(2, 17),
2020};
2021static const unsigned int pwm1_c_mux[] = {
2022 PWM1_C_MARK,
2023};
2024
2025/* - PWM2_A ------------------------------------------------------------------- */
2026static const unsigned int pwm2_a_pins[] = {
2027 /* PWM2_A */
2028 RCAR_GP_PIN(3, 14),
2029};
2030static const unsigned int pwm2_a_mux[] = {
2031 PWM2_A_MARK,
2032};
2033
2034/* - PWM2_B ------------------------------------------------------------------- */
2035static const unsigned int pwm2_b_pins[] = {
2036 /* PWM2_B */
2037 RCAR_GP_PIN(2, 14),
2038};
2039static const unsigned int pwm2_b_mux[] = {
2040 PWM2_B_MARK,
2041};
2042
2043/* - PWM2_C ------------------------------------------------------------------- */
2044static const unsigned int pwm2_c_pins[] = {
2045 /* PWM2_C */
2046 RCAR_GP_PIN(2, 19),
2047};
2048static const unsigned int pwm2_c_mux[] = {
2049 PWM2_C_MARK,
2050};
2051
2052/* - PWM3_A ------------------------------------------------------------------- */
2053static const unsigned int pwm3_a_pins[] = {
2054 /* PWM3_A */
2055 RCAR_GP_PIN(4, 14),
2056};
2057static const unsigned int pwm3_a_mux[] = {
2058 PWM3_A_MARK,
2059};
2060
2061/* - PWM3_B ------------------------------------------------------------------- */
2062static const unsigned int pwm3_b_pins[] = {
2063 /* PWM3_B */
2064 RCAR_GP_PIN(2, 15),
2065};
2066static const unsigned int pwm3_b_mux[] = {
2067 PWM3_B_MARK,
2068};
2069
2070/* - PWM3_C ------------------------------------------------------------------- */
2071static const unsigned int pwm3_c_pins[] = {
2072 /* PWM3_C */
2073 RCAR_GP_PIN(1, 22),
2074};
2075static const unsigned int pwm3_c_mux[] = {
2076 PWM3_C_MARK,
2077};
2078
2079/* - PWM4 ------------------------------------------------------------------- */
2080static const unsigned int pwm4_pins[] = {
2081 /* PWM4 */
2082 RCAR_GP_PIN(4, 15),
2083};
2084static const unsigned int pwm4_mux[] = {
2085 PWM4_MARK,
2086};
2087
2088/* - QSPI0 ------------------------------------------------------------------ */
2089static const unsigned int qspi0_ctrl_pins[] = {
2090 /* SPCLK, SSL */
2091 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2092};
2093static const unsigned int qspi0_ctrl_mux[] = {
2094 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2095};
2096static const unsigned int qspi0_data_pins[] = {
2097 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2098 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2099 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2100};
2101static const unsigned int qspi0_data_mux[] = {
2102 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2103 QSPI0_IO2_MARK, QSPI0_IO3_MARK
2104};
2105
2106/* - QSPI1 ------------------------------------------------------------------ */
2107static const unsigned int qspi1_ctrl_pins[] = {
2108 /* SPCLK, SSL */
2109 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2110};
2111static const unsigned int qspi1_ctrl_mux[] = {
2112 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2113};
2114static const unsigned int qspi1_data_pins[] = {
2115 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2116 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2117 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2118};
2119static const unsigned int qspi1_data_mux[] = {
2120 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2121 QSPI1_IO2_MARK, QSPI1_IO3_MARK
2122};
2123
2124/* - SCIF0 ------------------------------------------------------------------ */
2125static const unsigned int scif0_data_pins[] = {
2126 /* RX0, TX0 */
2127 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2128};
2129static const unsigned int scif0_data_mux[] = {
2130 RX0_MARK, TX0_MARK,
2131};
2132static const unsigned int scif0_clk_pins[] = {
2133 /* SCK0 */
2134 RCAR_GP_PIN(1, 15),
2135};
2136static const unsigned int scif0_clk_mux[] = {
2137 SCK0_MARK,
2138};
2139static const unsigned int scif0_ctrl_pins[] = {
2140 /* RTS0_N, CTS0_N */
2141 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2142};
2143static const unsigned int scif0_ctrl_mux[] = {
2144 RTS0_N_MARK, CTS0_N_MARK,
2145};
2146
2147/* - SCIF1_A ------------------------------------------------------------------ */
2148static const unsigned int scif1_data_a_pins[] = {
2149 /* RX1_A, TX1_A */
2150 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2151};
2152static const unsigned int scif1_data_a_mux[] = {
2153 RX1_A_MARK, TX1_A_MARK,
2154};
2155static const unsigned int scif1_clk_a_pins[] = {
2156 /* SCK1_A */
2157 RCAR_GP_PIN(0, 18),
2158};
2159static const unsigned int scif1_clk_a_mux[] = {
2160 SCK1_A_MARK,
2161};
2162static const unsigned int scif1_ctrl_a_pins[] = {
2163 /* RTS1_N_A, CTS1_N_A */
2164 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2165};
2166static const unsigned int scif1_ctrl_a_mux[] = {
2167 RTS1_N_A_MARK, CTS1_N_A_MARK,
2168};
2169
2170/* - SCIF1_B ------------------------------------------------------------------ */
2171static const unsigned int scif1_data_b_pins[] = {
2172 /* RX1_B, TX1_B */
2173 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2174};
2175static const unsigned int scif1_data_b_mux[] = {
2176 RX1_B_MARK, TX1_B_MARK,
2177};
2178static const unsigned int scif1_clk_b_pins[] = {
2179 /* SCK1_B */
2180 RCAR_GP_PIN(1, 10),
2181};
2182static const unsigned int scif1_clk_b_mux[] = {
2183 SCK1_B_MARK,
2184};
2185static const unsigned int scif1_ctrl_b_pins[] = {
2186 /* RTS1_N_B, CTS1_N_B */
2187 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2188};
2189static const unsigned int scif1_ctrl_b_mux[] = {
2190 RTS1_N_B_MARK, CTS1_N_B_MARK,
2191};
2192
2193/* - SCIF3_A ------------------------------------------------------------------ */
2194static const unsigned int scif3_data_a_pins[] = {
2195 /* RX3_A, TX3_A */
2196 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2197};
2198static const unsigned int scif3_data_a_mux[] = {
2199 RX3_A_MARK, TX3_A_MARK,
2200};
2201static const unsigned int scif3_clk_a_pins[] = {
2202 /* SCK3_A */
2203 RCAR_GP_PIN(1, 24),
2204};
2205static const unsigned int scif3_clk_a_mux[] = {
2206 SCK3_A_MARK,
2207};
2208static const unsigned int scif3_ctrl_a_pins[] = {
2209 /* RTS3_N_A, CTS3_N_A */
2210 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2211};
2212static const unsigned int scif3_ctrl_a_mux[] = {
2213 RTS3_N_A_MARK, CTS3_N_A_MARK,
2214};
2215
2216/* - SCIF3_B ------------------------------------------------------------------ */
2217static const unsigned int scif3_data_b_pins[] = {
2218 /* RX3_B, TX3_B */
2219 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2220};
2221static const unsigned int scif3_data_b_mux[] = {
2222 RX3_B_MARK, TX3_B_MARK,
2223};
2224static const unsigned int scif3_clk_b_pins[] = {
2225 /* SCK3_B */
2226 RCAR_GP_PIN(1, 4),
2227};
2228static const unsigned int scif3_clk_b_mux[] = {
2229 SCK3_B_MARK,
2230};
2231static const unsigned int scif3_ctrl_b_pins[] = {
2232 /* RTS3_N_B, CTS3_N_B */
2233 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2234};
2235static const unsigned int scif3_ctrl_b_mux[] = {
2236 RTS3_N_B_MARK, CTS3_N_B_MARK,
2237};
2238
2239/* - SCIF4 ------------------------------------------------------------------ */
2240static const unsigned int scif4_data_pins[] = {
2241 /* RX4, TX4 */
2242 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
2243};
2244static const unsigned int scif4_data_mux[] = {
2245 RX4_MARK, TX4_MARK,
2246};
2247static const unsigned int scif4_clk_pins[] = {
2248 /* SCK4 */
2249 RCAR_GP_PIN(4, 8),
2250};
2251static const unsigned int scif4_clk_mux[] = {
2252 SCK4_MARK,
2253};
2254static const unsigned int scif4_ctrl_pins[] = {
2255 /* RTS4_N, CTS4_N */
2256 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 9),
2257};
2258static const unsigned int scif4_ctrl_mux[] = {
2259 RTS4_N_MARK, CTS4_N_MARK,
2260};
2261
2262/* - SCIF Clock ------------------------------------------------------------- */
2263static const unsigned int scif_clk_pins[] = {
2264 /* SCIF_CLK */
2265 RCAR_GP_PIN(1, 17),
2266};
2267static const unsigned int scif_clk_mux[] = {
2268 SCIF_CLK_MARK,
2269};
2270
2271static const unsigned int scif_clk2_pins[] = {
2272 /* SCIF_CLK2 */
2273 RCAR_GP_PIN(4, 11),
2274};
2275static const unsigned int scif_clk2_mux[] = {
2276 SCIF_CLK2_MARK,
2277};
2278
2279/* - SSI ------------------------------------------------- */
2280static const unsigned int ssi_data_pins[] = {
2281 /* SSI_SD */
2282 RCAR_GP_PIN(1, 20),
2283};
2284static const unsigned int ssi_data_mux[] = {
2285 SSI_SD_MARK,
2286};
2287static const unsigned int ssi_ctrl_pins[] = {
2288 /* SSI_SCK, SSI_WS */
2289 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2290};
2291static const unsigned int ssi_ctrl_mux[] = {
2292 SSI_SCK_MARK, SSI_WS_MARK,
2293};
2294
2295/* - TPU_A ------------------------------------------------------------------- */
2296static const unsigned int tpu_to0_a_pins[] = {
2297 /* TPU0TO0_A */
2298 RCAR_GP_PIN(2, 8),
2299};
2300static const unsigned int tpu_to0_a_mux[] = {
2301 TPU0TO0_A_MARK,
2302};
2303static const unsigned int tpu_to1_a_pins[] = {
2304 /* TPU0TO1_A */
2305 RCAR_GP_PIN(2, 7),
2306};
2307static const unsigned int tpu_to1_a_mux[] = {
2308 TPU0TO1_A_MARK,
2309};
2310static const unsigned int tpu_to2_a_pins[] = {
2311 /* TPU0TO2_A */
2312 RCAR_GP_PIN(2, 12),
2313};
2314static const unsigned int tpu_to2_a_mux[] = {
2315 TPU0TO2_A_MARK,
2316};
2317static const unsigned int tpu_to3_a_pins[] = {
2318 /* TPU0TO3_A */
2319 RCAR_GP_PIN(2, 13),
2320};
2321static const unsigned int tpu_to3_a_mux[] = {
2322 TPU0TO3_A_MARK,
2323};
2324
2325/* - TPU_B ------------------------------------------------------------------- */
2326static const unsigned int tpu_to0_b_pins[] = {
2327 /* TPU0TO0_B */
2328 RCAR_GP_PIN(1, 25),
2329};
2330static const unsigned int tpu_to0_b_mux[] = {
2331 TPU0TO0_B_MARK,
2332};
2333static const unsigned int tpu_to1_b_pins[] = {
2334 /* TPU0TO1_B */
2335 RCAR_GP_PIN(1, 26),
2336};
2337static const unsigned int tpu_to1_b_mux[] = {
2338 TPU0TO1_B_MARK,
2339};
2340static const unsigned int tpu_to2_b_pins[] = {
2341 /* TPU0TO2_B */
2342 RCAR_GP_PIN(2, 0),
2343};
2344static const unsigned int tpu_to2_b_mux[] = {
2345 TPU0TO2_B_MARK,
2346};
2347static const unsigned int tpu_to3_b_pins[] = {
2348 /* TPU0TO3_B */
2349 RCAR_GP_PIN(2, 1),
2350};
2351static const unsigned int tpu_to3_b_mux[] = {
2352 TPU0TO3_B_MARK,
2353};
2354
2355static const struct sh_pfc_pin_group pinmux_groups[] = {
2356 SH_PFC_PIN_GROUP(audio_clkin),
2357 SH_PFC_PIN_GROUP(audio_clkout),
2358
2359 SH_PFC_PIN_GROUP(avb0_link),
2360 SH_PFC_PIN_GROUP(avb0_magic),
2361 SH_PFC_PIN_GROUP(avb0_phy_int),
2362 SH_PFC_PIN_GROUP(avb0_mdio),
2363 SH_PFC_PIN_GROUP(avb0_rgmii),
2364 SH_PFC_PIN_GROUP(avb0_txcrefclk),
2365 SH_PFC_PIN_GROUP(avb0_avtp_pps),
2366 SH_PFC_PIN_GROUP(avb0_avtp_capture),
2367 SH_PFC_PIN_GROUP(avb0_avtp_match),
2368
2369 SH_PFC_PIN_GROUP(avb1_link),
2370 SH_PFC_PIN_GROUP(avb1_magic),
2371 SH_PFC_PIN_GROUP(avb1_phy_int),
2372 SH_PFC_PIN_GROUP(avb1_mdio),
2373 SH_PFC_PIN_GROUP(avb1_rgmii),
2374 SH_PFC_PIN_GROUP(avb1_txcrefclk),
2375 SH_PFC_PIN_GROUP(avb1_avtp_pps),
2376 SH_PFC_PIN_GROUP(avb1_avtp_capture),
2377 SH_PFC_PIN_GROUP(avb1_avtp_match),
2378
2379 SH_PFC_PIN_GROUP(avb2_link),
2380 SH_PFC_PIN_GROUP(avb2_magic),
2381 SH_PFC_PIN_GROUP(avb2_phy_int),
2382 SH_PFC_PIN_GROUP(avb2_mdio),
2383 SH_PFC_PIN_GROUP(avb2_rgmii),
2384 SH_PFC_PIN_GROUP(avb2_txcrefclk),
2385 SH_PFC_PIN_GROUP(avb2_avtp_pps),
2386 SH_PFC_PIN_GROUP(avb2_avtp_capture),
2387 SH_PFC_PIN_GROUP(avb2_avtp_match),
2388
2389 SH_PFC_PIN_GROUP(canfd0_data),
2390 SH_PFC_PIN_GROUP(canfd1_data),
2391 SH_PFC_PIN_GROUP(canfd2_data),
2392 SH_PFC_PIN_GROUP(canfd3_data),
2393 SH_PFC_PIN_GROUP(can_clk),
2394
2395 SH_PFC_PIN_GROUP(hscif0_data),
2396 SH_PFC_PIN_GROUP(hscif0_clk),
2397 SH_PFC_PIN_GROUP(hscif0_ctrl),
2398 SH_PFC_PIN_GROUP(hscif1_data_a),
2399 SH_PFC_PIN_GROUP(hscif1_clk_a),
2400 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
2401 SH_PFC_PIN_GROUP(hscif1_data_b),
2402 SH_PFC_PIN_GROUP(hscif1_clk_b),
2403 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2404 SH_PFC_PIN_GROUP(hscif2_data),
2405 SH_PFC_PIN_GROUP(hscif2_clk),
2406 SH_PFC_PIN_GROUP(hscif2_ctrl),
2407 SH_PFC_PIN_GROUP(hscif3_data_a),
2408 SH_PFC_PIN_GROUP(hscif3_clk_a),
2409 SH_PFC_PIN_GROUP(hscif3_ctrl_a),
2410 SH_PFC_PIN_GROUP(hscif3_data_b),
2411 SH_PFC_PIN_GROUP(hscif3_clk_b),
2412 SH_PFC_PIN_GROUP(hscif3_ctrl_b),
2413
2414 SH_PFC_PIN_GROUP(i2c0),
2415 SH_PFC_PIN_GROUP(i2c1),
2416 SH_PFC_PIN_GROUP(i2c2),
2417 SH_PFC_PIN_GROUP(i2c3),
2418
2419 BUS_DATA_PIN_GROUP(mmc_data, 1),
2420 BUS_DATA_PIN_GROUP(mmc_data, 4),
2421 BUS_DATA_PIN_GROUP(mmc_data, 8),
2422 SH_PFC_PIN_GROUP(mmc_ctrl),
2423 SH_PFC_PIN_GROUP(mmc_cd),
2424 SH_PFC_PIN_GROUP(mmc_wp),
2425 SH_PFC_PIN_GROUP(mmc_ds),
2426
2427 SH_PFC_PIN_GROUP(msiof0_clk),
2428 SH_PFC_PIN_GROUP(msiof0_sync),
2429 SH_PFC_PIN_GROUP(msiof0_ss1),
2430 SH_PFC_PIN_GROUP(msiof0_ss2),
2431 SH_PFC_PIN_GROUP(msiof0_txd),
2432 SH_PFC_PIN_GROUP(msiof0_rxd),
2433
2434 SH_PFC_PIN_GROUP(msiof1_clk),
2435 SH_PFC_PIN_GROUP(msiof1_sync),
2436 SH_PFC_PIN_GROUP(msiof1_ss1),
2437 SH_PFC_PIN_GROUP(msiof1_ss2),
2438 SH_PFC_PIN_GROUP(msiof1_txd),
2439 SH_PFC_PIN_GROUP(msiof1_rxd),
2440
2441 SH_PFC_PIN_GROUP(msiof2_clk),
2442 SH_PFC_PIN_GROUP(msiof2_sync),
2443 SH_PFC_PIN_GROUP(msiof2_ss1),
2444 SH_PFC_PIN_GROUP(msiof2_ss2),
2445 SH_PFC_PIN_GROUP(msiof2_txd),
2446 SH_PFC_PIN_GROUP(msiof2_rxd),
2447
2448 SH_PFC_PIN_GROUP(msiof3_clk),
2449 SH_PFC_PIN_GROUP(msiof3_sync),
2450 SH_PFC_PIN_GROUP(msiof3_ss1),
2451 SH_PFC_PIN_GROUP(msiof3_ss2),
2452 SH_PFC_PIN_GROUP(msiof3_txd),
2453 SH_PFC_PIN_GROUP(msiof3_rxd),
2454
2455 SH_PFC_PIN_GROUP(msiof4_clk),
2456 SH_PFC_PIN_GROUP(msiof4_sync),
2457 SH_PFC_PIN_GROUP(msiof4_ss1),
2458 SH_PFC_PIN_GROUP(msiof4_ss2),
2459 SH_PFC_PIN_GROUP(msiof4_txd),
2460 SH_PFC_PIN_GROUP(msiof4_rxd),
2461
2462 SH_PFC_PIN_GROUP(msiof5_clk),
2463 SH_PFC_PIN_GROUP(msiof5_sync),
2464 SH_PFC_PIN_GROUP(msiof5_ss1),
2465 SH_PFC_PIN_GROUP(msiof5_ss2),
2466 SH_PFC_PIN_GROUP(msiof5_txd),
2467 SH_PFC_PIN_GROUP(msiof5_rxd),
2468
2469 SH_PFC_PIN_GROUP(pcie0_clkreq_n),
2470
2471 SH_PFC_PIN_GROUP(pwm0_a),
2472 SH_PFC_PIN_GROUP(pwm0_b),
2473 SH_PFC_PIN_GROUP(pwm1_a),
2474 SH_PFC_PIN_GROUP(pwm1_b),
2475 SH_PFC_PIN_GROUP(pwm1_c),
2476 SH_PFC_PIN_GROUP(pwm2_a),
2477 SH_PFC_PIN_GROUP(pwm2_b),
2478 SH_PFC_PIN_GROUP(pwm2_c),
2479 SH_PFC_PIN_GROUP(pwm3_a),
2480 SH_PFC_PIN_GROUP(pwm3_b),
2481 SH_PFC_PIN_GROUP(pwm3_c),
2482 SH_PFC_PIN_GROUP(pwm4),
2483
2484 SH_PFC_PIN_GROUP(qspi0_ctrl),
2485 BUS_DATA_PIN_GROUP(qspi0_data, 2),
2486 BUS_DATA_PIN_GROUP(qspi0_data, 4),
2487 SH_PFC_PIN_GROUP(qspi1_ctrl),
2488 BUS_DATA_PIN_GROUP(qspi1_data, 2),
2489 BUS_DATA_PIN_GROUP(qspi1_data, 4),
2490
2491 SH_PFC_PIN_GROUP(scif0_data),
2492 SH_PFC_PIN_GROUP(scif0_clk),
2493 SH_PFC_PIN_GROUP(scif0_ctrl),
2494 SH_PFC_PIN_GROUP(scif1_data_a),
2495 SH_PFC_PIN_GROUP(scif1_clk_a),
2496 SH_PFC_PIN_GROUP(scif1_ctrl_a),
2497 SH_PFC_PIN_GROUP(scif1_data_b),
2498 SH_PFC_PIN_GROUP(scif1_clk_b),
2499 SH_PFC_PIN_GROUP(scif1_ctrl_b),
2500 SH_PFC_PIN_GROUP(scif3_data_a),
2501 SH_PFC_PIN_GROUP(scif3_clk_a),
2502 SH_PFC_PIN_GROUP(scif3_ctrl_a),
2503 SH_PFC_PIN_GROUP(scif3_data_b),
2504 SH_PFC_PIN_GROUP(scif3_clk_b),
2505 SH_PFC_PIN_GROUP(scif3_ctrl_b),
2506 SH_PFC_PIN_GROUP(scif4_data),
2507 SH_PFC_PIN_GROUP(scif4_clk),
2508 SH_PFC_PIN_GROUP(scif4_ctrl),
2509 SH_PFC_PIN_GROUP(scif_clk),
2510 SH_PFC_PIN_GROUP(scif_clk2),
2511
2512 SH_PFC_PIN_GROUP(ssi_data),
2513 SH_PFC_PIN_GROUP(ssi_ctrl),
2514
2515 SH_PFC_PIN_GROUP(tpu_to0_a),
2516 SH_PFC_PIN_GROUP(tpu_to0_b),
2517 SH_PFC_PIN_GROUP(tpu_to1_a),
2518 SH_PFC_PIN_GROUP(tpu_to1_b),
2519 SH_PFC_PIN_GROUP(tpu_to2_a),
2520 SH_PFC_PIN_GROUP(tpu_to2_b),
2521 SH_PFC_PIN_GROUP(tpu_to3_a),
2522 SH_PFC_PIN_GROUP(tpu_to3_b),
2523};
2524
2525static const char * const audio_clk_groups[] = {
2526 "audio_clkin",
2527 "audio_clkout",
2528};
2529
2530static const char * const avb0_groups[] = {
2531 "avb0_link",
2532 "avb0_magic",
2533 "avb0_phy_int",
2534 "avb0_mdio",
2535 "avb0_rgmii",
2536 "avb0_txcrefclk",
2537 "avb0_avtp_pps",
2538 "avb0_avtp_capture",
2539 "avb0_avtp_match",
2540};
2541
2542static const char * const avb1_groups[] = {
2543 "avb1_link",
2544 "avb1_magic",
2545 "avb1_phy_int",
2546 "avb1_mdio",
2547 "avb1_rgmii",
2548 "avb1_txcrefclk",
2549 "avb1_avtp_pps",
2550 "avb1_avtp_capture",
2551 "avb1_avtp_match",
2552};
2553
2554static const char * const avb2_groups[] = {
2555 "avb2_link",
2556 "avb2_magic",
2557 "avb2_phy_int",
2558 "avb2_mdio",
2559 "avb2_rgmii",
2560 "avb2_txcrefclk",
2561 "avb2_avtp_pps",
2562 "avb2_avtp_capture",
2563 "avb2_avtp_match",
2564};
2565
2566static const char * const canfd0_groups[] = {
2567 "canfd0_data",
2568};
2569
2570static const char * const canfd1_groups[] = {
2571 "canfd1_data",
2572};
2573
2574static const char * const canfd2_groups[] = {
2575 "canfd2_data",
2576};
2577
2578static const char * const canfd3_groups[] = {
2579 "canfd3_data",
2580};
2581
2582static const char * const can_clk_groups[] = {
2583 "can_clk",
2584};
2585
2586static const char * const hscif0_groups[] = {
2587 "hscif0_data",
2588 "hscif0_clk",
2589 "hscif0_ctrl",
2590};
2591
2592static const char * const hscif1_groups[] = {
2593 "hscif1_data_a",
2594 "hscif1_clk_a",
2595 "hscif1_ctrl_a",
2596 "hscif1_data_b",
2597 "hscif1_clk_b",
2598 "hscif1_ctrl_b",
2599};
2600
2601static const char * const hscif2_groups[] = {
2602 "hscif2_data",
2603 "hscif2_clk",
2604 "hscif2_ctrl",
2605};
2606
2607static const char * const hscif3_groups[] = {
2608 "hscif3_data_a",
2609 "hscif3_clk_a",
2610 "hscif3_ctrl_a",
2611 "hscif3_data_b",
2612 "hscif3_clk_b",
2613 "hscif3_ctrl_b",
2614};
2615
2616static const char * const i2c0_groups[] = {
2617 "i2c0",
2618};
2619
2620static const char * const i2c1_groups[] = {
2621 "i2c1",
2622};
2623
2624static const char * const i2c2_groups[] = {
2625 "i2c2",
2626};
2627
2628static const char * const i2c3_groups[] = {
2629 "i2c3",
2630};
2631
2632static const char * const mmc_groups[] = {
2633 "mmc_data1",
2634 "mmc_data4",
2635 "mmc_data8",
2636 "mmc_ctrl",
2637 "mmc_cd",
2638 "mmc_wp",
2639 "mmc_ds",
2640};
2641
2642static const char * const msiof0_groups[] = {
2643 "msiof0_clk",
2644 "msiof0_sync",
2645 "msiof0_ss1",
2646 "msiof0_ss2",
2647 "msiof0_txd",
2648 "msiof0_rxd",
2649};
2650
2651static const char * const msiof1_groups[] = {
2652 "msiof1_clk",
2653 "msiof1_sync",
2654 "msiof1_ss1",
2655 "msiof1_ss2",
2656 "msiof1_txd",
2657 "msiof1_rxd",
2658};
2659
2660static const char * const msiof2_groups[] = {
2661 "msiof2_clk",
2662 "msiof2_sync",
2663 "msiof2_ss1",
2664 "msiof2_ss2",
2665 "msiof2_txd",
2666 "msiof2_rxd",
2667};
2668
2669static const char * const msiof3_groups[] = {
2670 "msiof3_clk",
2671 "msiof3_sync",
2672 "msiof3_ss1",
2673 "msiof3_ss2",
2674 "msiof3_txd",
2675 "msiof3_rxd",
2676};
2677
2678static const char * const msiof4_groups[] = {
2679 "msiof4_clk",
2680 "msiof4_sync",
2681 "msiof4_ss1",
2682 "msiof4_ss2",
2683 "msiof4_txd",
2684 "msiof4_rxd",
2685};
2686
2687static const char * const msiof5_groups[] = {
2688 "msiof5_clk",
2689 "msiof5_sync",
2690 "msiof5_ss1",
2691 "msiof5_ss2",
2692 "msiof5_txd",
2693 "msiof5_rxd",
2694};
2695
2696static const char * const pcie_groups[] = {
2697 "pcie0_clkreq_n",
2698};
2699
2700static const char * const pwm0_groups[] = {
2701 "pwm0_a",
2702 "pwm0_b",
2703};
2704
2705static const char * const pwm1_groups[] = {
2706 "pwm1_a",
2707 "pwm1_b",
2708 "pwm1_c",
2709};
2710
2711static const char * const pwm2_groups[] = {
2712 "pwm2_a",
2713 "pwm2_b",
2714 "pwm2_c",
2715};
2716
2717static const char * const pwm3_groups[] = {
2718 "pwm3_a",
2719 "pwm3_b",
2720 "pwm3_c",
2721};
2722
2723static const char * const pwm4_groups[] = {
2724 "pwm4",
2725};
2726
2727static const char * const qspi0_groups[] = {
2728 "qspi0_ctrl",
2729 "qspi0_data2",
2730 "qspi0_data4",
2731};
2732
2733static const char * const qspi1_groups[] = {
2734 "qspi1_ctrl",
2735 "qspi1_data2",
2736 "qspi1_data4",
2737};
2738
2739static const char * const scif0_groups[] = {
2740 "scif0_data",
2741 "scif0_clk",
2742 "scif0_ctrl",
2743};
2744
2745static const char * const scif1_groups[] = {
2746 "scif1_data_a",
2747 "scif1_clk_a",
2748 "scif1_ctrl_a",
2749 "scif1_data_b",
2750 "scif1_clk_b",
2751 "scif1_ctrl_b",
2752};
2753
2754static const char * const scif3_groups[] = {
2755 "scif3_data_a",
2756 "scif3_clk_a",
2757 "scif3_ctrl_a",
2758 "scif3_data_b",
2759 "scif3_clk_b",
2760 "scif3_ctrl_b",
2761};
2762
2763static const char * const scif4_groups[] = {
2764 "scif4_data",
2765 "scif4_clk",
2766 "scif4_ctrl",
2767};
2768
2769static const char * const scif_clk_groups[] = {
2770 "scif_clk",
2771};
2772
2773static const char * const scif_clk2_groups[] = {
2774 "scif_clk2",
2775};
2776
2777static const char * const ssi_groups[] = {
2778 "ssi_data",
2779 "ssi_ctrl",
2780};
2781
2782static const char * const tpu_groups[] = {
2783 "tpu_to0_a",
2784 "tpu_to0_b",
2785 "tpu_to1_a",
2786 "tpu_to1_b",
2787 "tpu_to2_a",
2788 "tpu_to2_b",
2789 "tpu_to3_a",
2790 "tpu_to3_b",
2791};
2792
2793static const struct sh_pfc_function pinmux_functions[] = {
2794 SH_PFC_FUNCTION(audio_clk),
2795
2796 SH_PFC_FUNCTION(avb0),
2797 SH_PFC_FUNCTION(avb1),
2798 SH_PFC_FUNCTION(avb2),
2799
2800 SH_PFC_FUNCTION(canfd0),
2801 SH_PFC_FUNCTION(canfd1),
2802 SH_PFC_FUNCTION(canfd2),
2803 SH_PFC_FUNCTION(canfd3),
2804 SH_PFC_FUNCTION(can_clk),
2805
2806 SH_PFC_FUNCTION(hscif0),
2807 SH_PFC_FUNCTION(hscif1),
2808 SH_PFC_FUNCTION(hscif2),
2809 SH_PFC_FUNCTION(hscif3),
2810
2811 SH_PFC_FUNCTION(i2c0),
2812 SH_PFC_FUNCTION(i2c1),
2813 SH_PFC_FUNCTION(i2c2),
2814 SH_PFC_FUNCTION(i2c3),
2815
2816 SH_PFC_FUNCTION(mmc),
2817
2818 SH_PFC_FUNCTION(msiof0),
2819 SH_PFC_FUNCTION(msiof1),
2820 SH_PFC_FUNCTION(msiof2),
2821 SH_PFC_FUNCTION(msiof3),
2822 SH_PFC_FUNCTION(msiof4),
2823 SH_PFC_FUNCTION(msiof5),
2824
2825 SH_PFC_FUNCTION(pcie),
2826
2827 SH_PFC_FUNCTION(pwm0),
2828 SH_PFC_FUNCTION(pwm1),
2829 SH_PFC_FUNCTION(pwm2),
2830 SH_PFC_FUNCTION(pwm3),
2831 SH_PFC_FUNCTION(pwm4),
2832
2833 SH_PFC_FUNCTION(qspi0),
2834 SH_PFC_FUNCTION(qspi1),
2835
2836 SH_PFC_FUNCTION(scif0),
2837 SH_PFC_FUNCTION(scif1),
2838 SH_PFC_FUNCTION(scif3),
2839 SH_PFC_FUNCTION(scif4),
2840 SH_PFC_FUNCTION(scif_clk),
2841 SH_PFC_FUNCTION(scif_clk2),
2842
2843 SH_PFC_FUNCTION(ssi),
2844
2845 SH_PFC_FUNCTION(tpu),
2846};
2847
2848static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2849#define F_(x, y) FN_##y
2850#define FM(x) FN_##x
2851 { PINMUX_CFG_REG_VAR("GPSR0", 0xE6050040, 32,
2852 GROUP(-13, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2853 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2854 GROUP(
2855 /* GP0_31_19 RESERVED */
2856 GP_0_18_FN, GPSR0_18,
2857 GP_0_17_FN, GPSR0_17,
2858 GP_0_16_FN, GPSR0_16,
2859 GP_0_15_FN, GPSR0_15,
2860 GP_0_14_FN, GPSR0_14,
2861 GP_0_13_FN, GPSR0_13,
2862 GP_0_12_FN, GPSR0_12,
2863 GP_0_11_FN, GPSR0_11,
2864 GP_0_10_FN, GPSR0_10,
2865 GP_0_9_FN, GPSR0_9,
2866 GP_0_8_FN, GPSR0_8,
2867 GP_0_7_FN, GPSR0_7,
2868 GP_0_6_FN, GPSR0_6,
2869 GP_0_5_FN, GPSR0_5,
2870 GP_0_4_FN, GPSR0_4,
2871 GP_0_3_FN, GPSR0_3,
2872 GP_0_2_FN, GPSR0_2,
2873 GP_0_1_FN, GPSR0_1,
2874 GP_0_0_FN, GPSR0_0, ))
2875 },
2876 { PINMUX_CFG_REG("GPSR1", 0xE6050840, 32, 1, GROUP(
2877 0, 0,
2878 0, 0,
2879 GP_1_29_FN, GPSR1_29,
2880 GP_1_28_FN, GPSR1_28,
2881 GP_1_27_FN, GPSR1_27,
2882 GP_1_26_FN, GPSR1_26,
2883 GP_1_25_FN, GPSR1_25,
2884 GP_1_24_FN, GPSR1_24,
2885 GP_1_23_FN, GPSR1_23,
2886 GP_1_22_FN, GPSR1_22,
2887 GP_1_21_FN, GPSR1_21,
2888 GP_1_20_FN, GPSR1_20,
2889 GP_1_19_FN, GPSR1_19,
2890 GP_1_18_FN, GPSR1_18,
2891 GP_1_17_FN, GPSR1_17,
2892 GP_1_16_FN, GPSR1_16,
2893 GP_1_15_FN, GPSR1_15,
2894 GP_1_14_FN, GPSR1_14,
2895 GP_1_13_FN, GPSR1_13,
2896 GP_1_12_FN, GPSR1_12,
2897 GP_1_11_FN, GPSR1_11,
2898 GP_1_10_FN, GPSR1_10,
2899 GP_1_9_FN, GPSR1_9,
2900 GP_1_8_FN, GPSR1_8,
2901 GP_1_7_FN, GPSR1_7,
2902 GP_1_6_FN, GPSR1_6,
2903 GP_1_5_FN, GPSR1_5,
2904 GP_1_4_FN, GPSR1_4,
2905 GP_1_3_FN, GPSR1_3,
2906 GP_1_2_FN, GPSR1_2,
2907 GP_1_1_FN, GPSR1_1,
2908 GP_1_0_FN, GPSR1_0, ))
2909 },
2910 { PINMUX_CFG_REG_VAR("GPSR2", 0xE6058040, 32,
2911 GROUP(-12, 1, -1, 1, -1, 1, 1, 1, 1, 1, 1,
2912 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2913 GROUP(
2914 /* GP2_31_20 RESERVED */
2915 GP_2_19_FN, GPSR2_19,
2916 /* GP2_18 RESERVED */
2917 GP_2_17_FN, GPSR2_17,
2918 /* GP2_16 RESERVED */
2919 GP_2_15_FN, GPSR2_15,
2920 GP_2_14_FN, GPSR2_14,
2921 GP_2_13_FN, GPSR2_13,
2922 GP_2_12_FN, GPSR2_12,
2923 GP_2_11_FN, GPSR2_11,
2924 GP_2_10_FN, GPSR2_10,
2925 GP_2_9_FN, GPSR2_9,
2926 GP_2_8_FN, GPSR2_8,
2927 GP_2_7_FN, GPSR2_7,
2928 GP_2_6_FN, GPSR2_6,
2929 GP_2_5_FN, GPSR2_5,
2930 GP_2_4_FN, GPSR2_4,
2931 GP_2_3_FN, GPSR2_3,
2932 GP_2_2_FN, GPSR2_2,
2933 GP_2_1_FN, GPSR2_1,
2934 GP_2_0_FN, GPSR2_0, ))
2935 },
2936 { PINMUX_CFG_REG("GPSR3", 0xE6058840, 32, 1, GROUP(
2937 GP_3_31_FN, GPSR3_31,
2938 GP_3_30_FN, GPSR3_30,
2939 GP_3_29_FN, GPSR3_29,
2940 GP_3_28_FN, GPSR3_28,
2941 GP_3_27_FN, GPSR3_27,
2942 GP_3_26_FN, GPSR3_26,
2943 GP_3_25_FN, GPSR3_25,
2944 GP_3_24_FN, GPSR3_24,
2945 GP_3_23_FN, GPSR3_23,
2946 GP_3_22_FN, GPSR3_22,
2947 GP_3_21_FN, GPSR3_21,
2948 GP_3_20_FN, GPSR3_20,
2949 GP_3_19_FN, GPSR3_19,
2950 GP_3_18_FN, GPSR3_18,
2951 GP_3_17_FN, GPSR3_17,
2952 GP_3_16_FN, GPSR3_16,
2953 GP_3_15_FN, GPSR3_15,
2954 GP_3_14_FN, GPSR3_14,
2955 GP_3_13_FN, GPSR3_13,
2956 GP_3_12_FN, GPSR3_12,
2957 GP_3_11_FN, GPSR3_11,
2958 GP_3_10_FN, GPSR3_10,
2959 GP_3_9_FN, GPSR3_9,
2960 GP_3_8_FN, GPSR3_8,
2961 GP_3_7_FN, GPSR3_7,
2962 GP_3_6_FN, GPSR3_6,
2963 GP_3_5_FN, GPSR3_5,
2964 GP_3_4_FN, GPSR3_4,
2965 GP_3_3_FN, GPSR3_3,
2966 GP_3_2_FN, GPSR3_2,
2967 GP_3_1_FN, GPSR3_1,
2968 GP_3_0_FN, GPSR3_0, ))
2969 },
2970 { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060040, 32,
2971 GROUP(-7, 1, 1, -1, 1, -5, 1, 1, 1, 1, 1,
2972 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2973 GROUP(
2974 /* GP4_31_25 RESERVED */
2975 GP_4_24_FN, GPSR4_24,
2976 GP_4_23_FN, GPSR4_23,
2977 /* GP4_22 RESERVED */
2978 GP_4_21_FN, GPSR4_21,
2979 /* GP4_20_16 RESERVED */
2980 GP_4_15_FN, GPSR4_15,
2981 GP_4_14_FN, GPSR4_14,
2982 GP_4_13_FN, GPSR4_13,
2983 GP_4_12_FN, GPSR4_12,
2984 GP_4_11_FN, GPSR4_11,
2985 GP_4_10_FN, GPSR4_10,
2986 GP_4_9_FN, GPSR4_9,
2987 GP_4_8_FN, GPSR4_8,
2988 GP_4_7_FN, GPSR4_7,
2989 GP_4_6_FN, GPSR4_6,
2990 GP_4_5_FN, GPSR4_5,
2991 GP_4_4_FN, GPSR4_4,
2992 GP_4_3_FN, GPSR4_3,
2993 GP_4_2_FN, GPSR4_2,
2994 GP_4_1_FN, GPSR4_1,
2995 GP_4_0_FN, GPSR4_0, ))
2996 },
2997 { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060840, 32,
2998 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2999 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3000 GROUP(
3001 /* GP5_31_21 RESERVED */
3002 GP_5_20_FN, GPSR5_20,
3003 GP_5_19_FN, GPSR5_19,
3004 GP_5_18_FN, GPSR5_18,
3005 GP_5_17_FN, GPSR5_17,
3006 GP_5_16_FN, GPSR5_16,
3007 GP_5_15_FN, GPSR5_15,
3008 GP_5_14_FN, GPSR5_14,
3009 GP_5_13_FN, GPSR5_13,
3010 GP_5_12_FN, GPSR5_12,
3011 GP_5_11_FN, GPSR5_11,
3012 GP_5_10_FN, GPSR5_10,
3013 GP_5_9_FN, GPSR5_9,
3014 GP_5_8_FN, GPSR5_8,
3015 GP_5_7_FN, GPSR5_7,
3016 GP_5_6_FN, GPSR5_6,
3017 GP_5_5_FN, GPSR5_5,
3018 GP_5_4_FN, GPSR5_4,
3019 GP_5_3_FN, GPSR5_3,
3020 GP_5_2_FN, GPSR5_2,
3021 GP_5_1_FN, GPSR5_1,
3022 GP_5_0_FN, GPSR5_0, ))
3023 },
3024 { PINMUX_CFG_REG_VAR("GPSR6", 0xE6061040, 32,
3025 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3026 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3027 GROUP(
3028 /* GP6_31_21 RESERVED */
3029 GP_6_20_FN, GPSR6_20,
3030 GP_6_19_FN, GPSR6_19,
3031 GP_6_18_FN, GPSR6_18,
3032 GP_6_17_FN, GPSR6_17,
3033 GP_6_16_FN, GPSR6_16,
3034 GP_6_15_FN, GPSR6_15,
3035 GP_6_14_FN, GPSR6_14,
3036 GP_6_13_FN, GPSR6_13,
3037 GP_6_12_FN, GPSR6_12,
3038 GP_6_11_FN, GPSR6_11,
3039 GP_6_10_FN, GPSR6_10,
3040 GP_6_9_FN, GPSR6_9,
3041 GP_6_8_FN, GPSR6_8,
3042 GP_6_7_FN, GPSR6_7,
3043 GP_6_6_FN, GPSR6_6,
3044 GP_6_5_FN, GPSR6_5,
3045 GP_6_4_FN, GPSR6_4,
3046 GP_6_3_FN, GPSR6_3,
3047 GP_6_2_FN, GPSR6_2,
3048 GP_6_1_FN, GPSR6_1,
3049 GP_6_0_FN, GPSR6_0, ))
3050 },
3051 { PINMUX_CFG_REG_VAR("GPSR7", 0xE6061840, 32,
3052 GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3053 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3054 GROUP(
3055 /* GP7_31_21 RESERVED */
3056 GP_7_20_FN, GPSR7_20,
3057 GP_7_19_FN, GPSR7_19,
3058 GP_7_18_FN, GPSR7_18,
3059 GP_7_17_FN, GPSR7_17,
3060 GP_7_16_FN, GPSR7_16,
3061 GP_7_15_FN, GPSR7_15,
3062 GP_7_14_FN, GPSR7_14,
3063 GP_7_13_FN, GPSR7_13,
3064 GP_7_12_FN, GPSR7_12,
3065 GP_7_11_FN, GPSR7_11,
3066 GP_7_10_FN, GPSR7_10,
3067 GP_7_9_FN, GPSR7_9,
3068 GP_7_8_FN, GPSR7_8,
3069 GP_7_7_FN, GPSR7_7,
3070 GP_7_6_FN, GPSR7_6,
3071 GP_7_5_FN, GPSR7_5,
3072 GP_7_4_FN, GPSR7_4,
3073 GP_7_3_FN, GPSR7_3,
3074 GP_7_2_FN, GPSR7_2,
3075 GP_7_1_FN, GPSR7_1,
3076 GP_7_0_FN, GPSR7_0, ))
3077 },
3078#undef F_
3079#undef FM
3080
3081#define F_(x, y) x,
3082#define FM(x) FN_##x,
3083 { PINMUX_CFG_REG("IP0SR0", 0xE6050060, 32, 4, GROUP(
3084 IP0SR0_31_28
3085 IP0SR0_27_24
3086 IP0SR0_23_20
3087 IP0SR0_19_16
3088 IP0SR0_15_12
3089 IP0SR0_11_8
3090 IP0SR0_7_4
3091 IP0SR0_3_0))
3092 },
3093 { PINMUX_CFG_REG("IP1SR0", 0xE6050064, 32, 4, GROUP(
3094 IP1SR0_31_28
3095 IP1SR0_27_24
3096 IP1SR0_23_20
3097 IP1SR0_19_16
3098 IP1SR0_15_12
3099 IP1SR0_11_8
3100 IP1SR0_7_4
3101 IP1SR0_3_0))
3102 },
3103 { PINMUX_CFG_REG_VAR("IP2SR0", 0xE6050068, 32,
3104 GROUP(-20, 4, 4, 4),
3105 GROUP(
3106 /* IP2SR0_31_12 RESERVED */
3107 IP2SR0_11_8
3108 IP2SR0_7_4
3109 IP2SR0_3_0))
3110 },
3111 { PINMUX_CFG_REG("IP0SR1", 0xE6050860, 32, 4, GROUP(
3112 IP0SR1_31_28
3113 IP0SR1_27_24
3114 IP0SR1_23_20
3115 IP0SR1_19_16
3116 IP0SR1_15_12
3117 IP0SR1_11_8
3118 IP0SR1_7_4
3119 IP0SR1_3_0))
3120 },
3121 { PINMUX_CFG_REG("IP1SR1", 0xE6050864, 32, 4, GROUP(
3122 IP1SR1_31_28
3123 IP1SR1_27_24
3124 IP1SR1_23_20
3125 IP1SR1_19_16
3126 IP1SR1_15_12
3127 IP1SR1_11_8
3128 IP1SR1_7_4
3129 IP1SR1_3_0))
3130 },
3131 { PINMUX_CFG_REG("IP2SR1", 0xE6050868, 32, 4, GROUP(
3132 IP2SR1_31_28
3133 IP2SR1_27_24
3134 IP2SR1_23_20
3135 IP2SR1_19_16
3136 IP2SR1_15_12
3137 IP2SR1_11_8
3138 IP2SR1_7_4
3139 IP2SR1_3_0))
3140 },
3141 { PINMUX_CFG_REG_VAR("IP3SR1", 0xE605086C, 32,
3142 GROUP(-8, 4, 4, 4, 4, 4, 4),
3143 GROUP(
3144 /* IP3SR1_31_24 RESERVED */
3145 IP3SR1_23_20
3146 IP3SR1_19_16
3147 IP3SR1_15_12
3148 IP3SR1_11_8
3149 IP3SR1_7_4
3150 IP3SR1_3_0))
3151 },
3152 { PINMUX_CFG_REG("IP0SR2", 0xE6058060, 32, 4, GROUP(
3153 IP0SR2_31_28
3154 IP0SR2_27_24
3155 IP0SR2_23_20
3156 IP0SR2_19_16
3157 IP0SR2_15_12
3158 IP0SR2_11_8
3159 IP0SR2_7_4
3160 IP0SR2_3_0))
3161 },
3162 { PINMUX_CFG_REG("IP1SR2", 0xE6058064, 32, 4, GROUP(
3163 IP1SR2_31_28
3164 IP1SR2_27_24
3165 IP1SR2_23_20
3166 IP1SR2_19_16
3167 IP1SR2_15_12
3168 IP1SR2_11_8
3169 IP1SR2_7_4
3170 IP1SR2_3_0))
3171 },
3172 { PINMUX_CFG_REG_VAR("IP2SR2", 0xE6058068, 32,
3173 GROUP(-16, 4, -4, 4, -4),
3174 GROUP(
3175 /* IP2SR2_31_16 RESERVED */
3176 IP2SR2_15_12
3177 /* IP2SR2_11_8 RESERVED */
3178 IP2SR2_7_4
3179 /* IP2SR2_3_0 RESERVED */))
3180 },
3181 { PINMUX_CFG_REG("IP0SR3", 0xE6058860, 32, 4, GROUP(
3182 IP0SR3_31_28
3183 IP0SR3_27_24
3184 IP0SR3_23_20
3185 IP0SR3_19_16
3186 IP0SR3_15_12
3187 IP0SR3_11_8
3188 IP0SR3_7_4
3189 IP0SR3_3_0))
3190 },
3191 { PINMUX_CFG_REG("IP1SR3", 0xE6058864, 32, 4, GROUP(
3192 IP1SR3_31_28
3193 IP1SR3_27_24
3194 IP1SR3_23_20
3195 IP1SR3_19_16
3196 IP1SR3_15_12
3197 IP1SR3_11_8
3198 IP1SR3_7_4
3199 IP1SR3_3_0))
3200 },
3201 { PINMUX_CFG_REG("IP2SR3", 0xE6058868, 32, 4, GROUP(
3202 IP2SR3_31_28
3203 IP2SR3_27_24
3204 IP2SR3_23_20
3205 IP2SR3_19_16
3206 IP2SR3_15_12
3207 IP2SR3_11_8
3208 IP2SR3_7_4
3209 IP2SR3_3_0))
3210 },
3211 { PINMUX_CFG_REG("IP3SR3", 0xE605886C, 32, 4, GROUP(
3212 IP3SR3_31_28
3213 IP3SR3_27_24
3214 IP3SR3_23_20
3215 IP3SR3_19_16
3216 IP3SR3_15_12
3217 IP3SR3_11_8
3218 IP3SR3_7_4
3219 IP3SR3_3_0))
3220 },
3221 { PINMUX_CFG_REG("IP0SR4", 0xE6060060, 32, 4, GROUP(
3222 IP0SR4_31_28
3223 IP0SR4_27_24
3224 IP0SR4_23_20
3225 IP0SR4_19_16
3226 IP0SR4_15_12
3227 IP0SR4_11_8
3228 IP0SR4_7_4
3229 IP0SR4_3_0))
3230 },
3231 { PINMUX_CFG_REG("IP1SR4", 0xE6060064, 32, 4, GROUP(
3232 IP1SR4_31_28
3233 IP1SR4_27_24
3234 IP1SR4_23_20
3235 IP1SR4_19_16
3236 IP1SR4_15_12
3237 IP1SR4_11_8
3238 IP1SR4_7_4
3239 IP1SR4_3_0))
3240 },
3241 { PINMUX_CFG_REG_VAR("IP2SR4", 0xE6060068, 32,
3242 GROUP(4, -4, 4, -20),
3243 GROUP(
3244 IP2SR4_31_28
3245 /* IP2SR4_27_24 RESERVED */
3246 IP2SR4_23_20
3247 /* IP2SR4_19_0 RESERVED */))
3248 },
3249 { PINMUX_CFG_REG_VAR("IP3SR4", 0xE606006C, 32,
3250 GROUP(-28, 4),
3251 GROUP(
3252 /* IP3SR4_31_4 RESERVED */
3253 IP3SR4_3_0))
3254 },
3255 { PINMUX_CFG_REG("IP0SR5", 0xE6060860, 32, 4, GROUP(
3256 IP0SR5_31_28
3257 IP0SR5_27_24
3258 IP0SR5_23_20
3259 IP0SR5_19_16
3260 IP0SR5_15_12
3261 IP0SR5_11_8
3262 IP0SR5_7_4
3263 IP0SR5_3_0))
3264 },
3265 { PINMUX_CFG_REG("IP1SR5", 0xE6060864, 32, 4, GROUP(
3266 IP1SR5_31_28
3267 IP1SR5_27_24
3268 IP1SR5_23_20
3269 IP1SR5_19_16
3270 IP1SR5_15_12
3271 IP1SR5_11_8
3272 IP1SR5_7_4
3273 IP1SR5_3_0))
3274 },
3275 { PINMUX_CFG_REG_VAR("IP2SR5", 0xE6060868, 32,
3276 GROUP(-12, 4, 4, 4, 4, 4),
3277 GROUP(
3278 /* IP2SR5_31_20 RESERVED */
3279 IP2SR5_19_16
3280 IP2SR5_15_12
3281 IP2SR5_11_8
3282 IP2SR5_7_4
3283 IP2SR5_3_0))
3284 },
3285 { PINMUX_CFG_REG("IP0SR6", 0xE6061060, 32, 4, GROUP(
3286 IP0SR6_31_28
3287 IP0SR6_27_24
3288 IP0SR6_23_20
3289 IP0SR6_19_16
3290 IP0SR6_15_12
3291 IP0SR6_11_8
3292 IP0SR6_7_4
3293 IP0SR6_3_0))
3294 },
3295 { PINMUX_CFG_REG("IP1SR6", 0xE6061064, 32, 4, GROUP(
3296 IP1SR6_31_28
3297 IP1SR6_27_24
3298 IP1SR6_23_20
3299 IP1SR6_19_16
3300 IP1SR6_15_12
3301 IP1SR6_11_8
3302 IP1SR6_7_4
3303 IP1SR6_3_0))
3304 },
3305 { PINMUX_CFG_REG_VAR("IP2SR6", 0xE6061068, 32,
3306 GROUP(-12, 4, 4, 4, 4, 4),
3307 GROUP(
3308 /* IP2SR6_31_20 RESERVED */
3309 IP2SR6_19_16
3310 IP2SR6_15_12
3311 IP2SR6_11_8
3312 IP2SR6_7_4
3313 IP2SR6_3_0))
3314 },
3315 { PINMUX_CFG_REG("IP0SR7", 0xE6061860, 32, 4, GROUP(
3316 IP0SR7_31_28
3317 IP0SR7_27_24
3318 IP0SR7_23_20
3319 IP0SR7_19_16
3320 IP0SR7_15_12
3321 IP0SR7_11_8
3322 IP0SR7_7_4
3323 IP0SR7_3_0))
3324 },
3325 { PINMUX_CFG_REG("IP1SR7", 0xE6061864, 32, 4, GROUP(
3326 IP1SR7_31_28
3327 IP1SR7_27_24
3328 IP1SR7_23_20
3329 IP1SR7_19_16
3330 IP1SR7_15_12
3331 IP1SR7_11_8
3332 IP1SR7_7_4
3333 IP1SR7_3_0))
3334 },
3335 { PINMUX_CFG_REG_VAR("IP2SR7", 0xE6061868, 32,
3336 GROUP(-12, 4, 4, 4, 4, 4),
3337 GROUP(
3338 /* IP2SR7_31_20 RESERVED */
3339 IP2SR7_19_16
3340 IP2SR7_15_12
3341 IP2SR7_11_8
3342 IP2SR7_7_4
3343 IP2SR7_3_0))
3344 },
3345#undef F_
3346#undef FM
3347
3348#define F_(x, y) x,
3349#define FM(x) FN_##x,
3350 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE6060100, 32,
3351 GROUP(-24, 1, 1, 1, 1, 1, 1, 1, 1),
3352 GROUP(
3353 /* RESERVED 31-8 */
3354 MOD_SEL4_7
3355 MOD_SEL4_6
3356 MOD_SEL4_5
3357 MOD_SEL4_4
3358 MOD_SEL4_3
3359 MOD_SEL4_2
3360 MOD_SEL4_1
3361 MOD_SEL4_0))
3362 },
3363 { },
3364};
3365
3366static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3367 { PINMUX_DRIVE_REG("DRV0CTRL0", 0xE6050080) {
3368 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3369 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3370 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3371 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3372 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3373 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3374 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3375 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3376 } },
3377 { PINMUX_DRIVE_REG("DRV1CTRL0", 0xE6050084) {
3378 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3379 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3380 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3381 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3382 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3383 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3384 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3385 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3386 } },
3387 { PINMUX_DRIVE_REG("DRV2CTRL0", 0xE6050088) {
3388 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3389 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3390 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3391 } },
3392 { PINMUX_DRIVE_REG("DRV0CTRL1", 0xE6050880) {
3393 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
3394 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
3395 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
3396 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
3397 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
3398 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
3399 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
3400 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3401 } },
3402 { PINMUX_DRIVE_REG("DRV1CTRL1", 0xE6050884) {
3403 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
3404 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
3405 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
3406 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
3407 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
3408 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
3409 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3410 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3411 } },
3412 { PINMUX_DRIVE_REG("DRV2CTRL1", 0xE6050888) {
3413 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
3414 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
3415 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
3416 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
3417 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
3418 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
3419 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
3420 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3421 } },
3422 { PINMUX_DRIVE_REG("DRV3CTRL1", 0xE605088C) {
3423 { RCAR_GP_PIN(1, 29), 20, 2 }, /* ERROROUTC_N */
3424 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
3425 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
3426 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
3427 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
3428 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3429 } },
3430 { PINMUX_DRIVE_REG("DRV0CTRL2", 0xE6058080) {
3431 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
3432 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
3433 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
3434 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
3435 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
3436 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
3437 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
3438 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3439 } },
3440 { PINMUX_DRIVE_REG("DRV1CTRL2", 0xE6058084) {
3441 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
3442 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
3443 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
3444 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
3445 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
3446 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
3447 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3448 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3449 } },
3450 { PINMUX_DRIVE_REG("DRV2CTRL2", 0xE6058088) {
3451 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD1_RX */
3452 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD1_TX */
3453 } },
3454 { PINMUX_DRIVE_REG("DRV0CTRL3", 0xE6058880) {
3455 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
3456 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
3457 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
3458 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
3459 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
3460 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
3461 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
3462 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3463 } },
3464 { PINMUX_DRIVE_REG("DRV1CTRL3", 0xE6058884) {
3465 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
3466 { RCAR_GP_PIN(3, 14), 24, 2 }, /* PWM2 */
3467 { RCAR_GP_PIN(3, 13), 20, 2 }, /* PWM1 */
3468 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
3469 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
3470 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
3471 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3472 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3473 } },
3474 { PINMUX_DRIVE_REG("DRV2CTRL3", 0xE6058888) {
3475 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
3476 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
3477 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
3478 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
3479 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
3480 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
3481 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
3482 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3483 } },
3484 { PINMUX_DRIVE_REG("DRV3CTRL3", 0xE605888C) {
3485 { RCAR_GP_PIN(3, 31), 28, 2 }, /* TCLK4 */
3486 { RCAR_GP_PIN(3, 30), 24, 2 }, /* TCLK3 */
3487 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
3488 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
3489 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
3490 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
3491 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
3492 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3493 } },
3494 { PINMUX_DRIVE_REG("DRV0CTRL4", 0xE6060080) {
3495 { RCAR_GP_PIN(4, 7), 28, 3 }, /* SDA3 */
3496 { RCAR_GP_PIN(4, 6), 24, 3 }, /* SCL3 */
3497 { RCAR_GP_PIN(4, 5), 20, 3 }, /* SDA2 */
3498 { RCAR_GP_PIN(4, 4), 16, 3 }, /* SCL2 */
3499 { RCAR_GP_PIN(4, 3), 12, 3 }, /* SDA1 */
3500 { RCAR_GP_PIN(4, 2), 8, 3 }, /* SCL1 */
3501 { RCAR_GP_PIN(4, 1), 4, 3 }, /* SDA0 */
3502 { RCAR_GP_PIN(4, 0), 0, 3 }, /* SCL0 */
3503 } },
3504 { PINMUX_DRIVE_REG("DRV1CTRL4", 0xE6060084) {
3505 { RCAR_GP_PIN(4, 15), 28, 3 }, /* PWM4 */
3506 { RCAR_GP_PIN(4, 14), 24, 3 }, /* PWM3 */
3507 { RCAR_GP_PIN(4, 13), 20, 3 }, /* HSCK2 */
3508 { RCAR_GP_PIN(4, 12), 16, 3 }, /* HCTS2_N */
3509 { RCAR_GP_PIN(4, 11), 12, 3 }, /* SCIF_CLK2 */
3510 { RCAR_GP_PIN(4, 10), 8, 3 }, /* HRTS2_N */
3511 { RCAR_GP_PIN(4, 9), 4, 3 }, /* HTX2 */
3512 { RCAR_GP_PIN(4, 8), 0, 3 }, /* HRX2 */
3513 } },
3514 { PINMUX_DRIVE_REG("DRV2CTRL4", 0xE6060088) {
3515 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
3516 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3517 } },
3518 { PINMUX_DRIVE_REG("DRV3CTRL4", 0xE606008C) {
3519 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3520 } },
3521 { PINMUX_DRIVE_REG("DRV0CTRL5", 0xE6060880) {
3522 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
3523 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
3524 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
3525 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
3526 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
3527 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
3528 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
3529 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3530 } },
3531 { PINMUX_DRIVE_REG("DRV1CTRL5", 0xE6060884) {
3532 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
3533 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
3534 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
3535 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
3536 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
3537 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
3538 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3539 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3540 } },
3541 { PINMUX_DRIVE_REG("DRV2CTRL5", 0xE6060888) {
3542 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
3543 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
3544 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
3545 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
3546 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3547 } },
3548 { PINMUX_DRIVE_REG("DRV0CTRL6", 0xE6061080) {
3549 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
3550 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
3551 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
3552 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
3553 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
3554 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
3555 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
3556 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
3557 } },
3558 { PINMUX_DRIVE_REG("DRV1CTRL6", 0xE6061084) {
3559 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
3560 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
3561 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
3562 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
3563 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3564 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
3565 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
3566 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
3567 } },
3568 { PINMUX_DRIVE_REG("DRV2CTRL6", 0xE6061088) {
3569 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
3570 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
3571 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
3572 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
3573 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
3574 } },
3575 { PINMUX_DRIVE_REG("DRV0CTRL7", 0xE6061880) {
3576 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
3577 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
3578 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
3579 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
3580 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
3581 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
3582 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
3583 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
3584 } },
3585 { PINMUX_DRIVE_REG("DRV1CTRL7", 0xE6061884) {
3586 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
3587 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
3588 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
3589 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
3590 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
3591 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
3592 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
3593 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
3594 } },
3595 { PINMUX_DRIVE_REG("DRV2CTRL7", 0xE6061888) {
3596 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
3597 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
3598 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
3599 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
3600 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
3601 } },
3602 { },
3603};
3604
3605enum ioctrl_regs {
3606 POC0,
3607 POC1,
3608 POC3,
3609 POC4,
3610 POC5,
3611 POC6,
3612 POC7,
3613};
3614
3615static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3616 [POC0] = { 0xE60500A0, },
3617 [POC1] = { .reg: 0xE60508A0, },
3618 [POC3] = { .reg: 0xE60588A0, },
3619 [POC4] = { .reg: 0xE60600A0, },
3620 [POC5] = { .reg: 0xE60608A0, },
3621 [POC6] = { .reg: 0xE60610A0, },
3622 [POC7] = { .reg: 0xE60618A0, },
3623 { /* sentinel */ },
3624};
3625
3626static int r8a779h0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
3627{
3628 int bit = pin & 0x1f;
3629
3630 switch (pin) {
3631 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
3632 *pocctrl = pinmux_ioctrl_regs[POC0].reg;
3633 return bit;
3634
3635 case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 28):
3636 *pocctrl = pinmux_ioctrl_regs[POC1].reg;
3637 return bit;
3638
3639 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
3640 *pocctrl = pinmux_ioctrl_regs[POC3].reg;
3641 return bit;
3642
3643 case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 13):
3644 *pocctrl = pinmux_ioctrl_regs[POC4].reg;
3645 return bit;
3646
3647 case PIN_VDDQ_AVB2:
3648 *pocctrl = pinmux_ioctrl_regs[POC5].reg;
3649 return 0;
3650
3651 case PIN_VDDQ_AVB1:
3652 *pocctrl = pinmux_ioctrl_regs[POC6].reg;
3653 return 0;
3654
3655 case PIN_VDDQ_AVB0:
3656 *pocctrl = pinmux_ioctrl_regs[POC7].reg;
3657 return 0;
3658
3659 default:
3660 return -EINVAL;
3661 }
3662}
3663
3664static const struct pinmux_bias_reg pinmux_bias_regs[] = {
3665 { PINMUX_BIAS_REG("PUEN0", 0xE60500C0, "PUD0", 0xE60500E0) {
3666 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
3667 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
3668 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
3669 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
3670 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
3671 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
3672 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
3673 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
3674 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
3675 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
3676 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
3677 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
3678 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
3679 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
3680 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
3681 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
3682 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
3683 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
3684 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
3685 [19] = SH_PFC_PIN_NONE,
3686 [20] = SH_PFC_PIN_NONE,
3687 [21] = SH_PFC_PIN_NONE,
3688 [22] = SH_PFC_PIN_NONE,
3689 [23] = SH_PFC_PIN_NONE,
3690 [24] = SH_PFC_PIN_NONE,
3691 [25] = SH_PFC_PIN_NONE,
3692 [26] = SH_PFC_PIN_NONE,
3693 [27] = SH_PFC_PIN_NONE,
3694 [28] = SH_PFC_PIN_NONE,
3695 [29] = SH_PFC_PIN_NONE,
3696 [30] = SH_PFC_PIN_NONE,
3697 [31] = SH_PFC_PIN_NONE,
3698 } },
3699 { PINMUX_BIAS_REG("PUEN1", 0xE60508C0, "PUD1", 0xE60508E0) {
3700 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
3701 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
3702 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
3703 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
3704 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
3705 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
3706 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
3707 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
3708 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
3709 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
3710 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
3711 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
3712 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */
3713 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
3714 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
3715 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
3716 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */
3717 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
3718 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
3719 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
3720 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
3721 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
3722 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
3723 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
3724 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */
3725 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
3726 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
3727 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
3728 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */
3729 [29] = RCAR_GP_PIN(1, 29), /* ERROROUTC_N */
3730 [30] = SH_PFC_PIN_NONE,
3731 [31] = SH_PFC_PIN_NONE,
3732 } },
3733 { PINMUX_BIAS_REG("PUEN2", 0xE60580C0, "PUD2", 0xE60580E0) {
3734 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
3735 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
3736 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
3737 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
3738 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
3739 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
3740 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
3741 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
3742 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
3743 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
3744 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
3745 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
3746 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
3747 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
3748 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
3749 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
3750 [16] = SH_PFC_PIN_NONE,
3751 [17] = RCAR_GP_PIN(2, 17), /* CANFD1_TX */
3752 [18] = SH_PFC_PIN_NONE,
3753 [19] = RCAR_GP_PIN(2, 19), /* CANFD1_RX */
3754 [20] = SH_PFC_PIN_NONE,
3755 [21] = SH_PFC_PIN_NONE,
3756 [22] = SH_PFC_PIN_NONE,
3757 [23] = SH_PFC_PIN_NONE,
3758 [24] = SH_PFC_PIN_NONE,
3759 [25] = SH_PFC_PIN_NONE,
3760 [26] = SH_PFC_PIN_NONE,
3761 [27] = SH_PFC_PIN_NONE,
3762 [28] = SH_PFC_PIN_NONE,
3763 [29] = SH_PFC_PIN_NONE,
3764 [30] = SH_PFC_PIN_NONE,
3765 [31] = SH_PFC_PIN_NONE,
3766 } },
3767 { PINMUX_BIAS_REG("PUEN3", 0xE60588C0, "PUD3", 0xE60588E0) {
3768 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
3769 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
3770 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
3771 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
3772 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
3773 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
3774 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
3775 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
3776 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
3777 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
3778 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
3779 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */
3780 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */
3781 [13] = RCAR_GP_PIN(3, 13), /* PWM1 */
3782 [14] = RCAR_GP_PIN(3, 14), /* PWM2 */
3783 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
3784 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
3785 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
3786 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
3787 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
3788 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
3789 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
3790 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
3791 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
3792 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
3793 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
3794 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
3795 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
3796 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
3797 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
3798 [30] = RCAR_GP_PIN(3, 30), /* TCLK3 */
3799 [31] = RCAR_GP_PIN(3, 31), /* TCLK4 */
3800 } },
3801 { PINMUX_BIAS_REG("PUEN4", 0xE60600C0, "PUD4", 0xE60600E0) {
3802 [ 0] = RCAR_GP_PIN(4, 0), /* SCL0 */
3803 [ 1] = RCAR_GP_PIN(4, 1), /* SDA0 */
3804 [ 2] = RCAR_GP_PIN(4, 2), /* SCL1 */
3805 [ 3] = RCAR_GP_PIN(4, 3), /* SDA1 */
3806 [ 4] = RCAR_GP_PIN(4, 4), /* SCL2 */
3807 [ 5] = RCAR_GP_PIN(4, 5), /* SDA2 */
3808 [ 6] = RCAR_GP_PIN(4, 6), /* SCL3 */
3809 [ 7] = RCAR_GP_PIN(4, 7), /* SDA3 */
3810 [ 8] = RCAR_GP_PIN(4, 8), /* HRX2 */
3811 [ 9] = RCAR_GP_PIN(4, 9), /* HTX2 */
3812 [10] = RCAR_GP_PIN(4, 10), /* HRTS2_N */
3813 [11] = RCAR_GP_PIN(4, 11), /* SCIF_CLK2 */
3814 [12] = RCAR_GP_PIN(4, 12), /* HCTS2_N */
3815 [13] = RCAR_GP_PIN(4, 13), /* HSCK2 */
3816 [14] = RCAR_GP_PIN(4, 14), /* PWM3 */
3817 [15] = RCAR_GP_PIN(4, 15), /* PWM4 */
3818 [16] = SH_PFC_PIN_NONE,
3819 [17] = SH_PFC_PIN_NONE,
3820 [18] = SH_PFC_PIN_NONE,
3821 [19] = SH_PFC_PIN_NONE,
3822 [20] = SH_PFC_PIN_NONE,
3823 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
3824 [22] = SH_PFC_PIN_NONE,
3825 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */
3826 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */
3827 [25] = SH_PFC_PIN_NONE,
3828 [26] = SH_PFC_PIN_NONE,
3829 [27] = SH_PFC_PIN_NONE,
3830 [28] = SH_PFC_PIN_NONE,
3831 [29] = SH_PFC_PIN_NONE,
3832 [30] = SH_PFC_PIN_NONE,
3833 [31] = SH_PFC_PIN_NONE,
3834 } },
3835 { PINMUX_BIAS_REG("PUEN5", 0xE60608C0, "PUD5", 0xE60608E0) {
3836 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
3837 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
3838 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
3839 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
3840 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
3841 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
3842 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
3843 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
3844 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
3845 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
3846 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
3847 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
3848 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
3849 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
3850 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
3851 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
3852 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
3853 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
3854 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
3855 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
3856 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
3857 [21] = SH_PFC_PIN_NONE,
3858 [22] = SH_PFC_PIN_NONE,
3859 [23] = SH_PFC_PIN_NONE,
3860 [24] = SH_PFC_PIN_NONE,
3861 [25] = SH_PFC_PIN_NONE,
3862 [26] = SH_PFC_PIN_NONE,
3863 [27] = SH_PFC_PIN_NONE,
3864 [28] = SH_PFC_PIN_NONE,
3865 [29] = SH_PFC_PIN_NONE,
3866 [30] = SH_PFC_PIN_NONE,
3867 [31] = SH_PFC_PIN_NONE,
3868 } },
3869 { PINMUX_BIAS_REG("PUEN6", 0xE60610C0, "PUD6", 0xE60610E0) {
3870 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
3871 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
3872 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
3873 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
3874 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
3875 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
3876 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
3877 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
3878 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
3879 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
3880 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
3881 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
3882 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
3883 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
3884 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
3885 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
3886 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
3887 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
3888 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
3889 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
3890 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
3891 [21] = SH_PFC_PIN_NONE,
3892 [22] = SH_PFC_PIN_NONE,
3893 [23] = SH_PFC_PIN_NONE,
3894 [24] = SH_PFC_PIN_NONE,
3895 [25] = SH_PFC_PIN_NONE,
3896 [26] = SH_PFC_PIN_NONE,
3897 [27] = SH_PFC_PIN_NONE,
3898 [28] = SH_PFC_PIN_NONE,
3899 [29] = SH_PFC_PIN_NONE,
3900 [30] = SH_PFC_PIN_NONE,
3901 [31] = SH_PFC_PIN_NONE,
3902 } },
3903 { PINMUX_BIAS_REG("PUEN7", 0xE60618C0, "PUD7", 0xE60618E0) {
3904 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
3905 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
3906 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
3907 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
3908 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
3909 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
3910 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
3911 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
3912 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
3913 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
3914 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
3915 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
3916 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
3917 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
3918 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
3919 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
3920 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
3921 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
3922 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
3923 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
3924 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
3925 [21] = SH_PFC_PIN_NONE,
3926 [22] = SH_PFC_PIN_NONE,
3927 [23] = SH_PFC_PIN_NONE,
3928 [24] = SH_PFC_PIN_NONE,
3929 [25] = SH_PFC_PIN_NONE,
3930 [26] = SH_PFC_PIN_NONE,
3931 [27] = SH_PFC_PIN_NONE,
3932 [28] = SH_PFC_PIN_NONE,
3933 [29] = SH_PFC_PIN_NONE,
3934 [30] = SH_PFC_PIN_NONE,
3935 [31] = SH_PFC_PIN_NONE,
3936 } },
3937 { /* sentinel */ },
3938};
3939
3940static const struct sh_pfc_soc_operations r8a779h0_pin_ops = {
3941 .pin_to_pocctrl = r8a779h0_pin_to_pocctrl,
3942 .get_bias = rcar_pinmux_get_bias,
3943 .set_bias = rcar_pinmux_set_bias,
3944};
3945
3946const struct sh_pfc_soc_info r8a779h0_pinmux_info = {
3947 .name = "r8a779h0_pfc",
3948 .ops = &r8a779h0_pin_ops,
3949 .unlock_reg = 0x1ff, /* PMMRn mask */
3950
3951 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3952
3953 .pins = pinmux_pins,
3954 .nr_pins = ARRAY_SIZE(pinmux_pins),
3955 .groups = pinmux_groups,
3956 .nr_groups = ARRAY_SIZE(pinmux_groups),
3957 .functions = pinmux_functions,
3958 .nr_functions = ARRAY_SIZE(pinmux_functions),
3959
3960 .cfg_regs = pinmux_config_regs,
3961 .drive_regs = pinmux_drive_regs,
3962 .bias_regs = pinmux_bias_regs,
3963 .ioctrl_regs = pinmux_ioctrl_regs,
3964
3965 .pinmux_data = pinmux_data,
3966 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3967};
3968

source code of linux/drivers/pinctrl/renesas/pfc-r8a779h0.c