1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2012 Linaro Ltd
8 * http://www.linaro.org
9 *
10 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 */
12
13#ifndef __PINCTRL_SAMSUNG_H
14#define __PINCTRL_SAMSUNG_H
15
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/pinctrl/machine.h>
21
22#include <linux/gpio/driver.h>
23
24/**
25 * enum pincfg_type - possible pin configuration types supported.
26 * @PINCFG_TYPE_FUNC: Function configuration.
27 * @PINCFG_TYPE_DAT: Pin value configuration.
28 * @PINCFG_TYPE_PUD: Pull up/down configuration.
29 * @PINCFG_TYPE_DRV: Drive strength configuration.
30 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
31 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
32 */
33enum pincfg_type {
34 PINCFG_TYPE_FUNC,
35 PINCFG_TYPE_DAT,
36 PINCFG_TYPE_PUD,
37 PINCFG_TYPE_DRV,
38 PINCFG_TYPE_CON_PDN,
39 PINCFG_TYPE_PUD_PDN,
40
41 PINCFG_TYPE_NUM
42};
43
44/*
45 * pin configuration (pull up/down and drive strength) type and its value are
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
48 */
49#define PINCFG_TYPE_MASK 0xFF
50#define PINCFG_VALUE_SHIFT 8
51#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
52#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
53#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
54#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
55 PINCFG_VALUE_SHIFT)
56/*
57 * Values for the pin CON register, choosing pin function.
58 * The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210,
59 * Exynos ARMv7, Exynos ARMv8, Tesla FSD.
60 */
61#define PIN_CON_FUNC_INPUT 0x0
62#define PIN_CON_FUNC_OUTPUT 0x1
63
64/**
65 * enum eint_type - possible external interrupt types.
66 * @EINT_TYPE_NONE: bank does not support external interrupts
67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
70 *
71 * Samsung GPIO controller groups all the available pins into banks. The pins
72 * in a pin bank can support external gpio interrupts or external wakeup
73 * interrupts or no interrupts at all. From a software perspective, the only
74 * difference between external gpio and external wakeup interrupts is that
75 * the wakeup interrupts can additionally wakeup the system if it is in
76 * suspended state.
77 */
78enum eint_type {
79 EINT_TYPE_NONE,
80 EINT_TYPE_GPIO,
81 EINT_TYPE_WKUP,
82 EINT_TYPE_WKUP_MUX,
83};
84
85/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
86#define PIN_NAME_LENGTH 10
87
88#define PIN_GROUP(n, p, f) \
89 { \
90 .name = n, \
91 .pins = p, \
92 .num_pins = ARRAY_SIZE(p), \
93 .func = f \
94 }
95
96#define PMX_FUNC(n, g) \
97 { \
98 .name = n, \
99 .groups = g, \
100 .num_groups = ARRAY_SIZE(g), \
101 }
102
103struct samsung_pinctrl_drv_data;
104
105/**
106 * struct samsung_pin_bank_type: pin bank type description
107 * @fld_width: widths of configuration bitfields (0 if unavailable)
108 * @reg_offset: offsets of configuration registers (don't care of width is 0)
109 */
110struct samsung_pin_bank_type {
111 u8 fld_width[PINCFG_TYPE_NUM];
112 u8 reg_offset[PINCFG_TYPE_NUM];
113};
114
115/**
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
117 * @type: type of the bank (register offsets and bitfield widths)
118 * @pctl_offset: starting offset of the pin-bank registers.
119 * @pctl_res_idx: index of base address for pin-bank registers.
120 * @nr_pins: number of pins included in this bank.
121 * @eint_func: function to set in CON register to configure pin as EINT.
122 * @eint_type: type of the external interrupt supported by the bank.
123 * @eint_mask: bit mask of pins which support EINT function.
124 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
125 * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
126 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
127 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
128 * @name: name to be prefixed for each pin in this pin bank.
129 */
130struct samsung_pin_bank_data {
131 const struct samsung_pin_bank_type *type;
132 u32 pctl_offset;
133 u8 pctl_res_idx;
134 u8 nr_pins;
135 u8 eint_func;
136 enum eint_type eint_type;
137 u32 eint_mask;
138 u32 eint_offset;
139 u32 eint_con_offset;
140 u32 eint_mask_offset;
141 u32 eint_pend_offset;
142 const char *name;
143};
144
145/**
146 * struct samsung_pin_bank: represent a controller pin-bank.
147 * @type: type of the bank (register offsets and bitfield widths)
148 * @pctl_base: base address of the pin-bank registers
149 * @pctl_offset: starting offset of the pin-bank registers.
150 * @nr_pins: number of pins included in this bank.
151 * @eint_base: base address of the pin-bank EINT registers.
152 * @eint_func: function to set in CON register to configure pin as EINT.
153 * @eint_type: type of the external interrupt supported by the bank.
154 * @eint_mask: bit mask of pins which support EINT function.
155 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
156 * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
157 * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
158 * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
159 * @name: name to be prefixed for each pin in this pin bank.
160 * @id: id of the bank, propagated to the pin range.
161 * @pin_base: starting pin number of the bank.
162 * @soc_priv: per-bank private data for SoC-specific code.
163 * @of_node: OF node of the bank.
164 * @drvdata: link to controller driver data
165 * @irq_domain: IRQ domain of the bank.
166 * @gpio_chip: GPIO chip of the bank.
167 * @grange: linux gpio pin range supported by this bank.
168 * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
169 * @slock: spinlock protecting bank registers
170 * @pm_save: saved register values during suspend
171 */
172struct samsung_pin_bank {
173 const struct samsung_pin_bank_type *type;
174 void __iomem *pctl_base;
175 u32 pctl_offset;
176 u8 nr_pins;
177 void __iomem *eint_base;
178 u8 eint_func;
179 enum eint_type eint_type;
180 u32 eint_mask;
181 u32 eint_offset;
182 u32 eint_con_offset;
183 u32 eint_mask_offset;
184 u32 eint_pend_offset;
185 const char *name;
186 u32 id;
187
188 u32 pin_base;
189 void *soc_priv;
190 struct fwnode_handle *fwnode;
191 struct samsung_pinctrl_drv_data *drvdata;
192 struct irq_domain *irq_domain;
193 struct gpio_chip gpio_chip;
194 struct pinctrl_gpio_range grange;
195 struct exynos_irq_chip *irq_chip;
196 raw_spinlock_t slock;
197
198 u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
199};
200
201/**
202 * struct samsung_retention_data: runtime pin-bank retention control data.
203 * @regs: array of PMU registers to control pad retention.
204 * @nr_regs: number of registers in @regs array.
205 * @value: value to store to registers to turn off retention.
206 * @refcnt: atomic counter if retention control affects more than one bank.
207 * @priv: retention control code private data
208 * @enable: platform specific callback to enter retention mode.
209 * @disable: platform specific callback to exit retention mode.
210 **/
211struct samsung_retention_ctrl {
212 const u32 *regs;
213 int nr_regs;
214 u32 value;
215 atomic_t *refcnt;
216 void *priv;
217 void (*enable)(struct samsung_pinctrl_drv_data *);
218 void (*disable)(struct samsung_pinctrl_drv_data *);
219};
220
221/**
222 * struct samsung_retention_data: represent a pin-bank retention control data.
223 * @regs: array of PMU registers to control pad retention.
224 * @nr_regs: number of registers in @regs array.
225 * @value: value to store to registers to turn off retention.
226 * @refcnt: atomic counter if retention control affects more than one bank.
227 * @init: platform specific callback to initialize retention control.
228 **/
229struct samsung_retention_data {
230 const u32 *regs;
231 int nr_regs;
232 u32 value;
233 atomic_t *refcnt;
234 struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *,
235 const struct samsung_retention_data *);
236};
237
238/**
239 * struct samsung_pin_ctrl: represent a pin controller.
240 * @pin_banks: list of pin banks included in this controller.
241 * @nr_banks: number of pin banks.
242 * @nr_ext_resources: number of the extra base address for pin banks.
243 * @retention_data: configuration data for retention control.
244 * @eint_gpio_init: platform specific callback to setup the external gpio
245 * interrupts for the controller.
246 * @eint_wkup_init: platform specific callback to setup the external wakeup
247 * interrupts for the controller.
248 * @suspend: platform specific suspend callback, executed during pin controller
249 * device suspend, see samsung_pinctrl_suspend()
250 * @resume: platform specific resume callback, executed during pin controller
251 * device suspend, see samsung_pinctrl_resume()
252 *
253 * External wakeup interrupts must define at least eint_wkup_init,
254 * retention_data and suspend in order for proper suspend/resume to work.
255 */
256struct samsung_pin_ctrl {
257 const struct samsung_pin_bank_data *pin_banks;
258 unsigned int nr_banks;
259 unsigned int nr_ext_resources;
260 const struct samsung_retention_data *retention_data;
261
262 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
263 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
264 void (*suspend)(struct samsung_pinctrl_drv_data *);
265 void (*resume)(struct samsung_pinctrl_drv_data *);
266};
267
268/**
269 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
270 * @node: global list node
271 * @virt_base: register base address of the controller; this will be equal
272 * to each bank samsung_pin_bank->pctl_base and used on legacy
273 * platforms (like S3C24XX or S3C64XX) which has to access the base
274 * through samsung_pinctrl_drv_data, not samsung_pin_bank).
275 * @dev: device instance representing the controller.
276 * @irq: interrpt number used by the controller to notify gpio interrupts.
277 * @ctrl: pin controller instance managed by the driver.
278 * @pctl: pin controller descriptor registered with the pinctrl subsystem.
279 * @pctl_dev: cookie representing pinctrl device instance.
280 * @pin_groups: list of pin groups available to the driver.
281 * @nr_groups: number of such pin groups.
282 * @pmx_functions: list of pin functions available to the driver.
283 * @nr_function: number of such pin functions.
284 * @nr_pins: number of pins supported by the controller.
285 * @retention_ctrl: retention control runtime data.
286 * @suspend: platform specific suspend callback, executed during pin controller
287 * device suspend, see samsung_pinctrl_suspend()
288 * @resume: platform specific resume callback, executed during pin controller
289 * device suspend, see samsung_pinctrl_resume()
290 */
291struct samsung_pinctrl_drv_data {
292 struct list_head node;
293 void __iomem *virt_base;
294 struct device *dev;
295 int irq;
296
297 struct pinctrl_desc pctl;
298 struct pinctrl_dev *pctl_dev;
299
300 const struct samsung_pin_group *pin_groups;
301 unsigned int nr_groups;
302 const struct samsung_pmx_func *pmx_functions;
303 unsigned int nr_functions;
304
305 struct samsung_pin_bank *pin_banks;
306 unsigned int nr_banks;
307 unsigned int nr_pins;
308
309 struct samsung_retention_ctrl *retention_ctrl;
310
311 void (*suspend)(struct samsung_pinctrl_drv_data *);
312 void (*resume)(struct samsung_pinctrl_drv_data *);
313};
314
315/**
316 * struct samsung_pinctrl_of_match_data: OF match device specific configuration data.
317 * @ctrl: array of pin controller data.
318 * @num_ctrl: size of array @ctrl.
319 */
320struct samsung_pinctrl_of_match_data {
321 const struct samsung_pin_ctrl *ctrl;
322 unsigned int num_ctrl;
323};
324
325/**
326 * struct samsung_pin_group: represent group of pins of a pinmux function.
327 * @name: name of the pin group, used to lookup the group.
328 * @pins: the pins included in this group.
329 * @num_pins: number of pins included in this group.
330 * @func: the function number to be programmed when selected.
331 */
332struct samsung_pin_group {
333 const char *name;
334 const unsigned int *pins;
335 u8 num_pins;
336 u8 func;
337};
338
339/**
340 * struct samsung_pmx_func: represent a pin function.
341 * @name: name of the pin function, used to lookup the function.
342 * @groups: one or more names of pin groups that provide this function.
343 * @num_groups: number of groups included in @groups.
344 */
345struct samsung_pmx_func {
346 const char *name;
347 const char **groups;
348 u8 num_groups;
349 u32 val;
350};
351
352/* list of all exported SoC specific data */
353extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
354extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
355extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data;
356extern const struct samsung_pinctrl_of_match_data exynos5250_of_data;
357extern const struct samsung_pinctrl_of_match_data exynos5260_of_data;
358extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
359extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
360extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
361extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
362extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
363extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
364extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
365extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
366extern const struct samsung_pinctrl_of_match_data fsd_of_data;
367extern const struct samsung_pinctrl_of_match_data gs101_of_data;
368extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
369extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
370extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
371extern const struct samsung_pinctrl_of_match_data s3c2440_of_data;
372extern const struct samsung_pinctrl_of_match_data s3c2450_of_data;
373extern const struct samsung_pinctrl_of_match_data s5pv210_of_data;
374
375#endif /* __PINCTRL_SAMSUNG_H */
376

source code of linux/drivers/pinctrl/samsung/pinctrl-samsung.h