1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> |
4 | * |
5 | * Based on: |
6 | * huangshuosheng <huangshuosheng@allwinnertech.com> |
7 | */ |
8 | |
9 | #include <linux/module.h> |
10 | #include <linux/of.h> |
11 | #include <linux/pinctrl/pinctrl.h> |
12 | #include <linux/platform_device.h> |
13 | |
14 | #include "pinctrl-sunxi.h" |
15 | |
16 | static const struct sunxi_desc_pin a100_pins[] = { |
17 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), |
18 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
19 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
20 | SUNXI_FUNCTION(0x2, "uart2" ), /* TX */ |
21 | SUNXI_FUNCTION(0x3, "spi2" ), /* CS */ |
22 | SUNXI_FUNCTION(0x4, "jtag" ), /* MS */ |
23 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), |
24 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), |
25 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
26 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
27 | SUNXI_FUNCTION(0x2, "uart2" ), /* RX */ |
28 | SUNXI_FUNCTION(0x3, "spi2" ), /* CLK */ |
29 | SUNXI_FUNCTION(0x4, "jtag" ), /* CK */ |
30 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), |
31 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), |
32 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
33 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
34 | SUNXI_FUNCTION(0x2, "uart2" ), /* RTS */ |
35 | SUNXI_FUNCTION(0x3, "spi2" ), /* MOSI */ |
36 | SUNXI_FUNCTION(0x4, "jtag" ), /* DO */ |
37 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), |
38 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), |
39 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
40 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
41 | SUNXI_FUNCTION(0x2, "uart2" ), /* CTS */ |
42 | SUNXI_FUNCTION(0x3, "spi2" ), /* MISO */ |
43 | SUNXI_FUNCTION(0x4, "jtag" ), /* DI */ |
44 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), |
45 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), |
46 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
47 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
48 | SUNXI_FUNCTION(0x2, "i2c1" ), /* SCK */ |
49 | SUNXI_FUNCTION(0x3, "i2s0" ), /* MCLK */ |
50 | SUNXI_FUNCTION(0x4, "jtag_gpu" ), /* MS_GPU */ |
51 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), |
52 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), |
53 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
54 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
55 | SUNXI_FUNCTION(0x2, "i2c1" ), /* SDA */ |
56 | SUNXI_FUNCTION(0x3, "i2s0" ), /* BCLK */ |
57 | SUNXI_FUNCTION(0x4, "jtag_gpu" ), /* CK_GPU */ |
58 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), |
59 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), |
60 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
61 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
62 | SUNXI_FUNCTION(0x3, "i2s0" ), /* LRCK */ |
63 | SUNXI_FUNCTION(0x4, "jtag_gpu" ), /* DO_GPU */ |
64 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), |
65 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), |
66 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
67 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
68 | SUNXI_FUNCTION(0x2, "spdif" ), /* DIN */ |
69 | SUNXI_FUNCTION(0x3, "i2s0_dout0" ), /* DOUT0 */ |
70 | SUNXI_FUNCTION(0x4, "i2s0_din1" ), /* DIN1 */ |
71 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), |
72 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), |
73 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
74 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
75 | SUNXI_FUNCTION(0x2, "spdif" ), /* DOUT */ |
76 | SUNXI_FUNCTION(0x3, "i2s0_din0" ), /* DIN0 */ |
77 | SUNXI_FUNCTION(0x4, "i2s0_dout1" ), /* DOUT1 */ |
78 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), |
79 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), |
80 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
81 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
82 | SUNXI_FUNCTION(0x2, "uart0" ), /* TX */ |
83 | SUNXI_FUNCTION(0x3, "i2c0" ), /* SCK */ |
84 | SUNXI_FUNCTION(0x4, "jtag_gpu" ), /* DI_GPU */ |
85 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), |
86 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), |
87 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
88 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
89 | SUNXI_FUNCTION(0x2, "uart0" ), /* RX */ |
90 | SUNXI_FUNCTION(0x3, "i2c0" ), /* SDA */ |
91 | SUNXI_FUNCTION(0x4, "pwm1" ), |
92 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), |
93 | /* HOLE */ |
94 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), |
95 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
96 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
97 | SUNXI_FUNCTION(0x2, "nand0" ), /* WE */ |
98 | SUNXI_FUNCTION(0x3, "mmc2" ), /* DS */ |
99 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), |
100 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), |
101 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
102 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
103 | SUNXI_FUNCTION(0x2, "nand0" ), /* ALE */ |
104 | SUNXI_FUNCTION(0x3, "mmc2" ), /* RST */ |
105 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), |
106 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), |
107 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
108 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
109 | SUNXI_FUNCTION(0x2, "nand0" ), /* CLE */ |
110 | SUNXI_FUNCTION(0x4, "spi0" ), /* MOSI */ |
111 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), |
112 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), |
113 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
114 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
115 | SUNXI_FUNCTION(0x2, "nand0" ), /* CE1 */ |
116 | SUNXI_FUNCTION(0x4, "spi0" ), /* CS0 */ |
117 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), |
118 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), |
119 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
120 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
121 | SUNXI_FUNCTION(0x2, "nand0" ), /* CE0 */ |
122 | SUNXI_FUNCTION(0x4, "spi0" ), /* MISO */ |
123 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), |
124 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), |
125 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
126 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
127 | SUNXI_FUNCTION(0x2, "nand0" ), /* RE */ |
128 | SUNXI_FUNCTION(0x3, "mmc2" ), /* CLK */ |
129 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), |
130 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), |
131 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
132 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
133 | SUNXI_FUNCTION(0x2, "nand0" ), /* RB0 */ |
134 | SUNXI_FUNCTION(0x3, "mmc2" ), /* CMD */ |
135 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), |
136 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), |
137 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
138 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
139 | SUNXI_FUNCTION(0x2, "nand0" ), /* RB1 */ |
140 | SUNXI_FUNCTION(0x4, "spi0" ), /* CS1 */ |
141 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), |
142 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), |
143 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
144 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
145 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ7 */ |
146 | SUNXI_FUNCTION(0x3, "mmc2" ), /* D3 */ |
147 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), |
148 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), |
149 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
150 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
151 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ6 */ |
152 | SUNXI_FUNCTION(0x3, "mmc2" ), /* D4 */ |
153 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), |
154 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), |
155 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
156 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
157 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ5 */ |
158 | SUNXI_FUNCTION(0x3, "mmc2" ), /* D0 */ |
159 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), |
160 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), |
161 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
162 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
163 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ4 */ |
164 | SUNXI_FUNCTION(0x3, "mmc2" ), /* D5 */ |
165 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), |
166 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), |
167 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
168 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
169 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQS */ |
170 | SUNXI_FUNCTION(0x4, "spi0" ), /* CLK */ |
171 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), |
172 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), |
173 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
174 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
175 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ3 */ |
176 | SUNXI_FUNCTION(0x3, "mmc2" ), /* D1 */ |
177 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), |
178 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), |
179 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
180 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
181 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ2 */ |
182 | SUNXI_FUNCTION(0x3, "mmc2" ), /* D6 */ |
183 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), |
184 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), |
185 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
186 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
187 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ1 */ |
188 | SUNXI_FUNCTION(0x3, "mmc2" ), /* D2 */ |
189 | SUNXI_FUNCTION(0x4, "spi0" ), /* WP */ |
190 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), |
191 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), |
192 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
193 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
194 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ0 */ |
195 | SUNXI_FUNCTION(0x3, "mmc2" ), /* D7 */ |
196 | SUNXI_FUNCTION(0x4, "spi0" ), /* HOLD */ |
197 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), |
198 | /* HOLE */ |
199 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), |
200 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
201 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
202 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D2 */ |
203 | SUNXI_FUNCTION(0x3, "lvds0" ), /* D0P */ |
204 | SUNXI_FUNCTION(0x4, "dsi0" ), /* DP0 */ |
205 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), |
206 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), |
207 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
208 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
209 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D3 */ |
210 | SUNXI_FUNCTION(0x3, "lvds0" ), /* D0N */ |
211 | SUNXI_FUNCTION(0x4, "dsi0" ), /* DM0 */ |
212 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), |
213 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), |
214 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
215 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
216 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D4 */ |
217 | SUNXI_FUNCTION(0x3, "lvds0" ), /* D1P */ |
218 | SUNXI_FUNCTION(0x4, "dsi0" ), /* DP1 */ |
219 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), |
220 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), |
221 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
222 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
223 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D5 */ |
224 | SUNXI_FUNCTION(0x3, "lvds0" ), /* D1N */ |
225 | SUNXI_FUNCTION(0x4, "dsi0" ), /* DM1 */ |
226 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), |
227 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), |
228 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
229 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
230 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D6 */ |
231 | SUNXI_FUNCTION(0x3, "lvds0" ), /* D2P */ |
232 | SUNXI_FUNCTION(0x4, "dsi0" ), /* CKP */ |
233 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), |
234 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), |
235 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
236 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
237 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D7 */ |
238 | SUNXI_FUNCTION(0x3, "lvds0" ), /* D2N */ |
239 | SUNXI_FUNCTION(0x4, "dsi0" ), /* CKM */ |
240 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), |
241 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), |
242 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
243 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
244 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D10 */ |
245 | SUNXI_FUNCTION(0x3, "lvds0" ), /* CKP */ |
246 | SUNXI_FUNCTION(0x4, "dsi0" ), /* DP2 */ |
247 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), |
248 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), |
249 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
250 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
251 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D11 */ |
252 | SUNXI_FUNCTION(0x3, "lvds0" ), /* CKN */ |
253 | SUNXI_FUNCTION(0x4, "dsi0" ), /* DM2 */ |
254 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), |
255 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), |
256 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
257 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
258 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D12 */ |
259 | SUNXI_FUNCTION(0x4, "dsi0" ), /* DP3 */ |
260 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), |
261 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), |
262 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
263 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
264 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D13 */ |
265 | SUNXI_FUNCTION(0x4, "dsi0" ), /* DM3 */ |
266 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), |
267 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), |
268 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
269 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
270 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D14 */ |
271 | SUNXI_FUNCTION(0x4, "spi1" ), /* CS */ |
272 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), |
273 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), |
274 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
275 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
276 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D15 */ |
277 | SUNXI_FUNCTION(0x4, "spi1" ), /* CLK */ |
278 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), |
279 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), |
280 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
281 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
282 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D18 */ |
283 | SUNXI_FUNCTION(0x4, "spi1" ), /* MOSI */ |
284 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), |
285 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), |
286 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
287 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
288 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D19 */ |
289 | SUNXI_FUNCTION(0x4, "spi1" ), /* MISO */ |
290 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), |
291 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), |
292 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
293 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
294 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D20 */ |
295 | SUNXI_FUNCTION(0x4, "uart3" ), /* TX */ |
296 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), |
297 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), |
298 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
299 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
300 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D21 */ |
301 | SUNXI_FUNCTION(0x4, "uart3" ), /* RX */ |
302 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), |
303 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), |
304 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
305 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
306 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D22 */ |
307 | SUNXI_FUNCTION(0x4, "uart3" ), /* RTS */ |
308 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), |
309 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), |
310 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
311 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
312 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D23 */ |
313 | SUNXI_FUNCTION(0x4, "uart3" ), /* CTS */ |
314 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), |
315 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), |
316 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
317 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
318 | SUNXI_FUNCTION(0x2, "lcd0" ), /* CLK */ |
319 | SUNXI_FUNCTION(0x4, "uart4" ), /* TX */ |
320 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), |
321 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), |
322 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
323 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
324 | SUNXI_FUNCTION(0x2, "lcd0" ), /* DE */ |
325 | SUNXI_FUNCTION(0x4, "uart4" ), /* RX */ |
326 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), |
327 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), |
328 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
329 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
330 | SUNXI_FUNCTION(0x2, "lcd0" ), /* HSYNC */ |
331 | SUNXI_FUNCTION(0x3, "pwm2" ), |
332 | SUNXI_FUNCTION(0x4, "uart4" ), /* RTS */ |
333 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)), |
334 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), |
335 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
336 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
337 | SUNXI_FUNCTION(0x2, "lcd0" ), /* VSYNC */ |
338 | SUNXI_FUNCTION(0x3, "pwm3" ), |
339 | SUNXI_FUNCTION(0x4, "uart4" ), /* CTS */ |
340 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)), |
341 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), |
342 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
343 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
344 | SUNXI_FUNCTION(0x2, "pwm1" ), |
345 | SUNXI_FUNCTION(0x4, "i2c0" ), /* SCK */ |
346 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)), |
347 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), |
348 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
349 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
350 | SUNXI_FUNCTION(0x2, "pwm0" ), |
351 | SUNXI_FUNCTION(0x4, "i2c0" ), /* SDA */ |
352 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)), |
353 | /* HOLE */ |
354 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), |
355 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
356 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
357 | SUNXI_FUNCTION(0x2, "csi" ), /* MCLK */ |
358 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), |
359 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), |
360 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
361 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
362 | SUNXI_FUNCTION(0x2, "i2c2" ), /* SCK */ |
363 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), |
364 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), |
365 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
366 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
367 | SUNXI_FUNCTION(0x2, "i2c2" ), /* SDA */ |
368 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), |
369 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), |
370 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
371 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
372 | SUNXI_FUNCTION(0x2, "i2c3" ), /* SCK */ |
373 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), |
374 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), |
375 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
376 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
377 | SUNXI_FUNCTION(0x2, "i2c3" ), /* SDA */ |
378 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), |
379 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), |
380 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
381 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
382 | SUNXI_FUNCTION(0x2, "csi" ), /* MCLK */ |
383 | SUNXI_FUNCTION(0x3, "pll" ), /* LOCK_DBG */ |
384 | SUNXI_FUNCTION(0x4, "i2s2" ), /* MCLK */ |
385 | SUNXI_FUNCTION(0x5, "ledc" ), /* LEDC */ |
386 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), |
387 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), |
388 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
389 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
390 | SUNXI_FUNCTION(0x3, "bist0" ), /* RESULT0 */ |
391 | SUNXI_FUNCTION(0x4, "i2s2" ), /* BCLK */ |
392 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), |
393 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), |
394 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
395 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
396 | SUNXI_FUNCTION(0x2, "csi" ), /* SM_VS */ |
397 | SUNXI_FUNCTION(0x3, "bist0" ), /* RESULT1 */ |
398 | SUNXI_FUNCTION(0x4, "i2s2" ), /* LRCK */ |
399 | SUNXI_FUNCTION(0x5, "tcon0" ), /* TRIG */ |
400 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), |
401 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), |
402 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
403 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
404 | SUNXI_FUNCTION(0x3, "bist0" ), /* RESULT2 */ |
405 | SUNXI_FUNCTION(0x4, "i2s2" ), /* DOUT0 */ |
406 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), |
407 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), |
408 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
409 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
410 | SUNXI_FUNCTION(0x3, "bist0" ), /* RESULT3 */ |
411 | SUNXI_FUNCTION(0x4, "i2s2" ), /* DIN0 */ |
412 | SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), |
413 | /* HOLE */ |
414 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), |
415 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
416 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
417 | SUNXI_FUNCTION(0x2, "mmc0" ), /* D1 */ |
418 | SUNXI_FUNCTION(0x3, "jtag" ), /* MS1 */ |
419 | SUNXI_FUNCTION(0x4, "jtag_gpu" ), /* MS_GPU */ |
420 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)), |
421 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), |
422 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
423 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
424 | SUNXI_FUNCTION(0x2, "mmc0" ), /* D0 */ |
425 | SUNXI_FUNCTION(0x3, "jtag" ), /* DI1 */ |
426 | SUNXI_FUNCTION(0x4, "jtag_gpu" ), /* DI_GPU */ |
427 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)), |
428 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), |
429 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
430 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
431 | SUNXI_FUNCTION(0x2, "mmc0" ), /* CLK */ |
432 | SUNXI_FUNCTION(0x3, "uart0" ), /* TX */ |
433 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)), |
434 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), |
435 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
436 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
437 | SUNXI_FUNCTION(0x2, "mmc0" ), /* CMD */ |
438 | SUNXI_FUNCTION(0x3, "jtag" ), /* DO */ |
439 | SUNXI_FUNCTION(0x4, "jtag_gpu" ), /* DO_GPU */ |
440 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)), |
441 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), |
442 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
443 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
444 | SUNXI_FUNCTION(0x2, "mmc0" ), /* D3 */ |
445 | SUNXI_FUNCTION(0x3, "uart0" ), /* RX */ |
446 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)), |
447 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), |
448 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
449 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
450 | SUNXI_FUNCTION(0x2, "mmc0" ), /* D2 */ |
451 | SUNXI_FUNCTION(0x3, "jtag" ), /* CK */ |
452 | SUNXI_FUNCTION(0x4, "jtag_gpu" ), /* CK_GPU */ |
453 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)), |
454 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), |
455 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
456 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
457 | SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)), |
458 | /* HOLE */ |
459 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), |
460 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
461 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
462 | SUNXI_FUNCTION(0x2, "mmc1" ), /* CLK */ |
463 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)), |
464 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), |
465 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
466 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
467 | SUNXI_FUNCTION(0x2, "mmc1" ), /* CMD */ |
468 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)), |
469 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), |
470 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
471 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
472 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D0 */ |
473 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)), |
474 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), |
475 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
476 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
477 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D1 */ |
478 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)), |
479 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), |
480 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
481 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
482 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D2 */ |
483 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)), |
484 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), |
485 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
486 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
487 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D3 */ |
488 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)), |
489 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), |
490 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
491 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
492 | SUNXI_FUNCTION(0x2, "uart1" ), /* TX */ |
493 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)), |
494 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), |
495 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
496 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
497 | SUNXI_FUNCTION(0x2, "uart1" ), /* RX */ |
498 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)), |
499 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), |
500 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
501 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
502 | SUNXI_FUNCTION(0x2, "uart1" ), /* RTS */ |
503 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)), |
504 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), |
505 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
506 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
507 | SUNXI_FUNCTION(0x2, "uart1" ), /* CTS */ |
508 | SUNXI_FUNCTION(0x3, "i2s1" ), /* MCLK */ |
509 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)), |
510 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), |
511 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
512 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
513 | SUNXI_FUNCTION(0x3, "i2s1" ), /* BCLK */ |
514 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)), |
515 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), |
516 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
517 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
518 | SUNXI_FUNCTION(0x3, "i2s1" ), /* LRCK */ |
519 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)), |
520 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), |
521 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
522 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
523 | SUNXI_FUNCTION(0x3, "i2s1_dout0" ), /* DOUT0 */ |
524 | SUNXI_FUNCTION(0x4, "i2s1_din1" ), /* DIN1 */ |
525 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)), |
526 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), |
527 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
528 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
529 | SUNXI_FUNCTION(0x3, "i2s1_din0" ), /* DIN0 */ |
530 | SUNXI_FUNCTION(0x4, "i2s1_dout1" ), /* DOUT1 */ |
531 | SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)), |
532 | /* HOLE */ |
533 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), |
534 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
535 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
536 | SUNXI_FUNCTION(0x2, "i2c0" ), /* SCK */ |
537 | SUNXI_FUNCTION(0x5, "emac0" ), /* RXD1 */ |
538 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)), |
539 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), |
540 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
541 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
542 | SUNXI_FUNCTION(0x2, "i2c0" ), /* SDA */ |
543 | SUNXI_FUNCTION(0x5, "emac0" ), /* RXD0 */ |
544 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)), |
545 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), |
546 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
547 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
548 | SUNXI_FUNCTION(0x2, "i2c1" ), /* SCK */ |
549 | SUNXI_FUNCTION(0x5, "emac0" ), /* RXCTL */ |
550 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)), |
551 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), |
552 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
553 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
554 | SUNXI_FUNCTION(0x2, "i2c1" ), /* SDA */ |
555 | SUNXI_FUNCTION(0x3, "cir0" ), /* OUT */ |
556 | SUNXI_FUNCTION(0x5, "emac0" ), /* CLKIN */ |
557 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)), |
558 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), |
559 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
560 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
561 | SUNXI_FUNCTION(0x2, "uart3" ), /* TX */ |
562 | SUNXI_FUNCTION(0x3, "spi1" ), /* CS */ |
563 | SUNXI_FUNCTION(0x5, "emac0" ), /* TXD1 */ |
564 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)), |
565 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), |
566 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
567 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
568 | SUNXI_FUNCTION(0x2, "uart3" ), /* RX */ |
569 | SUNXI_FUNCTION(0x3, "spi1" ), /* CLK */ |
570 | SUNXI_FUNCTION(0x4, "ledc" ), |
571 | SUNXI_FUNCTION(0x5, "emac0" ), /* TXD0 */ |
572 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)), |
573 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), |
574 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
575 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
576 | SUNXI_FUNCTION(0x2, "uart3" ), /* RTS */ |
577 | SUNXI_FUNCTION(0x3, "spi1" ), /* MOSI */ |
578 | SUNXI_FUNCTION(0x5, "emac0" ), /* TXCK */ |
579 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)), |
580 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), |
581 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
582 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
583 | SUNXI_FUNCTION(0x2, "uart3" ), /* CTS */ |
584 | SUNXI_FUNCTION(0x3, "spi1" ), /* MISO */ |
585 | SUNXI_FUNCTION(0x4, "spdif" ), /* OUT */ |
586 | SUNXI_FUNCTION(0x5, "emac0" ), /* TXCTL */ |
587 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)), |
588 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), |
589 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
590 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
591 | SUNXI_FUNCTION(0x2, "dmic" ), /* CLK */ |
592 | SUNXI_FUNCTION(0x3, "spi2" ), /* CS */ |
593 | SUNXI_FUNCTION(0x4, "i2s2" ), /* MCLK */ |
594 | SUNXI_FUNCTION(0x5, "i2s2_din2" ), /* DIN2 */ |
595 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)), |
596 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), |
597 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
598 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
599 | SUNXI_FUNCTION(0x2, "dmic" ), /* DATA0 */ |
600 | SUNXI_FUNCTION(0x3, "spi2" ), /* CLK */ |
601 | SUNXI_FUNCTION(0x4, "i2s2" ), /* BCLK */ |
602 | SUNXI_FUNCTION(0x5, "emac0" ), /* MDC */ |
603 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)), |
604 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), |
605 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
606 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
607 | SUNXI_FUNCTION(0x2, "dmic" ), /* DATA1 */ |
608 | SUNXI_FUNCTION(0x3, "spi2" ), /* MOSI */ |
609 | SUNXI_FUNCTION(0x4, "i2s2" ), /* LRCK */ |
610 | SUNXI_FUNCTION(0x5, "emac0" ), /* MDIO */ |
611 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), |
612 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), |
613 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
614 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
615 | SUNXI_FUNCTION(0x2, "dmic" ), /* DATA2 */ |
616 | SUNXI_FUNCTION(0x3, "spi2" ), /* MISO */ |
617 | SUNXI_FUNCTION(0x4, "i2s2_dout0" ), /* DOUT0 */ |
618 | SUNXI_FUNCTION(0x5, "i2s2_din1" ), /* DIN1 */ |
619 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 11)), |
620 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), |
621 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
622 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
623 | SUNXI_FUNCTION(0x2, "dmic" ), /* DATA3 */ |
624 | SUNXI_FUNCTION(0x3, "i2c3" ), /* SCK */ |
625 | SUNXI_FUNCTION(0x4, "i2s2_din0" ), /* DIN0 */ |
626 | SUNXI_FUNCTION(0x5, "i2s2_dout1" ), /* DOUT1 */ |
627 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 12)), |
628 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), |
629 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
630 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
631 | SUNXI_FUNCTION(0x3, "i2c3" ), /* SCK */ |
632 | SUNXI_FUNCTION(0x4, "i2s3" ), /* MCLK */ |
633 | SUNXI_FUNCTION(0x5, "emac0" ), /* EPHY */ |
634 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)), |
635 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), |
636 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
637 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
638 | SUNXI_FUNCTION(0x4, "i2s3" ), /* BCLK */ |
639 | SUNXI_FUNCTION(0x5, "emac0" ), /* RXD3 */ |
640 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)), |
641 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), |
642 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
643 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
644 | SUNXI_FUNCTION(0x4, "i2s3" ), /* LRCK */ |
645 | SUNXI_FUNCTION(0x5, "emac0" ), /* RXD2 */ |
646 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)), |
647 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), |
648 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
649 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
650 | SUNXI_FUNCTION(0x3, "i2s3_dout0" ), /* DOUT0 */ |
651 | SUNXI_FUNCTION(0x4, "i2s3_din1" ), /* DIN1 */ |
652 | SUNXI_FUNCTION(0x5, "emac0" ), /* RXCK */ |
653 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)), |
654 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), |
655 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
656 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
657 | SUNXI_FUNCTION(0x3, "i2s3_dout1" ), /* DOUT1 */ |
658 | SUNXI_FUNCTION(0x4, "i2s3_din0" ), /* DIN0 */ |
659 | SUNXI_FUNCTION(0x5, "emac0" ), /* TXD3 */ |
660 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)), |
661 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), |
662 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
663 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
664 | SUNXI_FUNCTION(0x2, "cir0" ), /* OUT */ |
665 | SUNXI_FUNCTION(0x3, "i2s3_dout2" ), /* DOUT2 */ |
666 | SUNXI_FUNCTION(0x4, "i2s3_din2" ), /* DIN2 */ |
667 | SUNXI_FUNCTION(0x5, "emac0" ), /* TXD2 */ |
668 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)), |
669 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), |
670 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
671 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
672 | SUNXI_FUNCTION(0x2, "cir0" ), /* IN */ |
673 | SUNXI_FUNCTION(0x3, "i2s3_dout3" ), /* DOUT3 */ |
674 | SUNXI_FUNCTION(0x4, "i2s3_din3" ), /* DIN3 */ |
675 | SUNXI_FUNCTION(0x5, "ledc" ), |
676 | SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)), |
677 | }; |
678 | |
679 | static const unsigned int a100_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7}; |
680 | |
681 | static const struct sunxi_pinctrl_desc a100_pinctrl_data = { |
682 | .pins = a100_pins, |
683 | .npins = ARRAY_SIZE(a100_pins), |
684 | .irq_banks = 7, |
685 | .irq_bank_map = a100_irq_bank_map, |
686 | .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL, |
687 | }; |
688 | |
689 | static int a100_pinctrl_probe(struct platform_device *pdev) |
690 | { |
691 | return sunxi_pinctrl_init(pdev, &a100_pinctrl_data); |
692 | } |
693 | |
694 | static const struct of_device_id a100_pinctrl_match[] = { |
695 | { .compatible = "allwinner,sun50i-a100-pinctrl" , }, |
696 | {} |
697 | }; |
698 | MODULE_DEVICE_TABLE(of, a100_pinctrl_match); |
699 | |
700 | static struct platform_driver a100_pinctrl_driver = { |
701 | .probe = a100_pinctrl_probe, |
702 | .driver = { |
703 | .name = "sun50i-a100-pinctrl" , |
704 | .of_match_table = a100_pinctrl_match, |
705 | }, |
706 | }; |
707 | module_platform_driver(a100_pinctrl_driver); |
708 | |