1 | /* |
2 | * Allwinner a83t SoCs pinctrl driver. |
3 | * |
4 | * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> |
5 | * |
6 | * Based on pinctrl-sun8i-a23.c, which is: |
7 | * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org> |
8 | * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> |
9 | * |
10 | * This file is licensed under the terms of the GNU General Public |
11 | * License version 2. This program is licensed "as is" without any |
12 | * warranty of any kind, whether express or implied. |
13 | */ |
14 | |
15 | #include <linux/init.h> |
16 | #include <linux/platform_device.h> |
17 | #include <linux/of.h> |
18 | #include <linux/pinctrl/pinctrl.h> |
19 | |
20 | #include "pinctrl-sunxi.h" |
21 | |
22 | static const struct sunxi_desc_pin sun8i_a83t_pins[] = { |
23 | /* Hole */ |
24 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), |
25 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
26 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
27 | SUNXI_FUNCTION(0x2, "uart2" ), /* TX */ |
28 | SUNXI_FUNCTION(0x3, "jtag" ), /* MS0 */ |
29 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ |
30 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), |
31 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
32 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
33 | SUNXI_FUNCTION(0x2, "uart2" ), /* RX */ |
34 | SUNXI_FUNCTION(0x3, "jtag" ), /* CK0 */ |
35 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ |
36 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), |
37 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
38 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
39 | SUNXI_FUNCTION(0x2, "uart2" ), /* RTS */ |
40 | SUNXI_FUNCTION(0x3, "jtag" ), /* DO0 */ |
41 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ |
42 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), |
43 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
44 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
45 | SUNXI_FUNCTION(0x2, "uart2" ), /* CTS */ |
46 | SUNXI_FUNCTION(0x3, "jtag" ), /* DI0 */ |
47 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ |
48 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), |
49 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
50 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
51 | SUNXI_FUNCTION(0x2, "i2s0" ), /* LRCK */ |
52 | SUNXI_FUNCTION(0x3, "tdm" ), /* LRCK */ |
53 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ |
54 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), |
55 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
56 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
57 | SUNXI_FUNCTION(0x2, "i2s0" ), /* BCLK */ |
58 | SUNXI_FUNCTION(0x3, "tdm" ), /* BCLK */ |
59 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ |
60 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), |
61 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
62 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
63 | SUNXI_FUNCTION(0x2, "i2s0" ), /* DOUT */ |
64 | SUNXI_FUNCTION(0x3, "tdm" ), /* DOUT */ |
65 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ |
66 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), |
67 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
68 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
69 | SUNXI_FUNCTION(0x2, "i2s0" ), /* DIN */ |
70 | SUNXI_FUNCTION(0x3, "tdm" ), /* DIN */ |
71 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ |
72 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), |
73 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
74 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
75 | SUNXI_FUNCTION(0x2, "i2s0" ), /* MCLK */ |
76 | SUNXI_FUNCTION(0x3, "tdm" ), /* MCLK */ |
77 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ |
78 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), |
79 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
80 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
81 | SUNXI_FUNCTION(0x2, "uart0" ), /* TX */ |
82 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ |
83 | SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), |
84 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
85 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
86 | SUNXI_FUNCTION(0x2, "uart0" ), /* RX */ |
87 | SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ |
88 | /* Hole */ |
89 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), |
90 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
91 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
92 | SUNXI_FUNCTION(0x2, "nand0" ), /* WE */ |
93 | SUNXI_FUNCTION(0x3, "spi0" )), /* MOSI */ |
94 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), |
95 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
96 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
97 | SUNXI_FUNCTION(0x2, "nand0" ), /* ALE */ |
98 | SUNXI_FUNCTION(0x3, "spi0" )), /* MISO */ |
99 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), |
100 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
101 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
102 | SUNXI_FUNCTION(0x2, "nand0" ), /* CLE */ |
103 | SUNXI_FUNCTION(0x3, "spi0" )), /* CLK */ |
104 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), |
105 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
106 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
107 | SUNXI_FUNCTION(0x2, "nand0" ), /* CE1 */ |
108 | SUNXI_FUNCTION(0x3, "spi0" )), /* CS */ |
109 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), |
110 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
111 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
112 | SUNXI_FUNCTION(0x2, "nand0" )), /* CE0 */ |
113 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), |
114 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
115 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
116 | SUNXI_FUNCTION(0x2, "nand0" ), /* RE */ |
117 | SUNXI_FUNCTION(0x3, "mmc2" )), /* CLK */ |
118 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), |
119 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
120 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
121 | SUNXI_FUNCTION(0x2, "nand0" ), /* RB0 */ |
122 | SUNXI_FUNCTION(0x3, "mmc2" )), /* CMD */ |
123 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), |
124 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
125 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
126 | SUNXI_FUNCTION(0x2, "nand0" )), /* RB1 */ |
127 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), |
128 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
129 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
130 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ0 */ |
131 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D0 */ |
132 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), |
133 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
134 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
135 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ1 */ |
136 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D1 */ |
137 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), |
138 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
139 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
140 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ2 */ |
141 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D2 */ |
142 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), |
143 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
144 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
145 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ3 */ |
146 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D3 */ |
147 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), |
148 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
149 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
150 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ4 */ |
151 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D4 */ |
152 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), |
153 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
154 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
155 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ5 */ |
156 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D5 */ |
157 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), |
158 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
159 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
160 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ6 */ |
161 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D6 */ |
162 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), |
163 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
164 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
165 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQ7 */ |
166 | SUNXI_FUNCTION(0x3, "mmc2" )), /* D7 */ |
167 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), |
168 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
169 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
170 | SUNXI_FUNCTION(0x2, "nand0" ), /* DQS */ |
171 | SUNXI_FUNCTION(0x3, "mmc2" )), /* RST */ |
172 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), |
173 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
174 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
175 | SUNXI_FUNCTION(0x2, "nand0" )), /* CE2 */ |
176 | SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), |
177 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
178 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
179 | SUNXI_FUNCTION(0x2, "nand0" )), /* CE3 */ |
180 | /* Hole */ |
181 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), |
182 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
183 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
184 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D2 */ |
185 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII RXD3 */ |
186 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), |
187 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
188 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
189 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D3 */ |
190 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII RXD2 */ |
191 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), |
192 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
193 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
194 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D4 */ |
195 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII RXD1 */ |
196 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), |
197 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
198 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
199 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D5 */ |
200 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII RXD0 */ |
201 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), |
202 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
203 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
204 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D6 */ |
205 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII RXCK */ |
206 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), |
207 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
208 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
209 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D7 */ |
210 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII RXDV */ |
211 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), |
212 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
213 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
214 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D10 */ |
215 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII RXERR */ |
216 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), |
217 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
218 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
219 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D11 */ |
220 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII TXD3 */ |
221 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), |
222 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
223 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
224 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D12 */ |
225 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII TXD2 */ |
226 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), |
227 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
228 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
229 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D13 */ |
230 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII TXD1 */ |
231 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), |
232 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
233 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
234 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D14 */ |
235 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII / MII TXD0 */ |
236 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), |
237 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
238 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
239 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D15 */ |
240 | SUNXI_FUNCTION(0x4, "gmac" )), /* RGMII-NULL / MII-CRS */ |
241 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), |
242 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
243 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
244 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D18 */ |
245 | SUNXI_FUNCTION(0x3, "lvds0" ), /* VP0 */ |
246 | SUNXI_FUNCTION(0x4, "gmac" )), /* GTXCK / ETXCK */ |
247 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), |
248 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
249 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
250 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D19 */ |
251 | SUNXI_FUNCTION(0x3, "lvds0" ), /* VN0 */ |
252 | SUNXI_FUNCTION(0x4, "gmac" )), /* GTXCTL / ETXEL */ |
253 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), |
254 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
255 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
256 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D20 */ |
257 | SUNXI_FUNCTION(0x3, "lvds0" ), /* VP1 */ |
258 | SUNXI_FUNCTION(0x4, "gmac" )), /* GNULL / ETXERR */ |
259 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), |
260 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
261 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
262 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D21 */ |
263 | SUNXI_FUNCTION(0x3, "lvds0" ), /* VN1 */ |
264 | SUNXI_FUNCTION(0x4, "gmac" )), /* GCLKIN / ECOL */ |
265 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), |
266 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
267 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
268 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D22 */ |
269 | SUNXI_FUNCTION(0x3, "lvds0" ), /* VP2 */ |
270 | SUNXI_FUNCTION(0x4, "gmac" )), /* GMDC */ |
271 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), |
272 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
273 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
274 | SUNXI_FUNCTION(0x2, "lcd0" ), /* D23 */ |
275 | SUNXI_FUNCTION(0x3, "lvds0" ), /* VN2 */ |
276 | SUNXI_FUNCTION(0x4, "gmac" )), /* GMDIO */ |
277 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), |
278 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
279 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
280 | SUNXI_FUNCTION(0x2, "lcd0" ), /* CLK */ |
281 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VPC */ |
282 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), |
283 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
284 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
285 | SUNXI_FUNCTION(0x2, "lcd0" ), /* DE */ |
286 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VNC */ |
287 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), |
288 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
289 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
290 | SUNXI_FUNCTION(0x2, "lcd0" ), /* HSYNC */ |
291 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VP3 */ |
292 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), |
293 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
294 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
295 | SUNXI_FUNCTION(0x2, "lcd0" ), /* VSYNC */ |
296 | SUNXI_FUNCTION(0x3, "lvds0" )), /* VN3 */ |
297 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), |
298 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
299 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
300 | SUNXI_FUNCTION(0x2, "pwm" )), /* PWM */ |
301 | SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29), |
302 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
303 | SUNXI_FUNCTION(0x1, "gpio_out" )), |
304 | /* Hole */ |
305 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), |
306 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
307 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
308 | SUNXI_FUNCTION(0x2, "csi" ), /* PCLK */ |
309 | SUNXI_FUNCTION(0x4, "ccir" )), /* CLK */ |
310 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), |
311 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
312 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
313 | SUNXI_FUNCTION(0x2, "csi" ), /* MCLK */ |
314 | SUNXI_FUNCTION(0x4, "ccir" )), /* DE */ |
315 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), |
316 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
317 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
318 | SUNXI_FUNCTION(0x2, "csi" ), /* HSYNC */ |
319 | SUNXI_FUNCTION(0x4, "ccir" )), /* HSYNC */ |
320 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), |
321 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
322 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
323 | SUNXI_FUNCTION(0x2, "csi" ), /* VSYNC */ |
324 | SUNXI_FUNCTION(0x4, "ccir" )), /* VSYNC */ |
325 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), |
326 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
327 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
328 | SUNXI_FUNCTION(0x2, "csi" )), /* D0 */ |
329 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), |
330 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
331 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
332 | SUNXI_FUNCTION(0x2, "csi" )), /* D1 */ |
333 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), |
334 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
335 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
336 | SUNXI_FUNCTION(0x2, "csi" ), /* D2 */ |
337 | SUNXI_FUNCTION(0x4, "ccir" )), /* D0 */ |
338 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), |
339 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
340 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
341 | SUNXI_FUNCTION(0x2, "csi" ), /* D3 */ |
342 | SUNXI_FUNCTION(0x4, "ccir" )), /* D1 */ |
343 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), |
344 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
345 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
346 | SUNXI_FUNCTION(0x2, "csi" ), /* D4 */ |
347 | SUNXI_FUNCTION(0x4, "ccir" )), /* D2 */ |
348 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), |
349 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
350 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
351 | SUNXI_FUNCTION(0x2, "csi" ), /* D5 */ |
352 | SUNXI_FUNCTION(0x4, "ccir" )), /* D3 */ |
353 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), |
354 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
355 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
356 | SUNXI_FUNCTION(0x2, "csi" ), /* D6 */ |
357 | SUNXI_FUNCTION(0x3, "uart4" ), /* TX */ |
358 | SUNXI_FUNCTION(0x4, "ccir" )), /* D4 */ |
359 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), |
360 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
361 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
362 | SUNXI_FUNCTION(0x2, "csi" ), /* D7 */ |
363 | SUNXI_FUNCTION(0x3, "uart4" ), /* RX */ |
364 | SUNXI_FUNCTION(0x4, "ccir" )), /* D5 */ |
365 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), |
366 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
367 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
368 | SUNXI_FUNCTION(0x2, "csi" ), /* D8 */ |
369 | SUNXI_FUNCTION(0x3, "uart4" ), /* RTS */ |
370 | SUNXI_FUNCTION(0x4, "ccir" )), /* D6 */ |
371 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), |
372 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
373 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
374 | SUNXI_FUNCTION(0x2, "csi" ), /* D9 */ |
375 | SUNXI_FUNCTION(0x3, "uart4" ), /* CTS */ |
376 | SUNXI_FUNCTION(0x4, "ccir" )), /* D7 */ |
377 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), |
378 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
379 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
380 | SUNXI_FUNCTION(0x2, "csi" ), /* SCK */ |
381 | SUNXI_FUNCTION(0x3, "i2c2" )), /* SCK */ |
382 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), |
383 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
384 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
385 | SUNXI_FUNCTION(0x2, "csi" ), /* SDA */ |
386 | SUNXI_FUNCTION(0x3, "i2c2" )), /* SDA */ |
387 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), |
388 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
389 | SUNXI_FUNCTION(0x1, "gpio_out" )), |
390 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), |
391 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
392 | SUNXI_FUNCTION(0x1, "gpio_out" )), |
393 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), |
394 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
395 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
396 | SUNXI_FUNCTION(0x3, "spdif" )), /* DOUT */ |
397 | SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), |
398 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
399 | SUNXI_FUNCTION(0x1, "gpio_out" )), |
400 | /* Hole */ |
401 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), |
402 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
403 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
404 | SUNXI_FUNCTION(0x2, "mmc0" ), /* D1 */ |
405 | SUNXI_FUNCTION(0x3, "jtag" )), /* MS1 */ |
406 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), |
407 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
408 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
409 | SUNXI_FUNCTION(0x2, "mmc0" ), /* D0 */ |
410 | SUNXI_FUNCTION(0x3, "jtag" )), /* DI1 */ |
411 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), |
412 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
413 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
414 | SUNXI_FUNCTION(0x2, "mmc0" ), /* CLK */ |
415 | SUNXI_FUNCTION(0x3, "uart0" )), /* TX */ |
416 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), |
417 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
418 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
419 | SUNXI_FUNCTION(0x2, "mmc0" ), /* CMD */ |
420 | SUNXI_FUNCTION(0x3, "jtag" )), /* DO1 */ |
421 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), |
422 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
423 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
424 | SUNXI_FUNCTION(0x2, "mmc0" ), /* D3 */ |
425 | SUNXI_FUNCTION(0x3, "uart0" )), /* RX */ |
426 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), |
427 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
428 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
429 | SUNXI_FUNCTION(0x2, "mmc0" ), /* D2 */ |
430 | SUNXI_FUNCTION(0x3, "jtag" )), /* CK1 */ |
431 | SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), |
432 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
433 | SUNXI_FUNCTION(0x1, "gpio_out" )), |
434 | /* Hole */ |
435 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), |
436 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
437 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
438 | SUNXI_FUNCTION(0x2, "mmc1" ), /* CLK */ |
439 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ |
440 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), |
441 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
442 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
443 | SUNXI_FUNCTION(0x2, "mmc1" ), /* CMD */ |
444 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ |
445 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), |
446 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
447 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
448 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D0 */ |
449 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ |
450 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), |
451 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
452 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
453 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D1 */ |
454 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ |
455 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), |
456 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
457 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
458 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D2 */ |
459 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ |
460 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), |
461 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
462 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
463 | SUNXI_FUNCTION(0x2, "mmc1" ), /* D3 */ |
464 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ |
465 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), |
466 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
467 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
468 | SUNXI_FUNCTION(0x2, "uart1" ), /* TX */ |
469 | SUNXI_FUNCTION(0x3, "spi1" ), /* CS */ |
470 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ |
471 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), |
472 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
473 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
474 | SUNXI_FUNCTION(0x2, "uart1" ), /* RX */ |
475 | SUNXI_FUNCTION(0x3, "spi1" ), /* CLK */ |
476 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ |
477 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), |
478 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
479 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
480 | SUNXI_FUNCTION(0x2, "uart1" ), /* RTS */ |
481 | SUNXI_FUNCTION(0x3, "spi1" ), /* MOSI */ |
482 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ |
483 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), |
484 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
485 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
486 | SUNXI_FUNCTION(0x2, "uart1" ), /* CTS */ |
487 | SUNXI_FUNCTION(0x3, "spi1" ), /* MISO */ |
488 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ |
489 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), |
490 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
491 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
492 | SUNXI_FUNCTION(0x2, "i2s1" ), /* BCLK */ |
493 | SUNXI_FUNCTION(0x3, "uart3" ), /* TX */ |
494 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ |
495 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), |
496 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
497 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
498 | SUNXI_FUNCTION(0x2, "i2s1" ), /* LRCK */ |
499 | SUNXI_FUNCTION(0x3, "uart3" ), /* RX */ |
500 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ |
501 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), |
502 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
503 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
504 | SUNXI_FUNCTION(0x2, "i2s1" ), /* DOUT */ |
505 | SUNXI_FUNCTION(0x3, "uart3" ), /* RTS */ |
506 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ |
507 | SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), |
508 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
509 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
510 | SUNXI_FUNCTION(0x2, "i2s1" ), /* DIN */ |
511 | SUNXI_FUNCTION(0x3, "uart3" ), /* CTS */ |
512 | SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ |
513 | /* Hole */ |
514 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), |
515 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
516 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
517 | SUNXI_FUNCTION(0x2, "i2c0" ), /* SCK */ |
518 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PH_EINT0 */ |
519 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), |
520 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
521 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
522 | SUNXI_FUNCTION(0x2, "i2c0" ), /* SDA */ |
523 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT1 */ |
524 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), |
525 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
526 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
527 | SUNXI_FUNCTION(0x2, "i2c1" ), /* SCK */ |
528 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PH_EINT2 */ |
529 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), |
530 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
531 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
532 | SUNXI_FUNCTION(0x2, "i2c1" ), /* SDA */ |
533 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PH_EINT3 */ |
534 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), |
535 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
536 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
537 | SUNXI_FUNCTION(0x2, "i2c2" ), /* SCK */ |
538 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PH_EINT4 */ |
539 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), |
540 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
541 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
542 | SUNXI_FUNCTION(0x2, "i2c2" ), /* SDA */ |
543 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PH_EINT5 */ |
544 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), |
545 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
546 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
547 | SUNXI_FUNCTION(0x2, "hdmi" ), /* HSCL */ |
548 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PH_EINT6 */ |
549 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), |
550 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
551 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
552 | SUNXI_FUNCTION(0x2, "hdmi" ), /* HSDA */ |
553 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PH_EINT7 */ |
554 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), |
555 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
556 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
557 | SUNXI_FUNCTION(0x2, "hdmi" ), /* HCEC */ |
558 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PH_EINT8 */ |
559 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), |
560 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
561 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
562 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PH_EINT9 */ |
563 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), |
564 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
565 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
566 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */ |
567 | SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), |
568 | SUNXI_FUNCTION(0x0, "gpio_in" ), |
569 | SUNXI_FUNCTION(0x1, "gpio_out" ), |
570 | SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PH_EINT11 */ |
571 | }; |
572 | |
573 | static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = { |
574 | .pins = sun8i_a83t_pins, |
575 | .npins = ARRAY_SIZE(sun8i_a83t_pins), |
576 | .irq_banks = 3, |
577 | }; |
578 | |
579 | static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev) |
580 | { |
581 | return sunxi_pinctrl_init(pdev, |
582 | &sun8i_a83t_pinctrl_data); |
583 | } |
584 | |
585 | static const struct of_device_id sun8i_a83t_pinctrl_match[] = { |
586 | { .compatible = "allwinner,sun8i-a83t-pinctrl" , }, |
587 | {} |
588 | }; |
589 | |
590 | static struct platform_driver sun8i_a83t_pinctrl_driver = { |
591 | .probe = sun8i_a83t_pinctrl_probe, |
592 | .driver = { |
593 | .name = "sun8i-a83t-pinctrl" , |
594 | .of_match_table = sun8i_a83t_pinctrl_match, |
595 | }, |
596 | }; |
597 | builtin_platform_driver(sun8i_a83t_pinctrl_driver); |
598 | |