1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Pinctrl data for the NVIDIA Tegra210 pinmux |
4 | * |
5 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. |
6 | */ |
7 | |
8 | #include <linux/init.h> |
9 | #include <linux/of.h> |
10 | #include <linux/platform_device.h> |
11 | #include <linux/pinctrl/pinctrl.h> |
12 | #include <linux/pinctrl/pinmux.h> |
13 | |
14 | #include "pinctrl-tegra.h" |
15 | |
16 | /* |
17 | * Most pins affected by the pinmux can also be GPIOs. Define these first. |
18 | * These must match how the GPIO driver names/numbers its pins. |
19 | */ |
20 | #define _GPIO(offset) (offset) |
21 | |
22 | #define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0) |
23 | #define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1) |
24 | #define TEGRA_PIN_PEX_WAKE_N_PA2 _GPIO(2) |
25 | #define TEGRA_PIN_PEX_L1_RST_N_PA3 _GPIO(3) |
26 | #define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4 _GPIO(4) |
27 | #define TEGRA_PIN_SATA_LED_ACTIVE_PA5 _GPIO(5) |
28 | #define TEGRA_PIN_PA6 _GPIO(6) |
29 | #define TEGRA_PIN_DAP1_FS_PB0 _GPIO(8) |
30 | #define TEGRA_PIN_DAP1_DIN_PB1 _GPIO(9) |
31 | #define TEGRA_PIN_DAP1_DOUT_PB2 _GPIO(10) |
32 | #define TEGRA_PIN_DAP1_SCLK_PB3 _GPIO(11) |
33 | #define TEGRA_PIN_SPI2_MOSI_PB4 _GPIO(12) |
34 | #define TEGRA_PIN_SPI2_MISO_PB5 _GPIO(13) |
35 | #define TEGRA_PIN_SPI2_SCK_PB6 _GPIO(14) |
36 | #define TEGRA_PIN_SPI2_CS0_PB7 _GPIO(15) |
37 | #define TEGRA_PIN_SPI1_MOSI_PC0 _GPIO(16) |
38 | #define TEGRA_PIN_SPI1_MISO_PC1 _GPIO(17) |
39 | #define TEGRA_PIN_SPI1_SCK_PC2 _GPIO(18) |
40 | #define TEGRA_PIN_SPI1_CS0_PC3 _GPIO(19) |
41 | #define TEGRA_PIN_SPI1_CS1_PC4 _GPIO(20) |
42 | #define TEGRA_PIN_SPI4_SCK_PC5 _GPIO(21) |
43 | #define TEGRA_PIN_SPI4_CS0_PC6 _GPIO(22) |
44 | #define TEGRA_PIN_SPI4_MOSI_PC7 _GPIO(23) |
45 | #define TEGRA_PIN_SPI4_MISO_PD0 _GPIO(24) |
46 | #define TEGRA_PIN_UART3_TX_PD1 _GPIO(25) |
47 | #define TEGRA_PIN_UART3_RX_PD2 _GPIO(26) |
48 | #define TEGRA_PIN_UART3_RTS_PD3 _GPIO(27) |
49 | #define TEGRA_PIN_UART3_CTS_PD4 _GPIO(28) |
50 | #define TEGRA_PIN_DMIC1_CLK_PE0 _GPIO(32) |
51 | #define TEGRA_PIN_DMIC1_DAT_PE1 _GPIO(33) |
52 | #define TEGRA_PIN_DMIC2_CLK_PE2 _GPIO(34) |
53 | #define TEGRA_PIN_DMIC2_DAT_PE3 _GPIO(35) |
54 | #define TEGRA_PIN_DMIC3_CLK_PE4 _GPIO(36) |
55 | #define TEGRA_PIN_DMIC3_DAT_PE5 _GPIO(37) |
56 | #define TEGRA_PIN_PE6 _GPIO(38) |
57 | #define TEGRA_PIN_PE7 _GPIO(39) |
58 | #define TEGRA_PIN_GEN3_I2C_SCL_PF0 _GPIO(40) |
59 | #define TEGRA_PIN_GEN3_I2C_SDA_PF1 _GPIO(41) |
60 | #define TEGRA_PIN_UART2_TX_PG0 _GPIO(48) |
61 | #define TEGRA_PIN_UART2_RX_PG1 _GPIO(49) |
62 | #define TEGRA_PIN_UART2_RTS_PG2 _GPIO(50) |
63 | #define TEGRA_PIN_UART2_CTS_PG3 _GPIO(51) |
64 | #define TEGRA_PIN_WIFI_EN_PH0 _GPIO(56) |
65 | #define TEGRA_PIN_WIFI_RST_PH1 _GPIO(57) |
66 | #define TEGRA_PIN_WIFI_WAKE_AP_PH2 _GPIO(58) |
67 | #define TEGRA_PIN_AP_WAKE_BT_PH3 _GPIO(59) |
68 | #define TEGRA_PIN_BT_RST_PH4 _GPIO(60) |
69 | #define TEGRA_PIN_BT_WAKE_AP_PH5 _GPIO(61) |
70 | #define TEGRA_PIN_PH6 _GPIO(62) |
71 | #define TEGRA_PIN_AP_WAKE_NFC_PH7 _GPIO(63) |
72 | #define TEGRA_PIN_NFC_EN_PI0 _GPIO(64) |
73 | #define TEGRA_PIN_NFC_INT_PI1 _GPIO(65) |
74 | #define TEGRA_PIN_GPS_EN_PI2 _GPIO(66) |
75 | #define TEGRA_PIN_GPS_RST_PI3 _GPIO(67) |
76 | #define TEGRA_PIN_UART4_TX_PI4 _GPIO(68) |
77 | #define TEGRA_PIN_UART4_RX_PI5 _GPIO(69) |
78 | #define TEGRA_PIN_UART4_RTS_PI6 _GPIO(70) |
79 | #define TEGRA_PIN_UART4_CTS_PI7 _GPIO(71) |
80 | #define TEGRA_PIN_GEN1_I2C_SDA_PJ0 _GPIO(72) |
81 | #define TEGRA_PIN_GEN1_I2C_SCL_PJ1 _GPIO(73) |
82 | #define TEGRA_PIN_GEN2_I2C_SCL_PJ2 _GPIO(74) |
83 | #define TEGRA_PIN_GEN2_I2C_SDA_PJ3 _GPIO(75) |
84 | #define TEGRA_PIN_DAP4_FS_PJ4 _GPIO(76) |
85 | #define TEGRA_PIN_DAP4_DIN_PJ5 _GPIO(77) |
86 | #define TEGRA_PIN_DAP4_DOUT_PJ6 _GPIO(78) |
87 | #define TEGRA_PIN_DAP4_SCLK_PJ7 _GPIO(79) |
88 | #define TEGRA_PIN_PK0 _GPIO(80) |
89 | #define TEGRA_PIN_PK1 _GPIO(81) |
90 | #define TEGRA_PIN_PK2 _GPIO(82) |
91 | #define TEGRA_PIN_PK3 _GPIO(83) |
92 | #define TEGRA_PIN_PK4 _GPIO(84) |
93 | #define TEGRA_PIN_PK5 _GPIO(85) |
94 | #define TEGRA_PIN_PK6 _GPIO(86) |
95 | #define TEGRA_PIN_PK7 _GPIO(87) |
96 | #define TEGRA_PIN_PL0 _GPIO(88) |
97 | #define TEGRA_PIN_PL1 _GPIO(89) |
98 | #define TEGRA_PIN_SDMMC1_CLK_PM0 _GPIO(96) |
99 | #define TEGRA_PIN_SDMMC1_CMD_PM1 _GPIO(97) |
100 | #define TEGRA_PIN_SDMMC1_DAT3_PM2 _GPIO(98) |
101 | #define TEGRA_PIN_SDMMC1_DAT2_PM3 _GPIO(99) |
102 | #define TEGRA_PIN_SDMMC1_DAT1_PM4 _GPIO(100) |
103 | #define TEGRA_PIN_SDMMC1_DAT0_PM5 _GPIO(101) |
104 | #define TEGRA_PIN_SDMMC3_CLK_PP0 _GPIO(120) |
105 | #define TEGRA_PIN_SDMMC3_CMD_PP1 _GPIO(121) |
106 | #define TEGRA_PIN_SDMMC3_DAT3_PP2 _GPIO(122) |
107 | #define TEGRA_PIN_SDMMC3_DAT2_PP3 _GPIO(123) |
108 | #define TEGRA_PIN_SDMMC3_DAT1_PP4 _GPIO(124) |
109 | #define TEGRA_PIN_SDMMC3_DAT0_PP5 _GPIO(125) |
110 | #define TEGRA_PIN_CAM1_MCLK_PS0 _GPIO(144) |
111 | #define TEGRA_PIN_CAM2_MCLK_PS1 _GPIO(145) |
112 | #define TEGRA_PIN_CAM_I2C_SCL_PS2 _GPIO(146) |
113 | #define TEGRA_PIN_CAM_I2C_SDA_PS3 _GPIO(147) |
114 | #define TEGRA_PIN_CAM_RST_PS4 _GPIO(148) |
115 | #define TEGRA_PIN_CAM_AF_EN_PS5 _GPIO(149) |
116 | #define TEGRA_PIN_CAM_FLASH_EN_PS6 _GPIO(150) |
117 | #define TEGRA_PIN_CAM1_PWDN_PS7 _GPIO(151) |
118 | #define TEGRA_PIN_CAM2_PWDN_PT0 _GPIO(152) |
119 | #define TEGRA_PIN_CAM1_STROBE_PT1 _GPIO(153) |
120 | #define TEGRA_PIN_UART1_TX_PU0 _GPIO(160) |
121 | #define TEGRA_PIN_UART1_RX_PU1 _GPIO(161) |
122 | #define TEGRA_PIN_UART1_RTS_PU2 _GPIO(162) |
123 | #define TEGRA_PIN_UART1_CTS_PU3 _GPIO(163) |
124 | #define TEGRA_PIN_LCD_BL_PWM_PV0 _GPIO(168) |
125 | #define TEGRA_PIN_LCD_BL_EN_PV1 _GPIO(169) |
126 | #define TEGRA_PIN_LCD_RST_PV2 _GPIO(170) |
127 | #define TEGRA_PIN_LCD_GPIO1_PV3 _GPIO(171) |
128 | #define TEGRA_PIN_LCD_GPIO2_PV4 _GPIO(172) |
129 | #define TEGRA_PIN_AP_READY_PV5 _GPIO(173) |
130 | #define TEGRA_PIN_TOUCH_RST_PV6 _GPIO(174) |
131 | #define TEGRA_PIN_TOUCH_CLK_PV7 _GPIO(175) |
132 | #define TEGRA_PIN_MODEM_WAKE_AP_PX0 _GPIO(184) |
133 | #define TEGRA_PIN_TOUCH_INT_PX1 _GPIO(185) |
134 | #define TEGRA_PIN_MOTION_INT_PX2 _GPIO(186) |
135 | #define TEGRA_PIN_ALS_PROX_INT_PX3 _GPIO(187) |
136 | #define TEGRA_PIN_TEMP_ALERT_PX4 _GPIO(188) |
137 | #define TEGRA_PIN_BUTTON_POWER_ON_PX5 _GPIO(189) |
138 | #define TEGRA_PIN_BUTTON_VOL_UP_PX6 _GPIO(190) |
139 | #define TEGRA_PIN_BUTTON_VOL_DOWN_PX7 _GPIO(191) |
140 | #define TEGRA_PIN_BUTTON_SLIDE_SW_PY0 _GPIO(192) |
141 | #define TEGRA_PIN_BUTTON_HOME_PY1 _GPIO(193) |
142 | #define TEGRA_PIN_LCD_TE_PY2 _GPIO(194) |
143 | #define TEGRA_PIN_PWR_I2C_SCL_PY3 _GPIO(195) |
144 | #define TEGRA_PIN_PWR_I2C_SDA_PY4 _GPIO(196) |
145 | #define TEGRA_PIN_CLK_32K_OUT_PY5 _GPIO(197) |
146 | #define TEGRA_PIN_PZ0 _GPIO(200) |
147 | #define TEGRA_PIN_PZ1 _GPIO(201) |
148 | #define TEGRA_PIN_PZ2 _GPIO(202) |
149 | #define TEGRA_PIN_PZ3 _GPIO(203) |
150 | #define TEGRA_PIN_PZ4 _GPIO(204) |
151 | #define TEGRA_PIN_PZ5 _GPIO(205) |
152 | #define TEGRA_PIN_DAP2_FS_PAA0 _GPIO(208) |
153 | #define TEGRA_PIN_DAP2_SCLK_PAA1 _GPIO(209) |
154 | #define TEGRA_PIN_DAP2_DIN_PAA2 _GPIO(210) |
155 | #define TEGRA_PIN_DAP2_DOUT_PAA3 _GPIO(211) |
156 | #define TEGRA_PIN_AUD_MCLK_PBB0 _GPIO(216) |
157 | #define TEGRA_PIN_DVFS_PWM_PBB1 _GPIO(217) |
158 | #define TEGRA_PIN_DVFS_CLK_PBB2 _GPIO(218) |
159 | #define TEGRA_PIN_GPIO_X1_AUD_PBB3 _GPIO(219) |
160 | #define TEGRA_PIN_GPIO_X3_AUD_PBB4 _GPIO(220) |
161 | #define TEGRA_PIN_HDMI_CEC_PCC0 _GPIO(224) |
162 | #define TEGRA_PIN_HDMI_INT_DP_HPD_PCC1 _GPIO(225) |
163 | #define TEGRA_PIN_SPDIF_OUT_PCC2 _GPIO(226) |
164 | #define TEGRA_PIN_SPDIF_IN_PCC3 _GPIO(227) |
165 | #define TEGRA_PIN_USB_VBUS_EN0_PCC4 _GPIO(228) |
166 | #define TEGRA_PIN_USB_VBUS_EN1_PCC5 _GPIO(229) |
167 | #define TEGRA_PIN_DP_HPD0_PCC6 _GPIO(230) |
168 | #define TEGRA_PIN_PCC7 _GPIO(231) |
169 | #define TEGRA_PIN_SPI2_CS1_PDD0 _GPIO(232) |
170 | #define TEGRA_PIN_QSPI_SCK_PEE0 _GPIO(240) |
171 | #define TEGRA_PIN_QSPI_CS_N_PEE1 _GPIO(241) |
172 | #define TEGRA_PIN_QSPI_IO0_PEE2 _GPIO(242) |
173 | #define TEGRA_PIN_QSPI_IO1_PEE3 _GPIO(243) |
174 | #define TEGRA_PIN_QSPI_IO2_PEE4 _GPIO(244) |
175 | #define TEGRA_PIN_QSPI_IO3_PEE5 _GPIO(245) |
176 | |
177 | /* All non-GPIO pins follow */ |
178 | #define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1) |
179 | #define _PIN(offset) (NUM_GPIOS + (offset)) |
180 | |
181 | /* Non-GPIO pins */ |
182 | #define TEGRA_PIN_CORE_PWR_REQ _PIN(0) |
183 | #define TEGRA_PIN_CPU_PWR_REQ _PIN(1) |
184 | #define TEGRA_PIN_PWR_INT_N _PIN(2) |
185 | #define TEGRA_PIN_CLK_32K_IN _PIN(3) |
186 | #define TEGRA_PIN_JTAG_RTCK _PIN(4) |
187 | #define TEGRA_PIN_BATT_BCL _PIN(5) |
188 | #define TEGRA_PIN_CLK_REQ _PIN(6) |
189 | #define TEGRA_PIN_SHUTDOWN _PIN(7) |
190 | |
191 | static const struct pinctrl_pin_desc tegra210_pins[] = { |
192 | PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N PA0" ), |
193 | PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N PA1" ), |
194 | PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N PA2" ), |
195 | PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N PA3" ), |
196 | PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N PA4" ), |
197 | PINCTRL_PIN(TEGRA_PIN_SATA_LED_ACTIVE_PA5, "SATA_LED_ACTIVE PA5" ), |
198 | PINCTRL_PIN(TEGRA_PIN_PA6, "PA6" ), |
199 | PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PB0, "DAP1_FS PB0" ), |
200 | PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PB1, "DAP1_DIN PB1" ), |
201 | PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PB2, "DAP1_DOUT PB2" ), |
202 | PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PB3, "DAP1_SCLK PB3" ), |
203 | PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PB4, "SPI2_MOSI PB4" ), |
204 | PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PB5, "SPI2_MISO PB5" ), |
205 | PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PB6, "SPI2_SCK PB6" ), |
206 | PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PB7, "SPI2_CS0 PB7" ), |
207 | PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PC0, "SPI1_MOSI PC0" ), |
208 | PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PC1, "SPI1_MISO PC1" ), |
209 | PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PC2, "SPI1_SCK PC2" ), |
210 | PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PC3, "SPI1_CS0 PC3" ), |
211 | PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PC4, "SPI1_CS1 PC4" ), |
212 | PINCTRL_PIN(TEGRA_PIN_SPI4_SCK_PC5, "SPI4_SCK PC5" ), |
213 | PINCTRL_PIN(TEGRA_PIN_SPI4_CS0_PC6, "SPI4_CS0 PC6" ), |
214 | PINCTRL_PIN(TEGRA_PIN_SPI4_MOSI_PC7, "SPI4_MOSI PC7" ), |
215 | PINCTRL_PIN(TEGRA_PIN_SPI4_MISO_PD0, "SPI4_MISO PD0" ), |
216 | PINCTRL_PIN(TEGRA_PIN_UART3_TX_PD1, "UART3_TX PD1" ), |
217 | PINCTRL_PIN(TEGRA_PIN_UART3_RX_PD2, "UART3_RX PD2" ), |
218 | PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PD3, "UART3_RTS PD3" ), |
219 | PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PD4, "UART3_CTS PD4" ), |
220 | PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PE0, "DMIC1_CLK PE0" ), |
221 | PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PE1, "DMIC1_DAT PE1" ), |
222 | PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PE2, "DMIC2_CLK PE2" ), |
223 | PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PE3, "DMIC2_DAT PE3" ), |
224 | PINCTRL_PIN(TEGRA_PIN_DMIC3_CLK_PE4, "DMIC3_CLK PE4" ), |
225 | PINCTRL_PIN(TEGRA_PIN_DMIC3_DAT_PE5, "DMIC3_DAT PE5" ), |
226 | PINCTRL_PIN(TEGRA_PIN_PE6, "PE6" ), |
227 | PINCTRL_PIN(TEGRA_PIN_PE7, "PE7" ), |
228 | PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PF0, "GEN3_I2C_SCL PF0" ), |
229 | PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PF1, "GEN3_I2C_SDA PF1" ), |
230 | PINCTRL_PIN(TEGRA_PIN_UART2_TX_PG0, "UART2_TX PG0" ), |
231 | PINCTRL_PIN(TEGRA_PIN_UART2_RX_PG1, "UART2_RX PG1" ), |
232 | PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PG2, "UART2_RTS PG2" ), |
233 | PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PG3, "UART2_CTS PG3" ), |
234 | PINCTRL_PIN(TEGRA_PIN_WIFI_EN_PH0, "WIFI_EN PH0" ), |
235 | PINCTRL_PIN(TEGRA_PIN_WIFI_RST_PH1, "WIFI_RST PH1" ), |
236 | PINCTRL_PIN(TEGRA_PIN_WIFI_WAKE_AP_PH2, "WIFI_WAKE_AP PH2" ), |
237 | PINCTRL_PIN(TEGRA_PIN_AP_WAKE_BT_PH3, "AP_WAKE_BT PH3" ), |
238 | PINCTRL_PIN(TEGRA_PIN_BT_RST_PH4, "BT_RST PH4" ), |
239 | PINCTRL_PIN(TEGRA_PIN_BT_WAKE_AP_PH5, "BT_WAKE_AP PH5" ), |
240 | PINCTRL_PIN(TEGRA_PIN_PH6, "PH6" ), |
241 | PINCTRL_PIN(TEGRA_PIN_AP_WAKE_NFC_PH7, "AP_WAKE_NFC PH7" ), |
242 | PINCTRL_PIN(TEGRA_PIN_NFC_EN_PI0, "NFC_EN PI0" ), |
243 | PINCTRL_PIN(TEGRA_PIN_NFC_INT_PI1, "NFC_INT PI1" ), |
244 | PINCTRL_PIN(TEGRA_PIN_GPS_EN_PI2, "GPS_EN PI2" ), |
245 | PINCTRL_PIN(TEGRA_PIN_GPS_RST_PI3, "GPS_RST PI3" ), |
246 | PINCTRL_PIN(TEGRA_PIN_UART4_TX_PI4, "UART4_TX PI4" ), |
247 | PINCTRL_PIN(TEGRA_PIN_UART4_RX_PI5, "UART4_RX PI5" ), |
248 | PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PI6, "UART4_RTS PI6" ), |
249 | PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PI7, "UART4_CTS PI7" ), |
250 | PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PJ0, "GEN1_I2C_SDA PJ0" ), |
251 | PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PJ1, "GEN1_I2C_SCL PJ1" ), |
252 | PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PJ2, "GEN2_I2C_SCL PJ2" ), |
253 | PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PJ3, "GEN2_I2C_SDA PJ3" ), |
254 | PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PJ4, "DAP4_FS PJ4" ), |
255 | PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PJ5, "DAP4_DIN PJ5" ), |
256 | PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PJ6, "DAP4_DOUT PJ6" ), |
257 | PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PJ7, "DAP4_SCLK PJ7" ), |
258 | PINCTRL_PIN(TEGRA_PIN_PK0, "PK0" ), |
259 | PINCTRL_PIN(TEGRA_PIN_PK1, "PK1" ), |
260 | PINCTRL_PIN(TEGRA_PIN_PK2, "PK2" ), |
261 | PINCTRL_PIN(TEGRA_PIN_PK3, "PK3" ), |
262 | PINCTRL_PIN(TEGRA_PIN_PK4, "PK4" ), |
263 | PINCTRL_PIN(TEGRA_PIN_PK5, "PK5" ), |
264 | PINCTRL_PIN(TEGRA_PIN_PK6, "PK6" ), |
265 | PINCTRL_PIN(TEGRA_PIN_PK7, "PK7" ), |
266 | PINCTRL_PIN(TEGRA_PIN_PL0, "PL0" ), |
267 | PINCTRL_PIN(TEGRA_PIN_PL1, "PL1" ), |
268 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PM0, "SDMMC1_CLK PM0" ), |
269 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PM1, "SDMMC1_CMD PM1" ), |
270 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PM2, "SDMMC1_DAT3 PM2" ), |
271 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PM3, "SDMMC1_DAT2 PM3" ), |
272 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PM4, "SDMMC1_DAT1 PM4" ), |
273 | PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PM5, "SDMMC1_DAT0 PM5" ), |
274 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PP0, "SDMMC3_CLK PP0" ), |
275 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PP1, "SDMMC3_CMD PP1" ), |
276 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PP2, "SDMMC3_DAT3 PP2" ), |
277 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PP3, "SDMMC3_DAT2 PP3" ), |
278 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PP4, "SDMMC3_DAT1 PP4" ), |
279 | PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PP5, "SDMMC3_DAT0 PP5" ), |
280 | PINCTRL_PIN(TEGRA_PIN_CAM1_MCLK_PS0, "CAM1_MCLK PS0" ), |
281 | PINCTRL_PIN(TEGRA_PIN_CAM2_MCLK_PS1, "CAM2_MCLK PS1" ), |
282 | PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PS2, "CAM_I2C_SCL PS2" ), |
283 | PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PS3, "CAM_I2C_SDA PS3" ), |
284 | PINCTRL_PIN(TEGRA_PIN_CAM_RST_PS4, "CAM_RST PS4" ), |
285 | PINCTRL_PIN(TEGRA_PIN_CAM_AF_EN_PS5, "CAM_AF_EN PS5" ), |
286 | PINCTRL_PIN(TEGRA_PIN_CAM_FLASH_EN_PS6, "CAM_FLASH_EN PS6" ), |
287 | PINCTRL_PIN(TEGRA_PIN_CAM1_PWDN_PS7, "CAM1_PWDN PS7" ), |
288 | PINCTRL_PIN(TEGRA_PIN_CAM2_PWDN_PT0, "CAM2_PWDN PT0" ), |
289 | PINCTRL_PIN(TEGRA_PIN_CAM1_STROBE_PT1, "CAM1_STROBE PT1" ), |
290 | PINCTRL_PIN(TEGRA_PIN_UART1_TX_PU0, "UART1_TX PU0" ), |
291 | PINCTRL_PIN(TEGRA_PIN_UART1_RX_PU1, "UART1_RX PU1" ), |
292 | PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PU2, "UART1_RTS PU2" ), |
293 | PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PU3, "UART1_CTS PU3" ), |
294 | PINCTRL_PIN(TEGRA_PIN_LCD_BL_PWM_PV0, "LCD_BL_PWM PV0" ), |
295 | PINCTRL_PIN(TEGRA_PIN_LCD_BL_EN_PV1, "LCD_BL_EN PV1" ), |
296 | PINCTRL_PIN(TEGRA_PIN_LCD_RST_PV2, "LCD_RST PV2" ), |
297 | PINCTRL_PIN(TEGRA_PIN_LCD_GPIO1_PV3, "LCD_GPIO1 PV3" ), |
298 | PINCTRL_PIN(TEGRA_PIN_LCD_GPIO2_PV4, "LCD_GPIO2 PV4" ), |
299 | PINCTRL_PIN(TEGRA_PIN_AP_READY_PV5, "AP_READY PV5" ), |
300 | PINCTRL_PIN(TEGRA_PIN_TOUCH_RST_PV6, "TOUCH_RST PV6" ), |
301 | PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PV7, "TOUCH_CLK PV7" ), |
302 | PINCTRL_PIN(TEGRA_PIN_MODEM_WAKE_AP_PX0, "MODEM_WAKE_AP PX0" ), |
303 | PINCTRL_PIN(TEGRA_PIN_TOUCH_INT_PX1, "TOUCH_INT PX1" ), |
304 | PINCTRL_PIN(TEGRA_PIN_MOTION_INT_PX2, "MOTION_INT PX2" ), |
305 | PINCTRL_PIN(TEGRA_PIN_ALS_PROX_INT_PX3, "ALS_PROX_INT PX3" ), |
306 | PINCTRL_PIN(TEGRA_PIN_TEMP_ALERT_PX4, "TEMP_ALERT PX4" ), |
307 | PINCTRL_PIN(TEGRA_PIN_BUTTON_POWER_ON_PX5, "BUTTON_POWER_ON PX5" ), |
308 | PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_UP_PX6, "BUTTON_VOL_UP PX6" ), |
309 | PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_DOWN_PX7, "BUTTON_VOL_DOWN PX7" ), |
310 | PINCTRL_PIN(TEGRA_PIN_BUTTON_SLIDE_SW_PY0, "BUTTON_SLIDE_SW PY0" ), |
311 | PINCTRL_PIN(TEGRA_PIN_BUTTON_HOME_PY1, "BUTTON_HOME PY1" ), |
312 | PINCTRL_PIN(TEGRA_PIN_LCD_TE_PY2, "LCD_TE PY2" ), |
313 | PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PY3, "PWR_I2C_SCL PY3" ), |
314 | PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PY4, "PWR_I2C_SDA PY4" ), |
315 | PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PY5, "CLK_32K_OUT PY5" ), |
316 | PINCTRL_PIN(TEGRA_PIN_PZ0, "PZ0" ), |
317 | PINCTRL_PIN(TEGRA_PIN_PZ1, "PZ1" ), |
318 | PINCTRL_PIN(TEGRA_PIN_PZ2, "PZ2" ), |
319 | PINCTRL_PIN(TEGRA_PIN_PZ3, "PZ3" ), |
320 | PINCTRL_PIN(TEGRA_PIN_PZ4, "PZ4" ), |
321 | PINCTRL_PIN(TEGRA_PIN_PZ5, "PZ5" ), |
322 | PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PAA0, "DAP2_FS PAA0" ), |
323 | PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PAA1, "DAP2_SCLK PAA1" ), |
324 | PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PAA2, "DAP2_DIN PAA2" ), |
325 | PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PAA3, "DAP2_DOUT PAA3" ), |
326 | PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PBB0, "AUD_MCLK PBB0" ), |
327 | PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PBB1, "DVFS_PWM PBB1" ), |
328 | PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PBB2, "DVFS_CLK PBB2" ), |
329 | PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PBB3, "GPIO_X1_AUD PBB3" ), |
330 | PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PBB4, "GPIO_X3_AUD PBB4" ), |
331 | PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PCC0, "HDMI_CEC PCC0" ), |
332 | PINCTRL_PIN(TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, "HDMI_INT_DP_HPD PCC1" ), |
333 | PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PCC2, "SPDIF_OUT PCC2" ), |
334 | PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PCC3, "SPDIF_IN PCC3" ), |
335 | PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PCC4, "USB_VBUS_EN0 PCC4" ), |
336 | PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PCC5, "USB_VBUS_EN1 PCC5" ), |
337 | PINCTRL_PIN(TEGRA_PIN_DP_HPD0_PCC6, "DP_HPD0 PCC6" ), |
338 | PINCTRL_PIN(TEGRA_PIN_PCC7, "PCC7" ), |
339 | PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PDD0, "SPI2_CS1 PDD0" ), |
340 | PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PEE0, "QSPI_SCK PEE0" ), |
341 | PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PEE1, "QSPI_CS_N PEE1" ), |
342 | PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PEE2, "QSPI_IO0 PEE2" ), |
343 | PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PEE3, "QSPI_IO1 PEE3" ), |
344 | PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PEE4, "QSPI_IO2 PEE4" ), |
345 | PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PEE5, "QSPI_IO3 PEE5" ), |
346 | PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ" ), |
347 | PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ" ), |
348 | PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N" ), |
349 | PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN" ), |
350 | PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK" ), |
351 | PINCTRL_PIN(TEGRA_PIN_BATT_BCL, "BATT_BCL" ), |
352 | PINCTRL_PIN(TEGRA_PIN_CLK_REQ, "CLK_REQ" ), |
353 | PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN" ), |
354 | }; |
355 | |
356 | static const unsigned pex_l0_rst_n_pa0_pins[] = { |
357 | TEGRA_PIN_PEX_L0_RST_N_PA0, |
358 | }; |
359 | |
360 | static const unsigned pex_l0_clkreq_n_pa1_pins[] = { |
361 | TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, |
362 | }; |
363 | |
364 | static const unsigned pex_wake_n_pa2_pins[] = { |
365 | TEGRA_PIN_PEX_WAKE_N_PA2, |
366 | }; |
367 | |
368 | static const unsigned pex_l1_rst_n_pa3_pins[] = { |
369 | TEGRA_PIN_PEX_L1_RST_N_PA3, |
370 | }; |
371 | |
372 | static const unsigned pex_l1_clkreq_n_pa4_pins[] = { |
373 | TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, |
374 | }; |
375 | |
376 | static const unsigned sata_led_active_pa5_pins[] = { |
377 | TEGRA_PIN_SATA_LED_ACTIVE_PA5, |
378 | }; |
379 | |
380 | static const unsigned pa6_pins[] = { |
381 | TEGRA_PIN_PA6, |
382 | }; |
383 | |
384 | static const unsigned dap1_fs_pb0_pins[] = { |
385 | TEGRA_PIN_DAP1_FS_PB0, |
386 | }; |
387 | |
388 | static const unsigned dap1_din_pb1_pins[] = { |
389 | TEGRA_PIN_DAP1_DIN_PB1, |
390 | }; |
391 | |
392 | static const unsigned dap1_dout_pb2_pins[] = { |
393 | TEGRA_PIN_DAP1_DOUT_PB2, |
394 | }; |
395 | |
396 | static const unsigned dap1_sclk_pb3_pins[] = { |
397 | TEGRA_PIN_DAP1_SCLK_PB3, |
398 | }; |
399 | |
400 | static const unsigned spi2_mosi_pb4_pins[] = { |
401 | TEGRA_PIN_SPI2_MOSI_PB4, |
402 | }; |
403 | |
404 | static const unsigned spi2_miso_pb5_pins[] = { |
405 | TEGRA_PIN_SPI2_MISO_PB5, |
406 | }; |
407 | |
408 | static const unsigned spi2_sck_pb6_pins[] = { |
409 | TEGRA_PIN_SPI2_SCK_PB6, |
410 | }; |
411 | |
412 | static const unsigned spi2_cs0_pb7_pins[] = { |
413 | TEGRA_PIN_SPI2_CS0_PB7, |
414 | }; |
415 | |
416 | static const unsigned spi1_mosi_pc0_pins[] = { |
417 | TEGRA_PIN_SPI1_MOSI_PC0, |
418 | }; |
419 | |
420 | static const unsigned spi1_miso_pc1_pins[] = { |
421 | TEGRA_PIN_SPI1_MISO_PC1, |
422 | }; |
423 | |
424 | static const unsigned spi1_sck_pc2_pins[] = { |
425 | TEGRA_PIN_SPI1_SCK_PC2, |
426 | }; |
427 | |
428 | static const unsigned spi1_cs0_pc3_pins[] = { |
429 | TEGRA_PIN_SPI1_CS0_PC3, |
430 | }; |
431 | |
432 | static const unsigned spi1_cs1_pc4_pins[] = { |
433 | TEGRA_PIN_SPI1_CS1_PC4, |
434 | }; |
435 | |
436 | static const unsigned spi4_sck_pc5_pins[] = { |
437 | TEGRA_PIN_SPI4_SCK_PC5, |
438 | }; |
439 | |
440 | static const unsigned spi4_cs0_pc6_pins[] = { |
441 | TEGRA_PIN_SPI4_CS0_PC6, |
442 | }; |
443 | |
444 | static const unsigned spi4_mosi_pc7_pins[] = { |
445 | TEGRA_PIN_SPI4_MOSI_PC7, |
446 | }; |
447 | |
448 | static const unsigned spi4_miso_pd0_pins[] = { |
449 | TEGRA_PIN_SPI4_MISO_PD0, |
450 | }; |
451 | |
452 | static const unsigned uart3_tx_pd1_pins[] = { |
453 | TEGRA_PIN_UART3_TX_PD1, |
454 | }; |
455 | |
456 | static const unsigned uart3_rx_pd2_pins[] = { |
457 | TEGRA_PIN_UART3_RX_PD2, |
458 | }; |
459 | |
460 | static const unsigned uart3_rts_pd3_pins[] = { |
461 | TEGRA_PIN_UART3_RTS_PD3, |
462 | }; |
463 | |
464 | static const unsigned uart3_cts_pd4_pins[] = { |
465 | TEGRA_PIN_UART3_CTS_PD4, |
466 | }; |
467 | |
468 | static const unsigned dmic1_clk_pe0_pins[] = { |
469 | TEGRA_PIN_DMIC1_CLK_PE0, |
470 | }; |
471 | |
472 | static const unsigned dmic1_dat_pe1_pins[] = { |
473 | TEGRA_PIN_DMIC1_DAT_PE1, |
474 | }; |
475 | |
476 | static const unsigned dmic2_clk_pe2_pins[] = { |
477 | TEGRA_PIN_DMIC2_CLK_PE2, |
478 | }; |
479 | |
480 | static const unsigned dmic2_dat_pe3_pins[] = { |
481 | TEGRA_PIN_DMIC2_DAT_PE3, |
482 | }; |
483 | |
484 | static const unsigned dmic3_clk_pe4_pins[] = { |
485 | TEGRA_PIN_DMIC3_CLK_PE4, |
486 | }; |
487 | |
488 | static const unsigned dmic3_dat_pe5_pins[] = { |
489 | TEGRA_PIN_DMIC3_DAT_PE5, |
490 | }; |
491 | |
492 | static const unsigned pe6_pins[] = { |
493 | TEGRA_PIN_PE6, |
494 | }; |
495 | |
496 | static const unsigned pe7_pins[] = { |
497 | TEGRA_PIN_PE7, |
498 | }; |
499 | |
500 | static const unsigned gen3_i2c_scl_pf0_pins[] = { |
501 | TEGRA_PIN_GEN3_I2C_SCL_PF0, |
502 | }; |
503 | |
504 | static const unsigned gen3_i2c_sda_pf1_pins[] = { |
505 | TEGRA_PIN_GEN3_I2C_SDA_PF1, |
506 | }; |
507 | |
508 | static const unsigned uart2_tx_pg0_pins[] = { |
509 | TEGRA_PIN_UART2_TX_PG0, |
510 | }; |
511 | |
512 | static const unsigned uart2_rx_pg1_pins[] = { |
513 | TEGRA_PIN_UART2_RX_PG1, |
514 | }; |
515 | |
516 | static const unsigned uart2_rts_pg2_pins[] = { |
517 | TEGRA_PIN_UART2_RTS_PG2, |
518 | }; |
519 | |
520 | static const unsigned uart2_cts_pg3_pins[] = { |
521 | TEGRA_PIN_UART2_CTS_PG3, |
522 | }; |
523 | |
524 | static const unsigned wifi_en_ph0_pins[] = { |
525 | TEGRA_PIN_WIFI_EN_PH0, |
526 | }; |
527 | |
528 | static const unsigned wifi_rst_ph1_pins[] = { |
529 | TEGRA_PIN_WIFI_RST_PH1, |
530 | }; |
531 | |
532 | static const unsigned wifi_wake_ap_ph2_pins[] = { |
533 | TEGRA_PIN_WIFI_WAKE_AP_PH2, |
534 | }; |
535 | |
536 | static const unsigned ap_wake_bt_ph3_pins[] = { |
537 | TEGRA_PIN_AP_WAKE_BT_PH3, |
538 | }; |
539 | |
540 | static const unsigned bt_rst_ph4_pins[] = { |
541 | TEGRA_PIN_BT_RST_PH4, |
542 | }; |
543 | |
544 | static const unsigned bt_wake_ap_ph5_pins[] = { |
545 | TEGRA_PIN_BT_WAKE_AP_PH5, |
546 | }; |
547 | |
548 | static const unsigned ph6_pins[] = { |
549 | TEGRA_PIN_PH6, |
550 | }; |
551 | |
552 | static const unsigned ap_wake_nfc_ph7_pins[] = { |
553 | TEGRA_PIN_AP_WAKE_NFC_PH7, |
554 | }; |
555 | |
556 | static const unsigned nfc_en_pi0_pins[] = { |
557 | TEGRA_PIN_NFC_EN_PI0, |
558 | }; |
559 | |
560 | static const unsigned nfc_int_pi1_pins[] = { |
561 | TEGRA_PIN_NFC_INT_PI1, |
562 | }; |
563 | |
564 | static const unsigned gps_en_pi2_pins[] = { |
565 | TEGRA_PIN_GPS_EN_PI2, |
566 | }; |
567 | |
568 | static const unsigned gps_rst_pi3_pins[] = { |
569 | TEGRA_PIN_GPS_RST_PI3, |
570 | }; |
571 | |
572 | static const unsigned uart4_tx_pi4_pins[] = { |
573 | TEGRA_PIN_UART4_TX_PI4, |
574 | }; |
575 | |
576 | static const unsigned uart4_rx_pi5_pins[] = { |
577 | TEGRA_PIN_UART4_RX_PI5, |
578 | }; |
579 | |
580 | static const unsigned uart4_rts_pi6_pins[] = { |
581 | TEGRA_PIN_UART4_RTS_PI6, |
582 | }; |
583 | |
584 | static const unsigned uart4_cts_pi7_pins[] = { |
585 | TEGRA_PIN_UART4_CTS_PI7, |
586 | }; |
587 | |
588 | static const unsigned gen1_i2c_sda_pj0_pins[] = { |
589 | TEGRA_PIN_GEN1_I2C_SDA_PJ0, |
590 | }; |
591 | |
592 | static const unsigned gen1_i2c_scl_pj1_pins[] = { |
593 | TEGRA_PIN_GEN1_I2C_SCL_PJ1, |
594 | }; |
595 | |
596 | static const unsigned gen2_i2c_scl_pj2_pins[] = { |
597 | TEGRA_PIN_GEN2_I2C_SCL_PJ2, |
598 | }; |
599 | |
600 | static const unsigned gen2_i2c_sda_pj3_pins[] = { |
601 | TEGRA_PIN_GEN2_I2C_SDA_PJ3, |
602 | }; |
603 | |
604 | static const unsigned dap4_fs_pj4_pins[] = { |
605 | TEGRA_PIN_DAP4_FS_PJ4, |
606 | }; |
607 | |
608 | static const unsigned dap4_din_pj5_pins[] = { |
609 | TEGRA_PIN_DAP4_DIN_PJ5, |
610 | }; |
611 | |
612 | static const unsigned dap4_dout_pj6_pins[] = { |
613 | TEGRA_PIN_DAP4_DOUT_PJ6, |
614 | }; |
615 | |
616 | static const unsigned dap4_sclk_pj7_pins[] = { |
617 | TEGRA_PIN_DAP4_SCLK_PJ7, |
618 | }; |
619 | |
620 | static const unsigned pk0_pins[] = { |
621 | TEGRA_PIN_PK0, |
622 | }; |
623 | |
624 | static const unsigned pk1_pins[] = { |
625 | TEGRA_PIN_PK1, |
626 | }; |
627 | |
628 | static const unsigned pk2_pins[] = { |
629 | TEGRA_PIN_PK2, |
630 | }; |
631 | |
632 | static const unsigned pk3_pins[] = { |
633 | TEGRA_PIN_PK3, |
634 | }; |
635 | |
636 | static const unsigned pk4_pins[] = { |
637 | TEGRA_PIN_PK4, |
638 | }; |
639 | |
640 | static const unsigned pk5_pins[] = { |
641 | TEGRA_PIN_PK5, |
642 | }; |
643 | |
644 | static const unsigned pk6_pins[] = { |
645 | TEGRA_PIN_PK6, |
646 | }; |
647 | |
648 | static const unsigned pk7_pins[] = { |
649 | TEGRA_PIN_PK7, |
650 | }; |
651 | |
652 | static const unsigned pl0_pins[] = { |
653 | TEGRA_PIN_PL0, |
654 | }; |
655 | |
656 | static const unsigned pl1_pins[] = { |
657 | TEGRA_PIN_PL1, |
658 | }; |
659 | |
660 | static const unsigned sdmmc1_clk_pm0_pins[] = { |
661 | TEGRA_PIN_SDMMC1_CLK_PM0, |
662 | }; |
663 | |
664 | static const unsigned sdmmc1_cmd_pm1_pins[] = { |
665 | TEGRA_PIN_SDMMC1_CMD_PM1, |
666 | }; |
667 | |
668 | static const unsigned sdmmc1_dat3_pm2_pins[] = { |
669 | TEGRA_PIN_SDMMC1_DAT3_PM2, |
670 | }; |
671 | |
672 | static const unsigned sdmmc1_dat2_pm3_pins[] = { |
673 | TEGRA_PIN_SDMMC1_DAT2_PM3, |
674 | }; |
675 | |
676 | static const unsigned sdmmc1_dat1_pm4_pins[] = { |
677 | TEGRA_PIN_SDMMC1_DAT1_PM4, |
678 | }; |
679 | |
680 | static const unsigned sdmmc1_dat0_pm5_pins[] = { |
681 | TEGRA_PIN_SDMMC1_DAT0_PM5, |
682 | }; |
683 | |
684 | static const unsigned sdmmc3_clk_pp0_pins[] = { |
685 | TEGRA_PIN_SDMMC3_CLK_PP0, |
686 | }; |
687 | |
688 | static const unsigned sdmmc3_cmd_pp1_pins[] = { |
689 | TEGRA_PIN_SDMMC3_CMD_PP1, |
690 | }; |
691 | |
692 | static const unsigned sdmmc3_dat3_pp2_pins[] = { |
693 | TEGRA_PIN_SDMMC3_DAT3_PP2, |
694 | }; |
695 | |
696 | static const unsigned sdmmc3_dat2_pp3_pins[] = { |
697 | TEGRA_PIN_SDMMC3_DAT2_PP3, |
698 | }; |
699 | |
700 | static const unsigned sdmmc3_dat1_pp4_pins[] = { |
701 | TEGRA_PIN_SDMMC3_DAT1_PP4, |
702 | }; |
703 | |
704 | static const unsigned sdmmc3_dat0_pp5_pins[] = { |
705 | TEGRA_PIN_SDMMC3_DAT0_PP5, |
706 | }; |
707 | |
708 | static const unsigned cam1_mclk_ps0_pins[] = { |
709 | TEGRA_PIN_CAM1_MCLK_PS0, |
710 | }; |
711 | |
712 | static const unsigned cam2_mclk_ps1_pins[] = { |
713 | TEGRA_PIN_CAM2_MCLK_PS1, |
714 | }; |
715 | |
716 | static const unsigned cam_i2c_scl_ps2_pins[] = { |
717 | TEGRA_PIN_CAM_I2C_SCL_PS2, |
718 | }; |
719 | |
720 | static const unsigned cam_i2c_sda_ps3_pins[] = { |
721 | TEGRA_PIN_CAM_I2C_SDA_PS3, |
722 | }; |
723 | |
724 | static const unsigned cam_rst_ps4_pins[] = { |
725 | TEGRA_PIN_CAM_RST_PS4, |
726 | }; |
727 | |
728 | static const unsigned cam_af_en_ps5_pins[] = { |
729 | TEGRA_PIN_CAM_AF_EN_PS5, |
730 | }; |
731 | |
732 | static const unsigned cam_flash_en_ps6_pins[] = { |
733 | TEGRA_PIN_CAM_FLASH_EN_PS6, |
734 | }; |
735 | |
736 | static const unsigned cam1_pwdn_ps7_pins[] = { |
737 | TEGRA_PIN_CAM1_PWDN_PS7, |
738 | }; |
739 | |
740 | static const unsigned cam2_pwdn_pt0_pins[] = { |
741 | TEGRA_PIN_CAM2_PWDN_PT0, |
742 | }; |
743 | |
744 | static const unsigned cam1_strobe_pt1_pins[] = { |
745 | TEGRA_PIN_CAM1_STROBE_PT1, |
746 | }; |
747 | |
748 | static const unsigned uart1_tx_pu0_pins[] = { |
749 | TEGRA_PIN_UART1_TX_PU0, |
750 | }; |
751 | |
752 | static const unsigned uart1_rx_pu1_pins[] = { |
753 | TEGRA_PIN_UART1_RX_PU1, |
754 | }; |
755 | |
756 | static const unsigned uart1_rts_pu2_pins[] = { |
757 | TEGRA_PIN_UART1_RTS_PU2, |
758 | }; |
759 | |
760 | static const unsigned uart1_cts_pu3_pins[] = { |
761 | TEGRA_PIN_UART1_CTS_PU3, |
762 | }; |
763 | |
764 | static const unsigned lcd_bl_pwm_pv0_pins[] = { |
765 | TEGRA_PIN_LCD_BL_PWM_PV0, |
766 | }; |
767 | |
768 | static const unsigned lcd_bl_en_pv1_pins[] = { |
769 | TEGRA_PIN_LCD_BL_EN_PV1, |
770 | }; |
771 | |
772 | static const unsigned lcd_rst_pv2_pins[] = { |
773 | TEGRA_PIN_LCD_RST_PV2, |
774 | }; |
775 | |
776 | static const unsigned lcd_gpio1_pv3_pins[] = { |
777 | TEGRA_PIN_LCD_GPIO1_PV3, |
778 | }; |
779 | |
780 | static const unsigned lcd_gpio2_pv4_pins[] = { |
781 | TEGRA_PIN_LCD_GPIO2_PV4, |
782 | }; |
783 | |
784 | static const unsigned ap_ready_pv5_pins[] = { |
785 | TEGRA_PIN_AP_READY_PV5, |
786 | }; |
787 | |
788 | static const unsigned touch_rst_pv6_pins[] = { |
789 | TEGRA_PIN_TOUCH_RST_PV6, |
790 | }; |
791 | |
792 | static const unsigned touch_clk_pv7_pins[] = { |
793 | TEGRA_PIN_TOUCH_CLK_PV7, |
794 | }; |
795 | |
796 | static const unsigned modem_wake_ap_px0_pins[] = { |
797 | TEGRA_PIN_MODEM_WAKE_AP_PX0, |
798 | }; |
799 | |
800 | static const unsigned touch_int_px1_pins[] = { |
801 | TEGRA_PIN_TOUCH_INT_PX1, |
802 | }; |
803 | |
804 | static const unsigned motion_int_px2_pins[] = { |
805 | TEGRA_PIN_MOTION_INT_PX2, |
806 | }; |
807 | |
808 | static const unsigned als_prox_int_px3_pins[] = { |
809 | TEGRA_PIN_ALS_PROX_INT_PX3, |
810 | }; |
811 | |
812 | static const unsigned temp_alert_px4_pins[] = { |
813 | TEGRA_PIN_TEMP_ALERT_PX4, |
814 | }; |
815 | |
816 | static const unsigned button_power_on_px5_pins[] = { |
817 | TEGRA_PIN_BUTTON_POWER_ON_PX5, |
818 | }; |
819 | |
820 | static const unsigned button_vol_up_px6_pins[] = { |
821 | TEGRA_PIN_BUTTON_VOL_UP_PX6, |
822 | }; |
823 | |
824 | static const unsigned button_vol_down_px7_pins[] = { |
825 | TEGRA_PIN_BUTTON_VOL_DOWN_PX7, |
826 | }; |
827 | |
828 | static const unsigned button_slide_sw_py0_pins[] = { |
829 | TEGRA_PIN_BUTTON_SLIDE_SW_PY0, |
830 | }; |
831 | |
832 | static const unsigned button_home_py1_pins[] = { |
833 | TEGRA_PIN_BUTTON_HOME_PY1, |
834 | }; |
835 | |
836 | static const unsigned lcd_te_py2_pins[] = { |
837 | TEGRA_PIN_LCD_TE_PY2, |
838 | }; |
839 | |
840 | static const unsigned pwr_i2c_scl_py3_pins[] = { |
841 | TEGRA_PIN_PWR_I2C_SCL_PY3, |
842 | }; |
843 | |
844 | static const unsigned pwr_i2c_sda_py4_pins[] = { |
845 | TEGRA_PIN_PWR_I2C_SDA_PY4, |
846 | }; |
847 | |
848 | static const unsigned clk_32k_out_py5_pins[] = { |
849 | TEGRA_PIN_CLK_32K_OUT_PY5, |
850 | }; |
851 | |
852 | static const unsigned pz0_pins[] = { |
853 | TEGRA_PIN_PZ0, |
854 | }; |
855 | |
856 | static const unsigned pz1_pins[] = { |
857 | TEGRA_PIN_PZ1, |
858 | }; |
859 | |
860 | static const unsigned pz2_pins[] = { |
861 | TEGRA_PIN_PZ2, |
862 | }; |
863 | |
864 | static const unsigned pz3_pins[] = { |
865 | TEGRA_PIN_PZ3, |
866 | }; |
867 | |
868 | static const unsigned pz4_pins[] = { |
869 | TEGRA_PIN_PZ4, |
870 | }; |
871 | |
872 | static const unsigned pz5_pins[] = { |
873 | TEGRA_PIN_PZ5, |
874 | }; |
875 | |
876 | static const unsigned dap2_fs_paa0_pins[] = { |
877 | TEGRA_PIN_DAP2_FS_PAA0, |
878 | }; |
879 | |
880 | static const unsigned dap2_sclk_paa1_pins[] = { |
881 | TEGRA_PIN_DAP2_SCLK_PAA1, |
882 | }; |
883 | |
884 | static const unsigned dap2_din_paa2_pins[] = { |
885 | TEGRA_PIN_DAP2_DIN_PAA2, |
886 | }; |
887 | |
888 | static const unsigned dap2_dout_paa3_pins[] = { |
889 | TEGRA_PIN_DAP2_DOUT_PAA3, |
890 | }; |
891 | |
892 | static const unsigned aud_mclk_pbb0_pins[] = { |
893 | TEGRA_PIN_AUD_MCLK_PBB0, |
894 | }; |
895 | |
896 | static const unsigned dvfs_pwm_pbb1_pins[] = { |
897 | TEGRA_PIN_DVFS_PWM_PBB1, |
898 | }; |
899 | |
900 | static const unsigned dvfs_clk_pbb2_pins[] = { |
901 | TEGRA_PIN_DVFS_CLK_PBB2, |
902 | }; |
903 | |
904 | static const unsigned gpio_x1_aud_pbb3_pins[] = { |
905 | TEGRA_PIN_GPIO_X1_AUD_PBB3, |
906 | }; |
907 | |
908 | static const unsigned gpio_x3_aud_pbb4_pins[] = { |
909 | TEGRA_PIN_GPIO_X3_AUD_PBB4, |
910 | }; |
911 | |
912 | static const unsigned hdmi_cec_pcc0_pins[] = { |
913 | TEGRA_PIN_HDMI_CEC_PCC0, |
914 | }; |
915 | |
916 | static const unsigned hdmi_int_dp_hpd_pcc1_pins[] = { |
917 | TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, |
918 | }; |
919 | |
920 | static const unsigned spdif_out_pcc2_pins[] = { |
921 | TEGRA_PIN_SPDIF_OUT_PCC2, |
922 | }; |
923 | |
924 | static const unsigned spdif_in_pcc3_pins[] = { |
925 | TEGRA_PIN_SPDIF_IN_PCC3, |
926 | }; |
927 | |
928 | static const unsigned usb_vbus_en0_pcc4_pins[] = { |
929 | TEGRA_PIN_USB_VBUS_EN0_PCC4, |
930 | }; |
931 | |
932 | static const unsigned usb_vbus_en1_pcc5_pins[] = { |
933 | TEGRA_PIN_USB_VBUS_EN1_PCC5, |
934 | }; |
935 | |
936 | static const unsigned dp_hpd0_pcc6_pins[] = { |
937 | TEGRA_PIN_DP_HPD0_PCC6, |
938 | }; |
939 | |
940 | static const unsigned pcc7_pins[] = { |
941 | TEGRA_PIN_PCC7, |
942 | }; |
943 | |
944 | static const unsigned spi2_cs1_pdd0_pins[] = { |
945 | TEGRA_PIN_SPI2_CS1_PDD0, |
946 | }; |
947 | |
948 | static const unsigned qspi_sck_pee0_pins[] = { |
949 | TEGRA_PIN_QSPI_SCK_PEE0, |
950 | }; |
951 | |
952 | static const unsigned qspi_cs_n_pee1_pins[] = { |
953 | TEGRA_PIN_QSPI_CS_N_PEE1, |
954 | }; |
955 | |
956 | static const unsigned qspi_io0_pee2_pins[] = { |
957 | TEGRA_PIN_QSPI_IO0_PEE2, |
958 | }; |
959 | |
960 | static const unsigned qspi_io1_pee3_pins[] = { |
961 | TEGRA_PIN_QSPI_IO1_PEE3, |
962 | }; |
963 | |
964 | static const unsigned qspi_io2_pee4_pins[] = { |
965 | TEGRA_PIN_QSPI_IO2_PEE4, |
966 | }; |
967 | |
968 | static const unsigned qspi_io3_pee5_pins[] = { |
969 | TEGRA_PIN_QSPI_IO3_PEE5, |
970 | }; |
971 | |
972 | static const unsigned core_pwr_req_pins[] = { |
973 | TEGRA_PIN_CORE_PWR_REQ, |
974 | }; |
975 | |
976 | static const unsigned cpu_pwr_req_pins[] = { |
977 | TEGRA_PIN_CPU_PWR_REQ, |
978 | }; |
979 | |
980 | static const unsigned pwr_int_n_pins[] = { |
981 | TEGRA_PIN_PWR_INT_N, |
982 | }; |
983 | |
984 | static const unsigned clk_32k_in_pins[] = { |
985 | TEGRA_PIN_CLK_32K_IN, |
986 | }; |
987 | |
988 | static const unsigned jtag_rtck_pins[] = { |
989 | TEGRA_PIN_JTAG_RTCK, |
990 | }; |
991 | |
992 | static const unsigned batt_bcl_pins[] = { |
993 | TEGRA_PIN_BATT_BCL, |
994 | }; |
995 | |
996 | static const unsigned clk_req_pins[] = { |
997 | TEGRA_PIN_CLK_REQ, |
998 | }; |
999 | |
1000 | static const unsigned shutdown_pins[] = { |
1001 | TEGRA_PIN_SHUTDOWN, |
1002 | }; |
1003 | |
1004 | static const unsigned drive_pa6_pins[] = { |
1005 | TEGRA_PIN_PA6, |
1006 | }; |
1007 | |
1008 | static const unsigned drive_pcc7_pins[] = { |
1009 | TEGRA_PIN_PCC7, |
1010 | }; |
1011 | |
1012 | static const unsigned drive_pe6_pins[] = { |
1013 | TEGRA_PIN_PE6, |
1014 | }; |
1015 | |
1016 | static const unsigned drive_pe7_pins[] = { |
1017 | TEGRA_PIN_PE7, |
1018 | }; |
1019 | |
1020 | static const unsigned drive_ph6_pins[] = { |
1021 | TEGRA_PIN_PH6, |
1022 | }; |
1023 | |
1024 | static const unsigned drive_pk0_pins[] = { |
1025 | TEGRA_PIN_PK0, |
1026 | }; |
1027 | |
1028 | static const unsigned drive_pk1_pins[] = { |
1029 | TEGRA_PIN_PK1, |
1030 | }; |
1031 | |
1032 | static const unsigned drive_pk2_pins[] = { |
1033 | TEGRA_PIN_PK2, |
1034 | }; |
1035 | |
1036 | static const unsigned drive_pk3_pins[] = { |
1037 | TEGRA_PIN_PK3, |
1038 | }; |
1039 | |
1040 | static const unsigned drive_pk4_pins[] = { |
1041 | TEGRA_PIN_PK4, |
1042 | }; |
1043 | |
1044 | static const unsigned drive_pk5_pins[] = { |
1045 | TEGRA_PIN_PK5, |
1046 | }; |
1047 | |
1048 | static const unsigned drive_pk6_pins[] = { |
1049 | TEGRA_PIN_PK6, |
1050 | }; |
1051 | |
1052 | static const unsigned drive_pk7_pins[] = { |
1053 | TEGRA_PIN_PK7, |
1054 | }; |
1055 | |
1056 | static const unsigned drive_pl0_pins[] = { |
1057 | TEGRA_PIN_PL0, |
1058 | }; |
1059 | |
1060 | static const unsigned drive_pl1_pins[] = { |
1061 | TEGRA_PIN_PL1, |
1062 | }; |
1063 | |
1064 | static const unsigned drive_pz0_pins[] = { |
1065 | TEGRA_PIN_PZ0, |
1066 | }; |
1067 | |
1068 | static const unsigned drive_pz1_pins[] = { |
1069 | TEGRA_PIN_PZ1, |
1070 | }; |
1071 | |
1072 | static const unsigned drive_pz2_pins[] = { |
1073 | TEGRA_PIN_PZ2, |
1074 | }; |
1075 | |
1076 | static const unsigned drive_pz3_pins[] = { |
1077 | TEGRA_PIN_PZ3, |
1078 | }; |
1079 | |
1080 | static const unsigned drive_pz4_pins[] = { |
1081 | TEGRA_PIN_PZ4, |
1082 | }; |
1083 | |
1084 | static const unsigned drive_pz5_pins[] = { |
1085 | TEGRA_PIN_PZ5, |
1086 | }; |
1087 | |
1088 | static const unsigned drive_sdmmc1_pins[] = { |
1089 | TEGRA_PIN_SDMMC1_CLK_PM0, |
1090 | TEGRA_PIN_SDMMC1_CMD_PM1, |
1091 | TEGRA_PIN_SDMMC1_DAT3_PM2, |
1092 | TEGRA_PIN_SDMMC1_DAT2_PM3, |
1093 | TEGRA_PIN_SDMMC1_DAT1_PM4, |
1094 | TEGRA_PIN_SDMMC1_DAT0_PM5, |
1095 | }; |
1096 | |
1097 | static const unsigned drive_sdmmc2_pins[] = { |
1098 | }; |
1099 | |
1100 | static const unsigned drive_sdmmc3_pins[] = { |
1101 | TEGRA_PIN_SDMMC3_CLK_PP0, |
1102 | TEGRA_PIN_SDMMC3_CMD_PP1, |
1103 | TEGRA_PIN_SDMMC3_DAT3_PP2, |
1104 | TEGRA_PIN_SDMMC3_DAT2_PP3, |
1105 | TEGRA_PIN_SDMMC3_DAT1_PP4, |
1106 | TEGRA_PIN_SDMMC3_DAT0_PP5, |
1107 | }; |
1108 | |
1109 | static const unsigned drive_sdmmc4_pins[] = { |
1110 | }; |
1111 | |
1112 | enum tegra_mux { |
1113 | TEGRA_MUX_AUD, |
1114 | TEGRA_MUX_BCL, |
1115 | TEGRA_MUX_BLINK, |
1116 | TEGRA_MUX_CCLA, |
1117 | TEGRA_MUX_CEC, |
1118 | TEGRA_MUX_CLDVFS, |
1119 | TEGRA_MUX_CLK, |
1120 | TEGRA_MUX_CORE, |
1121 | TEGRA_MUX_CPU, |
1122 | TEGRA_MUX_DISPLAYA, |
1123 | TEGRA_MUX_DISPLAYB, |
1124 | TEGRA_MUX_DMIC1, |
1125 | TEGRA_MUX_DMIC2, |
1126 | TEGRA_MUX_DMIC3, |
1127 | TEGRA_MUX_DP, |
1128 | TEGRA_MUX_DTV, |
1129 | TEGRA_MUX_EXTPERIPH3, |
1130 | TEGRA_MUX_I2C1, |
1131 | TEGRA_MUX_I2C2, |
1132 | TEGRA_MUX_I2C3, |
1133 | TEGRA_MUX_I2CPMU, |
1134 | TEGRA_MUX_I2CVI, |
1135 | TEGRA_MUX_I2S1, |
1136 | TEGRA_MUX_I2S2, |
1137 | TEGRA_MUX_I2S3, |
1138 | TEGRA_MUX_I2S4A, |
1139 | TEGRA_MUX_I2S4B, |
1140 | TEGRA_MUX_I2S5A, |
1141 | TEGRA_MUX_I2S5B, |
1142 | TEGRA_MUX_IQC0, |
1143 | TEGRA_MUX_IQC1, |
1144 | TEGRA_MUX_JTAG, |
1145 | TEGRA_MUX_PE, |
1146 | TEGRA_MUX_PE0, |
1147 | TEGRA_MUX_PE1, |
1148 | TEGRA_MUX_PMI, |
1149 | TEGRA_MUX_PWM0, |
1150 | TEGRA_MUX_PWM1, |
1151 | TEGRA_MUX_PWM2, |
1152 | TEGRA_MUX_PWM3, |
1153 | TEGRA_MUX_QSPI, |
1154 | TEGRA_MUX_RSVD0, |
1155 | TEGRA_MUX_RSVD1, |
1156 | TEGRA_MUX_RSVD2, |
1157 | TEGRA_MUX_RSVD3, |
1158 | TEGRA_MUX_SATA, |
1159 | TEGRA_MUX_SDMMC1, |
1160 | TEGRA_MUX_SDMMC3, |
1161 | TEGRA_MUX_SHUTDOWN, |
1162 | TEGRA_MUX_SOC, |
1163 | TEGRA_MUX_SOR0, |
1164 | TEGRA_MUX_SOR1, |
1165 | TEGRA_MUX_SPDIF, |
1166 | TEGRA_MUX_SPI1, |
1167 | TEGRA_MUX_SPI2, |
1168 | TEGRA_MUX_SPI3, |
1169 | TEGRA_MUX_SPI4, |
1170 | TEGRA_MUX_SYS, |
1171 | TEGRA_MUX_TOUCH, |
1172 | TEGRA_MUX_UART, |
1173 | TEGRA_MUX_UARTA, |
1174 | TEGRA_MUX_UARTB, |
1175 | TEGRA_MUX_UARTC, |
1176 | TEGRA_MUX_UARTD, |
1177 | TEGRA_MUX_USB, |
1178 | TEGRA_MUX_VGP1, |
1179 | TEGRA_MUX_VGP2, |
1180 | TEGRA_MUX_VGP3, |
1181 | TEGRA_MUX_VGP4, |
1182 | TEGRA_MUX_VGP5, |
1183 | TEGRA_MUX_VGP6, |
1184 | TEGRA_MUX_VIMCLK, |
1185 | TEGRA_MUX_VIMCLK2, |
1186 | }; |
1187 | |
1188 | #define FUNCTION(fname) #fname |
1189 | |
1190 | static const char * const tegra210_functions[] = { |
1191 | FUNCTION(aud), |
1192 | FUNCTION(bcl), |
1193 | FUNCTION(blink), |
1194 | FUNCTION(ccla), |
1195 | FUNCTION(cec), |
1196 | FUNCTION(cldvfs), |
1197 | FUNCTION(clk), |
1198 | FUNCTION(core), |
1199 | FUNCTION(cpu), |
1200 | FUNCTION(displaya), |
1201 | FUNCTION(displayb), |
1202 | FUNCTION(dmic1), |
1203 | FUNCTION(dmic2), |
1204 | FUNCTION(dmic3), |
1205 | FUNCTION(dp), |
1206 | FUNCTION(dtv), |
1207 | FUNCTION(extperiph3), |
1208 | FUNCTION(i2c1), |
1209 | FUNCTION(i2c2), |
1210 | FUNCTION(i2c3), |
1211 | FUNCTION(i2cpmu), |
1212 | FUNCTION(i2cvi), |
1213 | FUNCTION(i2s1), |
1214 | FUNCTION(i2s2), |
1215 | FUNCTION(i2s3), |
1216 | FUNCTION(i2s4a), |
1217 | FUNCTION(i2s4b), |
1218 | FUNCTION(i2s5a), |
1219 | FUNCTION(i2s5b), |
1220 | FUNCTION(iqc0), |
1221 | FUNCTION(iqc1), |
1222 | FUNCTION(jtag), |
1223 | FUNCTION(pe), |
1224 | FUNCTION(pe0), |
1225 | FUNCTION(pe1), |
1226 | FUNCTION(pmi), |
1227 | FUNCTION(pwm0), |
1228 | FUNCTION(pwm1), |
1229 | FUNCTION(pwm2), |
1230 | FUNCTION(pwm3), |
1231 | FUNCTION(qspi), |
1232 | FUNCTION(rsvd0), |
1233 | FUNCTION(rsvd1), |
1234 | FUNCTION(rsvd2), |
1235 | FUNCTION(rsvd3), |
1236 | FUNCTION(sata), |
1237 | FUNCTION(sdmmc1), |
1238 | FUNCTION(sdmmc3), |
1239 | FUNCTION(shutdown), |
1240 | FUNCTION(soc), |
1241 | FUNCTION(sor0), |
1242 | FUNCTION(sor1), |
1243 | FUNCTION(spdif), |
1244 | FUNCTION(spi1), |
1245 | FUNCTION(spi2), |
1246 | FUNCTION(spi3), |
1247 | FUNCTION(spi4), |
1248 | FUNCTION(sys), |
1249 | FUNCTION(touch), |
1250 | FUNCTION(uart), |
1251 | FUNCTION(uarta), |
1252 | FUNCTION(uartb), |
1253 | FUNCTION(uartc), |
1254 | FUNCTION(uartd), |
1255 | FUNCTION(usb), |
1256 | FUNCTION(vgp1), |
1257 | FUNCTION(vgp2), |
1258 | FUNCTION(vgp3), |
1259 | FUNCTION(vgp4), |
1260 | FUNCTION(vgp5), |
1261 | FUNCTION(vgp6), |
1262 | FUNCTION(vimclk), |
1263 | FUNCTION(vimclk2), |
1264 | }; |
1265 | |
1266 | #define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */ |
1267 | #define PINGROUP_REG_A 0x3000 /* bank 1 */ |
1268 | |
1269 | #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) |
1270 | #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) |
1271 | |
1272 | #define PINGROUP_BIT_Y(b) (b) |
1273 | #define PINGROUP_BIT_N(b) (-1) |
1274 | |
1275 | #define PINGROUP(pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, \ |
1276 | lpdr, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b,\ |
1277 | slwr_w, slwf_b, slwf_w) \ |
1278 | { \ |
1279 | .name = #pg_name, \ |
1280 | .pins = pg_name##_pins, \ |
1281 | .npins = ARRAY_SIZE(pg_name##_pins), \ |
1282 | .funcs = { \ |
1283 | TEGRA_MUX_##f0, \ |
1284 | TEGRA_MUX_##f1, \ |
1285 | TEGRA_MUX_##f2, \ |
1286 | TEGRA_MUX_##f3, \ |
1287 | }, \ |
1288 | .mux_reg = PINGROUP_REG(r), \ |
1289 | .mux_bank = 1, \ |
1290 | .mux_bit = 0, \ |
1291 | .pupd_reg = PINGROUP_REG(r), \ |
1292 | .pupd_bank = 1, \ |
1293 | .pupd_bit = 2, \ |
1294 | .tri_reg = PINGROUP_REG(r), \ |
1295 | .tri_bank = 1, \ |
1296 | .tri_bit = 4, \ |
1297 | .einput_bit = 6, \ |
1298 | .odrain_bit = 11, \ |
1299 | .lock_bit = 7, \ |
1300 | .ioreset_bit = -1, \ |
1301 | .rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \ |
1302 | .hsm_bit = PINGROUP_BIT_##hsm(9), \ |
1303 | .schmitt_bit = 12, \ |
1304 | .drvtype_bit = PINGROUP_BIT_##drvtype(13), \ |
1305 | .drv_reg = DRV_PINGROUP_REG(rdrv), \ |
1306 | .drv_bank = 0, \ |
1307 | .lpmd_bit = -1, \ |
1308 | .drvdn_bit = drvdn_b, \ |
1309 | .drvdn_width = drvdn_w, \ |
1310 | .drvup_bit = drvup_b, \ |
1311 | .drvup_width = drvup_w, \ |
1312 | .slwr_bit = slwr_b, \ |
1313 | .slwr_width = slwr_w, \ |
1314 | .slwf_bit = slwf_b, \ |
1315 | .slwf_width = slwf_w, \ |
1316 | .parked_bitmask = BIT(5), \ |
1317 | .lpdr_bit = PINGROUP_BIT_##lpdr(8), \ |
1318 | } |
1319 | |
1320 | #define DRV_PINGROUP(pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, \ |
1321 | drvup_w, slwr_b, slwr_w, slwf_b, slwf_w) \ |
1322 | { \ |
1323 | .name = "drive_" #pg_name, \ |
1324 | .pins = drive_##pg_name##_pins, \ |
1325 | .npins = ARRAY_SIZE(drive_##pg_name##_pins), \ |
1326 | .mux_reg = -1, \ |
1327 | .pupd_reg = -1, \ |
1328 | .tri_reg = -1, \ |
1329 | .einput_bit = -1, \ |
1330 | .odrain_bit = -1, \ |
1331 | .lock_bit = -1, \ |
1332 | .ioreset_bit = -1, \ |
1333 | .rcv_sel_bit = -1, \ |
1334 | .drv_reg = DRV_PINGROUP_REG(r), \ |
1335 | .drv_bank = 0, \ |
1336 | .hsm_bit = -1, \ |
1337 | .schmitt_bit = -1, \ |
1338 | .lpdr_bit = -1, \ |
1339 | .lpmd_bit = -1, \ |
1340 | .drvdn_bit = drvdn_b, \ |
1341 | .drvdn_width = drvdn_w, \ |
1342 | .drvup_bit = drvup_b, \ |
1343 | .drvup_width = drvup_w, \ |
1344 | .slwr_bit = slwr_b, \ |
1345 | .slwr_width = slwr_w, \ |
1346 | .slwf_bit = slwf_b, \ |
1347 | .slwf_width = slwf_w, \ |
1348 | .drvtype_bit = -1, \ |
1349 | .parked_bitmask = prk_mask, \ |
1350 | } |
1351 | |
1352 | static const struct tegra_pingroup tegra210_groups[] = { |
1353 | /* pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, lpdr, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */ |
1354 | PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1355 | PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1356 | PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1357 | PINGROUP(sdmmc1_dat2_pm3, SDMMC1, SPI3, RSVD2, RSVD3, 0x300c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1358 | PINGROUP(sdmmc1_dat1_pm4, SDMMC1, SPI3, RSVD2, RSVD3, 0x3010, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1359 | PINGROUP(sdmmc1_dat0_pm5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3014, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1360 | PINGROUP(sdmmc3_clk_pp0, SDMMC3, RSVD1, RSVD2, RSVD3, 0x301c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1361 | PINGROUP(sdmmc3_cmd_pp1, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3020, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1362 | PINGROUP(sdmmc3_dat0_pp5, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3024, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1363 | PINGROUP(sdmmc3_dat1_pp4, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3028, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1364 | PINGROUP(sdmmc3_dat2_pp3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x302c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1365 | PINGROUP(sdmmc3_dat3_pp2, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3030, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1366 | PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x3038, N, N, Y, Y, 0xa5c, 12, 5, 20, 5, -1, -1, -1, -1), |
1367 | PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x303c, N, N, Y, Y, 0xa58, 12, 5, 20, 5, -1, -1, -1, -1), |
1368 | PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x3040, N, N, Y, Y, 0xa68, 12, 5, 20, 5, -1, -1, -1, -1), |
1369 | PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x3044, N, N, Y, Y, 0xa64, 12, 5, 20, 5, -1, -1, -1, -1), |
1370 | PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x3048, N, N, Y, Y, 0xa60, 12, 5, 20, 5, -1, -1, -1, -1), |
1371 | PINGROUP(sata_led_active_pa5, SATA, RSVD1, RSVD2, RSVD3, 0x304c, N, N, N, Y, 0xa94, 12, 5, 20, 5, -1, -1, -1, -1), |
1372 | PINGROUP(spi1_mosi_pc0, SPI1, RSVD1, RSVD2, RSVD3, 0x3050, Y, Y, N, N, 0xae0, -1, -1, -1, -1, 28, 2, 30, 2), |
1373 | PINGROUP(spi1_miso_pc1, SPI1, RSVD1, RSVD2, RSVD3, 0x3054, Y, Y, N, N, 0xadc, -1, -1, -1, -1, 28, 2, 30, 2), |
1374 | PINGROUP(spi1_sck_pc2, SPI1, RSVD1, RSVD2, RSVD3, 0x3058, Y, Y, N, N, 0xae4, -1, -1, -1, -1, 28, 2, 30, 2), |
1375 | PINGROUP(spi1_cs0_pc3, SPI1, RSVD1, RSVD2, RSVD3, 0x305c, Y, Y, N, N, 0xad4, -1, -1, -1, -1, 28, 2, 30, 2), |
1376 | PINGROUP(spi1_cs1_pc4, SPI1, RSVD1, RSVD2, RSVD3, 0x3060, Y, Y, N, N, 0xad8, -1, -1, -1, -1, 28, 2, 30, 2), |
1377 | PINGROUP(spi2_mosi_pb4, SPI2, DTV, RSVD2, RSVD3, 0x3064, Y, Y, N, N, 0xaf4, -1, -1, -1, -1, 28, 2, 30, 2), |
1378 | PINGROUP(spi2_miso_pb5, SPI2, DTV, RSVD2, RSVD3, 0x3068, Y, Y, N, N, 0xaf0, -1, -1, -1, -1, 28, 2, 30, 2), |
1379 | PINGROUP(spi2_sck_pb6, SPI2, DTV, RSVD2, RSVD3, 0x306c, Y, Y, N, N, 0xaf8, -1, -1, -1, -1, 28, 2, 30, 2), |
1380 | PINGROUP(spi2_cs0_pb7, SPI2, DTV, RSVD2, RSVD3, 0x3070, Y, Y, N, N, 0xae8, -1, -1, -1, -1, 28, 2, 30, 2), |
1381 | PINGROUP(spi2_cs1_pdd0, SPI2, RSVD1, RSVD2, RSVD3, 0x3074, Y, Y, N, N, 0xaec, -1, -1, -1, -1, 28, 2, 30, 2), |
1382 | PINGROUP(spi4_mosi_pc7, SPI4, RSVD1, RSVD2, RSVD3, 0x3078, Y, Y, N, N, 0xb04, -1, -1, -1, -1, 28, 2, 30, 2), |
1383 | PINGROUP(spi4_miso_pd0, SPI4, RSVD1, RSVD2, RSVD3, 0x307c, Y, Y, N, N, 0xb00, -1, -1, -1, -1, 28, 2, 30, 2), |
1384 | PINGROUP(spi4_sck_pc5, SPI4, RSVD1, RSVD2, RSVD3, 0x3080, Y, Y, N, N, 0xb08, -1, -1, -1, -1, 28, 2, 30, 2), |
1385 | PINGROUP(spi4_cs0_pc6, SPI4, RSVD1, RSVD2, RSVD3, 0x3084, Y, Y, N, N, 0xafc, -1, -1, -1, -1, 28, 2, 30, 2), |
1386 | PINGROUP(qspi_sck_pee0, QSPI, RSVD1, RSVD2, RSVD3, 0x3088, Y, Y, N, N, 0xa90, -1, -1, -1, -1, 28, 2, 30, 2), |
1387 | PINGROUP(qspi_cs_n_pee1, QSPI, RSVD1, RSVD2, RSVD3, 0x308c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1388 | PINGROUP(qspi_io0_pee2, QSPI, RSVD1, RSVD2, RSVD3, 0x3090, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1389 | PINGROUP(qspi_io1_pee3, QSPI, RSVD1, RSVD2, RSVD3, 0x3094, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1390 | PINGROUP(qspi_io2_pee4, QSPI, RSVD1, RSVD2, RSVD3, 0x3098, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1391 | PINGROUP(qspi_io3_pee5, QSPI, RSVD1, RSVD2, RSVD3, 0x309c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1392 | PINGROUP(dmic1_clk_pe0, DMIC1, I2S3, RSVD2, RSVD3, 0x30a4, N, N, N, Y, 0x984, 12, 5, 20, 5, -1, -1, -1, -1), |
1393 | PINGROUP(dmic1_dat_pe1, DMIC1, I2S3, RSVD2, RSVD3, 0x30a8, N, N, N, Y, 0x988, 12, 5, 20, 5, -1, -1, -1, -1), |
1394 | PINGROUP(dmic2_clk_pe2, DMIC2, I2S3, RSVD2, RSVD3, 0x30ac, N, N, N, Y, 0x98c, 12, 5, 20, 5, -1, -1, -1, -1), |
1395 | PINGROUP(dmic2_dat_pe3, DMIC2, I2S3, RSVD2, RSVD3, 0x30b0, N, N, N, Y, 0x990, 12, 5, 20, 5, -1, -1, -1, -1), |
1396 | PINGROUP(dmic3_clk_pe4, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b4, N, N, N, Y, 0x994, 12, 5, 20, 5, -1, -1, -1, -1), |
1397 | PINGROUP(dmic3_dat_pe5, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b8, N, N, N, Y, 0x998, 12, 5, 20, 5, -1, -1, -1, -1), |
1398 | PINGROUP(gen1_i2c_scl_pj1, I2C1, RSVD1, RSVD2, RSVD3, 0x30bc, N, N, Y, Y, 0x9a8, 12, 5, 20, 5, -1, -1, -1, -1), |
1399 | PINGROUP(gen1_i2c_sda_pj0, I2C1, RSVD1, RSVD2, RSVD3, 0x30c0, N, N, Y, Y, 0x9ac, 12, 5, 20, 5, -1, -1, -1, -1), |
1400 | PINGROUP(gen2_i2c_scl_pj2, I2C2, RSVD1, RSVD2, RSVD3, 0x30c4, N, N, Y, Y, 0x9b0, 12, 5, 20, 5, -1, -1, -1, -1), |
1401 | PINGROUP(gen2_i2c_sda_pj3, I2C2, RSVD1, RSVD2, RSVD3, 0x30c8, N, N, Y, Y, 0x9b4, 12, 5, 20, 5, -1, -1, -1, -1), |
1402 | PINGROUP(gen3_i2c_scl_pf0, I2C3, RSVD1, RSVD2, RSVD3, 0x30cc, N, N, Y, Y, 0x9b8, 12, 5, 20, 5, -1, -1, -1, -1), |
1403 | PINGROUP(gen3_i2c_sda_pf1, I2C3, RSVD1, RSVD2, RSVD3, 0x30d0, N, N, Y, Y, 0x9bc, 12, 5, 20, 5, -1, -1, -1, -1), |
1404 | PINGROUP(cam_i2c_scl_ps2, I2C3, I2CVI, RSVD2, RSVD3, 0x30d4, N, N, Y, Y, 0x934, 12, 5, 20, 5, -1, -1, -1, -1), |
1405 | PINGROUP(cam_i2c_sda_ps3, I2C3, I2CVI, RSVD2, RSVD3, 0x30d8, N, N, Y, Y, 0x938, 12, 5, 20, 5, -1, -1, -1, -1), |
1406 | PINGROUP(pwr_i2c_scl_py3, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30dc, N, N, Y, Y, 0xa6c, 12, 5, 20, 5, -1, -1, -1, -1), |
1407 | PINGROUP(pwr_i2c_sda_py4, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30e0, N, N, Y, Y, 0xa70, 12, 5, 20, 5, -1, -1, -1, -1), |
1408 | PINGROUP(uart1_tx_pu0, UARTA, RSVD1, RSVD2, RSVD3, 0x30e4, N, N, N, Y, 0xb28, 12, 5, 20, 5, -1, -1, -1, -1), |
1409 | PINGROUP(uart1_rx_pu1, UARTA, RSVD1, RSVD2, RSVD3, 0x30e8, N, N, N, Y, 0xb24, 12, 5, 20, 5, -1, -1, -1, -1), |
1410 | PINGROUP(uart1_rts_pu2, UARTA, RSVD1, RSVD2, RSVD3, 0x30ec, N, N, N, Y, 0xb20, 12, 5, 20, 5, -1, -1, -1, -1), |
1411 | PINGROUP(uart1_cts_pu3, UARTA, RSVD1, RSVD2, RSVD3, 0x30f0, N, N, N, Y, 0xb1c, 12, 5, 20, 5, -1, -1, -1, -1), |
1412 | PINGROUP(uart2_tx_pg0, UARTB, I2S4A, SPDIF, UART, 0x30f4, N, N, N, Y, 0xb38, 12, 5, 20, 5, -1, -1, -1, -1), |
1413 | PINGROUP(uart2_rx_pg1, UARTB, I2S4A, SPDIF, UART, 0x30f8, N, N, N, Y, 0xb34, 12, 5, 20, 5, -1, -1, -1, -1), |
1414 | PINGROUP(uart2_rts_pg2, UARTB, I2S4A, RSVD2, UART, 0x30fc, N, N, N, Y, 0xb30, 12, 5, 20, 5, -1, -1, -1, -1), |
1415 | PINGROUP(uart2_cts_pg3, UARTB, I2S4A, RSVD2, UART, 0x3100, N, N, N, Y, 0xb2c, 12, 5, 20, 5, -1, -1, -1, -1), |
1416 | PINGROUP(uart3_tx_pd1, UARTC, SPI4, RSVD2, RSVD3, 0x3104, N, N, N, Y, 0xb48, 12, 5, 20, 5, -1, -1, -1, -1), |
1417 | PINGROUP(uart3_rx_pd2, UARTC, SPI4, RSVD2, RSVD3, 0x3108, N, N, N, Y, 0xb44, 12, 5, 20, 5, -1, -1, -1, -1), |
1418 | PINGROUP(uart3_rts_pd3, UARTC, SPI4, RSVD2, RSVD3, 0x310c, N, N, N, Y, 0xb40, 12, 5, 20, 5, -1, -1, -1, -1), |
1419 | PINGROUP(uart3_cts_pd4, UARTC, SPI4, RSVD2, RSVD3, 0x3110, N, N, N, Y, 0xb3c, 12, 5, 20, 5, -1, -1, -1, -1), |
1420 | PINGROUP(uart4_tx_pi4, UARTD, UART, RSVD2, RSVD3, 0x3114, N, N, N, Y, 0xb58, 12, 5, 20, 5, -1, -1, -1, -1), |
1421 | PINGROUP(uart4_rx_pi5, UARTD, UART, RSVD2, RSVD3, 0x3118, N, N, N, Y, 0xb54, 12, 5, 20, 5, -1, -1, -1, -1), |
1422 | PINGROUP(uart4_rts_pi6, UARTD, UART, RSVD2, RSVD3, 0x311c, N, N, N, Y, 0xb50, 12, 5, 20, 5, -1, -1, -1, -1), |
1423 | PINGROUP(uart4_cts_pi7, UARTD, UART, RSVD2, RSVD3, 0x3120, N, N, N, Y, 0xb4c, 12, 5, 20, 5, -1, -1, -1, -1), |
1424 | PINGROUP(dap1_fs_pb0, I2S1, RSVD1, RSVD2, RSVD3, 0x3124, Y, Y, N, Y, 0x95c, -1, -1, -1, -1, 28, 2, 30, 2), |
1425 | PINGROUP(dap1_din_pb1, I2S1, RSVD1, RSVD2, RSVD3, 0x3128, Y, Y, N, N, 0x954, -1, -1, -1, -1, 28, 2, 30, 2), |
1426 | PINGROUP(dap1_dout_pb2, I2S1, RSVD1, RSVD2, RSVD3, 0x312c, Y, Y, N, N, 0x958, -1, -1, -1, -1, 28, 2, 30, 2), |
1427 | PINGROUP(dap1_sclk_pb3, I2S1, RSVD1, RSVD2, RSVD3, 0x3130, Y, Y, N, N, 0x960, -1, -1, -1, -1, 28, 2, 30, 2), |
1428 | PINGROUP(dap2_fs_paa0, I2S2, RSVD1, RSVD2, RSVD3, 0x3134, Y, Y, N, N, 0x96c, -1, -1, -1, -1, 28, 2, 30, 2), |
1429 | PINGROUP(dap2_din_paa2, I2S2, RSVD1, RSVD2, RSVD3, 0x3138, Y, Y, N, N, 0x964, -1, -1, -1, -1, 28, 2, 30, 2), |
1430 | PINGROUP(dap2_dout_paa3, I2S2, RSVD1, RSVD2, RSVD3, 0x313c, Y, Y, N, N, 0x968, -1, -1, -1, -1, 28, 2, 30, 2), |
1431 | PINGROUP(dap2_sclk_paa1, I2S2, RSVD1, RSVD2, RSVD3, 0x3140, Y, Y, N, N, 0x970, -1, -1, -1, -1, 28, 2, 30, 2), |
1432 | PINGROUP(dap4_fs_pj4, I2S4B, RSVD1, RSVD2, RSVD3, 0x3144, N, N, N, Y, 0x97c, 12, 5, 20, 5, -1, -1, -1, -1), |
1433 | PINGROUP(dap4_din_pj5, I2S4B, RSVD1, RSVD2, RSVD3, 0x3148, N, N, N, Y, 0x974, 12, 5, 20, 5, -1, -1, -1, -1), |
1434 | PINGROUP(dap4_dout_pj6, I2S4B, RSVD1, RSVD2, RSVD3, 0x314c, N, N, N, Y, 0x978, 12, 5, 20, 5, -1, -1, -1, -1), |
1435 | PINGROUP(dap4_sclk_pj7, I2S4B, RSVD1, RSVD2, RSVD3, 0x3150, N, N, N, Y, 0x980, 12, 5, 20, 5, -1, -1, -1, -1), |
1436 | PINGROUP(cam1_mclk_ps0, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3154, N, N, N, Y, 0x918, 12, 5, 20, 5, -1, -1, -1, -1), |
1437 | PINGROUP(cam2_mclk_ps1, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3158, N, N, N, Y, 0x924, 12, 5, 20, 5, -1, -1, -1, -1), |
1438 | PINGROUP(jtag_rtck, JTAG, RSVD1, RSVD2, RSVD3, 0x315c, N, N, N, Y, 0xa2c, 12, 5, 20, 5, -1, -1, -1, -1), |
1439 | PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, Y, 0x940, 12, 5, 20, 5, -1, -1, -1, -1), |
1440 | PINGROUP(clk_32k_out_py5, SOC, BLINK, RSVD2, RSVD3, 0x3164, N, N, N, Y, 0x944, 12, 5, 20, 5, -1, -1, -1, -1), |
1441 | PINGROUP(batt_bcl, BCL, RSVD1, RSVD2, RSVD3, 0x3168, N, N, Y, Y, 0x8f8, 12, 5, 20, 5, -1, -1, -1, -1), |
1442 | PINGROUP(clk_req, SYS, RSVD1, RSVD2, RSVD3, 0x316c, N, N, N, Y, 0x948, 12, 5, 20, 5, -1, -1, -1, -1), |
1443 | PINGROUP(cpu_pwr_req, CPU, RSVD1, RSVD2, RSVD3, 0x3170, N, N, N, Y, 0x950, 12, 5, 20, 5, -1, -1, -1, -1), |
1444 | PINGROUP(pwr_int_n, PMI, RSVD1, RSVD2, RSVD3, 0x3174, N, N, N, Y, 0xa74, 12, 5, 20, 5, -1, -1, -1, -1), |
1445 | PINGROUP(shutdown, SHUTDOWN, RSVD1, RSVD2, RSVD3, 0x3178, N, N, N, Y, 0xac8, 12, 5, 20, 5, -1, -1, -1, -1), |
1446 | PINGROUP(core_pwr_req, CORE, RSVD1, RSVD2, RSVD3, 0x317c, N, N, N, Y, 0x94c, 12, 5, 20, 5, -1, -1, -1, -1), |
1447 | PINGROUP(aud_mclk_pbb0, AUD, RSVD1, RSVD2, RSVD3, 0x3180, N, N, N, Y, 0x8f4, 12, 5, 20, 5, -1, -1, -1, -1), |
1448 | PINGROUP(dvfs_pwm_pbb1, RSVD0, CLDVFS, SPI3, RSVD3, 0x3184, N, N, N, Y, 0x9a4, 12, 5, 20, 5, -1, -1, -1, -1), |
1449 | PINGROUP(dvfs_clk_pbb2, RSVD0, CLDVFS, SPI3, RSVD3, 0x3188, N, N, N, Y, 0x9a0, 12, 5, 20, 5, -1, -1, -1, -1), |
1450 | PINGROUP(gpio_x1_aud_pbb3, RSVD0, RSVD1, SPI3, RSVD3, 0x318c, N, N, N, Y, 0xa14, 12, 5, 20, 5, -1, -1, -1, -1), |
1451 | PINGROUP(gpio_x3_aud_pbb4, RSVD0, RSVD1, SPI3, RSVD3, 0x3190, N, N, N, Y, 0xa18, 12, 5, 20, 5, -1, -1, -1, -1), |
1452 | PINGROUP(pcc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3194, N, N, Y, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1453 | PINGROUP(hdmi_cec_pcc0, CEC, RSVD1, RSVD2, RSVD3, 0x3198, N, N, Y, Y, 0xa24, 12, 5, 20, 5, -1, -1, -1, -1), |
1454 | PINGROUP(hdmi_int_dp_hpd_pcc1, DP, RSVD1, RSVD2, RSVD3, 0x319c, N, N, Y, Y, 0xa28, 12, 5, 20, 5, -1, -1, -1, -1), |
1455 | PINGROUP(spdif_out_pcc2, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a0, N, N, N, Y, 0xad0, 12, 5, 20, 5, -1, -1, -1, -1), |
1456 | PINGROUP(spdif_in_pcc3, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a4, N, N, N, Y, 0xacc, 12, 5, 20, 5, -1, -1, -1, -1), |
1457 | PINGROUP(usb_vbus_en0_pcc4, USB, RSVD1, RSVD2, RSVD3, 0x31a8, N, N, Y, Y, 0xb5c, 12, 5, 20, 5, -1, -1, -1, -1), |
1458 | PINGROUP(usb_vbus_en1_pcc5, USB, RSVD1, RSVD2, RSVD3, 0x31ac, N, N, Y, Y, 0xb60, 12, 5, 20, 5, -1, -1, -1, -1), |
1459 | PINGROUP(dp_hpd0_pcc6, DP, RSVD1, RSVD2, RSVD3, 0x31b0, N, N, N, Y, 0x99c, 12, 5, 20, 5, -1, -1, -1, -1), |
1460 | PINGROUP(wifi_en_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b4, N, N, N, Y, 0xb64, 12, 5, 20, 5, -1, -1, -1, -1), |
1461 | PINGROUP(wifi_rst_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b8, N, N, N, Y, 0xb68, 12, 5, 20, 5, -1, -1, -1, -1), |
1462 | PINGROUP(wifi_wake_ap_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31bc, N, N, N, Y, 0xb6c, 12, 5, 20, 5, -1, -1, -1, -1), |
1463 | PINGROUP(ap_wake_bt_ph3, RSVD0, UARTB, SPDIF, RSVD3, 0x31c0, N, N, N, Y, 0x8ec, 12, 5, 20, 5, -1, -1, -1, -1), |
1464 | PINGROUP(bt_rst_ph4, RSVD0, UARTB, SPDIF, RSVD3, 0x31c4, N, N, N, Y, 0x8fc, 12, 5, 20, 5, -1, -1, -1, -1), |
1465 | PINGROUP(bt_wake_ap_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x31c8, N, N, N, Y, 0x900, 12, 5, 20, 5, -1, -1, -1, -1), |
1466 | PINGROUP(ap_wake_nfc_ph7, RSVD0, RSVD1, RSVD2, RSVD3, 0x31cc, N, N, N, Y, 0x8f0, 12, 5, 20, 5, -1, -1, -1, -1), |
1467 | PINGROUP(nfc_en_pi0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d0, N, N, N, Y, 0xa50, 12, 5, 20, 5, -1, -1, -1, -1), |
1468 | PINGROUP(nfc_int_pi1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d4, N, N, N, Y, 0xa54, 12, 5, 20, 5, -1, -1, -1, -1), |
1469 | PINGROUP(gps_en_pi2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d8, N, N, N, Y, 0xa1c, 12, 5, 20, 5, -1, -1, -1, -1), |
1470 | PINGROUP(gps_rst_pi3, RSVD0, RSVD1, RSVD2, RSVD3, 0x31dc, N, N, N, Y, 0xa20, 12, 5, 20, 5, -1, -1, -1, -1), |
1471 | PINGROUP(cam_rst_ps4, VGP1, RSVD1, RSVD2, RSVD3, 0x31e0, N, N, N, Y, 0x93c, 12, 5, 20, 5, -1, -1, -1, -1), |
1472 | PINGROUP(cam_af_en_ps5, VIMCLK, VGP2, RSVD2, RSVD3, 0x31e4, N, N, N, Y, 0x92c, 12, 5, 20, 5, -1, -1, -1, -1), |
1473 | PINGROUP(cam_flash_en_ps6, VIMCLK, VGP3, RSVD2, RSVD3, 0x31e8, N, N, N, Y, 0x930, 12, 5, 20, 5, -1, -1, -1, -1), |
1474 | PINGROUP(cam1_pwdn_ps7, VGP4, RSVD1, RSVD2, RSVD3, 0x31ec, N, N, N, Y, 0x91c, 12, 5, 20, 5, -1, -1, -1, -1), |
1475 | PINGROUP(cam2_pwdn_pt0, VGP5, RSVD1, RSVD2, RSVD3, 0x31f0, N, N, N, Y, 0x928, 12, 5, 20, 5, -1, -1, -1, -1), |
1476 | PINGROUP(cam1_strobe_pt1, VGP6, RSVD1, RSVD2, RSVD3, 0x31f4, N, N, N, Y, 0x920, 12, 5, 20, 5, -1, -1, -1, -1), |
1477 | PINGROUP(lcd_te_py2, DISPLAYA, RSVD1, RSVD2, RSVD3, 0x31f8, N, N, N, Y, 0xa44, 12, 5, 20, 5, -1, -1, -1, -1), |
1478 | PINGROUP(lcd_bl_pwm_pv0, DISPLAYA, PWM0, SOR0, RSVD3, 0x31fc, N, N, N, Y, 0xa34, 12, 5, 20, 5, -1, -1, -1, -1), |
1479 | PINGROUP(lcd_bl_en_pv1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3200, N, N, N, Y, 0xa30, 12, 5, 20, 5, -1, -1, -1, -1), |
1480 | PINGROUP(lcd_rst_pv2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3204, N, N, N, Y, 0xa40, 12, 5, 20, 5, -1, -1, -1, -1), |
1481 | PINGROUP(lcd_gpio1_pv3, DISPLAYB, RSVD1, RSVD2, RSVD3, 0x3208, N, N, N, Y, 0xa38, 12, 5, 20, 5, -1, -1, -1, -1), |
1482 | PINGROUP(lcd_gpio2_pv4, DISPLAYB, PWM1, RSVD2, SOR1, 0x320c, N, N, N, Y, 0xa3c, 12, 5, 20, 5, -1, -1, -1, -1), |
1483 | PINGROUP(ap_ready_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3210, N, N, N, Y, 0x8e8, 12, 5, 20, 5, -1, -1, -1, -1), |
1484 | PINGROUP(touch_rst_pv6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3214, N, N, N, Y, 0xb18, 12, 5, 20, 5, -1, -1, -1, -1), |
1485 | PINGROUP(touch_clk_pv7, TOUCH, RSVD1, RSVD2, RSVD3, 0x3218, N, N, N, Y, 0xb10, 12, 5, 20, 5, -1, -1, -1, -1), |
1486 | PINGROUP(modem_wake_ap_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x321c, N, N, N, Y, 0xa48, 12, 5, 20, 5, -1, -1, -1, -1), |
1487 | PINGROUP(touch_int_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3220, N, N, N, Y, 0xb14, 12, 5, 20, 5, -1, -1, -1, -1), |
1488 | PINGROUP(motion_int_px2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3224, N, N, N, Y, 0xa4c, 12, 5, 20, 5, -1, -1, -1, -1), |
1489 | PINGROUP(als_prox_int_px3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3228, N, N, N, Y, 0x8e4, 12, 5, 20, 5, -1, -1, -1, -1), |
1490 | PINGROUP(temp_alert_px4, RSVD0, RSVD1, RSVD2, RSVD3, 0x322c, N, N, N, Y, 0xb0c, 12, 5, 20, 5, -1, -1, -1, -1), |
1491 | PINGROUP(button_power_on_px5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3230, N, N, N, Y, 0x908, 12, 5, 20, 5, -1, -1, -1, -1), |
1492 | PINGROUP(button_vol_up_px6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3234, N, N, N, Y, 0x914, 12, 5, 20, 5, -1, -1, -1, -1), |
1493 | PINGROUP(button_vol_down_px7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3238, N, N, N, Y, 0x910, 12, 5, 20, 5, -1, -1, -1, -1), |
1494 | PINGROUP(button_slide_sw_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0x323c, N, N, N, Y, 0x90c, 12, 5, 20, 5, -1, -1, -1, -1), |
1495 | PINGROUP(button_home_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3240, N, N, N, Y, 0x904, 12, 5, 20, 5, -1, -1, -1, -1), |
1496 | PINGROUP(pa6, SATA, RSVD1, RSVD2, RSVD3, 0x3244, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1497 | PINGROUP(pe6, RSVD0, I2S5A, PWM2, RSVD3, 0x3248, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1498 | PINGROUP(pe7, RSVD0, I2S5A, PWM3, RSVD3, 0x324c, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1499 | PINGROUP(ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3250, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1500 | PINGROUP(pk0, IQC0, I2S5B, RSVD2, RSVD3, 0x3254, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1501 | PINGROUP(pk1, IQC0, I2S5B, RSVD2, RSVD3, 0x3258, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1502 | PINGROUP(pk2, IQC0, I2S5B, RSVD2, RSVD3, 0x325c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1503 | PINGROUP(pk3, IQC0, I2S5B, RSVD2, RSVD3, 0x3260, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1504 | PINGROUP(pk4, IQC1, RSVD1, RSVD2, RSVD3, 0x3264, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1505 | PINGROUP(pk5, IQC1, RSVD1, RSVD2, RSVD3, 0x3268, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1506 | PINGROUP(pk6, IQC1, RSVD1, RSVD2, RSVD3, 0x326c, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1507 | PINGROUP(pk7, IQC1, RSVD1, RSVD2, RSVD3, 0x3270, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1508 | PINGROUP(pl0, RSVD0, RSVD1, RSVD2, RSVD3, 0x3274, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1509 | PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1510 | PINGROUP(pz0, VIMCLK2, RSVD1, RSVD2, RSVD3, 0x327c, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1511 | PINGROUP(pz1, VIMCLK2, SDMMC1, RSVD2, RSVD3, 0x3280, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1512 | PINGROUP(pz2, SDMMC3, CCLA, RSVD2, RSVD3, 0x3284, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1513 | PINGROUP(pz3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3288, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1514 | PINGROUP(pz4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x328c, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1515 | PINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1), |
1516 | |
1517 | /* pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */ |
1518 | DRV_PINGROUP(pa6, 0x9c0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1), |
1519 | DRV_PINGROUP(pcc7, 0x9c4, 0x0, 12, 5, 20, 5, -1, -1, -1, -1), |
1520 | DRV_PINGROUP(pe6, 0x9c8, 0x0, 12, 5, 20, 5, -1, -1, -1, -1), |
1521 | DRV_PINGROUP(pe7, 0x9cc, 0x0, 12, 5, 20, 5, -1, -1, -1, -1), |
1522 | DRV_PINGROUP(ph6, 0x9d0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1), |
1523 | DRV_PINGROUP(pk0, 0x9d4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1524 | DRV_PINGROUP(pk1, 0x9d8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1525 | DRV_PINGROUP(pk2, 0x9dc, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1526 | DRV_PINGROUP(pk3, 0x9e0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1527 | DRV_PINGROUP(pk4, 0x9e4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1528 | DRV_PINGROUP(pk5, 0x9e8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1529 | DRV_PINGROUP(pk6, 0x9ec, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1530 | DRV_PINGROUP(pk7, 0x9f0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1531 | DRV_PINGROUP(pl0, 0x9f4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1532 | DRV_PINGROUP(pl1, 0x9f8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2), |
1533 | DRV_PINGROUP(pz0, 0x9fc, 0x0, 12, 7, 20, 7, -1, -1, -1, -1), |
1534 | DRV_PINGROUP(pz1, 0xa00, 0x0, 12, 7, 20, 7, -1, -1, -1, -1), |
1535 | DRV_PINGROUP(pz2, 0xa04, 0x0, 12, 7, 20, 7, -1, -1, -1, -1), |
1536 | DRV_PINGROUP(pz3, 0xa08, 0x0, 12, 7, 20, 7, -1, -1, -1, -1), |
1537 | DRV_PINGROUP(pz4, 0xa0c, 0x0, 12, 7, 20, 7, -1, -1, -1, -1), |
1538 | DRV_PINGROUP(pz5, 0xa10, 0x0, 12, 7, 20, 7, -1, -1, -1, -1), |
1539 | DRV_PINGROUP(sdmmc1, 0xa98, 0x0, 12, 7, 20, 7, 28, 2, 30, 2), |
1540 | DRV_PINGROUP(sdmmc2, 0xa9c, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2), |
1541 | DRV_PINGROUP(sdmmc3, 0xab0, 0x0, 12, 7, 20, 7, 28, 2, 30, 2), |
1542 | DRV_PINGROUP(sdmmc4, 0xab4, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2), |
1543 | }; |
1544 | |
1545 | static const struct tegra_pinctrl_soc_data tegra210_pinctrl = { |
1546 | .ngpios = NUM_GPIOS, |
1547 | .gpio_compatible = "nvidia,tegra210-gpio" , |
1548 | .pins = tegra210_pins, |
1549 | .npins = ARRAY_SIZE(tegra210_pins), |
1550 | .functions = tegra210_functions, |
1551 | .nfunctions = ARRAY_SIZE(tegra210_functions), |
1552 | .groups = tegra210_groups, |
1553 | .ngroups = ARRAY_SIZE(tegra210_groups), |
1554 | .hsm_in_mux = true, |
1555 | .schmitt_in_mux = true, |
1556 | .drvtype_in_mux = true, |
1557 | }; |
1558 | |
1559 | static int tegra210_pinctrl_probe(struct platform_device *pdev) |
1560 | { |
1561 | return tegra_pinctrl_probe(pdev, soc_data: &tegra210_pinctrl); |
1562 | } |
1563 | |
1564 | static const struct of_device_id tegra210_pinctrl_of_match[] = { |
1565 | { .compatible = "nvidia,tegra210-pinmux" , }, |
1566 | { }, |
1567 | }; |
1568 | |
1569 | static struct platform_driver tegra210_pinctrl_driver = { |
1570 | .driver = { |
1571 | .name = "tegra210-pinctrl" , |
1572 | .of_match_table = tegra210_pinctrl_of_match, |
1573 | .pm = pm_sleep_ptr(&tegra_pinctrl_pm), |
1574 | }, |
1575 | .probe = tegra210_pinctrl_probe, |
1576 | }; |
1577 | |
1578 | static int __init tegra210_pinctrl_init(void) |
1579 | { |
1580 | return platform_driver_register(&tegra210_pinctrl_driver); |
1581 | } |
1582 | arch_initcall(tegra210_pinctrl_init); |
1583 | |