1 | /* |
2 | * Support for configuration of IO Delay module found on Texas Instruments SoCs |
3 | * such as DRA7 |
4 | * |
5 | * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public |
8 | * License version 2. This program is licensed "as is" without any |
9 | * warranty of any kind, whether express or implied. |
10 | */ |
11 | |
12 | #include <linux/err.h> |
13 | #include <linux/init.h> |
14 | #include <linux/io.h> |
15 | #include <linux/module.h> |
16 | #include <linux/of.h> |
17 | #include <linux/platform_device.h> |
18 | #include <linux/property.h> |
19 | #include <linux/regmap.h> |
20 | #include <linux/seq_file.h> |
21 | #include <linux/slab.h> |
22 | |
23 | #include <linux/pinctrl/pinconf-generic.h> |
24 | #include <linux/pinctrl/pinconf.h> |
25 | #include <linux/pinctrl/pinctrl.h> |
26 | |
27 | #include "../core.h" |
28 | #include "../devicetree.h" |
29 | |
30 | #define DRIVER_NAME "ti-iodelay" |
31 | |
32 | /** |
33 | * struct ti_iodelay_reg_data - Describes the registers for the iodelay instance |
34 | * @signature_mask: CONFIG_REG mask for the signature bits (see TRM) |
35 | * @signature_value: CONFIG_REG signature value to be written (see TRM) |
36 | * @lock_mask: CONFIG_REG mask for the lock bits (see TRM) |
37 | * @lock_val: CONFIG_REG lock value for the lock bits (see TRM) |
38 | * @unlock_val:CONFIG_REG unlock value for the lock bits (see TRM) |
39 | * @binary_data_coarse_mask: CONFIG_REG coarse mask (see TRM) |
40 | * @binary_data_fine_mask: CONFIG_REG fine mask (see TRM) |
41 | * @reg_refclk_offset: Refclk register offset |
42 | * @refclk_period_mask: Refclk mask |
43 | * @reg_coarse_offset: Coarse register configuration offset |
44 | * @coarse_delay_count_mask: Coarse delay count mask |
45 | * @coarse_ref_count_mask: Coarse ref count mask |
46 | * @reg_fine_offset: Fine register configuration offset |
47 | * @fine_delay_count_mask: Fine delay count mask |
48 | * @fine_ref_count_mask: Fine ref count mask |
49 | * @reg_global_lock_offset: Global iodelay module lock register offset |
50 | * @global_lock_mask: Lock mask |
51 | * @global_unlock_val: Unlock value |
52 | * @global_lock_val: Lock value |
53 | * @reg_start_offset: Offset to iodelay registers after the CONFIG_REG_0 to 8 |
54 | * @reg_nr_per_pin: Number of iodelay registers for each pin |
55 | * @regmap_config: Regmap configuration for the IODelay region |
56 | */ |
57 | struct ti_iodelay_reg_data { |
58 | u32 signature_mask; |
59 | u32 signature_value; |
60 | u32 lock_mask; |
61 | u32 lock_val; |
62 | u32 unlock_val; |
63 | u32 binary_data_coarse_mask; |
64 | u32 binary_data_fine_mask; |
65 | |
66 | u32 reg_refclk_offset; |
67 | u32 refclk_period_mask; |
68 | |
69 | u32 reg_coarse_offset; |
70 | u32 coarse_delay_count_mask; |
71 | u32 coarse_ref_count_mask; |
72 | |
73 | u32 reg_fine_offset; |
74 | u32 fine_delay_count_mask; |
75 | u32 fine_ref_count_mask; |
76 | |
77 | u32 reg_global_lock_offset; |
78 | u32 global_lock_mask; |
79 | u32 global_unlock_val; |
80 | u32 global_lock_val; |
81 | |
82 | u32 reg_start_offset; |
83 | u32 reg_nr_per_pin; |
84 | |
85 | struct regmap_config *regmap_config; |
86 | }; |
87 | |
88 | /** |
89 | * struct ti_iodelay_reg_values - Computed io_reg configuration values (see TRM) |
90 | * @coarse_ref_count: Coarse reference count |
91 | * @coarse_delay_count: Coarse delay count |
92 | * @fine_ref_count: Fine reference count |
93 | * @fine_delay_count: Fine Delay count |
94 | * @ref_clk_period: Reference Clock period |
95 | * @cdpe: Coarse delay parameter |
96 | * @fdpe: Fine delay parameter |
97 | */ |
98 | struct ti_iodelay_reg_values { |
99 | u16 coarse_ref_count; |
100 | u16 coarse_delay_count; |
101 | |
102 | u16 fine_ref_count; |
103 | u16 fine_delay_count; |
104 | |
105 | u16 ref_clk_period; |
106 | |
107 | u32 cdpe; |
108 | u32 fdpe; |
109 | }; |
110 | |
111 | /** |
112 | * struct ti_iodelay_cfg - Description of each configuration parameters |
113 | * @offset: Configuration register offset |
114 | * @a_delay: Agnostic Delay (in ps) |
115 | * @g_delay: Gnostic Delay (in ps) |
116 | */ |
117 | struct ti_iodelay_cfg { |
118 | u16 offset; |
119 | u16 a_delay; |
120 | u16 g_delay; |
121 | }; |
122 | |
123 | /** |
124 | * struct ti_iodelay_pingroup - Structure that describes one group |
125 | * @cfg: configuration array for the pin (from dt) |
126 | * @ncfg: number of configuration values allocated |
127 | * @config: pinconf "Config" - currently a dummy value |
128 | */ |
129 | struct ti_iodelay_pingroup { |
130 | struct ti_iodelay_cfg *cfg; |
131 | int ncfg; |
132 | unsigned long config; |
133 | }; |
134 | |
135 | /** |
136 | * struct ti_iodelay_device - Represents information for a iodelay instance |
137 | * @dev: Device pointer |
138 | * @phys_base: Physical address base of the iodelay device |
139 | * @reg_base: Virtual address base of the iodelay device |
140 | * @regmap: Regmap for this iodelay instance |
141 | * @pctl: Pinctrl device |
142 | * @desc: pinctrl descriptor for pctl |
143 | * @pa: pinctrl pin wise description |
144 | * @reg_data: Register definition data for the IODelay instance |
145 | * @reg_init_conf_values: Initial configuration values. |
146 | */ |
147 | struct ti_iodelay_device { |
148 | struct device *dev; |
149 | unsigned long phys_base; |
150 | void __iomem *reg_base; |
151 | struct regmap *regmap; |
152 | |
153 | struct pinctrl_dev *pctl; |
154 | struct pinctrl_desc desc; |
155 | struct pinctrl_pin_desc *pa; |
156 | |
157 | const struct ti_iodelay_reg_data *reg_data; |
158 | struct ti_iodelay_reg_values reg_init_conf_values; |
159 | }; |
160 | |
161 | /** |
162 | * ti_iodelay_extract() - extract bits for a field |
163 | * @val: Register value |
164 | * @mask: Mask |
165 | * |
166 | * Return: extracted value which is appropriately shifted |
167 | */ |
168 | static inline u32 (u32 val, u32 mask) |
169 | { |
170 | return (val & mask) >> __ffs(mask); |
171 | } |
172 | |
173 | /** |
174 | * ti_iodelay_compute_dpe() - Compute equation for delay parameter |
175 | * @period: Period to use |
176 | * @ref: Reference Count |
177 | * @delay: Delay count |
178 | * @delay_m: Delay multiplier |
179 | * |
180 | * Return: Computed delay parameter |
181 | */ |
182 | static inline u32 ti_iodelay_compute_dpe(u16 period, u16 ref, u16 delay, |
183 | u16 delay_m) |
184 | { |
185 | u64 m, d; |
186 | |
187 | /* Handle overflow conditions */ |
188 | m = 10 * (u64)period * (u64)ref; |
189 | d = 2 * (u64)delay * (u64)delay_m; |
190 | |
191 | /* Truncate result back to 32 bits */ |
192 | return div64_u64(dividend: m, divisor: d); |
193 | } |
194 | |
195 | /** |
196 | * ti_iodelay_pinconf_set() - Configure the pin configuration |
197 | * @iod: iodelay device |
198 | * @cfg: Configuration |
199 | * |
200 | * Update the configuration register as per TRM and lockup once done. |
201 | * *IMPORTANT NOTE* SoC TRM does recommend doing iodelay programmation only |
202 | * while in Isolation. But, then, isolation also implies that every pin |
203 | * on the SoC (including DDR) will be isolated out. The only benefit being |
204 | * a glitchless configuration, However, the intent of this driver is purely |
205 | * to support a "glitchy" configuration where applicable. |
206 | * |
207 | * Return: 0 in case of success, else appropriate error value |
208 | */ |
209 | static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, |
210 | struct ti_iodelay_cfg *cfg) |
211 | { |
212 | const struct ti_iodelay_reg_data *reg = iod->reg_data; |
213 | struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; |
214 | struct device *dev = iod->dev; |
215 | u32 g_delay_coarse, g_delay_fine; |
216 | u32 a_delay_coarse, a_delay_fine; |
217 | u32 c_elements, f_elements; |
218 | u32 total_delay; |
219 | u32 reg_mask, reg_val, tmp_val; |
220 | int r; |
221 | |
222 | /* NOTE: Truncation is expected in all division below */ |
223 | g_delay_coarse = cfg->g_delay / 920; |
224 | g_delay_fine = ((cfg->g_delay % 920) * 10) / 60; |
225 | |
226 | a_delay_coarse = cfg->a_delay / ival->cdpe; |
227 | a_delay_fine = ((cfg->a_delay % ival->cdpe) * 10) / ival->fdpe; |
228 | |
229 | c_elements = g_delay_coarse + a_delay_coarse; |
230 | f_elements = (g_delay_fine + a_delay_fine) / 10; |
231 | |
232 | if (f_elements > 22) { |
233 | total_delay = c_elements * ival->cdpe + f_elements * ival->fdpe; |
234 | c_elements = total_delay / ival->cdpe; |
235 | f_elements = (total_delay % ival->cdpe) / ival->fdpe; |
236 | } |
237 | |
238 | reg_mask = reg->signature_mask; |
239 | reg_val = reg->signature_value << __ffs(reg->signature_mask); |
240 | |
241 | reg_mask |= reg->binary_data_coarse_mask; |
242 | tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask); |
243 | if (tmp_val & ~reg->binary_data_coarse_mask) { |
244 | dev_err(dev, "Masking overflow of coarse elements %08x\n" , |
245 | tmp_val); |
246 | tmp_val &= reg->binary_data_coarse_mask; |
247 | } |
248 | reg_val |= tmp_val; |
249 | |
250 | reg_mask |= reg->binary_data_fine_mask; |
251 | tmp_val = f_elements << __ffs(reg->binary_data_fine_mask); |
252 | if (tmp_val & ~reg->binary_data_fine_mask) { |
253 | dev_err(dev, "Masking overflow of fine elements %08x\n" , |
254 | tmp_val); |
255 | tmp_val &= reg->binary_data_fine_mask; |
256 | } |
257 | reg_val |= tmp_val; |
258 | |
259 | /* |
260 | * NOTE: we leave the iodelay values unlocked - this is to work around |
261 | * situations such as those found with mmc mode change. |
262 | * However, this leaves open any unwarranted changes to padconf register |
263 | * impacting iodelay configuration. Use with care! |
264 | */ |
265 | reg_mask |= reg->lock_mask; |
266 | reg_val |= reg->unlock_val << __ffs(reg->lock_mask); |
267 | r = regmap_update_bits(map: iod->regmap, reg: cfg->offset, mask: reg_mask, val: reg_val); |
268 | |
269 | dev_dbg(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n" , |
270 | cfg->offset, cfg->a_delay, cfg->g_delay, c_elements, |
271 | f_elements, reg_val); |
272 | |
273 | return r; |
274 | } |
275 | |
276 | /** |
277 | * ti_iodelay_pinconf_init_dev() - Initialize IODelay device |
278 | * @iod: iodelay device |
279 | * |
280 | * Unlocks the iodelay region, computes the common parameters |
281 | * |
282 | * Return: 0 in case of success, else appropriate error value |
283 | */ |
284 | static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod) |
285 | { |
286 | const struct ti_iodelay_reg_data *reg = iod->reg_data; |
287 | struct device *dev = iod->dev; |
288 | struct ti_iodelay_reg_values *ival = &iod->reg_init_conf_values; |
289 | u32 val; |
290 | int r; |
291 | |
292 | /* unlock the iodelay region */ |
293 | r = regmap_update_bits(map: iod->regmap, reg: reg->reg_global_lock_offset, |
294 | mask: reg->global_lock_mask, val: reg->global_unlock_val); |
295 | if (r) |
296 | return r; |
297 | |
298 | /* Read up Recalibration sequence done by bootloader */ |
299 | r = regmap_read(map: iod->regmap, reg: reg->reg_refclk_offset, val: &val); |
300 | if (r) |
301 | return r; |
302 | ival->ref_clk_period = ti_iodelay_extract(val, mask: reg->refclk_period_mask); |
303 | dev_dbg(dev, "refclk_period=0x%04x\n" , ival->ref_clk_period); |
304 | |
305 | r = regmap_read(map: iod->regmap, reg: reg->reg_coarse_offset, val: &val); |
306 | if (r) |
307 | return r; |
308 | ival->coarse_ref_count = |
309 | ti_iodelay_extract(val, mask: reg->coarse_ref_count_mask); |
310 | ival->coarse_delay_count = |
311 | ti_iodelay_extract(val, mask: reg->coarse_delay_count_mask); |
312 | if (!ival->coarse_delay_count) { |
313 | dev_err(dev, "Invalid Coarse delay count (0) (reg=0x%08x)\n" , |
314 | val); |
315 | return -EINVAL; |
316 | } |
317 | ival->cdpe = ti_iodelay_compute_dpe(period: ival->ref_clk_period, |
318 | ref: ival->coarse_ref_count, |
319 | delay: ival->coarse_delay_count, delay_m: 88); |
320 | if (!ival->cdpe) { |
321 | dev_err(dev, "Invalid cdpe computed params = %d %d %d\n" , |
322 | ival->ref_clk_period, ival->coarse_ref_count, |
323 | ival->coarse_delay_count); |
324 | return -EINVAL; |
325 | } |
326 | dev_dbg(iod->dev, "coarse: ref=0x%04x delay=0x%04x cdpe=0x%08x\n" , |
327 | ival->coarse_ref_count, ival->coarse_delay_count, ival->cdpe); |
328 | |
329 | r = regmap_read(map: iod->regmap, reg: reg->reg_fine_offset, val: &val); |
330 | if (r) |
331 | return r; |
332 | ival->fine_ref_count = |
333 | ti_iodelay_extract(val, mask: reg->fine_ref_count_mask); |
334 | ival->fine_delay_count = |
335 | ti_iodelay_extract(val, mask: reg->fine_delay_count_mask); |
336 | if (!ival->fine_delay_count) { |
337 | dev_err(dev, "Invalid Fine delay count (0) (reg=0x%08x)\n" , |
338 | val); |
339 | return -EINVAL; |
340 | } |
341 | ival->fdpe = ti_iodelay_compute_dpe(period: ival->ref_clk_period, |
342 | ref: ival->fine_ref_count, |
343 | delay: ival->fine_delay_count, delay_m: 264); |
344 | if (!ival->fdpe) { |
345 | dev_err(dev, "Invalid fdpe(0) computed params = %d %d %d\n" , |
346 | ival->ref_clk_period, ival->fine_ref_count, |
347 | ival->fine_delay_count); |
348 | return -EINVAL; |
349 | } |
350 | dev_dbg(iod->dev, "fine: ref=0x%04x delay=0x%04x fdpe=0x%08x\n" , |
351 | ival->fine_ref_count, ival->fine_delay_count, ival->fdpe); |
352 | |
353 | return 0; |
354 | } |
355 | |
356 | /** |
357 | * ti_iodelay_pinconf_deinit_dev() - deinit the iodelay device |
358 | * @iod: IODelay device |
359 | * |
360 | * Deinitialize the IODelay device (basically just lock the region back up. |
361 | */ |
362 | static void ti_iodelay_pinconf_deinit_dev(struct ti_iodelay_device *iod) |
363 | { |
364 | const struct ti_iodelay_reg_data *reg = iod->reg_data; |
365 | |
366 | /* lock the iodelay region back again */ |
367 | regmap_update_bits(map: iod->regmap, reg: reg->reg_global_lock_offset, |
368 | mask: reg->global_lock_mask, val: reg->global_lock_val); |
369 | } |
370 | |
371 | /** |
372 | * ti_iodelay_get_pingroup() - Find the group mapped by a group selector |
373 | * @iod: iodelay device |
374 | * @selector: Group Selector |
375 | * |
376 | * Return: Corresponding group representing group selector |
377 | */ |
378 | static struct ti_iodelay_pingroup * |
379 | ti_iodelay_get_pingroup(struct ti_iodelay_device *iod, unsigned int selector) |
380 | { |
381 | struct group_desc *g; |
382 | |
383 | g = pinctrl_generic_get_group(pctldev: iod->pctl, group_selector: selector); |
384 | if (!g) { |
385 | dev_err(iod->dev, "%s could not find pingroup %i\n" , __func__, |
386 | selector); |
387 | |
388 | return NULL; |
389 | } |
390 | |
391 | return g->data; |
392 | } |
393 | |
394 | /** |
395 | * ti_iodelay_offset_to_pin() - get a pin index based on the register offset |
396 | * @iod: iodelay driver instance |
397 | * @offset: register offset from the base |
398 | */ |
399 | static int ti_iodelay_offset_to_pin(struct ti_iodelay_device *iod, |
400 | unsigned int offset) |
401 | { |
402 | const struct ti_iodelay_reg_data *r = iod->reg_data; |
403 | unsigned int index; |
404 | |
405 | if (offset > r->regmap_config->max_register) { |
406 | dev_err(iod->dev, "mux offset out of range: 0x%x (0x%x)\n" , |
407 | offset, r->regmap_config->max_register); |
408 | return -EINVAL; |
409 | } |
410 | |
411 | index = (offset - r->reg_start_offset) / r->regmap_config->reg_stride; |
412 | index /= r->reg_nr_per_pin; |
413 | |
414 | return index; |
415 | } |
416 | |
417 | /** |
418 | * ti_iodelay_node_iterator() - Iterate iodelay node |
419 | * @pctldev: Pin controller driver |
420 | * @np: Device node |
421 | * @pinctrl_spec: Parsed arguments from device tree |
422 | * @pins: Array of pins in the pin group |
423 | * @pin_index: Pin index in the pin array |
424 | * @data: Pin controller driver specific data |
425 | * |
426 | */ |
427 | static int ti_iodelay_node_iterator(struct pinctrl_dev *pctldev, |
428 | struct device_node *np, |
429 | const struct of_phandle_args *pinctrl_spec, |
430 | int *pins, int pin_index, void *data) |
431 | { |
432 | struct ti_iodelay_device *iod; |
433 | struct ti_iodelay_cfg *cfg = data; |
434 | const struct ti_iodelay_reg_data *r; |
435 | struct pinctrl_pin_desc *pd; |
436 | int pin; |
437 | |
438 | iod = pinctrl_dev_get_drvdata(pctldev); |
439 | if (!iod) |
440 | return -EINVAL; |
441 | |
442 | r = iod->reg_data; |
443 | |
444 | if (pinctrl_spec->args_count < r->reg_nr_per_pin) { |
445 | dev_err(iod->dev, "invalid args_count for spec: %i\n" , |
446 | pinctrl_spec->args_count); |
447 | |
448 | return -EINVAL; |
449 | } |
450 | |
451 | /* Index plus two value cells */ |
452 | cfg[pin_index].offset = pinctrl_spec->args[0]; |
453 | cfg[pin_index].a_delay = pinctrl_spec->args[1] & 0xffff; |
454 | cfg[pin_index].g_delay = pinctrl_spec->args[2] & 0xffff; |
455 | |
456 | pin = ti_iodelay_offset_to_pin(iod, offset: cfg[pin_index].offset); |
457 | if (pin < 0) { |
458 | dev_err(iod->dev, "could not add functions for %pOFn %ux\n" , |
459 | np, cfg[pin_index].offset); |
460 | return -ENODEV; |
461 | } |
462 | pins[pin_index] = pin; |
463 | |
464 | pd = &iod->pa[pin]; |
465 | pd->drv_data = &cfg[pin_index]; |
466 | |
467 | dev_dbg(iod->dev, "%pOFn offset=%x a_delay = %d g_delay = %d\n" , |
468 | np, cfg[pin_index].offset, cfg[pin_index].a_delay, |
469 | cfg[pin_index].g_delay); |
470 | |
471 | return 0; |
472 | } |
473 | |
474 | /** |
475 | * ti_iodelay_dt_node_to_map() - Map a device tree node to appropriate group |
476 | * @pctldev: pinctrl device representing IODelay device |
477 | * @np: Node Pointer (device tree) |
478 | * @map: Pinctrl Map returned back to pinctrl framework |
479 | * @num_maps: Number of maps (1) |
480 | * |
481 | * Maps the device tree description into a group of configuration parameters |
482 | * for iodelay block entry. |
483 | * |
484 | * Return: 0 in case of success, else appropriate error value |
485 | */ |
486 | static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev, |
487 | struct device_node *np, |
488 | struct pinctrl_map **map, |
489 | unsigned int *num_maps) |
490 | { |
491 | struct ti_iodelay_device *iod; |
492 | struct ti_iodelay_cfg *cfg; |
493 | struct ti_iodelay_pingroup *g; |
494 | const char *name = "pinctrl-pin-array" ; |
495 | int rows, *pins, error = -EINVAL, i; |
496 | |
497 | iod = pinctrl_dev_get_drvdata(pctldev); |
498 | if (!iod) |
499 | return -EINVAL; |
500 | |
501 | rows = pinctrl_count_index_with_args(np, list_name: name); |
502 | if (rows < 0) |
503 | return rows; |
504 | |
505 | *map = devm_kzalloc(dev: iod->dev, size: sizeof(**map), GFP_KERNEL); |
506 | if (!*map) |
507 | return -ENOMEM; |
508 | *num_maps = 0; |
509 | |
510 | g = devm_kzalloc(dev: iod->dev, size: sizeof(*g), GFP_KERNEL); |
511 | if (!g) { |
512 | error = -ENOMEM; |
513 | goto free_map; |
514 | } |
515 | |
516 | pins = devm_kcalloc(dev: iod->dev, n: rows, size: sizeof(*pins), GFP_KERNEL); |
517 | if (!pins) { |
518 | error = -ENOMEM; |
519 | goto free_group; |
520 | } |
521 | |
522 | cfg = devm_kcalloc(dev: iod->dev, n: rows, size: sizeof(*cfg), GFP_KERNEL); |
523 | if (!cfg) { |
524 | error = -ENOMEM; |
525 | goto free_pins; |
526 | } |
527 | |
528 | for (i = 0; i < rows; i++) { |
529 | struct of_phandle_args pinctrl_spec; |
530 | |
531 | error = pinctrl_parse_index_with_args(np, list_name: name, index: i, |
532 | out_args: &pinctrl_spec); |
533 | if (error) |
534 | goto free_data; |
535 | |
536 | error = ti_iodelay_node_iterator(pctldev, np, pinctrl_spec: &pinctrl_spec, |
537 | pins, pin_index: i, data: cfg); |
538 | if (error) |
539 | goto free_data; |
540 | } |
541 | |
542 | g->cfg = cfg; |
543 | g->ncfg = i; |
544 | g->config = PIN_CONFIG_END; |
545 | |
546 | error = pinctrl_generic_add_group(pctldev: iod->pctl, name: np->name, pins, num_pins: i, data: g); |
547 | if (error < 0) |
548 | goto free_data; |
549 | |
550 | (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP; |
551 | (*map)->data.configs.group_or_pin = np->name; |
552 | (*map)->data.configs.configs = &g->config; |
553 | (*map)->data.configs.num_configs = 1; |
554 | *num_maps = 1; |
555 | |
556 | return 0; |
557 | |
558 | free_data: |
559 | devm_kfree(dev: iod->dev, p: cfg); |
560 | free_pins: |
561 | devm_kfree(dev: iod->dev, p: pins); |
562 | free_group: |
563 | devm_kfree(dev: iod->dev, p: g); |
564 | free_map: |
565 | devm_kfree(dev: iod->dev, p: *map); |
566 | |
567 | return error; |
568 | } |
569 | |
570 | /** |
571 | * ti_iodelay_pinconf_group_get() - Get the group configuration |
572 | * @pctldev: pinctrl device representing IODelay device |
573 | * @selector: Group selector |
574 | * @config: Configuration returned |
575 | * |
576 | * Return: The configuration if the group is valid, else returns -EINVAL |
577 | */ |
578 | static int ti_iodelay_pinconf_group_get(struct pinctrl_dev *pctldev, |
579 | unsigned int selector, |
580 | unsigned long *config) |
581 | { |
582 | struct ti_iodelay_device *iod; |
583 | struct ti_iodelay_pingroup *group; |
584 | |
585 | iod = pinctrl_dev_get_drvdata(pctldev); |
586 | group = ti_iodelay_get_pingroup(iod, selector); |
587 | |
588 | if (!group) |
589 | return -EINVAL; |
590 | |
591 | *config = group->config; |
592 | return 0; |
593 | } |
594 | |
595 | /** |
596 | * ti_iodelay_pinconf_group_set() - Configure the groups of pins |
597 | * @pctldev: pinctrl device representing IODelay device |
598 | * @selector: Group selector |
599 | * @configs: Configurations |
600 | * @num_configs: Number of configurations |
601 | * |
602 | * Return: 0 if all went fine, else appropriate error value. |
603 | */ |
604 | static int ti_iodelay_pinconf_group_set(struct pinctrl_dev *pctldev, |
605 | unsigned int selector, |
606 | unsigned long *configs, |
607 | unsigned int num_configs) |
608 | { |
609 | struct ti_iodelay_device *iod; |
610 | struct device *dev; |
611 | struct ti_iodelay_pingroup *group; |
612 | int i; |
613 | |
614 | iod = pinctrl_dev_get_drvdata(pctldev); |
615 | dev = iod->dev; |
616 | group = ti_iodelay_get_pingroup(iod, selector); |
617 | |
618 | if (num_configs != 1) { |
619 | dev_err(dev, "Unsupported number of configurations %d\n" , |
620 | num_configs); |
621 | return -EINVAL; |
622 | } |
623 | |
624 | if (*configs != PIN_CONFIG_END) { |
625 | dev_err(dev, "Unsupported configuration\n" ); |
626 | return -EINVAL; |
627 | } |
628 | |
629 | for (i = 0; i < group->ncfg; i++) { |
630 | if (ti_iodelay_pinconf_set(iod, cfg: &group->cfg[i])) |
631 | return -ENOTSUPP; |
632 | } |
633 | |
634 | return 0; |
635 | } |
636 | |
637 | #ifdef CONFIG_DEBUG_FS |
638 | /** |
639 | * ti_iodelay_pin_to_offset() - get pin register offset based on the pin index |
640 | * @iod: iodelay driver instance |
641 | * @selector: Pin index |
642 | */ |
643 | static unsigned int ti_iodelay_pin_to_offset(struct ti_iodelay_device *iod, |
644 | unsigned int selector) |
645 | { |
646 | const struct ti_iodelay_reg_data *r = iod->reg_data; |
647 | unsigned int offset; |
648 | |
649 | offset = selector * r->regmap_config->reg_stride; |
650 | offset *= r->reg_nr_per_pin; |
651 | offset += r->reg_start_offset; |
652 | |
653 | return offset; |
654 | } |
655 | |
656 | static void ti_iodelay_pin_dbg_show(struct pinctrl_dev *pctldev, |
657 | struct seq_file *s, |
658 | unsigned int pin) |
659 | { |
660 | struct ti_iodelay_device *iod; |
661 | struct pinctrl_pin_desc *pd; |
662 | struct ti_iodelay_cfg *cfg; |
663 | const struct ti_iodelay_reg_data *r; |
664 | unsigned long offset; |
665 | u32 in, oen, out; |
666 | |
667 | iod = pinctrl_dev_get_drvdata(pctldev); |
668 | r = iod->reg_data; |
669 | |
670 | offset = ti_iodelay_pin_to_offset(iod, selector: pin); |
671 | pd = &iod->pa[pin]; |
672 | cfg = pd->drv_data; |
673 | |
674 | regmap_read(map: iod->regmap, reg: offset, val: &in); |
675 | regmap_read(map: iod->regmap, reg: offset + r->regmap_config->reg_stride, val: &oen); |
676 | regmap_read(map: iod->regmap, reg: offset + r->regmap_config->reg_stride * 2, |
677 | val: &out); |
678 | |
679 | seq_printf(m: s, fmt: "%lx a: %i g: %i (%08x %08x %08x) %s " , |
680 | iod->phys_base + offset, |
681 | cfg ? cfg->a_delay : -1, |
682 | cfg ? cfg->g_delay : -1, |
683 | in, oen, out, DRIVER_NAME); |
684 | } |
685 | |
686 | /** |
687 | * ti_iodelay_pinconf_group_dbg_show() - show the group information |
688 | * @pctldev: Show the group information |
689 | * @s: Sequence file |
690 | * @selector: Group selector |
691 | * |
692 | * Provide the configuration information of the selected group |
693 | */ |
694 | static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, |
695 | struct seq_file *s, |
696 | unsigned int selector) |
697 | { |
698 | struct ti_iodelay_device *iod; |
699 | struct ti_iodelay_pingroup *group; |
700 | int i; |
701 | |
702 | iod = pinctrl_dev_get_drvdata(pctldev); |
703 | group = ti_iodelay_get_pingroup(iod, selector); |
704 | if (!group) |
705 | return; |
706 | |
707 | for (i = 0; i < group->ncfg; i++) { |
708 | struct ti_iodelay_cfg *cfg; |
709 | u32 reg = 0; |
710 | |
711 | cfg = &group->cfg[i]; |
712 | regmap_read(map: iod->regmap, reg: cfg->offset, val: ®); |
713 | seq_printf(m: s, fmt: "\n\t0x%08x = 0x%08x (%3d, %3d)" , |
714 | cfg->offset, reg, cfg->a_delay, cfg->g_delay); |
715 | } |
716 | } |
717 | #endif |
718 | |
719 | static const struct pinctrl_ops ti_iodelay_pinctrl_ops = { |
720 | .get_groups_count = pinctrl_generic_get_group_count, |
721 | .get_group_name = pinctrl_generic_get_group_name, |
722 | .get_group_pins = pinctrl_generic_get_group_pins, |
723 | #ifdef CONFIG_DEBUG_FS |
724 | .pin_dbg_show = ti_iodelay_pin_dbg_show, |
725 | #endif |
726 | .dt_node_to_map = ti_iodelay_dt_node_to_map, |
727 | }; |
728 | |
729 | static const struct pinconf_ops ti_iodelay_pinctrl_pinconf_ops = { |
730 | .pin_config_group_get = ti_iodelay_pinconf_group_get, |
731 | .pin_config_group_set = ti_iodelay_pinconf_group_set, |
732 | #ifdef CONFIG_DEBUG_FS |
733 | .pin_config_group_dbg_show = ti_iodelay_pinconf_group_dbg_show, |
734 | #endif |
735 | }; |
736 | |
737 | /** |
738 | * ti_iodelay_alloc_pins() - Allocate structures needed for pins for iodelay |
739 | * @dev: Device pointer |
740 | * @iod: iodelay device |
741 | * @base_phy: Base Physical Address |
742 | * |
743 | * Return: 0 if all went fine, else appropriate error value. |
744 | */ |
745 | static int ti_iodelay_alloc_pins(struct device *dev, |
746 | struct ti_iodelay_device *iod, u32 base_phy) |
747 | { |
748 | const struct ti_iodelay_reg_data *r = iod->reg_data; |
749 | struct pinctrl_pin_desc *pin; |
750 | u32 phy_reg; |
751 | int nr_pins, i; |
752 | |
753 | nr_pins = ti_iodelay_offset_to_pin(iod, offset: r->regmap_config->max_register); |
754 | dev_dbg(dev, "Allocating %i pins\n" , nr_pins); |
755 | |
756 | iod->pa = devm_kcalloc(dev, n: nr_pins, size: sizeof(*iod->pa), GFP_KERNEL); |
757 | if (!iod->pa) |
758 | return -ENOMEM; |
759 | |
760 | iod->desc.pins = iod->pa; |
761 | iod->desc.npins = nr_pins; |
762 | |
763 | phy_reg = r->reg_start_offset + base_phy; |
764 | |
765 | for (i = 0; i < nr_pins; i++, phy_reg += 4) { |
766 | pin = &iod->pa[i]; |
767 | pin->number = i; |
768 | } |
769 | |
770 | return 0; |
771 | } |
772 | |
773 | static struct regmap_config dra7_iodelay_regmap_config = { |
774 | .reg_bits = 32, |
775 | .reg_stride = 4, |
776 | .val_bits = 32, |
777 | .max_register = 0xd1c, |
778 | }; |
779 | |
780 | static struct ti_iodelay_reg_data dra7_iodelay_data = { |
781 | .signature_mask = 0x0003f000, |
782 | .signature_value = 0x29, |
783 | .lock_mask = 0x00000400, |
784 | .lock_val = 1, |
785 | .unlock_val = 0, |
786 | .binary_data_coarse_mask = 0x000003e0, |
787 | .binary_data_fine_mask = 0x0000001f, |
788 | |
789 | .reg_refclk_offset = 0x14, |
790 | .refclk_period_mask = 0xffff, |
791 | |
792 | .reg_coarse_offset = 0x18, |
793 | .coarse_delay_count_mask = 0xffff0000, |
794 | .coarse_ref_count_mask = 0x0000ffff, |
795 | |
796 | .reg_fine_offset = 0x1C, |
797 | .fine_delay_count_mask = 0xffff0000, |
798 | .fine_ref_count_mask = 0x0000ffff, |
799 | |
800 | .reg_global_lock_offset = 0x2c, |
801 | .global_lock_mask = 0x0000ffff, |
802 | .global_unlock_val = 0x0000aaaa, |
803 | .global_lock_val = 0x0000aaab, |
804 | |
805 | .reg_start_offset = 0x30, |
806 | .reg_nr_per_pin = 3, |
807 | .regmap_config = &dra7_iodelay_regmap_config, |
808 | }; |
809 | |
810 | static const struct of_device_id ti_iodelay_of_match[] = { |
811 | {.compatible = "ti,dra7-iodelay" , .data = &dra7_iodelay_data}, |
812 | { /* Hopefully no more.. */ }, |
813 | }; |
814 | MODULE_DEVICE_TABLE(of, ti_iodelay_of_match); |
815 | |
816 | /** |
817 | * ti_iodelay_probe() - Standard probe |
818 | * @pdev: platform device |
819 | * |
820 | * Return: 0 if all went fine, else appropriate error value. |
821 | */ |
822 | static int ti_iodelay_probe(struct platform_device *pdev) |
823 | { |
824 | struct device *dev = &pdev->dev; |
825 | struct device_node *np = of_node_get(node: dev->of_node); |
826 | struct resource *res; |
827 | struct ti_iodelay_device *iod; |
828 | int ret = 0; |
829 | |
830 | if (!np) { |
831 | ret = -EINVAL; |
832 | dev_err(dev, "No OF node\n" ); |
833 | goto exit_out; |
834 | } |
835 | |
836 | iod = devm_kzalloc(dev, size: sizeof(*iod), GFP_KERNEL); |
837 | if (!iod) { |
838 | ret = -ENOMEM; |
839 | goto exit_out; |
840 | } |
841 | iod->dev = dev; |
842 | iod->reg_data = device_get_match_data(dev); |
843 | if (!iod->reg_data) { |
844 | ret = -EINVAL; |
845 | dev_err(dev, "No DATA match\n" ); |
846 | goto exit_out; |
847 | } |
848 | |
849 | /* So far We can assume there is only 1 bank of registers */ |
850 | iod->reg_base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res); |
851 | if (IS_ERR(ptr: iod->reg_base)) { |
852 | ret = PTR_ERR(ptr: iod->reg_base); |
853 | goto exit_out; |
854 | } |
855 | iod->phys_base = res->start; |
856 | |
857 | iod->regmap = devm_regmap_init_mmio(dev, iod->reg_base, |
858 | iod->reg_data->regmap_config); |
859 | if (IS_ERR(ptr: iod->regmap)) { |
860 | dev_err(dev, "Regmap MMIO init failed.\n" ); |
861 | ret = PTR_ERR(ptr: iod->regmap); |
862 | goto exit_out; |
863 | } |
864 | |
865 | ret = ti_iodelay_pinconf_init_dev(iod); |
866 | if (ret) |
867 | goto exit_out; |
868 | |
869 | ret = ti_iodelay_alloc_pins(dev, iod, base_phy: res->start); |
870 | if (ret) |
871 | goto exit_out; |
872 | |
873 | iod->desc.pctlops = &ti_iodelay_pinctrl_ops; |
874 | /* no pinmux ops - we are pinconf */ |
875 | iod->desc.confops = &ti_iodelay_pinctrl_pinconf_ops; |
876 | iod->desc.name = dev_name(dev); |
877 | iod->desc.owner = THIS_MODULE; |
878 | |
879 | ret = pinctrl_register_and_init(pctldesc: &iod->desc, dev, driver_data: iod, pctldev: &iod->pctl); |
880 | if (ret) { |
881 | dev_err(dev, "Failed to register pinctrl\n" ); |
882 | goto exit_out; |
883 | } |
884 | |
885 | platform_set_drvdata(pdev, data: iod); |
886 | |
887 | return pinctrl_enable(pctldev: iod->pctl); |
888 | |
889 | exit_out: |
890 | of_node_put(node: np); |
891 | return ret; |
892 | } |
893 | |
894 | /** |
895 | * ti_iodelay_remove() - standard remove |
896 | * @pdev: platform device |
897 | */ |
898 | static void ti_iodelay_remove(struct platform_device *pdev) |
899 | { |
900 | struct ti_iodelay_device *iod = platform_get_drvdata(pdev); |
901 | |
902 | if (iod->pctl) |
903 | pinctrl_unregister(pctldev: iod->pctl); |
904 | |
905 | ti_iodelay_pinconf_deinit_dev(iod); |
906 | |
907 | /* Expect other allocations to be freed by devm */ |
908 | } |
909 | |
910 | static struct platform_driver ti_iodelay_driver = { |
911 | .probe = ti_iodelay_probe, |
912 | .remove_new = ti_iodelay_remove, |
913 | .driver = { |
914 | .name = DRIVER_NAME, |
915 | .of_match_table = ti_iodelay_of_match, |
916 | }, |
917 | }; |
918 | module_platform_driver(ti_iodelay_driver); |
919 | |
920 | MODULE_AUTHOR("Texas Instruments, Inc." ); |
921 | MODULE_DESCRIPTION("Pinconf driver for TI's IO Delay module" ); |
922 | MODULE_LICENSE("GPL v2" ); |
923 | |