| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2019, Mellanox Technologies. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __MLXBF_TMFIFO_REGS_H__ |
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| 7 | #define __MLXBF_TMFIFO_REGS_H__ |
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| 8 | |
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| 9 | #include <linux/types.h> |
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| 10 | #include <linux/bits.h> |
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| 11 | |
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| 12 | #define MLXBF_TMFIFO_TX_DATA 0x00 |
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| 13 | #define MLXBF_TMFIFO_TX_STS 0x08 |
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| 14 | #define MLXBF_TMFIFO_TX_STS__LENGTH 0x0001 |
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| 15 | #define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT 0 |
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| 16 | #define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH 9 |
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| 17 | #define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL 0 |
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| 18 | #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0) |
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| 19 | #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0) |
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| 20 | #define MLXBF_TMFIFO_TX_CTL 0x10 |
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| 21 | #define MLXBF_TMFIFO_TX_CTL__LENGTH 0x0001 |
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| 22 | #define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT 0 |
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| 23 | #define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH 8 |
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| 24 | #define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL 128 |
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| 25 | #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0) |
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| 26 | #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0) |
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| 27 | #define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT 8 |
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| 28 | #define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH 8 |
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| 29 | #define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL 128 |
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| 30 | #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0) |
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| 31 | #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8) |
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| 32 | #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT 32 |
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| 33 | #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH 9 |
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| 34 | #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL 256 |
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| 35 | #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0) |
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| 36 | #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32) |
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| 37 | #define MLXBF_TMFIFO_RX_DATA 0x00 |
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| 38 | #define MLXBF_TMFIFO_RX_STS 0x08 |
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| 39 | #define MLXBF_TMFIFO_RX_STS__LENGTH 0x0001 |
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| 40 | #define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT 0 |
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| 41 | #define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH 9 |
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| 42 | #define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL 0 |
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| 43 | #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0) |
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| 44 | #define MLXBF_TMFIFO_RX_STS__COUNT_MASK GENMASK_ULL(8, 0) |
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| 45 | #define MLXBF_TMFIFO_RX_CTL 0x10 |
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| 46 | #define MLXBF_TMFIFO_RX_CTL__LENGTH 0x0001 |
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| 47 | #define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT 0 |
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| 48 | #define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH 8 |
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| 49 | #define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL 128 |
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| 50 | #define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0) |
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| 51 | #define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0) |
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| 52 | #define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT 8 |
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| 53 | #define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH 8 |
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| 54 | #define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL 128 |
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| 55 | #define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0) |
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| 56 | #define MLXBF_TMFIFO_RX_CTL__HWM_MASK GENMASK_ULL(15, 8) |
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| 57 | #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT 32 |
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| 58 | #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH 9 |
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| 59 | #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL 256 |
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| 60 | #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK GENMASK_ULL(8, 0) |
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| 61 | #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK GENMASK_ULL(40, 32) |
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| 62 | |
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| 63 | /* BF3 register offsets within resource 0. */ |
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| 64 | #define MLXBF_TMFIFO_RX_DATA_BF3 0x0000 |
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| 65 | #define MLXBF_TMFIFO_TX_DATA_BF3 0x1000 |
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| 66 | |
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| 67 | /* BF3 register offsets within resource 1. */ |
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| 68 | #define MLXBF_TMFIFO_RX_STS_BF3 0x0000 |
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| 69 | #define MLXBF_TMFIFO_RX_CTL_BF3 0x0008 |
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| 70 | #define MLXBF_TMFIFO_TX_STS_BF3 0x0100 |
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| 71 | #define MLXBF_TMFIFO_TX_CTL_BF3 0x0108 |
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| 72 | |
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| 73 | #endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */ |
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| 74 | |
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