1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Renesas R-Car V4H System Controller |
4 | * |
5 | * Copyright (C) 2022 Renesas Electronics Corp. |
6 | */ |
7 | |
8 | #include <linux/kernel.h> |
9 | |
10 | #include <dt-bindings/power/r8a779g0-sysc.h> |
11 | |
12 | #include "rcar-gen4-sysc.h" |
13 | |
14 | static struct rcar_gen4_sysc_area r8a779g0_areas[] __initdata = { |
15 | { "always-on" , R8A779G0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, |
16 | { "a3e0" , R8A779G0_PD_A3E0, R8A779G0_PD_ALWAYS_ON, PD_SCU }, |
17 | { "a2e0d0" , R8A779G0_PD_A2E0D0, R8A779G0_PD_A3E0, PD_SCU }, |
18 | { "a2e0d1" , R8A779G0_PD_A2E0D1, R8A779G0_PD_A3E0, PD_SCU }, |
19 | { "a1e0d0c0" , R8A779G0_PD_A1E0D0C0, R8A779G0_PD_A2E0D0, PD_CPU_NOCR }, |
20 | { "a1e0d0c1" , R8A779G0_PD_A1E0D0C1, R8A779G0_PD_A2E0D0, PD_CPU_NOCR }, |
21 | { "a1e0d1c0" , R8A779G0_PD_A1E0D1C0, R8A779G0_PD_A2E0D1, PD_CPU_NOCR }, |
22 | { "a1e0d1c1" , R8A779G0_PD_A1E0D1C1, R8A779G0_PD_A2E0D1, PD_CPU_NOCR }, |
23 | { "a33dga" , R8A779G0_PD_A33DGA, R8A779G0_PD_ALWAYS_ON }, |
24 | { "a23dgb" , R8A779G0_PD_A23DGB, R8A779G0_PD_A33DGA }, |
25 | { "a3vip0" , R8A779G0_PD_A3VIP0, R8A779G0_PD_ALWAYS_ON }, |
26 | { "a3vip1" , R8A779G0_PD_A3VIP1, R8A779G0_PD_ALWAYS_ON }, |
27 | { "a3vip2" , R8A779G0_PD_A3VIP2, R8A779G0_PD_ALWAYS_ON }, |
28 | { "a3dul" , R8A779G0_PD_A3DUL, R8A779G0_PD_ALWAYS_ON }, |
29 | { "a3isp0" , R8A779G0_PD_A3ISP0, R8A779G0_PD_ALWAYS_ON }, |
30 | { "a3isp1" , R8A779G0_PD_A3ISP1, R8A779G0_PD_ALWAYS_ON }, |
31 | { "a3ir" , R8A779G0_PD_A3IR, R8A779G0_PD_ALWAYS_ON }, |
32 | { "a2cn0" , R8A779G0_PD_A2CN0, R8A779G0_PD_A3IR }, |
33 | { "a1cnn0" , R8A779G0_PD_A1CNN0, R8A779G0_PD_A2CN0 }, |
34 | { "a1dsp0" , R8A779G0_PD_A1DSP0, R8A779G0_PD_A2CN0 }, |
35 | { "a1dsp1" , R8A779G0_PD_A1DSP1, R8A779G0_PD_A2CN0 }, |
36 | { "a1dsp2" , R8A779G0_PD_A1DSP2, R8A779G0_PD_A2CN0 }, |
37 | { "a1dsp3" , R8A779G0_PD_A1DSP3, R8A779G0_PD_A2CN0 }, |
38 | { "a2imp01" , R8A779G0_PD_A2IMP01, R8A779G0_PD_A3IR }, |
39 | { "a2imp23" , R8A779G0_PD_A2IMP23, R8A779G0_PD_A3IR }, |
40 | { "a2psc" , R8A779G0_PD_A2PSC, R8A779G0_PD_A3IR }, |
41 | { "a2dma" , R8A779G0_PD_A2DMA, R8A779G0_PD_A3IR }, |
42 | { "a2cv0" , R8A779G0_PD_A2CV0, R8A779G0_PD_A3IR }, |
43 | { "a2cv1" , R8A779G0_PD_A2CV1, R8A779G0_PD_A3IR }, |
44 | { "a2cv2" , R8A779G0_PD_A2CV2, R8A779G0_PD_A3IR }, |
45 | { "a2cv3" , R8A779G0_PD_A2CV3, R8A779G0_PD_A3IR }, |
46 | }; |
47 | |
48 | const struct rcar_gen4_sysc_info r8a779g0_sysc_info __initconst = { |
49 | .areas = r8a779g0_areas, |
50 | .num_areas = ARRAY_SIZE(r8a779g0_areas), |
51 | }; |
52 | |