1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023, Linaro Ltd.
5 * Author: Caleb Connolly <caleb.connolly@linaro.org>
6 *
7 * This driver is for the switch-mode battery charger and boost
8 * hardware found in pmi8998 and related PMICs.
9 */
10
11#include <linux/bits.h>
12#include <linux/devm-helpers.h>
13#include <linux/iio/consumer.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/minmax.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/pm_wakeirq.h>
20#include <linux/of.h>
21#include <linux/power_supply.h>
22#include <linux/regmap.h>
23#include <linux/types.h>
24#include <linux/workqueue.h>
25
26/* clang-format off */
27#define BATTERY_CHARGER_STATUS_1 0x06
28#define BVR_INITIAL_RAMP_BIT BIT(7)
29#define CC_SOFT_TERMINATE_BIT BIT(6)
30#define STEP_CHARGING_STATUS_SHIFT 3
31#define STEP_CHARGING_STATUS_MASK GENMASK(5, 3)
32#define BATTERY_CHARGER_STATUS_MASK GENMASK(2, 0)
33
34#define BATTERY_CHARGER_STATUS_2 0x07
35#define INPUT_CURRENT_LIMITED_BIT BIT(7)
36#define CHARGER_ERROR_STATUS_SFT_EXPIRE_BIT BIT(6)
37#define CHARGER_ERROR_STATUS_BAT_OV_BIT BIT(5)
38#define CHARGER_ERROR_STATUS_BAT_TERM_MISSING_BIT BIT(4)
39#define BAT_TEMP_STATUS_MASK GENMASK(3, 0)
40#define BAT_TEMP_STATUS_SOFT_LIMIT_MASK GENMASK(3, 2)
41#define BAT_TEMP_STATUS_HOT_SOFT_LIMIT_BIT BIT(3)
42#define BAT_TEMP_STATUS_COLD_SOFT_LIMIT_BIT BIT(2)
43#define BAT_TEMP_STATUS_TOO_HOT_BIT BIT(1)
44#define BAT_TEMP_STATUS_TOO_COLD_BIT BIT(0)
45
46#define BATTERY_CHARGER_STATUS_4 0x0A
47#define CHARGE_CURRENT_POST_JEITA_MASK GENMASK(7, 0)
48
49#define BATTERY_CHARGER_STATUS_7 0x0D
50#define ENABLE_TRICKLE_BIT BIT(7)
51#define ENABLE_PRE_CHARGING_BIT BIT(6)
52#define ENABLE_FAST_CHARGING_BIT BIT(5)
53#define ENABLE_FULLON_MODE_BIT BIT(4)
54#define TOO_COLD_ADC_BIT BIT(3)
55#define TOO_HOT_ADC_BIT BIT(2)
56#define HOT_SL_ADC_BIT BIT(1)
57#define COLD_SL_ADC_BIT BIT(0)
58
59#define CHARGING_ENABLE_CMD 0x42
60#define CHARGING_ENABLE_CMD_BIT BIT(0)
61
62#define CHGR_CFG2 0x51
63#define CHG_EN_SRC_BIT BIT(7)
64#define CHG_EN_POLARITY_BIT BIT(6)
65#define PRETOFAST_TRANSITION_CFG_BIT BIT(5)
66#define BAT_OV_ECC_BIT BIT(4)
67#define I_TERM_BIT BIT(3)
68#define AUTO_RECHG_BIT BIT(2)
69#define EN_ANALOG_DROP_IN_VBATT_BIT BIT(1)
70#define CHARGER_INHIBIT_BIT BIT(0)
71
72#define PRE_CHARGE_CURRENT_CFG 0x60
73#define PRE_CHARGE_CURRENT_SETTING_MASK GENMASK(5, 0)
74
75#define FAST_CHARGE_CURRENT_CFG 0x61
76#define FAST_CHARGE_CURRENT_SETTING_MASK GENMASK(7, 0)
77
78#define FLOAT_VOLTAGE_CFG 0x70
79#define FLOAT_VOLTAGE_SETTING_MASK GENMASK(7, 0)
80
81#define FG_UPDATE_CFG_2_SEL 0x7D
82#define SOC_LT_OTG_THRESH_SEL_BIT BIT(3)
83#define SOC_LT_CHG_RECHARGE_THRESH_SEL_BIT BIT(2)
84#define VBT_LT_CHG_RECHARGE_THRESH_SEL_BIT BIT(1)
85#define IBT_LT_CHG_TERM_THRESH_SEL_BIT BIT(0)
86
87#define JEITA_EN_CFG 0x90
88#define JEITA_EN_HARDLIMIT_BIT BIT(4)
89#define JEITA_EN_HOT_SL_FCV_BIT BIT(3)
90#define JEITA_EN_COLD_SL_FCV_BIT BIT(2)
91#define JEITA_EN_HOT_SL_CCC_BIT BIT(1)
92#define JEITA_EN_COLD_SL_CCC_BIT BIT(0)
93
94#define INT_RT_STS 0x310
95#define TYPE_C_CHANGE_RT_STS_BIT BIT(7)
96#define USBIN_ICL_CHANGE_RT_STS_BIT BIT(6)
97#define USBIN_SOURCE_CHANGE_RT_STS_BIT BIT(5)
98#define USBIN_PLUGIN_RT_STS_BIT BIT(4)
99#define USBIN_OV_RT_STS_BIT BIT(3)
100#define USBIN_UV_RT_STS_BIT BIT(2)
101#define USBIN_LT_3P6V_RT_STS_BIT BIT(1)
102#define USBIN_COLLAPSE_RT_STS_BIT BIT(0)
103
104#define OTG_CFG 0x153
105#define OTG_RESERVED_MASK GENMASK(7, 6)
106#define DIS_OTG_ON_TLIM_BIT BIT(5)
107#define QUICKSTART_OTG_FASTROLESWAP_BIT BIT(4)
108#define INCREASE_DFP_TIME_BIT BIT(3)
109#define ENABLE_OTG_IN_DEBUG_MODE_BIT BIT(2)
110#define OTG_EN_SRC_CFG_BIT BIT(1)
111#define CONCURRENT_MODE_CFG_BIT BIT(0)
112
113#define OTG_ENG_OTG_CFG 0x1C0
114#define ENG_BUCKBOOST_HALT1_8_MODE_BIT BIT(0)
115
116#define APSD_STATUS 0x307
117#define APSD_STATUS_7_BIT BIT(7)
118#define HVDCP_CHECK_TIMEOUT_BIT BIT(6)
119#define SLOW_PLUGIN_TIMEOUT_BIT BIT(5)
120#define ENUMERATION_DONE_BIT BIT(4)
121#define VADP_CHANGE_DONE_AFTER_AUTH_BIT BIT(3)
122#define QC_AUTH_DONE_STATUS_BIT BIT(2)
123#define QC_CHARGER_BIT BIT(1)
124#define APSD_DTC_STATUS_DONE_BIT BIT(0)
125
126#define APSD_RESULT_STATUS 0x308
127#define ICL_OVERRIDE_LATCH_BIT BIT(7)
128#define APSD_RESULT_STATUS_MASK GENMASK(6, 0)
129#define QC_3P0_BIT BIT(6)
130#define QC_2P0_BIT BIT(5)
131#define FLOAT_CHARGER_BIT BIT(4)
132#define DCP_CHARGER_BIT BIT(3)
133#define CDP_CHARGER_BIT BIT(2)
134#define OCP_CHARGER_BIT BIT(1)
135#define SDP_CHARGER_BIT BIT(0)
136
137#define TYPE_C_STATUS_1 0x30B
138#define UFP_TYPEC_MASK GENMASK(7, 5)
139#define UFP_TYPEC_RDSTD_BIT BIT(7)
140#define UFP_TYPEC_RD1P5_BIT BIT(6)
141#define UFP_TYPEC_RD3P0_BIT BIT(5)
142#define UFP_TYPEC_FMB_255K_BIT BIT(4)
143#define UFP_TYPEC_FMB_301K_BIT BIT(3)
144#define UFP_TYPEC_FMB_523K_BIT BIT(2)
145#define UFP_TYPEC_FMB_619K_BIT BIT(1)
146#define UFP_TYPEC_OPEN_OPEN_BIT BIT(0)
147
148#define TYPE_C_STATUS_2 0x30C
149#define DFP_RA_OPEN_BIT BIT(7)
150#define TIMER_STAGE_BIT BIT(6)
151#define EXIT_UFP_MODE_BIT BIT(5)
152#define EXIT_DFP_MODE_BIT BIT(4)
153#define DFP_TYPEC_MASK GENMASK(3, 0)
154#define DFP_RD_OPEN_BIT BIT(3)
155#define DFP_RD_RA_VCONN_BIT BIT(2)
156#define DFP_RD_RD_BIT BIT(1)
157#define DFP_RA_RA_BIT BIT(0)
158
159#define TYPE_C_STATUS_3 0x30D
160#define ENABLE_BANDGAP_BIT BIT(7)
161#define U_USB_GND_NOVBUS_BIT BIT(6)
162#define U_USB_FLOAT_NOVBUS_BIT BIT(5)
163#define U_USB_GND_BIT BIT(4)
164#define U_USB_FMB1_BIT BIT(3)
165#define U_USB_FLOAT1_BIT BIT(2)
166#define U_USB_FMB2_BIT BIT(1)
167#define U_USB_FLOAT2_BIT BIT(0)
168
169#define TYPE_C_STATUS_4 0x30E
170#define UFP_DFP_MODE_STATUS_BIT BIT(7)
171#define TYPEC_VBUS_STATUS_BIT BIT(6)
172#define TYPEC_VBUS_ERROR_STATUS_BIT BIT(5)
173#define TYPEC_DEBOUNCE_DONE_STATUS_BIT BIT(4)
174#define TYPEC_UFP_AUDIO_ADAPT_STATUS_BIT BIT(3)
175#define TYPEC_VCONN_OVERCURR_STATUS_BIT BIT(2)
176#define CC_ORIENTATION_BIT BIT(1)
177#define CC_ATTACHED_BIT BIT(0)
178
179#define TYPE_C_STATUS_5 0x30F
180#define TRY_SOURCE_FAILED_BIT BIT(6)
181#define TRY_SINK_FAILED_BIT BIT(5)
182#define TIMER_STAGE_2_BIT BIT(4)
183#define TYPEC_LEGACY_CABLE_STATUS_BIT BIT(3)
184#define TYPEC_NONCOMP_LEGACY_CABLE_STATUS_BIT BIT(2)
185#define TYPEC_TRYSOURCE_DETECT_STATUS_BIT BIT(1)
186#define TYPEC_TRYSINK_DETECT_STATUS_BIT BIT(0)
187
188#define CMD_APSD 0x341
189#define ICL_OVERRIDE_BIT BIT(1)
190#define APSD_RERUN_BIT BIT(0)
191
192#define TYPE_C_CFG 0x358
193#define APSD_START_ON_CC_BIT BIT(7)
194#define WAIT_FOR_APSD_BIT BIT(6)
195#define FACTORY_MODE_DETECTION_EN_BIT BIT(5)
196#define FACTORY_MODE_ICL_3A_4A_BIT BIT(4)
197#define FACTORY_MODE_DIS_CHGING_CFG_BIT BIT(3)
198#define SUSPEND_NON_COMPLIANT_CFG_BIT BIT(2)
199#define VCONN_OC_CFG_BIT BIT(1)
200#define TYPE_C_OR_U_USB_BIT BIT(0)
201
202#define TYPE_C_CFG_2 0x359
203#define TYPE_C_DFP_CURRSRC_MODE_BIT BIT(7)
204#define DFP_CC_1P4V_OR_1P6V_BIT BIT(6)
205#define VCONN_SOFTSTART_CFG_MASK GENMASK(5, 4)
206#define EN_TRY_SOURCE_MODE_BIT BIT(3)
207#define USB_FACTORY_MODE_ENABLE_BIT BIT(2)
208#define TYPE_C_UFP_MODE_BIT BIT(1)
209#define EN_80UA_180UA_CUR_SOURCE_BIT BIT(0)
210
211#define TYPE_C_CFG_3 0x35A
212#define TVBUS_DEBOUNCE_BIT BIT(7)
213#define TYPEC_LEGACY_CABLE_INT_EN_BIT BIT(6)
214#define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN_B BIT(5)
215#define TYPEC_TRYSOURCE_DETECT_INT_EN_BIT BIT(4)
216#define TYPEC_TRYSINK_DETECT_INT_EN_BIT BIT(3)
217#define EN_TRYSINK_MODE_BIT BIT(2)
218#define EN_LEGACY_CABLE_DETECTION_BIT BIT(1)
219#define ALLOW_PD_DRING_UFP_TCCDB_BIT BIT(0)
220
221#define USBIN_OPTIONS_1_CFG 0x362
222#define CABLE_R_SEL_BIT BIT(7)
223#define HVDCP_AUTH_ALG_EN_CFG_BIT BIT(6)
224#define HVDCP_AUTONOMOUS_MODE_EN_CFG_BIT BIT(5)
225#define INPUT_PRIORITY_BIT BIT(4)
226#define AUTO_SRC_DETECT_BIT BIT(3)
227#define HVDCP_EN_BIT BIT(2)
228#define VADP_INCREMENT_VOLTAGE_LIMIT_BIT BIT(1)
229#define VADP_TAPER_TIMER_EN_BIT BIT(0)
230
231#define USBIN_OPTIONS_2_CFG 0x363
232#define WIPWR_RST_EUD_CFG_BIT BIT(7)
233#define SWITCHER_START_CFG_BIT BIT(6)
234#define DCD_TIMEOUT_SEL_BIT BIT(5)
235#define OCD_CURRENT_SEL_BIT BIT(4)
236#define SLOW_PLUGIN_TIMER_EN_CFG_BIT BIT(3)
237#define FLOAT_OPTIONS_MASK GENMASK(2, 0)
238#define FLOAT_DIS_CHGING_CFG_BIT BIT(2)
239#define SUSPEND_FLOAT_CFG_BIT BIT(1)
240#define FORCE_FLOAT_SDP_CFG_BIT BIT(0)
241
242#define TAPER_TIMER_SEL_CFG 0x364
243#define TYPEC_SPARE_CFG_BIT BIT(7)
244#define TYPEC_DRP_DFP_TIME_CFG_BIT BIT(5)
245#define TAPER_TIMER_SEL_MASK GENMASK(1, 0)
246
247#define USBIN_LOAD_CFG 0x365
248#define USBIN_OV_CH_LOAD_OPTION_BIT BIT(7)
249#define ICL_OVERRIDE_AFTER_APSD_BIT BIT(4)
250
251#define USBIN_ICL_OPTIONS 0x366
252#define CFG_USB3P0_SEL_BIT BIT(2)
253#define USB51_MODE_BIT BIT(1)
254#define USBIN_MODE_CHG_BIT BIT(0)
255
256#define TYPE_C_INTRPT_ENB_SOFTWARE_CTRL 0x368
257#define EXIT_SNK_BASED_ON_CC_BIT BIT(7)
258#define VCONN_EN_ORIENTATION_BIT BIT(6)
259#define TYPEC_VCONN_OVERCURR_INT_EN_BIT BIT(5)
260#define VCONN_EN_SRC_BIT BIT(4)
261#define VCONN_EN_VALUE_BIT BIT(3)
262#define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0)
263#define UFP_EN_CMD_BIT BIT(2)
264#define DFP_EN_CMD_BIT BIT(1)
265#define TYPEC_DISABLE_CMD_BIT BIT(0)
266
267#define USBIN_CURRENT_LIMIT_CFG 0x370
268#define USBIN_CURRENT_LIMIT_MASK GENMASK(7, 0)
269
270#define USBIN_AICL_OPTIONS_CFG 0x380
271#define SUSPEND_ON_COLLAPSE_USBIN_BIT BIT(7)
272#define USBIN_AICL_HDC_EN_BIT BIT(6)
273#define USBIN_AICL_START_AT_MAX_BIT BIT(5)
274#define USBIN_AICL_RERUN_EN_BIT BIT(4)
275#define USBIN_AICL_ADC_EN_BIT BIT(3)
276#define USBIN_AICL_EN_BIT BIT(2)
277#define USBIN_HV_COLLAPSE_RESPONSE_BIT BIT(1)
278#define USBIN_LV_COLLAPSE_RESPONSE_BIT BIT(0)
279
280#define USBIN_5V_AICL_THRESHOLD_CFG 0x381
281#define USBIN_5V_AICL_THRESHOLD_CFG_MASK GENMASK(2, 0)
282
283#define USBIN_CONT_AICL_THRESHOLD_CFG 0x384
284#define USBIN_CONT_AICL_THRESHOLD_CFG_MASK GENMASK(5, 0)
285
286#define DC_ENG_SSUPPLY_CFG2 0x4C1
287#define ENG_SSUPPLY_IVREF_OTG_SS_MASK GENMASK(2, 0)
288#define OTG_SS_SLOW 0x3
289
290#define DCIN_AICL_REF_SEL_CFG 0x481
291#define DCIN_CONT_AICL_THRESHOLD_CFG_MASK GENMASK(5, 0)
292
293#define WI_PWR_OPTIONS 0x495
294#define CHG_OK_BIT BIT(7)
295#define WIPWR_UVLO_IRQ_OPT_BIT BIT(6)
296#define BUCK_HOLDOFF_ENABLE_BIT BIT(5)
297#define CHG_OK_HW_SW_SELECT_BIT BIT(4)
298#define WIPWR_RST_ENABLE_BIT BIT(3)
299#define DCIN_WIPWR_IRQ_SELECT_BIT BIT(2)
300#define AICL_SWITCH_ENABLE_BIT BIT(1)
301#define ZIN_ICL_ENABLE_BIT BIT(0)
302
303#define ICL_STATUS 0x607
304#define INPUT_CURRENT_LIMIT_MASK GENMASK(7, 0)
305
306#define POWER_PATH_STATUS 0x60B
307#define P_PATH_INPUT_SS_DONE_BIT BIT(7)
308#define P_PATH_USBIN_SUSPEND_STS_BIT BIT(6)
309#define P_PATH_DCIN_SUSPEND_STS_BIT BIT(5)
310#define P_PATH_USE_USBIN_BIT BIT(4)
311#define P_PATH_USE_DCIN_BIT BIT(3)
312#define P_PATH_POWER_PATH_MASK GENMASK(2, 1)
313#define P_PATH_VALID_INPUT_POWER_SOURCE_STS_BIT BIT(0)
314
315#define BARK_BITE_WDOG_PET 0x643
316#define BARK_BITE_WDOG_PET_BIT BIT(0)
317
318#define WD_CFG 0x651
319#define WATCHDOG_TRIGGER_AFP_EN_BIT BIT(7)
320#define BARK_WDOG_INT_EN_BIT BIT(6)
321#define BITE_WDOG_INT_EN_BIT BIT(5)
322#define SFT_AFTER_WDOG_IRQ_MASK GENMASK(4, 3)
323#define WDOG_IRQ_SFT_BIT BIT(2)
324#define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1)
325#define WDOG_TIMER_EN_BIT BIT(0)
326
327#define SNARL_BARK_BITE_WD_CFG 0x653
328#define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7)
329#define SNARL_WDOG_TIMEOUT_MASK GENMASK(6, 4)
330#define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2)
331#define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0)
332
333#define AICL_RERUN_TIME_CFG 0x661
334#define AICL_RERUN_TIME_MASK GENMASK(1, 0)
335
336#define STAT_CFG 0x690
337#define STAT_SW_OVERRIDE_VALUE_BIT BIT(7)
338#define STAT_SW_OVERRIDE_CFG_BIT BIT(6)
339#define STAT_PARALLEL_OFF_DG_CFG_MASK GENMASK(5, 4)
340#define STAT_POLARITY_CFG_BIT BIT(3)
341#define STAT_PARALLEL_CFG_BIT BIT(2)
342#define STAT_FUNCTION_CFG_BIT BIT(1)
343#define STAT_IRQ_PULSING_EN_BIT BIT(0)
344
345#define SDP_CURRENT_UA 500000
346#define CDP_CURRENT_UA 1500000
347#define DCP_CURRENT_UA 1500000
348#define CURRENT_MAX_UA DCP_CURRENT_UA
349
350/* pmi8998 registers represent current in increments of 1/40th of an amp */
351#define CURRENT_SCALE_FACTOR 25000
352/* clang-format on */
353
354enum charger_status {
355 TRICKLE_CHARGE = 0,
356 PRE_CHARGE,
357 FAST_CHARGE,
358 FULLON_CHARGE,
359 TAPER_CHARGE,
360 TERMINATE_CHARGE,
361 INHIBIT_CHARGE,
362 DISABLE_CHARGE,
363};
364
365struct smb2_register {
366 u16 addr;
367 u8 mask;
368 u8 val;
369};
370
371/**
372 * struct smb2_chip - smb2 chip structure
373 * @dev: Device reference for power_supply
374 * @name: The platform device name
375 * @base: Base address for smb2 registers
376 * @regmap: Register map
377 * @batt_info: Battery data from DT
378 * @status_change_work: Worker to handle plug/unplug events
379 * @cable_irq: USB plugin IRQ
380 * @wakeup_enabled: If the cable IRQ will cause a wakeup
381 * @usb_in_i_chan: USB_IN current measurement channel
382 * @usb_in_v_chan: USB_IN voltage measurement channel
383 * @chg_psy: Charger power supply instance
384 */
385struct smb2_chip {
386 struct device *dev;
387 const char *name;
388 unsigned int base;
389 struct regmap *regmap;
390 struct power_supply_battery_info *batt_info;
391
392 struct delayed_work status_change_work;
393 int cable_irq;
394 bool wakeup_enabled;
395
396 struct iio_channel *usb_in_i_chan;
397 struct iio_channel *usb_in_v_chan;
398
399 struct power_supply *chg_psy;
400};
401
402static enum power_supply_property smb2_properties[] = {
403 POWER_SUPPLY_PROP_MANUFACTURER,
404 POWER_SUPPLY_PROP_MODEL_NAME,
405 POWER_SUPPLY_PROP_CURRENT_MAX,
406 POWER_SUPPLY_PROP_CURRENT_NOW,
407 POWER_SUPPLY_PROP_VOLTAGE_NOW,
408 POWER_SUPPLY_PROP_STATUS,
409 POWER_SUPPLY_PROP_HEALTH,
410 POWER_SUPPLY_PROP_ONLINE,
411 POWER_SUPPLY_PROP_USB_TYPE,
412};
413
414static enum power_supply_usb_type smb2_usb_types[] = {
415 POWER_SUPPLY_USB_TYPE_UNKNOWN,
416 POWER_SUPPLY_USB_TYPE_SDP,
417 POWER_SUPPLY_USB_TYPE_DCP,
418 POWER_SUPPLY_USB_TYPE_CDP,
419};
420
421static int smb2_get_prop_usb_online(struct smb2_chip *chip, int *val)
422{
423 unsigned int stat;
424 int rc;
425
426 rc = regmap_read(map: chip->regmap, reg: chip->base + POWER_PATH_STATUS, val: &stat);
427 if (rc < 0) {
428 dev_err(chip->dev, "Couldn't read power path status: %d\n", rc);
429 return rc;
430 }
431
432 *val = (stat & P_PATH_USE_USBIN_BIT) &&
433 (stat & P_PATH_VALID_INPUT_POWER_SOURCE_STS_BIT);
434 return 0;
435}
436
437/*
438 * Qualcomm "automatic power source detection" aka APSD
439 * tells us what type of charger we're connected to.
440 */
441static int smb2_apsd_get_charger_type(struct smb2_chip *chip, int *val)
442{
443 unsigned int apsd_stat, stat;
444 int usb_online = 0;
445 int rc;
446
447 rc = smb2_get_prop_usb_online(chip, val: &usb_online);
448 if (!usb_online) {
449 *val = POWER_SUPPLY_USB_TYPE_UNKNOWN;
450 return rc;
451 }
452
453 rc = regmap_read(map: chip->regmap, reg: chip->base + APSD_STATUS, val: &apsd_stat);
454 if (rc < 0) {
455 dev_err(chip->dev, "Failed to read apsd status, rc = %d", rc);
456 return rc;
457 }
458 if (!(apsd_stat & APSD_DTC_STATUS_DONE_BIT)) {
459 dev_dbg(chip->dev, "Apsd not ready");
460 return -EAGAIN;
461 }
462
463 rc = regmap_read(map: chip->regmap, reg: chip->base + APSD_RESULT_STATUS, val: &stat);
464 if (rc < 0) {
465 dev_err(chip->dev, "Failed to read apsd result, rc = %d", rc);
466 return rc;
467 }
468
469 stat &= APSD_RESULT_STATUS_MASK;
470
471 if (stat & CDP_CHARGER_BIT)
472 *val = POWER_SUPPLY_USB_TYPE_CDP;
473 else if (stat & (DCP_CHARGER_BIT | OCP_CHARGER_BIT | FLOAT_CHARGER_BIT))
474 *val = POWER_SUPPLY_USB_TYPE_DCP;
475 else /* SDP_CHARGER_BIT (or others) */
476 *val = POWER_SUPPLY_USB_TYPE_SDP;
477
478 return 0;
479}
480
481static int smb2_get_prop_status(struct smb2_chip *chip, int *val)
482{
483 unsigned char stat[2];
484 int usb_online = 0;
485 int rc;
486
487 rc = smb2_get_prop_usb_online(chip, val: &usb_online);
488 if (!usb_online) {
489 *val = POWER_SUPPLY_STATUS_DISCHARGING;
490 return rc;
491 }
492
493 rc = regmap_bulk_read(map: chip->regmap,
494 reg: chip->base + BATTERY_CHARGER_STATUS_1, val: &stat, val_count: 2);
495 if (rc < 0) {
496 dev_err(chip->dev, "Failed to read charging status ret=%d\n",
497 rc);
498 return rc;
499 }
500
501 if (stat[1] & CHARGER_ERROR_STATUS_BAT_OV_BIT) {
502 *val = POWER_SUPPLY_STATUS_NOT_CHARGING;
503 return 0;
504 }
505
506 stat[0] = stat[0] & BATTERY_CHARGER_STATUS_MASK;
507
508 switch (stat[0]) {
509 case TRICKLE_CHARGE:
510 case PRE_CHARGE:
511 case FAST_CHARGE:
512 case FULLON_CHARGE:
513 case TAPER_CHARGE:
514 *val = POWER_SUPPLY_STATUS_CHARGING;
515 return rc;
516 case DISABLE_CHARGE:
517 *val = POWER_SUPPLY_STATUS_NOT_CHARGING;
518 return rc;
519 case TERMINATE_CHARGE:
520 case INHIBIT_CHARGE:
521 *val = POWER_SUPPLY_STATUS_FULL;
522 return rc;
523 default:
524 *val = POWER_SUPPLY_STATUS_UNKNOWN;
525 return rc;
526 }
527}
528
529static inline int smb2_get_current_limit(struct smb2_chip *chip,
530 unsigned int *val)
531{
532 int rc = regmap_read(map: chip->regmap, reg: chip->base + ICL_STATUS, val);
533
534 if (rc >= 0)
535 *val *= CURRENT_SCALE_FACTOR;
536 return rc;
537}
538
539static int smb2_set_current_limit(struct smb2_chip *chip, unsigned int val)
540{
541 unsigned char val_raw;
542
543 if (val > 4800000) {
544 dev_err(chip->dev,
545 "Can't set current limit higher than 4800000uA");
546 return -EINVAL;
547 }
548 val_raw = val / CURRENT_SCALE_FACTOR;
549
550 return regmap_write(map: chip->regmap, reg: chip->base + USBIN_CURRENT_LIMIT_CFG,
551 val: val_raw);
552}
553
554static void smb2_status_change_work(struct work_struct *work)
555{
556 unsigned int charger_type, current_ua;
557 int usb_online = 0;
558 int count, rc;
559 struct smb2_chip *chip;
560
561 chip = container_of(work, struct smb2_chip, status_change_work.work);
562
563 smb2_get_prop_usb_online(chip, val: &usb_online);
564 if (!usb_online)
565 return;
566
567 for (count = 0; count < 3; count++) {
568 dev_dbg(chip->dev, "get charger type retry %d\n", count);
569 rc = smb2_apsd_get_charger_type(chip, val: &charger_type);
570 if (rc != -EAGAIN)
571 break;
572 msleep(msecs: 100);
573 }
574
575 if (rc < 0 && rc != -EAGAIN) {
576 dev_err(chip->dev, "get charger type failed: %d\n", rc);
577 return;
578 }
579
580 if (rc < 0) {
581 rc = regmap_update_bits(map: chip->regmap, reg: chip->base + CMD_APSD,
582 APSD_RERUN_BIT, APSD_RERUN_BIT);
583 schedule_delayed_work(dwork: &chip->status_change_work,
584 delay: msecs_to_jiffies(m: 1000));
585 dev_dbg(chip->dev, "get charger type failed, rerun apsd\n");
586 return;
587 }
588
589 switch (charger_type) {
590 case POWER_SUPPLY_USB_TYPE_CDP:
591 current_ua = CDP_CURRENT_UA;
592 break;
593 case POWER_SUPPLY_USB_TYPE_DCP:
594 current_ua = DCP_CURRENT_UA;
595 break;
596 case POWER_SUPPLY_USB_TYPE_SDP:
597 default:
598 current_ua = SDP_CURRENT_UA;
599 break;
600 }
601
602 smb2_set_current_limit(chip, val: current_ua);
603 power_supply_changed(psy: chip->chg_psy);
604}
605
606static int smb2_get_iio_chan(struct smb2_chip *chip, struct iio_channel *chan,
607 int *val)
608{
609 int rc;
610 union power_supply_propval status;
611
612 rc = power_supply_get_property(psy: chip->chg_psy, psp: POWER_SUPPLY_PROP_STATUS,
613 val: &status);
614 if (rc < 0 || status.intval != POWER_SUPPLY_STATUS_CHARGING) {
615 *val = 0;
616 return 0;
617 }
618
619 if (IS_ERR(ptr: chan)) {
620 dev_err(chip->dev, "Failed to chan, err = %li", PTR_ERR(chan));
621 return PTR_ERR(ptr: chan);
622 }
623
624 return iio_read_channel_processed(chan, val);
625}
626
627static int smb2_get_prop_health(struct smb2_chip *chip, int *val)
628{
629 int rc;
630 unsigned int stat;
631
632 rc = regmap_read(map: chip->regmap, reg: chip->base + BATTERY_CHARGER_STATUS_2,
633 val: &stat);
634 if (rc < 0) {
635 dev_err(chip->dev, "Couldn't read charger status rc=%d\n", rc);
636 return rc;
637 }
638
639 switch (stat) {
640 case CHARGER_ERROR_STATUS_BAT_OV_BIT:
641 *val = POWER_SUPPLY_HEALTH_OVERVOLTAGE;
642 return 0;
643 case BAT_TEMP_STATUS_TOO_COLD_BIT:
644 *val = POWER_SUPPLY_HEALTH_COLD;
645 return 0;
646 case BAT_TEMP_STATUS_TOO_HOT_BIT:
647 *val = POWER_SUPPLY_HEALTH_OVERHEAT;
648 return 0;
649 case BAT_TEMP_STATUS_COLD_SOFT_LIMIT_BIT:
650 *val = POWER_SUPPLY_HEALTH_COOL;
651 return 0;
652 case BAT_TEMP_STATUS_HOT_SOFT_LIMIT_BIT:
653 *val = POWER_SUPPLY_HEALTH_WARM;
654 return 0;
655 default:
656 *val = POWER_SUPPLY_HEALTH_GOOD;
657 return 0;
658 }
659}
660
661static int smb2_get_property(struct power_supply *psy,
662 enum power_supply_property psp,
663 union power_supply_propval *val)
664{
665 struct smb2_chip *chip = power_supply_get_drvdata(psy);
666
667 switch (psp) {
668 case POWER_SUPPLY_PROP_MANUFACTURER:
669 val->strval = "Qualcomm";
670 return 0;
671 case POWER_SUPPLY_PROP_MODEL_NAME:
672 val->strval = chip->name;
673 return 0;
674 case POWER_SUPPLY_PROP_CURRENT_MAX:
675 return smb2_get_current_limit(chip, val: &val->intval);
676 case POWER_SUPPLY_PROP_CURRENT_NOW:
677 return smb2_get_iio_chan(chip, chan: chip->usb_in_i_chan,
678 val: &val->intval);
679 case POWER_SUPPLY_PROP_VOLTAGE_NOW:
680 return smb2_get_iio_chan(chip, chan: chip->usb_in_v_chan,
681 val: &val->intval);
682 case POWER_SUPPLY_PROP_ONLINE:
683 return smb2_get_prop_usb_online(chip, val: &val->intval);
684 case POWER_SUPPLY_PROP_STATUS:
685 return smb2_get_prop_status(chip, val: &val->intval);
686 case POWER_SUPPLY_PROP_HEALTH:
687 return smb2_get_prop_health(chip, val: &val->intval);
688 case POWER_SUPPLY_PROP_USB_TYPE:
689 return smb2_apsd_get_charger_type(chip, val: &val->intval);
690 default:
691 dev_err(chip->dev, "invalid property: %d\n", psp);
692 return -EINVAL;
693 }
694}
695
696static int smb2_set_property(struct power_supply *psy,
697 enum power_supply_property psp,
698 const union power_supply_propval *val)
699{
700 struct smb2_chip *chip = power_supply_get_drvdata(psy);
701
702 switch (psp) {
703 case POWER_SUPPLY_PROP_CURRENT_MAX:
704 return smb2_set_current_limit(chip, val: val->intval);
705 default:
706 dev_err(chip->dev, "No setter for property: %d\n", psp);
707 return -EINVAL;
708 }
709}
710
711static int smb2_property_is_writable(struct power_supply *psy,
712 enum power_supply_property psp)
713{
714 switch (psp) {
715 case POWER_SUPPLY_PROP_CURRENT_MAX:
716 return 1;
717 default:
718 return 0;
719 }
720}
721
722static irqreturn_t smb2_handle_batt_overvoltage(int irq, void *data)
723{
724 struct smb2_chip *chip = data;
725 unsigned int status;
726
727 regmap_read(map: chip->regmap, reg: chip->base + BATTERY_CHARGER_STATUS_2,
728 val: &status);
729
730 if (status & CHARGER_ERROR_STATUS_BAT_OV_BIT) {
731 /* The hardware stops charging automatically */
732 dev_err(chip->dev, "battery overvoltage detected\n");
733 power_supply_changed(psy: chip->chg_psy);
734 }
735
736 return IRQ_HANDLED;
737}
738
739static irqreturn_t smb2_handle_usb_plugin(int irq, void *data)
740{
741 struct smb2_chip *chip = data;
742
743 power_supply_changed(psy: chip->chg_psy);
744
745 schedule_delayed_work(dwork: &chip->status_change_work,
746 delay: msecs_to_jiffies(m: 1500));
747
748 return IRQ_HANDLED;
749}
750
751static irqreturn_t smb2_handle_usb_icl_change(int irq, void *data)
752{
753 struct smb2_chip *chip = data;
754
755 power_supply_changed(psy: chip->chg_psy);
756
757 return IRQ_HANDLED;
758}
759
760static irqreturn_t smb2_handle_wdog_bark(int irq, void *data)
761{
762 struct smb2_chip *chip = data;
763 int rc;
764
765 power_supply_changed(psy: chip->chg_psy);
766
767 rc = regmap_write(map: chip->regmap, BARK_BITE_WDOG_PET,
768 BARK_BITE_WDOG_PET_BIT);
769 if (rc < 0)
770 dev_err(chip->dev, "Couldn't pet the dog rc=%d\n", rc);
771
772 return IRQ_HANDLED;
773}
774
775static const struct power_supply_desc smb2_psy_desc = {
776 .name = "pmi8998_charger",
777 .type = POWER_SUPPLY_TYPE_USB,
778 .usb_types = smb2_usb_types,
779 .num_usb_types = ARRAY_SIZE(smb2_usb_types),
780 .properties = smb2_properties,
781 .num_properties = ARRAY_SIZE(smb2_properties),
782 .get_property = smb2_get_property,
783 .set_property = smb2_set_property,
784 .property_is_writeable = smb2_property_is_writable,
785};
786
787/* Init sequence derived from vendor downstream driver */
788static const struct smb2_register smb2_init_seq[] = {
789 { .addr = AICL_RERUN_TIME_CFG, .mask = AICL_RERUN_TIME_MASK, .val = 0 },
790 /*
791 * By default configure us as an upstream facing port
792 * FIXME: This will be handled by the type-c driver
793 */
794 { .addr = TYPE_C_INTRPT_ENB_SOFTWARE_CTRL,
795 .mask = TYPEC_POWER_ROLE_CMD_MASK | VCONN_EN_SRC_BIT |
796 VCONN_EN_VALUE_BIT,
797 .val = VCONN_EN_SRC_BIT },
798 /*
799 * Disable Type-C factory mode and stay in Attached.SRC state when VCONN
800 * over-current happens
801 */
802 { .addr = TYPE_C_CFG,
803 .mask = FACTORY_MODE_DETECTION_EN_BIT | VCONN_OC_CFG_BIT,
804 .val = 0 },
805 /* Configure VBUS for software control */
806 { .addr = OTG_CFG, .mask = OTG_EN_SRC_CFG_BIT, .val = 0 },
807 /*
808 * Use VBAT to determine the recharge threshold when battery is full
809 * rather than the state of charge.
810 */
811 { .addr = FG_UPDATE_CFG_2_SEL,
812 .mask = SOC_LT_CHG_RECHARGE_THRESH_SEL_BIT |
813 VBT_LT_CHG_RECHARGE_THRESH_SEL_BIT,
814 .val = VBT_LT_CHG_RECHARGE_THRESH_SEL_BIT },
815 /* Enable charging */
816 { .addr = USBIN_OPTIONS_1_CFG, .mask = HVDCP_EN_BIT, .val = 0 },
817 { .addr = CHARGING_ENABLE_CMD,
818 .mask = CHARGING_ENABLE_CMD_BIT,
819 .val = CHARGING_ENABLE_CMD_BIT },
820 /*
821 * Match downstream defaults
822 * CHG_EN_SRC_BIT - charger enable is controlled by software
823 * CHG_EN_POLARITY_BIT - polarity of charge enable pin when in HW control
824 * pulled low on OnePlus 6 and SHIFT6mq
825 * PRETOFAST_TRANSITION_CFG_BIT -
826 * BAT_OV_ECC_BIT -
827 * I_TERM_BIT - Current termination ?? 0 = enabled
828 * AUTO_RECHG_BIT - Enable automatic recharge when battery is full
829 * 0 = enabled
830 * EN_ANALOG_DROP_IN_VBATT_BIT
831 * CHARGER_INHIBIT_BIT - Inhibit charging based on battery voltage
832 * instead of ??
833 */
834 { .addr = CHGR_CFG2,
835 .mask = CHG_EN_SRC_BIT | CHG_EN_POLARITY_BIT |
836 PRETOFAST_TRANSITION_CFG_BIT | BAT_OV_ECC_BIT | I_TERM_BIT |
837 AUTO_RECHG_BIT | EN_ANALOG_DROP_IN_VBATT_BIT |
838 CHARGER_INHIBIT_BIT,
839 .val = CHARGER_INHIBIT_BIT },
840 /* STAT pin software override, match downstream. Parallell charging? */
841 { .addr = STAT_CFG,
842 .mask = STAT_SW_OVERRIDE_CFG_BIT,
843 .val = STAT_SW_OVERRIDE_CFG_BIT },
844 /* Set the default SDP charger type to a 500ma USB 2.0 port */
845 { .addr = USBIN_ICL_OPTIONS,
846 .mask = USB51_MODE_BIT | USBIN_MODE_CHG_BIT,
847 .val = USB51_MODE_BIT },
848 /* Disable watchdog */
849 { .addr = SNARL_BARK_BITE_WD_CFG, .mask = 0xff, .val = 0 },
850 { .addr = WD_CFG,
851 .mask = WATCHDOG_TRIGGER_AFP_EN_BIT | WDOG_TIMER_EN_ON_PLUGIN_BIT |
852 BARK_WDOG_INT_EN_BIT,
853 .val = 0 },
854 /* These bits aren't documented anywhere */
855 { .addr = USBIN_5V_AICL_THRESHOLD_CFG,
856 .mask = USBIN_5V_AICL_THRESHOLD_CFG_MASK,
857 .val = 0x3 },
858 { .addr = USBIN_CONT_AICL_THRESHOLD_CFG,
859 .mask = USBIN_CONT_AICL_THRESHOLD_CFG_MASK,
860 .val = 0x3 },
861 /*
862 * Enable Automatic Input Current Limit, this will slowly ramp up the current
863 * When connected to a wall charger, and automatically stop when it detects
864 * the charger current limit (voltage drop?) or it reaches the programmed limit.
865 */
866 { .addr = USBIN_AICL_OPTIONS_CFG,
867 .mask = USBIN_AICL_START_AT_MAX_BIT | USBIN_AICL_ADC_EN_BIT |
868 USBIN_AICL_EN_BIT | SUSPEND_ON_COLLAPSE_USBIN_BIT |
869 USBIN_HV_COLLAPSE_RESPONSE_BIT |
870 USBIN_LV_COLLAPSE_RESPONSE_BIT,
871 .val = USBIN_HV_COLLAPSE_RESPONSE_BIT |
872 USBIN_LV_COLLAPSE_RESPONSE_BIT | USBIN_AICL_EN_BIT },
873 /*
874 * Set pre charge current to default, the OnePlus 6 bootloader
875 * sets this very conservatively.
876 */
877 { .addr = PRE_CHARGE_CURRENT_CFG,
878 .mask = PRE_CHARGE_CURRENT_SETTING_MASK,
879 .val = 500000 / CURRENT_SCALE_FACTOR },
880 /*
881 * This overrides all of the current limit options exposed to userspace
882 * and prevents the device from pulling more than ~1A. This is done
883 * to minimise potential fire hazard risks.
884 */
885 { .addr = FAST_CHARGE_CURRENT_CFG,
886 .mask = FAST_CHARGE_CURRENT_SETTING_MASK,
887 .val = 1000000 / CURRENT_SCALE_FACTOR },
888};
889
890static int smb2_init_hw(struct smb2_chip *chip)
891{
892 int rc, i;
893
894 for (i = 0; i < ARRAY_SIZE(smb2_init_seq); i++) {
895 dev_dbg(chip->dev, "%d: Writing 0x%02x to 0x%02x\n", i,
896 smb2_init_seq[i].val, smb2_init_seq[i].addr);
897 rc = regmap_update_bits(map: chip->regmap,
898 reg: chip->base + smb2_init_seq[i].addr,
899 mask: smb2_init_seq[i].mask,
900 val: smb2_init_seq[i].val);
901 if (rc < 0)
902 return dev_err_probe(dev: chip->dev, err: rc,
903 fmt: "%s: init command %d failed\n",
904 __func__, i);
905 }
906
907 return 0;
908}
909
910static int smb2_init_irq(struct smb2_chip *chip, int *irq, const char *name,
911 irqreturn_t (*handler)(int irq, void *data))
912{
913 int irqnum;
914 int rc;
915
916 irqnum = platform_get_irq_byname(to_platform_device(chip->dev), name);
917 if (irqnum < 0)
918 return irqnum;
919
920 rc = devm_request_threaded_irq(dev: chip->dev, irq: irqnum, NULL, thread_fn: handler,
921 IRQF_ONESHOT, devname: name, dev_id: chip);
922 if (rc < 0)
923 return dev_err_probe(dev: chip->dev, err: rc, fmt: "Couldn't request irq %s\n",
924 name);
925
926 if (irq)
927 *irq = irqnum;
928
929 return 0;
930}
931
932static int smb2_probe(struct platform_device *pdev)
933{
934 struct power_supply_config supply_config = {};
935 struct power_supply_desc *desc;
936 struct smb2_chip *chip;
937 int rc, irq;
938
939 chip = devm_kzalloc(dev: &pdev->dev, size: sizeof(*chip), GFP_KERNEL);
940 if (!chip)
941 return -ENOMEM;
942
943 chip->dev = &pdev->dev;
944 chip->name = pdev->name;
945
946 chip->regmap = dev_get_regmap(dev: pdev->dev.parent, NULL);
947 if (!chip->regmap)
948 return dev_err_probe(dev: chip->dev, err: -ENODEV,
949 fmt: "failed to locate the regmap\n");
950
951 rc = device_property_read_u32(dev: chip->dev, propname: "reg", val: &chip->base);
952 if (rc < 0)
953 return dev_err_probe(dev: chip->dev, err: rc,
954 fmt: "Couldn't read base address\n");
955
956 chip->usb_in_v_chan = devm_iio_channel_get(dev: chip->dev, consumer_channel: "usbin_v");
957 if (IS_ERR(ptr: chip->usb_in_v_chan))
958 return dev_err_probe(dev: chip->dev, err: PTR_ERR(ptr: chip->usb_in_v_chan),
959 fmt: "Couldn't get usbin_v IIO channel\n");
960
961 chip->usb_in_i_chan = devm_iio_channel_get(dev: chip->dev, consumer_channel: "usbin_i");
962 if (IS_ERR(ptr: chip->usb_in_i_chan)) {
963 return dev_err_probe(dev: chip->dev, err: PTR_ERR(ptr: chip->usb_in_i_chan),
964 fmt: "Couldn't get usbin_i IIO channel\n");
965 }
966
967 rc = smb2_init_hw(chip);
968 if (rc < 0)
969 return rc;
970
971 supply_config.drv_data = chip;
972 supply_config.of_node = pdev->dev.of_node;
973
974 desc = devm_kzalloc(dev: chip->dev, size: sizeof(smb2_psy_desc), GFP_KERNEL);
975 if (!desc)
976 return -ENOMEM;
977 memcpy(desc, &smb2_psy_desc, sizeof(smb2_psy_desc));
978 desc->name =
979 devm_kasprintf(dev: chip->dev, GFP_KERNEL, fmt: "%s-charger",
980 (const char *)device_get_match_data(dev: chip->dev));
981 if (!desc->name)
982 return -ENOMEM;
983
984 chip->chg_psy =
985 devm_power_supply_register(parent: chip->dev, desc, cfg: &supply_config);
986 if (IS_ERR(ptr: chip->chg_psy))
987 return dev_err_probe(dev: chip->dev, err: PTR_ERR(ptr: chip->chg_psy),
988 fmt: "failed to register power supply\n");
989
990 rc = power_supply_get_battery_info(psy: chip->chg_psy, info_out: &chip->batt_info);
991 if (rc)
992 return dev_err_probe(dev: chip->dev, err: rc,
993 fmt: "Failed to get battery info\n");
994
995 rc = devm_delayed_work_autocancel(dev: chip->dev, w: &chip->status_change_work,
996 worker: smb2_status_change_work);
997 if (rc)
998 return dev_err_probe(dev: chip->dev, err: rc,
999 fmt: "Failed to init status change work\n");
1000
1001 rc = (chip->batt_info->voltage_max_design_uv - 3487500) / 7500 + 1;
1002 rc = regmap_update_bits(map: chip->regmap, reg: chip->base + FLOAT_VOLTAGE_CFG,
1003 FLOAT_VOLTAGE_SETTING_MASK, val: rc);
1004 if (rc < 0)
1005 return dev_err_probe(dev: chip->dev, err: rc, fmt: "Couldn't set vbat max\n");
1006
1007 rc = smb2_init_irq(chip, irq: &irq, name: "bat-ov", handler: smb2_handle_batt_overvoltage);
1008 if (rc < 0)
1009 return rc;
1010
1011 rc = smb2_init_irq(chip, irq: &chip->cable_irq, name: "usb-plugin",
1012 handler: smb2_handle_usb_plugin);
1013 if (rc < 0)
1014 return rc;
1015
1016 rc = smb2_init_irq(chip, irq: &irq, name: "usbin-icl-change",
1017 handler: smb2_handle_usb_icl_change);
1018 if (rc < 0)
1019 return rc;
1020 rc = smb2_init_irq(chip, irq: &irq, name: "wdog-bark", handler: smb2_handle_wdog_bark);
1021 if (rc < 0)
1022 return rc;
1023
1024 rc = dev_pm_set_wake_irq(dev: chip->dev, irq: chip->cable_irq);
1025 if (rc < 0)
1026 return dev_err_probe(dev: chip->dev, err: rc, fmt: "Couldn't set wake irq\n");
1027
1028 platform_set_drvdata(pdev, data: chip);
1029
1030 /* Initialise charger state */
1031 schedule_delayed_work(dwork: &chip->status_change_work, delay: 0);
1032
1033 return 0;
1034}
1035
1036static const struct of_device_id smb2_match_id_table[] = {
1037 { .compatible = "qcom,pmi8998-charger", .data = "pmi8998" },
1038 { .compatible = "qcom,pm660-charger", .data = "pm660" },
1039 { /* sentinal */ }
1040};
1041MODULE_DEVICE_TABLE(of, smb2_match_id_table);
1042
1043static struct platform_driver qcom_spmi_smb2 = {
1044 .probe = smb2_probe,
1045 .driver = {
1046 .name = "qcom-pmi8998/pm660-charger",
1047 .of_match_table = smb2_match_id_table,
1048 },
1049};
1050
1051module_platform_driver(qcom_spmi_smb2);
1052
1053MODULE_AUTHOR("Caleb Connolly <caleb.connolly@linaro.org>");
1054MODULE_DESCRIPTION("Qualcomm SMB2 Charger Driver");
1055MODULE_LICENSE("GPL");
1056

source code of linux/drivers/power/supply/qcom_pmi8998_charger.c