1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 2015 Intel Corporation. All rights reserved. |
4 | * |
5 | * Author: Shobhit Kumar <shobhit.kumar@intel.com> |
6 | */ |
7 | |
8 | #include <linux/platform_device.h> |
9 | #include <linux/regmap.h> |
10 | #include <linux/mfd/intel_soc_pmic.h> |
11 | #include <linux/pwm.h> |
12 | |
13 | #define PWM0_CLK_DIV 0x4B |
14 | #define PWM_OUTPUT_ENABLE BIT(7) |
15 | #define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */ |
16 | #define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */ |
17 | #define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */ |
18 | |
19 | #define PWM0_DUTY_CYCLE 0x4E |
20 | #define BACKLIGHT_EN 0x51 |
21 | |
22 | #define PWM_MAX_LEVEL 0xFF |
23 | |
24 | #define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ |
25 | #define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */ |
26 | |
27 | /** |
28 | * struct crystalcove_pwm - Crystal Cove PWM controller |
29 | * @chip: the abstract pwm_chip structure. |
30 | * @regmap: the regmap from the parent device. |
31 | */ |
32 | struct crystalcove_pwm { |
33 | struct pwm_chip chip; |
34 | struct regmap *regmap; |
35 | }; |
36 | |
37 | static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *chip) |
38 | { |
39 | return container_of(chip, struct crystalcove_pwm, chip); |
40 | } |
41 | |
42 | static int crc_pwm_calc_clk_div(int period_ns) |
43 | { |
44 | int clk_div; |
45 | |
46 | clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); |
47 | /* clk_div 1 - 128, maps to register values 0-127 */ |
48 | if (clk_div > 0) |
49 | clk_div--; |
50 | |
51 | return clk_div; |
52 | } |
53 | |
54 | static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
55 | const struct pwm_state *state) |
56 | { |
57 | struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); |
58 | struct device *dev = crc_pwm->chip.dev; |
59 | int err; |
60 | |
61 | if (state->period > PWM_MAX_PERIOD_NS) { |
62 | dev_err(dev, "un-supported period_ns\n" ); |
63 | return -EINVAL; |
64 | } |
65 | |
66 | if (state->polarity != PWM_POLARITY_NORMAL) |
67 | return -EINVAL; |
68 | |
69 | if (pwm_is_enabled(pwm) && !state->enabled) { |
70 | err = regmap_write(map: crc_pwm->regmap, BACKLIGHT_EN, val: 0); |
71 | if (err) { |
72 | dev_err(dev, "Error writing BACKLIGHT_EN %d\n" , err); |
73 | return err; |
74 | } |
75 | } |
76 | |
77 | if (pwm_get_duty_cycle(pwm) != state->duty_cycle || |
78 | pwm_get_period(pwm) != state->period) { |
79 | u64 level = state->duty_cycle * PWM_MAX_LEVEL; |
80 | |
81 | do_div(level, state->period); |
82 | |
83 | err = regmap_write(map: crc_pwm->regmap, PWM0_DUTY_CYCLE, val: level); |
84 | if (err) { |
85 | dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n" , err); |
86 | return err; |
87 | } |
88 | } |
89 | |
90 | if (pwm_is_enabled(pwm) && state->enabled && |
91 | pwm_get_period(pwm) != state->period) { |
92 | /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ |
93 | err = regmap_write(map: crc_pwm->regmap, PWM0_CLK_DIV, val: 0); |
94 | if (err) { |
95 | dev_err(dev, "Error writing PWM0_CLK_DIV %d\n" , err); |
96 | return err; |
97 | } |
98 | } |
99 | |
100 | if (pwm_get_period(pwm) != state->period || |
101 | pwm_is_enabled(pwm) != state->enabled) { |
102 | int clk_div = crc_pwm_calc_clk_div(period_ns: state->period); |
103 | int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0; |
104 | |
105 | err = regmap_write(map: crc_pwm->regmap, PWM0_CLK_DIV, |
106 | val: clk_div | pwm_output_enable); |
107 | if (err) { |
108 | dev_err(dev, "Error writing PWM0_CLK_DIV %d\n" , err); |
109 | return err; |
110 | } |
111 | } |
112 | |
113 | if (!pwm_is_enabled(pwm) && state->enabled) { |
114 | err = regmap_write(map: crc_pwm->regmap, BACKLIGHT_EN, val: 1); |
115 | if (err) { |
116 | dev_err(dev, "Error writing BACKLIGHT_EN %d\n" , err); |
117 | return err; |
118 | } |
119 | } |
120 | |
121 | return 0; |
122 | } |
123 | |
124 | static int crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, |
125 | struct pwm_state *state) |
126 | { |
127 | struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); |
128 | struct device *dev = crc_pwm->chip.dev; |
129 | unsigned int clk_div, clk_div_reg, duty_cycle_reg; |
130 | int error; |
131 | |
132 | error = regmap_read(map: crc_pwm->regmap, PWM0_CLK_DIV, val: &clk_div_reg); |
133 | if (error) { |
134 | dev_err(dev, "Error reading PWM0_CLK_DIV %d\n" , error); |
135 | return error; |
136 | } |
137 | |
138 | error = regmap_read(map: crc_pwm->regmap, PWM0_DUTY_CYCLE, val: &duty_cycle_reg); |
139 | if (error) { |
140 | dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n" , error); |
141 | return error; |
142 | } |
143 | |
144 | clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; |
145 | |
146 | state->period = |
147 | DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ); |
148 | state->duty_cycle = |
149 | DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL); |
150 | state->polarity = PWM_POLARITY_NORMAL; |
151 | state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); |
152 | |
153 | return 0; |
154 | } |
155 | |
156 | static const struct pwm_ops crc_pwm_ops = { |
157 | .apply = crc_pwm_apply, |
158 | .get_state = crc_pwm_get_state, |
159 | }; |
160 | |
161 | static int crystalcove_pwm_probe(struct platform_device *pdev) |
162 | { |
163 | struct crystalcove_pwm *pwm; |
164 | struct device *dev = pdev->dev.parent; |
165 | struct intel_soc_pmic *pmic = dev_get_drvdata(dev); |
166 | |
167 | pwm = devm_kzalloc(dev: &pdev->dev, size: sizeof(*pwm), GFP_KERNEL); |
168 | if (!pwm) |
169 | return -ENOMEM; |
170 | |
171 | pwm->chip.dev = &pdev->dev; |
172 | pwm->chip.ops = &crc_pwm_ops; |
173 | pwm->chip.npwm = 1; |
174 | |
175 | /* get the PMIC regmap */ |
176 | pwm->regmap = pmic->regmap; |
177 | |
178 | return devm_pwmchip_add(dev: &pdev->dev, chip: &pwm->chip); |
179 | } |
180 | |
181 | static struct platform_driver crystalcove_pwm_driver = { |
182 | .probe = crystalcove_pwm_probe, |
183 | .driver = { |
184 | .name = "crystal_cove_pwm" , |
185 | }, |
186 | }; |
187 | |
188 | builtin_platform_driver(crystalcove_pwm_driver); |
189 | |