1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright 2018-2019 NXP. |
4 | * |
5 | * Limitations: |
6 | * - The TPM counter and period counter are shared between |
7 | * multiple channels, so all channels should use same period |
8 | * settings. |
9 | * - Changes to polarity cannot be latched at the time of the |
10 | * next period start. |
11 | * - Changing period and duty cycle together isn't atomic, |
12 | * with the wrong timing it might happen that a period is |
13 | * produced with old duty cycle but new period settings. |
14 | */ |
15 | |
16 | #include <linux/bitfield.h> |
17 | #include <linux/bitops.h> |
18 | #include <linux/clk.h> |
19 | #include <linux/err.h> |
20 | #include <linux/io.h> |
21 | #include <linux/module.h> |
22 | #include <linux/of.h> |
23 | #include <linux/platform_device.h> |
24 | #include <linux/pwm.h> |
25 | #include <linux/slab.h> |
26 | |
27 | #define PWM_IMX_TPM_PARAM 0x4 |
28 | #define PWM_IMX_TPM_GLOBAL 0x8 |
29 | #define PWM_IMX_TPM_SC 0x10 |
30 | #define PWM_IMX_TPM_CNT 0x14 |
31 | #define PWM_IMX_TPM_MOD 0x18 |
32 | #define PWM_IMX_TPM_CnSC(n) (0x20 + (n) * 0x8) |
33 | #define PWM_IMX_TPM_CnV(n) (0x24 + (n) * 0x8) |
34 | |
35 | #define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0) |
36 | |
37 | #define PWM_IMX_TPM_SC_PS GENMASK(2, 0) |
38 | #define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3) |
39 | #define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1) |
40 | #define PWM_IMX_TPM_SC_CPWMS BIT(5) |
41 | |
42 | #define PWM_IMX_TPM_CnSC_CHF BIT(7) |
43 | #define PWM_IMX_TPM_CnSC_MSB BIT(5) |
44 | #define PWM_IMX_TPM_CnSC_MSA BIT(4) |
45 | |
46 | /* |
47 | * The reference manual describes this field as two separate bits. The |
48 | * semantic of the two bits isn't orthogonal though, so they are treated |
49 | * together as a 2-bit field here. |
50 | */ |
51 | #define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2) |
52 | #define PWM_IMX_TPM_CnSC_ELS_INVERSED FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1) |
53 | #define PWM_IMX_TPM_CnSC_ELS_NORMAL FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2) |
54 | |
55 | |
56 | #define PWM_IMX_TPM_MOD_WIDTH 16 |
57 | #define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0) |
58 | |
59 | struct imx_tpm_pwm_chip { |
60 | struct clk *clk; |
61 | void __iomem *base; |
62 | struct mutex lock; |
63 | u32 user_count; |
64 | u32 enable_count; |
65 | u32 real_period; |
66 | }; |
67 | |
68 | struct imx_tpm_pwm_param { |
69 | u8 prescale; |
70 | u32 mod; |
71 | u32 val; |
72 | }; |
73 | |
74 | static inline struct imx_tpm_pwm_chip * |
75 | to_imx_tpm_pwm_chip(struct pwm_chip *chip) |
76 | { |
77 | return pwmchip_get_drvdata(chip); |
78 | } |
79 | |
80 | /* |
81 | * This function determines for a given pwm_state *state that a consumer |
82 | * might request the pwm_state *real_state that eventually is implemented |
83 | * by the hardware and the necessary register values (in *p) to achieve |
84 | * this. |
85 | */ |
86 | static int pwm_imx_tpm_round_state(struct pwm_chip *chip, |
87 | struct imx_tpm_pwm_param *p, |
88 | struct pwm_state *real_state, |
89 | const struct pwm_state *state) |
90 | { |
91 | struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); |
92 | u32 rate, prescale, period_count, clock_unit; |
93 | u64 tmp; |
94 | |
95 | rate = clk_get_rate(clk: tpm->clk); |
96 | tmp = (u64)state->period * rate; |
97 | clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); |
98 | if (clock_unit <= PWM_IMX_TPM_MOD_MOD) |
99 | prescale = 0; |
100 | else |
101 | prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH; |
102 | |
103 | if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale))) |
104 | return -ERANGE; |
105 | p->prescale = prescale; |
106 | |
107 | period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale; |
108 | p->mod = period_count; |
109 | |
110 | /* calculate real period HW can support */ |
111 | tmp = (u64)period_count << prescale; |
112 | tmp *= NSEC_PER_SEC; |
113 | real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); |
114 | |
115 | /* |
116 | * if eventually the PWM output is inactive, either |
117 | * duty cycle is 0 or status is disabled, need to |
118 | * make sure the output pin is inactive. |
119 | */ |
120 | if (!state->enabled) |
121 | real_state->duty_cycle = 0; |
122 | else |
123 | real_state->duty_cycle = state->duty_cycle; |
124 | |
125 | tmp = (u64)p->mod * real_state->duty_cycle; |
126 | p->val = DIV64_U64_ROUND_CLOSEST(tmp, real_state->period); |
127 | |
128 | real_state->polarity = state->polarity; |
129 | real_state->enabled = state->enabled; |
130 | |
131 | return 0; |
132 | } |
133 | |
134 | static int pwm_imx_tpm_get_state(struct pwm_chip *chip, |
135 | struct pwm_device *pwm, |
136 | struct pwm_state *state) |
137 | { |
138 | struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); |
139 | u32 rate, val, prescale; |
140 | u64 tmp; |
141 | |
142 | /* get period */ |
143 | state->period = tpm->real_period; |
144 | |
145 | /* get duty cycle */ |
146 | rate = clk_get_rate(clk: tpm->clk); |
147 | val = readl(addr: tpm->base + PWM_IMX_TPM_SC); |
148 | prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val); |
149 | tmp = readl(addr: tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); |
150 | tmp = (tmp << prescale) * NSEC_PER_SEC; |
151 | state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); |
152 | |
153 | /* get polarity */ |
154 | val = readl(addr: tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); |
155 | if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED) |
156 | state->polarity = PWM_POLARITY_INVERSED; |
157 | else |
158 | /* |
159 | * Assume reserved values (2b00 and 2b11) to yield |
160 | * normal polarity. |
161 | */ |
162 | state->polarity = PWM_POLARITY_NORMAL; |
163 | |
164 | /* get channel status */ |
165 | state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false; |
166 | |
167 | return 0; |
168 | } |
169 | |
170 | /* this function is supposed to be called with mutex hold */ |
171 | static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip, |
172 | struct imx_tpm_pwm_param *p, |
173 | struct pwm_state *state, |
174 | struct pwm_device *pwm) |
175 | { |
176 | struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); |
177 | bool period_update = false; |
178 | bool duty_update = false; |
179 | u32 val, cmod, cur_prescale; |
180 | unsigned long timeout; |
181 | struct pwm_state c; |
182 | |
183 | if (state->period != tpm->real_period) { |
184 | /* |
185 | * TPM counter is shared by multiple channels, so |
186 | * prescale and period can NOT be modified when |
187 | * there are multiple channels in use with different |
188 | * period settings. |
189 | */ |
190 | if (tpm->user_count > 1) |
191 | return -EBUSY; |
192 | |
193 | val = readl(addr: tpm->base + PWM_IMX_TPM_SC); |
194 | cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val); |
195 | cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val); |
196 | if (cmod && cur_prescale != p->prescale) |
197 | return -EBUSY; |
198 | |
199 | /* set TPM counter prescale */ |
200 | val &= ~PWM_IMX_TPM_SC_PS; |
201 | val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale); |
202 | writel(val, addr: tpm->base + PWM_IMX_TPM_SC); |
203 | |
204 | /* |
205 | * set period count: |
206 | * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register |
207 | * is updated when MOD register is written. |
208 | * |
209 | * if the PWM is enabled (CMOD[1:0] ≠2b00), the period length |
210 | * is latched into hardware when the next period starts. |
211 | */ |
212 | writel(val: p->mod, addr: tpm->base + PWM_IMX_TPM_MOD); |
213 | tpm->real_period = state->period; |
214 | period_update = true; |
215 | } |
216 | |
217 | pwm_imx_tpm_get_state(chip, pwm, state: &c); |
218 | |
219 | /* polarity is NOT allowed to be changed if PWM is active */ |
220 | if (c.enabled && c.polarity != state->polarity) |
221 | return -EBUSY; |
222 | |
223 | if (state->duty_cycle != c.duty_cycle) { |
224 | /* |
225 | * set channel value: |
226 | * if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register |
227 | * is updated when CnV register is written. |
228 | * |
229 | * if the PWM is enabled (CMOD[1:0] ≠2b00), the duty length |
230 | * is latched into hardware when the next period starts. |
231 | */ |
232 | writel(val: p->val, addr: tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); |
233 | duty_update = true; |
234 | } |
235 | |
236 | /* make sure MOD & CnV registers are updated */ |
237 | if (period_update || duty_update) { |
238 | timeout = jiffies + msecs_to_jiffies(m: tpm->real_period / |
239 | NSEC_PER_MSEC + 1); |
240 | while (readl(addr: tpm->base + PWM_IMX_TPM_MOD) != p->mod |
241 | || readl(addr: tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)) |
242 | != p->val) { |
243 | if (time_after(jiffies, timeout)) |
244 | return -ETIME; |
245 | cpu_relax(); |
246 | } |
247 | } |
248 | |
249 | /* |
250 | * polarity settings will enabled/disable output status |
251 | * immediately, so if the channel is disabled, need to |
252 | * make sure MSA/MSB/ELS are set to 0 which means channel |
253 | * disabled. |
254 | */ |
255 | val = readl(addr: tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); |
256 | val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA | |
257 | PWM_IMX_TPM_CnSC_MSB); |
258 | if (state->enabled) { |
259 | /* |
260 | * set polarity (for edge-aligned PWM modes) |
261 | * |
262 | * ELS[1:0] = 2b10 yields normal polarity behaviour, |
263 | * ELS[1:0] = 2b01 yields inversed polarity. |
264 | * The other values are reserved. |
265 | */ |
266 | val |= PWM_IMX_TPM_CnSC_MSB; |
267 | val |= (state->polarity == PWM_POLARITY_NORMAL) ? |
268 | PWM_IMX_TPM_CnSC_ELS_NORMAL : |
269 | PWM_IMX_TPM_CnSC_ELS_INVERSED; |
270 | } |
271 | writel(val, addr: tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); |
272 | |
273 | /* control the counter status */ |
274 | if (state->enabled != c.enabled) { |
275 | val = readl(addr: tpm->base + PWM_IMX_TPM_SC); |
276 | if (state->enabled) { |
277 | if (++tpm->enable_count == 1) |
278 | val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK; |
279 | } else { |
280 | if (--tpm->enable_count == 0) |
281 | val &= ~PWM_IMX_TPM_SC_CMOD; |
282 | } |
283 | writel(val, addr: tpm->base + PWM_IMX_TPM_SC); |
284 | } |
285 | |
286 | return 0; |
287 | } |
288 | |
289 | static int pwm_imx_tpm_apply(struct pwm_chip *chip, |
290 | struct pwm_device *pwm, |
291 | const struct pwm_state *state) |
292 | { |
293 | struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); |
294 | struct imx_tpm_pwm_param param; |
295 | struct pwm_state real_state; |
296 | int ret; |
297 | |
298 | ret = pwm_imx_tpm_round_state(chip, p: ¶m, real_state: &real_state, state); |
299 | if (ret) |
300 | return ret; |
301 | |
302 | mutex_lock(&tpm->lock); |
303 | ret = pwm_imx_tpm_apply_hw(chip, p: ¶m, state: &real_state, pwm); |
304 | mutex_unlock(lock: &tpm->lock); |
305 | |
306 | return ret; |
307 | } |
308 | |
309 | static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm) |
310 | { |
311 | struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); |
312 | |
313 | mutex_lock(&tpm->lock); |
314 | tpm->user_count++; |
315 | mutex_unlock(lock: &tpm->lock); |
316 | |
317 | return 0; |
318 | } |
319 | |
320 | static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
321 | { |
322 | struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); |
323 | |
324 | mutex_lock(&tpm->lock); |
325 | tpm->user_count--; |
326 | mutex_unlock(lock: &tpm->lock); |
327 | } |
328 | |
329 | static const struct pwm_ops imx_tpm_pwm_ops = { |
330 | .request = pwm_imx_tpm_request, |
331 | .free = pwm_imx_tpm_free, |
332 | .get_state = pwm_imx_tpm_get_state, |
333 | .apply = pwm_imx_tpm_apply, |
334 | }; |
335 | |
336 | static int pwm_imx_tpm_probe(struct platform_device *pdev) |
337 | { |
338 | struct pwm_chip *chip; |
339 | struct imx_tpm_pwm_chip *tpm; |
340 | struct clk *clk; |
341 | void __iomem *base; |
342 | int ret; |
343 | unsigned int npwm; |
344 | u32 val; |
345 | |
346 | base = devm_platform_ioremap_resource(pdev, index: 0); |
347 | if (IS_ERR(ptr: base)) |
348 | return PTR_ERR(ptr: base); |
349 | |
350 | clk = devm_clk_get_enabled(dev: &pdev->dev, NULL); |
351 | if (IS_ERR(ptr: clk)) |
352 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: clk), |
353 | fmt: "failed to get PWM clock\n" ); |
354 | |
355 | /* get number of channels */ |
356 | val = readl(addr: base + PWM_IMX_TPM_PARAM); |
357 | npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val); |
358 | |
359 | chip = devm_pwmchip_alloc(parent: &pdev->dev, npwm, sizeof_priv: sizeof(*tpm)); |
360 | if (IS_ERR(ptr: chip)) |
361 | return PTR_ERR(ptr: chip); |
362 | tpm = to_imx_tpm_pwm_chip(chip); |
363 | |
364 | platform_set_drvdata(pdev, data: tpm); |
365 | |
366 | tpm->base = base; |
367 | tpm->clk = clk; |
368 | |
369 | chip->ops = &imx_tpm_pwm_ops; |
370 | |
371 | mutex_init(&tpm->lock); |
372 | |
373 | ret = devm_pwmchip_add(&pdev->dev, chip); |
374 | if (ret) |
375 | return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "failed to add PWM chip\n" ); |
376 | |
377 | return 0; |
378 | } |
379 | |
380 | static int pwm_imx_tpm_suspend(struct device *dev) |
381 | { |
382 | struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev); |
383 | |
384 | if (tpm->enable_count > 0) |
385 | return -EBUSY; |
386 | |
387 | /* |
388 | * Force 'real_period' to be zero to force period update code |
389 | * can be executed after system resume back, since suspend causes |
390 | * the period related registers to become their reset values. |
391 | */ |
392 | tpm->real_period = 0; |
393 | |
394 | clk_disable_unprepare(clk: tpm->clk); |
395 | |
396 | return 0; |
397 | } |
398 | |
399 | static int pwm_imx_tpm_resume(struct device *dev) |
400 | { |
401 | struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev); |
402 | int ret = 0; |
403 | |
404 | ret = clk_prepare_enable(clk: tpm->clk); |
405 | if (ret) |
406 | dev_err(dev, "failed to prepare or enable clock: %d\n" , ret); |
407 | |
408 | return ret; |
409 | } |
410 | |
411 | static DEFINE_SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm, |
412 | pwm_imx_tpm_suspend, pwm_imx_tpm_resume); |
413 | |
414 | static const struct of_device_id imx_tpm_pwm_dt_ids[] = { |
415 | { .compatible = "fsl,imx7ulp-pwm" , }, |
416 | { /* sentinel */ } |
417 | }; |
418 | MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids); |
419 | |
420 | static struct platform_driver imx_tpm_pwm_driver = { |
421 | .driver = { |
422 | .name = "imx7ulp-tpm-pwm" , |
423 | .of_match_table = imx_tpm_pwm_dt_ids, |
424 | .pm = pm_ptr(&imx_tpm_pwm_pm), |
425 | }, |
426 | .probe = pwm_imx_tpm_probe, |
427 | }; |
428 | module_platform_driver(imx_tpm_pwm_driver); |
429 | |
430 | MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>" ); |
431 | MODULE_DESCRIPTION("i.MX TPM PWM Driver" ); |
432 | MODULE_LICENSE("GPL v2" ); |
433 | |