1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R-Car PWM Timer driver
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 *
7 * Limitations:
8 * - The hardware cannot generate a 0% duty cycle.
9 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/log2.h>
15#include <linux/math64.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/pwm.h>
21#include <linux/slab.h>
22
23#define RCAR_PWM_MAX_DIVISION 24
24#define RCAR_PWM_MAX_CYCLE 1023
25
26#define RCAR_PWMCR 0x00
27#define RCAR_PWMCR_CC0_MASK 0x000f0000
28#define RCAR_PWMCR_CC0_SHIFT 16
29#define RCAR_PWMCR_CCMD BIT(15)
30#define RCAR_PWMCR_SYNC BIT(11)
31#define RCAR_PWMCR_SS0 BIT(4)
32#define RCAR_PWMCR_EN0 BIT(0)
33
34#define RCAR_PWMCNT 0x04
35#define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
36#define RCAR_PWMCNT_CYC0_SHIFT 16
37#define RCAR_PWMCNT_PH0_MASK 0x000003ff
38#define RCAR_PWMCNT_PH0_SHIFT 0
39
40struct rcar_pwm_chip {
41 void __iomem *base;
42 struct clk *clk;
43};
44
45static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
46{
47 return pwmchip_get_drvdata(chip);
48}
49
50static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
51 unsigned int offset)
52{
53 writel(val: data, addr: rp->base + offset);
54}
55
56static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
57{
58 return readl(addr: rp->base + offset);
59}
60
61static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
62 unsigned int offset)
63{
64 u32 value;
65
66 value = rcar_pwm_read(rp, offset);
67 value &= ~mask;
68 value |= data & mask;
69 rcar_pwm_write(rp, data: value, offset);
70}
71
72static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
73{
74 unsigned long clk_rate = clk_get_rate(clk: rp->clk);
75 u64 div, tmp;
76
77 if (clk_rate == 0)
78 return -EINVAL;
79
80 div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
81 tmp = (u64)period_ns * clk_rate + div - 1;
82 tmp = div64_u64(dividend: tmp, divisor: div);
83 div = ilog2(tmp - 1) + 1;
84
85 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
86}
87
88static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
89 unsigned int div)
90{
91 u32 value;
92
93 value = rcar_pwm_read(rp, RCAR_PWMCR);
94 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
95
96 if (div & 1)
97 value |= RCAR_PWMCR_CCMD;
98
99 div >>= 1;
100
101 value |= div << RCAR_PWMCR_CC0_SHIFT;
102 rcar_pwm_write(rp, data: value, RCAR_PWMCR);
103}
104
105static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
106 int period_ns)
107{
108 unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */
109 unsigned long clk_rate = clk_get_rate(clk: rp->clk);
110 u32 cyc, ph;
111
112 one_cycle = NSEC_PER_SEC * 100ULL << div;
113 do_div(one_cycle, clk_rate);
114
115 tmp = period_ns * 100ULL;
116 do_div(tmp, one_cycle);
117 cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
118
119 tmp = duty_ns * 100ULL;
120 do_div(tmp, one_cycle);
121 ph = tmp & RCAR_PWMCNT_PH0_MASK;
122
123 /* Avoid prohibited setting */
124 if (cyc == 0 || ph == 0)
125 return -EINVAL;
126
127 rcar_pwm_write(rp, data: cyc | ph, RCAR_PWMCNT);
128
129 return 0;
130}
131
132static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
133{
134 return pm_runtime_get_sync(dev: pwmchip_parent(chip));
135}
136
137static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
138{
139 pm_runtime_put(dev: pwmchip_parent(chip));
140}
141
142static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
143{
144 u32 value;
145
146 /* Don't enable the PWM device if CYC0 or PH0 is 0 */
147 value = rcar_pwm_read(rp, RCAR_PWMCNT);
148 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
149 (value & RCAR_PWMCNT_PH0_MASK) == 0)
150 return -EINVAL;
151
152 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
153
154 return 0;
155}
156
157static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
158{
159 rcar_pwm_update(rp, RCAR_PWMCR_EN0, data: 0, RCAR_PWMCR);
160}
161
162static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
163 const struct pwm_state *state)
164{
165 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
166 int div, ret;
167
168 /* This HW/driver only supports normal polarity */
169 if (state->polarity != PWM_POLARITY_NORMAL)
170 return -EINVAL;
171
172 if (!state->enabled) {
173 rcar_pwm_disable(rp);
174 return 0;
175 }
176
177 div = rcar_pwm_get_clock_division(rp, period_ns: state->period);
178 if (div < 0)
179 return div;
180
181 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
182
183 ret = rcar_pwm_set_counter(rp, div, duty_ns: state->duty_cycle, period_ns: state->period);
184 if (!ret)
185 rcar_pwm_set_clock_control(rp, div);
186
187 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
188 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, data: 0, RCAR_PWMCR);
189
190 if (!ret)
191 ret = rcar_pwm_enable(rp);
192
193 return ret;
194}
195
196static const struct pwm_ops rcar_pwm_ops = {
197 .request = rcar_pwm_request,
198 .free = rcar_pwm_free,
199 .apply = rcar_pwm_apply,
200};
201
202static int rcar_pwm_probe(struct platform_device *pdev)
203{
204 struct pwm_chip *chip;
205 struct rcar_pwm_chip *rcar_pwm;
206 int ret;
207
208 chip = devm_pwmchip_alloc(parent: &pdev->dev, npwm: 1, sizeof_priv: sizeof(*rcar_pwm));
209 if (IS_ERR(ptr: chip))
210 return PTR_ERR(ptr: chip);
211 rcar_pwm = to_rcar_pwm_chip(chip);
212
213 rcar_pwm->base = devm_platform_ioremap_resource(pdev, index: 0);
214 if (IS_ERR(ptr: rcar_pwm->base))
215 return PTR_ERR(ptr: rcar_pwm->base);
216
217 rcar_pwm->clk = devm_clk_get(dev: &pdev->dev, NULL);
218 if (IS_ERR(ptr: rcar_pwm->clk)) {
219 dev_err(&pdev->dev, "cannot get clock\n");
220 return PTR_ERR(ptr: rcar_pwm->clk);
221 }
222
223 chip->ops = &rcar_pwm_ops;
224
225 platform_set_drvdata(pdev, data: chip);
226
227 pm_runtime_enable(dev: &pdev->dev);
228
229 ret = pwmchip_add(chip);
230 if (ret < 0) {
231 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
232 pm_runtime_disable(dev: &pdev->dev);
233 return ret;
234 }
235
236 return 0;
237}
238
239static void rcar_pwm_remove(struct platform_device *pdev)
240{
241 struct pwm_chip *chip = platform_get_drvdata(pdev);
242
243 pwmchip_remove(chip);
244
245 pm_runtime_disable(dev: &pdev->dev);
246}
247
248static const struct of_device_id rcar_pwm_of_table[] = {
249 { .compatible = "renesas,pwm-rcar", },
250 { },
251};
252MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
253
254static struct platform_driver rcar_pwm_driver = {
255 .probe = rcar_pwm_probe,
256 .remove_new = rcar_pwm_remove,
257 .driver = {
258 .name = "pwm-rcar",
259 .of_match_table = rcar_pwm_of_table,
260 }
261};
262module_platform_driver(rcar_pwm_driver);
263
264MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
265MODULE_DESCRIPTION("Renesas PWM Timer Driver");
266MODULE_LICENSE("GPL v2");
267MODULE_ALIAS("platform:pwm-rcar");
268

source code of linux/drivers/pwm/pwm-rcar.c