| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * DA9121 Single-channel dual-phase 10A buck converter |
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| 4 | * DA9130 Single-channel dual-phase 10A buck converter (Automotive) |
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| 5 | * DA9217 Single-channel dual-phase 6A buck converter |
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| 6 | * DA9122 Dual-channel single-phase 5A buck converter |
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| 7 | * DA9131 Dual-channel single-phase 5A buck converter (Automotive) |
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| 8 | * DA9220 Dual-channel single-phase 3A buck converter |
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| 9 | * DA9132 Dual-channel single-phase 3A buck converter (Automotive) |
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| 10 | * |
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| 11 | * Copyright (C) 2020 Dialog Semiconductor |
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| 12 | * |
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| 13 | * Authors: Steve Twiss, Dialog Semiconductor |
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| 14 | * Adam Ward, Dialog Semiconductor |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef __DA9121_REGISTERS_H__ |
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| 18 | #define __DA9121_REGISTERS_H__ |
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| 19 | |
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| 20 | /* Values for: DA9121_REG_BUCK_BUCKx_4 registers, fields CHx_y_MODE |
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| 21 | * DA9121_REG_BUCK_BUCKx_7 registers, fields CHx_RIPPLE_CANCEL |
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| 22 | */ |
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| 23 | #include <dt-bindings/regulator/dlg,da9121-regulator.h> |
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| 24 | |
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| 25 | enum da9121_variant { |
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| 26 | DA9121_TYPE_DA9121_DA9130, |
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| 27 | DA9121_TYPE_DA9220_DA9132, |
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| 28 | DA9121_TYPE_DA9122_DA9131, |
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| 29 | DA9121_TYPE_DA9217, |
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| 30 | DA9121_TYPE_DA9141, |
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| 31 | DA9121_TYPE_DA9142 |
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| 32 | }; |
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| 33 | |
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| 34 | enum da9121_subvariant { |
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| 35 | DA9121_SUBTYPE_DA9121, |
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| 36 | DA9121_SUBTYPE_DA9130, |
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| 37 | DA9121_SUBTYPE_DA9220, |
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| 38 | DA9121_SUBTYPE_DA9132, |
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| 39 | DA9121_SUBTYPE_DA9122, |
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| 40 | DA9121_SUBTYPE_DA9131, |
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| 41 | DA9121_SUBTYPE_DA9217, |
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| 42 | DA9121_SUBTYPE_DA9141, |
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| 43 | DA9121_SUBTYPE_DA9142 |
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| 44 | }; |
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| 45 | |
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| 46 | /* Minimum, maximum and default polling millisecond periods are provided |
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| 47 | * here as an example. It is expected that any final implementation will |
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| 48 | * include a modification of these settings to match the required |
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| 49 | * application. |
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| 50 | */ |
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| 51 | #define DA9121_DEFAULT_POLLING_PERIOD_MS 3000 |
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| 52 | #define DA9121_MAX_POLLING_PERIOD_MS 10000 |
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| 53 | #define DA9121_MIN_POLLING_PERIOD_MS 1000 |
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| 54 | |
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| 55 | /* Registers */ |
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| 56 | |
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| 57 | #define DA9121_REG_SYS_STATUS_0 0x01 |
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| 58 | #define DA9121_REG_SYS_STATUS_1 0x02 |
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| 59 | #define DA9121_REG_SYS_STATUS_2 0x03 |
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| 60 | #define DA9121_REG_SYS_EVENT_0 0x04 |
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| 61 | #define DA9121_REG_SYS_EVENT_1 0x05 |
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| 62 | #define DA9121_REG_SYS_EVENT_2 0x06 |
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| 63 | #define DA9121_REG_SYS_MASK_0 0x07 |
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| 64 | #define DA9121_REG_SYS_MASK_1 0x08 |
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| 65 | #define DA9121_REG_SYS_MASK_2 0x09 |
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| 66 | #define DA9121_REG_SYS_MASK_3 0x0A |
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| 67 | #define DA9121_REG_SYS_CONFIG_0 0x0B |
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| 68 | #define DA9121_REG_SYS_CONFIG_1 0x0C |
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| 69 | #define DA9121_REG_SYS_CONFIG_2 0x0D |
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| 70 | #define DA9121_REG_SYS_CONFIG_3 0x0E |
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| 71 | #define DA9121_REG_SYS_GPIO0_0 0x10 |
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| 72 | #define DA9121_REG_SYS_GPIO0_1 0x11 |
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| 73 | #define DA9121_REG_SYS_GPIO1_0 0x12 |
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| 74 | #define DA9121_REG_SYS_GPIO1_1 0x13 |
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| 75 | #define DA9121_REG_SYS_GPIO2_0 0x14 |
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| 76 | #define DA9121_REG_SYS_GPIO2_1 0x15 |
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| 77 | #define DA914x_REG_SYS_GPIO3_0 0x16 |
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| 78 | #define DA914x_REG_SYS_GPIO3_1 0x17 |
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| 79 | #define DA914x_REG_SYS_GPIO4_0 0x18 |
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| 80 | #define DA914x_REG_SYS_GPIO4_1 0x19 |
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| 81 | #define DA914x_REG_SYS_ADMUX1_0 0x1A |
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| 82 | #define DA914x_REG_SYS_ADMUX1_1 0x1B |
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| 83 | #define DA914x_REG_SYS_ADMUX2_0 0x1C |
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| 84 | #define DA914x_REG_SYS_ADMUX2_1 0x1D |
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| 85 | #define DA9121_REG_BUCK_BUCK1_0 0x20 |
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| 86 | #define DA9121_REG_BUCK_BUCK1_1 0x21 |
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| 87 | #define DA9121_REG_BUCK_BUCK1_2 0x22 |
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| 88 | #define DA9121_REG_BUCK_BUCK1_3 0x23 |
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| 89 | #define DA9121_REG_BUCK_BUCK1_4 0x24 |
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| 90 | #define DA9121_REG_BUCK_BUCK1_5 0x25 |
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| 91 | #define DA9121_REG_BUCK_BUCK1_6 0x26 |
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| 92 | #define DA9121_REG_BUCK_BUCK1_7 0x27 |
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| 93 | #define DA9xxx_REG_BUCK_BUCK2_0 0x28 |
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| 94 | #define DA9xxx_REG_BUCK_BUCK2_1 0x29 |
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| 95 | #define DA9xxx_REG_BUCK_BUCK2_2 0x2A |
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| 96 | #define DA9xxx_REG_BUCK_BUCK2_3 0x2B |
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| 97 | #define DA9xxx_REG_BUCK_BUCK2_4 0x2C |
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| 98 | #define DA9xxx_REG_BUCK_BUCK2_5 0x2D |
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| 99 | #define DA9xxx_REG_BUCK_BUCK2_6 0x2E |
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| 100 | #define DA9xxx_REG_BUCK_BUCK2_7 0x2F |
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| 101 | #define DA9121_REG_OTP_DEVICE_ID 0x48 |
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| 102 | #define DA9121_REG_OTP_VARIANT_ID 0x49 |
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| 103 | #define DA9121_REG_OTP_CUSTOMER_ID 0x4A |
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| 104 | #define DA9121_REG_OTP_CONFIG_ID 0x4B |
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| 105 | |
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| 106 | /* Register bits */ |
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| 107 | |
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| 108 | /* DA9121_REG_SYS_STATUS_0 */ |
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| 109 | |
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| 110 | #define DA9xxx_MASK_SYS_STATUS_0_SG BIT(2) |
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| 111 | #define DA9121_MASK_SYS_STATUS_0_TEMP_CRIT BIT(1) |
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| 112 | #define DA9121_MASK_SYS_STATUS_0_TEMP_WARN BIT(0) |
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| 113 | |
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| 114 | /* DA9121_REG_SYS_STATUS_1 */ |
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| 115 | |
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| 116 | #define DA9xxx_MASK_SYS_STATUS_1_PG2 BIT(7) |
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| 117 | #define DA9xxx_MASK_SYS_STATUS_1_OV2 BIT(6) |
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| 118 | #define DA9xxx_MASK_SYS_STATUS_1_UV2 BIT(5) |
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| 119 | #define DA9xxx_MASK_SYS_STATUS_1_OC2 BIT(4) |
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| 120 | #define DA9121_MASK_SYS_STATUS_1_PG1 BIT(3) |
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| 121 | #define DA9121_MASK_SYS_STATUS_1_OV1 BIT(2) |
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| 122 | #define DA9121_MASK_SYS_STATUS_1_UV1 BIT(1) |
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| 123 | #define DA9121_MASK_SYS_STATUS_1_OC1 BIT(0) |
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| 124 | |
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| 125 | /* DA9121_REG_SYS_STATUS_2 */ |
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| 126 | |
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| 127 | #define DA9121_MASK_SYS_STATUS_2_GPIO2 BIT(2) |
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| 128 | #define DA9121_MASK_SYS_STATUS_2_GPIO1 BIT(1) |
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| 129 | #define DA9121_MASK_SYS_STATUS_2_GPIO0 BIT(0) |
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| 130 | |
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| 131 | /* DA9121_REG_SYS_EVENT_0 */ |
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| 132 | |
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| 133 | #define DA9xxx_MASK_SYS_EVENT_0_E_SG BIT(2) |
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| 134 | #define DA9121_MASK_SYS_EVENT_0_E_TEMP_CRIT BIT(1) |
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| 135 | #define DA9121_MASK_SYS_EVENT_0_E_TEMP_WARN BIT(0) |
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| 136 | |
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| 137 | /* DA9121_REG_SYS_EVENT_1 */ |
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| 138 | |
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| 139 | #define DA9xxx_MASK_SYS_EVENT_1_E_PG2 BIT(7) |
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| 140 | #define DA9xxx_MASK_SYS_EVENT_1_E_OV2 BIT(6) |
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| 141 | #define DA9xxx_MASK_SYS_EVENT_1_E_UV2 BIT(5) |
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| 142 | #define DA9xxx_MASK_SYS_EVENT_1_E_OC2 BIT(4) |
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| 143 | #define DA9121_MASK_SYS_EVENT_1_E_PG1 BIT(3) |
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| 144 | #define DA9121_MASK_SYS_EVENT_1_E_OV1 BIT(2) |
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| 145 | #define DA9121_MASK_SYS_EVENT_1_E_UV1 BIT(1) |
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| 146 | #define DA9121_MASK_SYS_EVENT_1_E_OC1 BIT(0) |
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| 147 | |
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| 148 | /* DA9121_REG_SYS_EVENT_2 */ |
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| 149 | |
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| 150 | #define DA9121_MASK_SYS_EVENT_2_E_GPIO2 BIT(2) |
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| 151 | #define DA9121_MASK_SYS_EVENT_2_E_GPIO1 BIT(1) |
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| 152 | #define DA9121_MASK_SYS_EVENT_2_E_GPIO0 BIT(0) |
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| 153 | |
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| 154 | /* DA9121_REG_SYS_MASK_0 */ |
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| 155 | |
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| 156 | #define DA9xxx_MASK_SYS_MASK_0_M_SG BIT(2) |
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| 157 | #define DA9121_MASK_SYS_MASK_0_M_TEMP_CRIT BIT(1) |
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| 158 | #define DA9121_MASK_SYS_MASK_0_M_TEMP_WARN BIT(0) |
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| 159 | |
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| 160 | /* DA9121_REG_SYS_MASK_1 */ |
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| 161 | |
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| 162 | #define DA9xxx_MASK_SYS_MASK_1_M_PG2 BIT(7) |
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| 163 | #define DA9xxx_MASK_SYS_MASK_1_M_OV2 BIT(6) |
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| 164 | #define DA9xxx_MASK_SYS_MASK_1_M_UV2 BIT(5) |
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| 165 | #define DA9xxx_MASK_SYS_MASK_1_M_OC2 BIT(4) |
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| 166 | #define DA9121_MASK_SYS_MASK_1_M_PG1 BIT(3) |
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| 167 | #define DA9121_MASK_SYS_MASK_1_M_OV1 BIT(2) |
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| 168 | #define DA9121_MASK_SYS_MASK_1_M_UV1 BIT(1) |
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| 169 | #define DA9121_MASK_SYS_MASK_1_M_OC1 BIT(0) |
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| 170 | |
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| 171 | /* DA9121_REG_SYS_MASK_2 */ |
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| 172 | |
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| 173 | #define DA9121_MASK_SYS_MASK_2_M_GPIO2 BIT(2) |
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| 174 | #define DA9121_MASK_SYS_MASK_2_M_GPIO1 BIT(1) |
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| 175 | #define DA9121_MASK_SYS_MASK_2_M_GPIO0 BIT(0) |
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| 176 | |
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| 177 | /* DA9122_REG_SYS_MASK_3 */ |
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| 178 | |
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| 179 | #define DA9121_MASK_SYS_MASK_3_M_VR_HOT BIT(3) |
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| 180 | #define DA9xxx_MASK_SYS_MASK_3_M_SG_STAT BIT(2) |
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| 181 | #define DA9xxx_MASK_SYS_MASK_3_M_PG2_STAT BIT(1) |
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| 182 | #define DA9121_MASK_SYS_MASK_3_M_PG1_STAT BIT(0) |
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| 183 | |
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| 184 | /* DA9121_REG_SYS_CONFIG_0 */ |
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| 185 | |
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| 186 | #define DA9121_MASK_SYS_CONFIG_0_CH1_DIS_DLY 0xF0 |
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| 187 | #define DA9121_MASK_SYS_CONFIG_0_CH1_EN_DLY 0x0F |
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| 188 | |
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| 189 | /* DA9xxx_REG_SYS_CONFIG_1 */ |
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| 190 | |
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| 191 | #define DA9xxx_MASK_SYS_CONFIG_1_CH2_DIS_DLY 0xF0 |
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| 192 | #define DA9xxx_MASK_SYS_CONFIG_1_CH2_EN_DLY 0x0F |
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| 193 | |
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| 194 | /* DA9121_REG_SYS_CONFIG_2 */ |
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| 195 | |
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| 196 | #define DA9121_MASK_SYS_CONFIG_2_OC_LATCHOFF 0x60 |
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| 197 | #define DA9121_MASK_SYS_CONFIG_2_OC_DVC_MASK BIT(4) |
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| 198 | #define DA9121_MASK_SYS_CONFIG_2_PG_DVC_MASK 0x0C |
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| 199 | |
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| 200 | /* DA9121_REG_SYS_CONFIG_3 */ |
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| 201 | |
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| 202 | #define DA9121_MASK_SYS_CONFIG_3_OSC_TUNE 0X70 |
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| 203 | #define DA9121_MASK_SYS_CONFIG_3_I2C_TIMEOUT BIT(1) |
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| 204 | |
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| 205 | /* DA9121_REG_SYS_GPIO0_0 */ |
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| 206 | |
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| 207 | #define DA9121_MASK_SYS_GPIO0_0_GPIO0_MODE 0X1E |
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| 208 | #define DA9121_MASK_SYS_GPIO0_0_GPIO0_OBUF BIT(0) |
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| 209 | |
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| 210 | /* DA9121_REG_SYS_GPIO0_1 */ |
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| 211 | |
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| 212 | #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_FALL BIT(7) |
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| 213 | #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_RISE BIT(6) |
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| 214 | #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB 0x30 |
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| 215 | #define DA9121_MASK_SYS_GPIO0_1_GPIO0_PUPD BIT(3) |
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| 216 | #define DA9121_MASK_SYS_GPIO0_1_GPIO0_POL BIT(2) |
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| 217 | #define DA9121_MASK_SYS_GPIO0_1_GPIO0_TRIG 0x03 |
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| 218 | |
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| 219 | /* DA9121_REG_SYS_GPIO1_0 */ |
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| 220 | |
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| 221 | #define DA9121_MASK_SYS_GPIO1_0_GPIO1_MODE 0x1E |
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| 222 | #define DA9121_MASK_SYS_GPIO1_0_GPIO1_OBUF BIT(0) |
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| 223 | |
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| 224 | /* DA9121_REG_SYS_GPIO1_1 */ |
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| 225 | |
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| 226 | #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_FALL BIT(7) |
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| 227 | #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_RISE BIT(6) |
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| 228 | #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB 0x30 |
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| 229 | #define DA9121_MASK_SYS_GPIO1_1_GPIO1_PUPD BIT(3) |
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| 230 | #define DA9121_MASK_SYS_GPIO1_1_GPIO1_POL BIT(2) |
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| 231 | #define DA9121_MASK_SYS_GPIO1_1_GPIO1_TRIG 0x03 |
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| 232 | |
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| 233 | /* DA9121_REG_SYS_GPIO2_0 */ |
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| 234 | |
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| 235 | #define DA9121_MASK_SYS_GPIO2_0_GPIO2_MODE 0x1E |
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| 236 | #define DA9121_MASK_SYS_GPIO2_0_GPIO2_OBUF BIT(0) |
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| 237 | |
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| 238 | /* DA9121_REG_SYS_GPIO2_1 */ |
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| 239 | |
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| 240 | #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_FALL BIT(7) |
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| 241 | #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_RISE BIT(6) |
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| 242 | #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB 0x30 |
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| 243 | #define DA9121_MASK_SYS_GPIO2_1_GPIO2_PUPD BIT(3) |
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| 244 | #define DA9121_MASK_SYS_GPIO2_1_GPIO2_POL BIT(2) |
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| 245 | #define DA9121_MASK_SYS_GPIO2_1_GPIO2_TRIG 0x03 |
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| 246 | |
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| 247 | /* DA9121_REG_BUCK_BUCK1_0 / DA9xxx_REG_BUCK_BUCK2_0 */ |
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| 248 | |
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| 249 | #define DA9121_MASK_BUCK_BUCKx_0_CHx_SR_DVC_DWN 0x70 |
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| 250 | #define DA9121_MASK_BUCK_BUCKx_0_CHx_SR_DVC_UP 0x0E |
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| 251 | #define DA9121_MASK_BUCK_BUCKx_0_CHx_EN BIT(0) |
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| 252 | |
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| 253 | /* DA9121_REG_BUCK_BUCK1_1 / DA9xxx_REG_BUCK_BUCK2_1 */ |
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| 254 | |
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| 255 | #define DA9121_MASK_BUCK_BUCKx_1_CHx_SR_SHDN 0x70 |
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| 256 | #define DA9121_MASK_BUCK_BUCKx_1_CHx_SR_STARTUP 0x0E |
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| 257 | #define DA9121_MASK_BUCK_BUCKx_1_CHx_PD_DIS BIT(0) |
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| 258 | |
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| 259 | /* DA9121_REG_BUCK_BUCK1_2 / DA9xxx_REG_BUCK_BUCK2_2 */ |
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| 260 | |
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| 261 | #define DA9121_MASK_BUCK_BUCKx_2_CHx_ILIM 0x0F |
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| 262 | |
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| 263 | /* DA9121_REG_BUCK_BUCK1_3 / DA9xxx_REG_BUCK_BUCK2_3 */ |
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| 264 | |
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| 265 | #define DA9121_MASK_BUCK_BUCKx_3_CHx_VMAX 0xFF |
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| 266 | |
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| 267 | /* DA9121_REG_BUCK_BUCK1_4 / DA9xxx_REG_BUCK_BUCK2_4 */ |
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| 268 | |
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| 269 | #define DA9121_MASK_BUCK_BUCKx_4_CHx_VSEL BIT(4) |
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| 270 | #define DA9121_MASK_BUCK_BUCKx_4_CHx_B_MODE 0x0C |
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| 271 | #define DA9121_MASK_BUCK_BUCKx_4_CHx_A_MODE 0x03 |
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| 272 | |
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| 273 | /* DA9121_REG_BUCK_BUCK1_5 / DA9xxx_REG_BUCK_BUCK2_5 */ |
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| 274 | |
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| 275 | #define DA9121_MASK_BUCK_BUCKx_5_CHx_A_VOUT 0xFF |
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| 276 | |
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| 277 | /* DA9121_REG_BUCK_BUCK1_6 / DA9xxx_REG_BUCK_BUCK2_6 */ |
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| 278 | |
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| 279 | #define DA9121_MASK_BUCK_BUCKx_6_CHx_B_VOUT 0xFF |
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| 280 | |
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| 281 | /* DA9121_REG_BUCK_BUCK1_7 / DA9xxx_REG_BUCK_BUCK2_7 */ |
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| 282 | |
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| 283 | #define DA9xxx_MASK_BUCK_BUCKx_7_CHx_RIPPLE_CANCEL 0x03 |
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| 284 | |
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| 285 | |
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| 286 | /* DA9121_REG_OTP_DEVICE_ID */ |
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| 287 | |
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| 288 | #define DA9121_MASK_OTP_DEVICE_ID_DEV_ID 0xFF |
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| 289 | |
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| 290 | #define DA9121_DEVICE_ID 0x05 |
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| 291 | #define DA914x_DEVICE_ID 0x26 |
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| 292 | |
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| 293 | /* DA9121_REG_OTP_VARIANT_ID */ |
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| 294 | |
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| 295 | #define DA9121_SHIFT_OTP_VARIANT_ID_MRC 4 |
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| 296 | #define DA9121_MASK_OTP_VARIANT_ID_MRC 0xF0 |
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| 297 | #define DA9121_SHIFT_OTP_VARIANT_ID_VRC 0 |
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| 298 | #define DA9121_MASK_OTP_VARIANT_ID_VRC 0x0F |
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| 299 | |
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| 300 | #define DA9121_VARIANT_MRC_BASE 0x2 |
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| 301 | #define DA9121_VARIANT_VRC 0x1 |
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| 302 | #define DA9220_VARIANT_VRC 0x0 |
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| 303 | #define DA9122_VARIANT_VRC 0x2 |
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| 304 | #define DA9217_VARIANT_VRC 0x7 |
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| 305 | #define DA9130_VARIANT_VRC 0x0 |
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| 306 | #define DA9131_VARIANT_VRC 0x1 |
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| 307 | #define DA9132_VARIANT_VRC 0x2 |
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| 308 | |
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| 309 | #define DA914x_VARIANT_MRC_BASE 0x0 |
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| 310 | #define DA9141_VARIANT_VRC 0x1 |
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| 311 | #define DA9142_VARIANT_VRC 0x2 |
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| 312 | |
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| 313 | /* DA9121_REG_OTP_CUSTOMER_ID */ |
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| 314 | |
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| 315 | #define DA9121_MASK_OTP_CUSTOMER_ID_CUST_ID 0xFF |
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| 316 | |
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| 317 | /* DA9121_REG_OTP_CONFIG_ID */ |
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| 318 | |
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| 319 | #define DA9121_MASK_OTP_CONFIG_ID_CONFIG_REV 0xFF |
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| 320 | |
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| 321 | #endif /* __DA9121_REGISTERS_H__ */ |
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| 322 | |
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