1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Delta TN48M CPLD reset driver |
4 | * |
5 | * Copyright (C) 2021 Sartura Ltd. |
6 | * |
7 | * Author: Robert Marko <robert.marko@sartura.hr> |
8 | */ |
9 | |
10 | #include <linux/device.h> |
11 | #include <linux/kernel.h> |
12 | #include <linux/mod_devicetable.h> |
13 | #include <linux/module.h> |
14 | #include <linux/platform_device.h> |
15 | #include <linux/regmap.h> |
16 | #include <linux/reset-controller.h> |
17 | |
18 | #include <dt-bindings/reset/delta,tn48m-reset.h> |
19 | |
20 | #define TN48M_RESET_REG 0x10 |
21 | |
22 | #define TN48M_RESET_TIMEOUT_US 125000 |
23 | #define TN48M_RESET_SLEEP_US 10 |
24 | |
25 | struct tn48_reset_map { |
26 | u8 bit; |
27 | }; |
28 | |
29 | struct tn48_reset_data { |
30 | struct reset_controller_dev rcdev; |
31 | struct regmap *regmap; |
32 | }; |
33 | |
34 | static const struct tn48_reset_map tn48m_resets[] = { |
35 | [CPU_88F7040_RESET] = {0}, |
36 | [CPU_88F6820_RESET] = {1}, |
37 | [MAC_98DX3265_RESET] = {2}, |
38 | [PHY_88E1680_RESET] = {4}, |
39 | [PHY_88E1512_RESET] = {6}, |
40 | [POE_RESET] = {7}, |
41 | }; |
42 | |
43 | static inline struct tn48_reset_data *to_tn48_reset_data( |
44 | struct reset_controller_dev *rcdev) |
45 | { |
46 | return container_of(rcdev, struct tn48_reset_data, rcdev); |
47 | } |
48 | |
49 | static int tn48m_control_reset(struct reset_controller_dev *rcdev, |
50 | unsigned long id) |
51 | { |
52 | struct tn48_reset_data *data = to_tn48_reset_data(rcdev); |
53 | unsigned int val; |
54 | |
55 | regmap_update_bits(map: data->regmap, TN48M_RESET_REG, |
56 | BIT(tn48m_resets[id].bit), val: 0); |
57 | |
58 | return regmap_read_poll_timeout(data->regmap, |
59 | TN48M_RESET_REG, |
60 | val, |
61 | val & BIT(tn48m_resets[id].bit), |
62 | TN48M_RESET_SLEEP_US, |
63 | TN48M_RESET_TIMEOUT_US); |
64 | } |
65 | |
66 | static int tn48m_control_status(struct reset_controller_dev *rcdev, |
67 | unsigned long id) |
68 | { |
69 | struct tn48_reset_data *data = to_tn48_reset_data(rcdev); |
70 | unsigned int regval; |
71 | int ret; |
72 | |
73 | ret = regmap_read(map: data->regmap, TN48M_RESET_REG, val: ®val); |
74 | if (ret < 0) |
75 | return ret; |
76 | |
77 | if (BIT(tn48m_resets[id].bit) & regval) |
78 | return 0; |
79 | else |
80 | return 1; |
81 | } |
82 | |
83 | static const struct reset_control_ops tn48_reset_ops = { |
84 | .reset = tn48m_control_reset, |
85 | .status = tn48m_control_status, |
86 | }; |
87 | |
88 | static int tn48m_reset_probe(struct platform_device *pdev) |
89 | { |
90 | struct tn48_reset_data *data; |
91 | struct regmap *regmap; |
92 | |
93 | regmap = dev_get_regmap(dev: pdev->dev.parent, NULL); |
94 | if (!regmap) |
95 | return -ENODEV; |
96 | |
97 | data = devm_kzalloc(dev: &pdev->dev, size: sizeof(*data), GFP_KERNEL); |
98 | if (!data) |
99 | return -ENOMEM; |
100 | |
101 | data->regmap = regmap; |
102 | |
103 | data->rcdev.owner = THIS_MODULE; |
104 | data->rcdev.ops = &tn48_reset_ops; |
105 | data->rcdev.nr_resets = ARRAY_SIZE(tn48m_resets); |
106 | data->rcdev.of_node = pdev->dev.of_node; |
107 | |
108 | return devm_reset_controller_register(dev: &pdev->dev, rcdev: &data->rcdev); |
109 | } |
110 | |
111 | static const struct of_device_id tn48m_reset_of_match[] = { |
112 | { .compatible = "delta,tn48m-reset" }, |
113 | { } |
114 | }; |
115 | MODULE_DEVICE_TABLE(of, tn48m_reset_of_match); |
116 | |
117 | static struct platform_driver tn48m_reset_driver = { |
118 | .driver = { |
119 | .name = "delta-tn48m-reset" , |
120 | .of_match_table = tn48m_reset_of_match, |
121 | }, |
122 | .probe = tn48m_reset_probe, |
123 | }; |
124 | module_platform_driver(tn48m_reset_driver); |
125 | |
126 | MODULE_AUTHOR("Robert Marko <robert.marko@sartura.hr>" ); |
127 | MODULE_DESCRIPTION("Delta TN48M CPLD reset driver" ); |
128 | MODULE_LICENSE("GPL" ); |
129 | |