| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> |
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| 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
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| 5 | * |
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| 6 | * S3C2410 Internal RTC register definition |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __ASM_ARCH_REGS_RTC_H |
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| 10 | #define __ASM_ARCH_REGS_RTC_H __FILE__ |
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| 11 | |
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| 12 | #define S3C2410_RTCREG(x) (x) |
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| 13 | #define S3C2410_INTP S3C2410_RTCREG(0x30) |
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| 14 | #define S3C2410_INTP_ALM (1 << 1) |
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| 15 | #define S3C2410_INTP_TIC (1 << 0) |
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| 16 | |
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| 17 | #define S3C2410_RTCCON S3C2410_RTCREG(0x40) |
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| 18 | #define S3C2410_RTCCON_RTCEN (1 << 0) |
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| 19 | #define S3C2410_RTCCON_CNTSEL (1 << 2) |
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| 20 | #define S3C2410_RTCCON_CLKRST (1 << 3) |
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| 21 | #define S3C2443_RTCCON_TICSEL (1 << 4) |
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| 22 | #define S3C64XX_RTCCON_TICEN (1 << 8) |
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| 23 | |
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| 24 | #define S3C2410_TICNT S3C2410_RTCREG(0x44) |
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| 25 | #define S3C2410_TICNT_ENABLE (1 << 7) |
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| 26 | |
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| 27 | /* S3C2443: tick count is 15 bit wide |
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| 28 | * TICNT[6:0] contains upper 7 bits |
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| 29 | * TICNT1[7:0] contains lower 8 bits |
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| 30 | */ |
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| 31 | #define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8) |
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| 32 | #define S3C2443_TICNT1 S3C2410_RTCREG(0x4C) |
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| 33 | #define S3C2443_TICNT1_PART(x) (x & 0xff) |
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| 34 | |
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| 35 | /* S3C2416: tick count is 32 bit wide |
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| 36 | * TICNT[6:0] contains bits [14:8] |
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| 37 | * TICNT1[7:0] contains lower 8 bits |
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| 38 | * TICNT2[16:0] contains upper 17 bits |
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| 39 | */ |
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| 40 | #define S3C2416_TICNT2 S3C2410_RTCREG(0x48) |
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| 41 | #define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15) |
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| 42 | |
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| 43 | #define S3C2410_RTCALM S3C2410_RTCREG(0x50) |
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| 44 | #define S3C2410_RTCALM_ALMEN (1 << 6) |
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| 45 | #define S3C2410_RTCALM_YEAREN (1 << 5) |
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| 46 | #define S3C2410_RTCALM_MONEN (1 << 4) |
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| 47 | #define S3C2410_RTCALM_DAYEN (1 << 3) |
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| 48 | #define S3C2410_RTCALM_HOUREN (1 << 2) |
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| 49 | #define S3C2410_RTCALM_MINEN (1 << 1) |
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| 50 | #define S3C2410_RTCALM_SECEN (1 << 0) |
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| 51 | |
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| 52 | #define S3C2410_ALMSEC S3C2410_RTCREG(0x54) |
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| 53 | #define S3C2410_ALMMIN S3C2410_RTCREG(0x58) |
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| 54 | #define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) |
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| 55 | |
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| 56 | #define S3C2410_ALMDATE S3C2410_RTCREG(0x60) |
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| 57 | #define S3C2410_ALMMON S3C2410_RTCREG(0x64) |
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| 58 | #define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) |
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| 59 | |
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| 60 | #define S3C2410_RTCSEC S3C2410_RTCREG(0x70) |
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| 61 | #define S3C2410_RTCMIN S3C2410_RTCREG(0x74) |
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| 62 | #define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) |
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| 63 | #define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) |
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| 64 | #define S3C2410_RTCMON S3C2410_RTCREG(0x84) |
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| 65 | #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) |
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| 66 | |
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| 67 | #endif /* __ASM_ARCH_REGS_RTC_H */ |
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| 68 | |
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