1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. |
4 | * Copyright (c) 2014- QLogic Corporation. |
5 | * All rights reserved |
6 | * www.qlogic.com |
7 | * |
8 | * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter. |
9 | */ |
10 | |
11 | #ifndef __BFI_H__ |
12 | #define __BFI_H__ |
13 | |
14 | #include "bfa_defs.h" |
15 | #include "bfa_defs_svc.h" |
16 | |
17 | #pragma pack(1) |
18 | |
19 | /* Per dma segment max size */ |
20 | #define BFI_MEM_DMA_SEG_SZ (131072) |
21 | |
22 | /* Get number of dma segments required */ |
23 | #define BFI_MEM_DMA_NSEGS(_num_reqs, _req_sz) \ |
24 | ((u16)(((((_num_reqs) * (_req_sz)) + BFI_MEM_DMA_SEG_SZ - 1) & \ |
25 | ~(BFI_MEM_DMA_SEG_SZ - 1)) / BFI_MEM_DMA_SEG_SZ)) |
26 | |
27 | /* Get num dma reqs - that fit in a segment */ |
28 | #define BFI_MEM_NREQS_SEG(_rqsz) (BFI_MEM_DMA_SEG_SZ / (_rqsz)) |
29 | |
30 | /* Get segment num from tag */ |
31 | #define BFI_MEM_SEG_FROM_TAG(_tag, _rqsz) ((_tag) / BFI_MEM_NREQS_SEG(_rqsz)) |
32 | |
33 | /* Get dma req offset in a segment */ |
34 | #define BFI_MEM_SEG_REQ_OFFSET(_tag, _sz) \ |
35 | ((_tag) - (BFI_MEM_SEG_FROM_TAG(_tag, _sz) * BFI_MEM_NREQS_SEG(_sz))) |
36 | |
37 | /* |
38 | * BFI FW image type |
39 | */ |
40 | #define BFI_FLASH_CHUNK_SZ 256 /* Flash chunk size */ |
41 | #define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32)) |
42 | #define BFI_FLASH_IMAGE_SZ 0x100000 |
43 | |
44 | /* |
45 | * Msg header common to all msgs |
46 | */ |
47 | struct bfi_mhdr_s { |
48 | u8 msg_class; /* @ref bfi_mclass_t */ |
49 | u8 msg_id; /* msg opcode with in the class */ |
50 | union { |
51 | struct { |
52 | u8 qid; |
53 | u8 fn_lpu; /* msg destination */ |
54 | } h2i; |
55 | u16 i2htok; /* token in msgs to host */ |
56 | } mtag; |
57 | }; |
58 | |
59 | #define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu)) |
60 | #define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1) |
61 | |
62 | #define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do { \ |
63 | (_mh).msg_class = (_mc); \ |
64 | (_mh).msg_id = (_op); \ |
65 | (_mh).mtag.h2i.fn_lpu = (_fn_lpu); \ |
66 | } while (0) |
67 | |
68 | #define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \ |
69 | (_mh).msg_class = (_mc); \ |
70 | (_mh).msg_id = (_op); \ |
71 | (_mh).mtag.i2htok = (_i2htok); \ |
72 | } while (0) |
73 | |
74 | /* |
75 | * Message opcodes: 0-127 to firmware, 128-255 to host |
76 | */ |
77 | #define BFI_I2H_OPCODE_BASE 128 |
78 | #define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE) |
79 | |
80 | /* |
81 | **************************************************************************** |
82 | * |
83 | * Scatter Gather Element and Page definition |
84 | * |
85 | **************************************************************************** |
86 | */ |
87 | |
88 | #define BFI_SGE_INLINE 1 |
89 | #define BFI_SGE_INLINE_MAX (BFI_SGE_INLINE + 1) |
90 | |
91 | /* |
92 | * SG Flags |
93 | */ |
94 | enum { |
95 | BFI_SGE_DATA = 0, /* data address, not last */ |
96 | BFI_SGE_DATA_CPL = 1, /* data addr, last in current page */ |
97 | BFI_SGE_DATA_LAST = 3, /* data address, last */ |
98 | BFI_SGE_LINK = 2, /* link address */ |
99 | BFI_SGE_PGDLEN = 2, /* cumulative data length for page */ |
100 | }; |
101 | |
102 | /* |
103 | * DMA addresses |
104 | */ |
105 | union bfi_addr_u { |
106 | struct { |
107 | __be32 addr_lo; |
108 | __be32 addr_hi; |
109 | } a32; |
110 | }; |
111 | |
112 | /* |
113 | * Scatter Gather Element used for fast-path IO requests |
114 | */ |
115 | struct bfi_sge_s { |
116 | #ifdef __BIG_ENDIAN |
117 | u32 flags:2, |
118 | rsvd:2, |
119 | sg_len:28; |
120 | #else |
121 | u32 sg_len:28, |
122 | rsvd:2, |
123 | flags:2; |
124 | #endif |
125 | union bfi_addr_u sga; |
126 | }; |
127 | |
128 | /** |
129 | * Generic DMA addr-len pair. |
130 | */ |
131 | struct bfi_alen_s { |
132 | union bfi_addr_u al_addr; /* DMA addr of buffer */ |
133 | u32 al_len; /* length of buffer */ |
134 | }; |
135 | |
136 | /* |
137 | * Scatter Gather Page |
138 | */ |
139 | #define BFI_SGPG_DATA_SGES 7 |
140 | #define BFI_SGPG_SGES_MAX (BFI_SGPG_DATA_SGES + 1) |
141 | #define BFI_SGPG_RSVD_WD_LEN 8 |
142 | struct bfi_sgpg_s { |
143 | struct bfi_sge_s sges[BFI_SGPG_SGES_MAX]; |
144 | u32 rsvd[BFI_SGPG_RSVD_WD_LEN]; |
145 | }; |
146 | |
147 | /* FCP module definitions */ |
148 | #define BFI_IO_MAX (2000) |
149 | #define BFI_IOIM_SNSLEN (256) |
150 | #define BFI_IOIM_SNSBUF_SEGS \ |
151 | BFI_MEM_DMA_NSEGS(BFI_IO_MAX, BFI_IOIM_SNSLEN) |
152 | |
153 | /* |
154 | * Large Message structure - 128 Bytes size Msgs |
155 | */ |
156 | #define BFI_LMSG_SZ 128 |
157 | #define BFI_LMSG_PL_WSZ \ |
158 | ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr_s)) / 4) |
159 | |
160 | struct bfi_msg_s { |
161 | struct bfi_mhdr_s mhdr; |
162 | u32 pl[BFI_LMSG_PL_WSZ]; |
163 | }; |
164 | |
165 | /* |
166 | * Mailbox message structure |
167 | */ |
168 | #define BFI_MBMSG_SZ 7 |
169 | struct bfi_mbmsg_s { |
170 | struct bfi_mhdr_s mh; |
171 | u32 pl[BFI_MBMSG_SZ]; |
172 | }; |
173 | |
174 | /* |
175 | * Supported PCI function class codes (personality) |
176 | */ |
177 | enum bfi_pcifn_class { |
178 | BFI_PCIFN_CLASS_FC = 0x0c04, |
179 | BFI_PCIFN_CLASS_ETH = 0x0200, |
180 | }; |
181 | |
182 | /* |
183 | * Message Classes |
184 | */ |
185 | enum bfi_mclass { |
186 | BFI_MC_IOC = 1, /* IO Controller (IOC) */ |
187 | BFI_MC_DIAG = 2, /* Diagnostic Msgs */ |
188 | BFI_MC_FLASH = 3, /* Flash message class */ |
189 | BFI_MC_CEE = 4, /* CEE */ |
190 | BFI_MC_FCPORT = 5, /* FC port */ |
191 | BFI_MC_IOCFC = 6, /* FC - IO Controller (IOC) */ |
192 | BFI_MC_ABLK = 7, /* ASIC block configuration */ |
193 | BFI_MC_UF = 8, /* Unsolicited frame receive */ |
194 | BFI_MC_FCXP = 9, /* FC Transport */ |
195 | BFI_MC_LPS = 10, /* lport fc login services */ |
196 | BFI_MC_RPORT = 11, /* Remote port */ |
197 | BFI_MC_ITN = 12, /* I-T nexus (Initiator mode) */ |
198 | BFI_MC_IOIM_READ = 13, /* read IO (Initiator mode) */ |
199 | BFI_MC_IOIM_WRITE = 14, /* write IO (Initiator mode) */ |
200 | BFI_MC_IOIM_IO = 15, /* IO (Initiator mode) */ |
201 | BFI_MC_IOIM = 16, /* IO (Initiator mode) */ |
202 | BFI_MC_IOIM_IOCOM = 17, /* good IO completion */ |
203 | BFI_MC_TSKIM = 18, /* Initiator Task management */ |
204 | BFI_MC_PORT = 21, /* Physical port */ |
205 | BFI_MC_SFP = 22, /* SFP module */ |
206 | BFI_MC_PHY = 25, /* External PHY message class */ |
207 | BFI_MC_FRU = 34, |
208 | BFI_MC_MAX = 35 |
209 | }; |
210 | |
211 | #define BFI_IOC_MAX_CQS 4 |
212 | #define BFI_IOC_MAX_CQS_ASIC 8 |
213 | #define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */ |
214 | |
215 | /* |
216 | *---------------------------------------------------------------------- |
217 | * IOC |
218 | *---------------------------------------------------------------------- |
219 | */ |
220 | |
221 | /* |
222 | * Different asic generations |
223 | */ |
224 | enum bfi_asic_gen { |
225 | BFI_ASIC_GEN_CB = 1, /* crossbow 8G FC */ |
226 | BFI_ASIC_GEN_CT = 2, /* catapult 8G FC or 10G CNA */ |
227 | BFI_ASIC_GEN_CT2 = 3, /* catapult-2 16G FC or 10G CNA */ |
228 | }; |
229 | |
230 | enum bfi_asic_mode { |
231 | BFI_ASIC_MODE_FC = 1, /* FC upto 8G speed */ |
232 | BFI_ASIC_MODE_FC16 = 2, /* FC upto 16G speed */ |
233 | BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */ |
234 | BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */ |
235 | }; |
236 | |
237 | enum bfi_ioc_h2i_msgs { |
238 | BFI_IOC_H2I_ENABLE_REQ = 1, |
239 | BFI_IOC_H2I_DISABLE_REQ = 2, |
240 | BFI_IOC_H2I_GETATTR_REQ = 3, |
241 | BFI_IOC_H2I_DBG_SYNC = 4, |
242 | BFI_IOC_H2I_DBG_DUMP = 5, |
243 | }; |
244 | |
245 | enum bfi_ioc_i2h_msgs { |
246 | BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1), |
247 | BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2), |
248 | BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3), |
249 | BFI_IOC_I2H_HBEAT = BFA_I2HM(4), |
250 | BFI_IOC_I2H_ACQ_ADDR_REPLY = BFA_I2HM(5), |
251 | }; |
252 | |
253 | /* |
254 | * BFI_IOC_H2I_GETATTR_REQ message |
255 | */ |
256 | struct bfi_ioc_getattr_req_s { |
257 | struct bfi_mhdr_s mh; |
258 | union bfi_addr_u attr_addr; |
259 | }; |
260 | |
261 | #define BFI_IOC_ATTR_UUID_SZ 16 |
262 | struct bfi_ioc_attr_s { |
263 | wwn_t mfg_pwwn; /* Mfg port wwn */ |
264 | wwn_t mfg_nwwn; /* Mfg node wwn */ |
265 | mac_t mfg_mac; /* Mfg mac */ |
266 | u8 port_mode; /* bfi_port_mode */ |
267 | u8 rsvd_a; |
268 | wwn_t pwwn; |
269 | wwn_t nwwn; |
270 | mac_t mac; /* PBC or Mfg mac */ |
271 | u16 rsvd_b; |
272 | mac_t fcoe_mac; |
273 | u16 rsvd_c; |
274 | char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)]; |
275 | u8 pcie_gen; |
276 | u8 pcie_lanes_orig; |
277 | u8 pcie_lanes; |
278 | u8 rx_bbcredit; /* receive buffer credits */ |
279 | u32 adapter_prop; /* adapter properties */ |
280 | u16 maxfrsize; /* max receive frame size */ |
281 | char asic_rev; |
282 | u8 rsvd_d; |
283 | char fw_version[BFA_VERSION_LEN]; |
284 | char optrom_version[BFA_VERSION_LEN]; |
285 | struct bfa_mfg_vpd_s vpd; |
286 | u32 card_type; /* card type */ |
287 | u8 mfg_day; /* manufacturing day */ |
288 | u8 mfg_month; /* manufacturing month */ |
289 | u16 mfg_year; /* manufacturing year */ |
290 | u8 uuid[BFI_IOC_ATTR_UUID_SZ]; /*!< chinook uuid */ |
291 | }; |
292 | |
293 | /* |
294 | * BFI_IOC_I2H_GETATTR_REPLY message |
295 | */ |
296 | struct bfi_ioc_getattr_reply_s { |
297 | struct bfi_mhdr_s mh; /* Common msg header */ |
298 | u8 status; /* cfg reply status */ |
299 | u8 rsvd[3]; |
300 | }; |
301 | |
302 | /* |
303 | * Firmware memory page offsets |
304 | */ |
305 | #define BFI_IOC_SMEM_PG0_CB (0x40) |
306 | #define BFI_IOC_SMEM_PG0_CT (0x180) |
307 | |
308 | /* |
309 | * Firmware statistic offset |
310 | */ |
311 | #define BFI_IOC_FWSTATS_OFF (0x6B40) |
312 | #define BFI_IOC_FWSTATS_SZ (4096) |
313 | |
314 | /* |
315 | * Firmware trace offset |
316 | */ |
317 | #define BFI_IOC_TRC_OFF (0x4b00) |
318 | #define BFI_IOC_TRC_ENTS 256 |
319 | |
320 | #define BFI_IOC_FW_SIGNATURE (0xbfadbfad) |
321 | #define BFA_IOC_FW_INV_SIGN (0xdeaddead) |
322 | #define BFI_IOC_MD5SUM_SZ 4 |
323 | |
324 | struct bfi_ioc_fwver_s { |
325 | #ifdef __BIG_ENDIAN |
326 | uint8_t patch; |
327 | uint8_t maint; |
328 | uint8_t minor; |
329 | uint8_t major; |
330 | uint8_t rsvd[2]; |
331 | uint8_t build; |
332 | uint8_t phase; |
333 | #else |
334 | uint8_t major; |
335 | uint8_t minor; |
336 | uint8_t maint; |
337 | uint8_t patch; |
338 | uint8_t phase; |
339 | uint8_t build; |
340 | uint8_t rsvd[2]; |
341 | #endif |
342 | }; |
343 | |
344 | struct bfi_ioc_image_hdr_s { |
345 | u32 signature; /* constant signature */ |
346 | u8 asic_gen; /* asic generation */ |
347 | u8 asic_mode; |
348 | u8 port0_mode; /* device mode for port 0 */ |
349 | u8 port1_mode; /* device mode for port 1 */ |
350 | u32 exec; /* exec vector */ |
351 | u32 bootenv; /* firmware boot env */ |
352 | u32 rsvd_b[2]; |
353 | struct bfi_ioc_fwver_s fwver; |
354 | u32 md5sum[BFI_IOC_MD5SUM_SZ]; |
355 | }; |
356 | |
357 | enum bfi_ioc_img_ver_cmp_e { |
358 | BFI_IOC_IMG_VER_INCOMP, |
359 | BFI_IOC_IMG_VER_OLD, |
360 | BFI_IOC_IMG_VER_SAME, |
361 | BFI_IOC_IMG_VER_BETTER |
362 | }; |
363 | |
364 | #define BFI_FWBOOT_DEVMODE_OFF 4 |
365 | #define BFI_FWBOOT_TYPE_OFF 8 |
366 | #define BFI_FWBOOT_ENV_OFF 12 |
367 | #define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \ |
368 | (((u32)(__asic_gen)) << 24 | \ |
369 | ((u32)(__asic_mode)) << 16 | \ |
370 | ((u32)(__p0_mode)) << 8 | \ |
371 | ((u32)(__p1_mode))) |
372 | |
373 | enum bfi_fwboot_type { |
374 | BFI_FWBOOT_TYPE_NORMAL = 0, |
375 | BFI_FWBOOT_TYPE_FLASH = 1, |
376 | BFI_FWBOOT_TYPE_MEMTEST = 2, |
377 | }; |
378 | |
379 | #define BFI_FWBOOT_TYPE_NORMAL 0 |
380 | #define BFI_FWBOOT_TYPE_MEMTEST 2 |
381 | #define BFI_FWBOOT_ENV_OS 0 |
382 | |
383 | enum bfi_port_mode { |
384 | BFI_PORT_MODE_FC = 1, |
385 | BFI_PORT_MODE_ETH = 2, |
386 | }; |
387 | |
388 | struct bfi_ioc_hbeat_s { |
389 | struct bfi_mhdr_s mh; /* common msg header */ |
390 | u32 hb_count; /* current heart beat count */ |
391 | }; |
392 | |
393 | /* |
394 | * IOC hardware/firmware state |
395 | */ |
396 | enum bfi_ioc_state { |
397 | BFI_IOC_UNINIT = 0, /* not initialized */ |
398 | BFI_IOC_INITING = 1, /* h/w is being initialized */ |
399 | BFI_IOC_HWINIT = 2, /* h/w is initialized */ |
400 | BFI_IOC_CFG = 3, /* IOC configuration in progress */ |
401 | BFI_IOC_OP = 4, /* IOC is operational */ |
402 | BFI_IOC_DISABLING = 5, /* IOC is being disabled */ |
403 | BFI_IOC_DISABLED = 6, /* IOC is disabled */ |
404 | BFI_IOC_CFG_DISABLED = 7, /* IOC is being disabled;transient */ |
405 | BFI_IOC_FAIL = 8, /* IOC heart-beat failure */ |
406 | BFI_IOC_MEMTEST = 9, /* IOC is doing memtest */ |
407 | }; |
408 | |
409 | #define BFA_IOC_CB_JOIN_SH 16 |
410 | #define BFA_IOC_CB_FWSTATE_MASK 0x0000ffff |
411 | #define BFA_IOC_CB_JOIN_MASK 0xffff0000 |
412 | |
413 | #define BFI_IOC_ENDIAN_SIG 0x12345678 |
414 | |
415 | enum { |
416 | BFI_ADAPTER_TYPE_FC = 0x01, /* FC adapters */ |
417 | BFI_ADAPTER_TYPE_MK = 0x0f0000, /* adapter type mask */ |
418 | BFI_ADAPTER_TYPE_SH = 16, /* adapter type shift */ |
419 | BFI_ADAPTER_NPORTS_MK = 0xff00, /* number of ports mask */ |
420 | BFI_ADAPTER_NPORTS_SH = 8, /* number of ports shift */ |
421 | BFI_ADAPTER_SPEED_MK = 0xff, /* adapter speed mask */ |
422 | BFI_ADAPTER_SPEED_SH = 0, /* adapter speed shift */ |
423 | BFI_ADAPTER_PROTO = 0x100000, /* prototype adapaters */ |
424 | BFI_ADAPTER_TTV = 0x200000, /* TTV debug capable */ |
425 | BFI_ADAPTER_UNSUPP = 0x400000, /* unknown adapter type */ |
426 | }; |
427 | |
428 | #define BFI_ADAPTER_GETP(__prop, __adap_prop) \ |
429 | (((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \ |
430 | BFI_ADAPTER_ ## __prop ## _SH) |
431 | #define BFI_ADAPTER_SETP(__prop, __val) \ |
432 | ((__val) << BFI_ADAPTER_ ## __prop ## _SH) |
433 | #define BFI_ADAPTER_IS_PROTO(__adap_type) \ |
434 | ((__adap_type) & BFI_ADAPTER_PROTO) |
435 | #define BFI_ADAPTER_IS_TTV(__adap_type) \ |
436 | ((__adap_type) & BFI_ADAPTER_TTV) |
437 | #define BFI_ADAPTER_IS_UNSUPP(__adap_type) \ |
438 | ((__adap_type) & BFI_ADAPTER_UNSUPP) |
439 | #define BFI_ADAPTER_IS_SPECIAL(__adap_type) \ |
440 | ((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \ |
441 | BFI_ADAPTER_UNSUPP)) |
442 | |
443 | /* |
444 | * BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages |
445 | */ |
446 | struct bfi_ioc_ctrl_req_s { |
447 | struct bfi_mhdr_s mh; |
448 | u16 clscode; |
449 | u16 rsvd; |
450 | u32 tv_sec; |
451 | }; |
452 | #define bfi_ioc_enable_req_t struct bfi_ioc_ctrl_req_s; |
453 | #define bfi_ioc_disable_req_t struct bfi_ioc_ctrl_req_s; |
454 | |
455 | /* |
456 | * BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages |
457 | */ |
458 | struct bfi_ioc_ctrl_reply_s { |
459 | struct bfi_mhdr_s mh; /* Common msg header */ |
460 | u8 status; /* enable/disable status */ |
461 | u8 port_mode; /* bfa_mode_s */ |
462 | u8 cap_bm; /* capability bit mask */ |
463 | u8 rsvd; |
464 | }; |
465 | #define bfi_ioc_enable_reply_t struct bfi_ioc_ctrl_reply_s; |
466 | #define bfi_ioc_disable_reply_t struct bfi_ioc_ctrl_reply_s; |
467 | |
468 | #define BFI_IOC_MSGSZ 8 |
469 | /* |
470 | * H2I Messages |
471 | */ |
472 | union bfi_ioc_h2i_msg_u { |
473 | struct bfi_mhdr_s mh; |
474 | struct bfi_ioc_ctrl_req_s enable_req; |
475 | struct bfi_ioc_ctrl_req_s disable_req; |
476 | struct bfi_ioc_getattr_req_s getattr_req; |
477 | u32 mboxmsg[BFI_IOC_MSGSZ]; |
478 | }; |
479 | |
480 | /* |
481 | * I2H Messages |
482 | */ |
483 | union bfi_ioc_i2h_msg_u { |
484 | struct bfi_mhdr_s mh; |
485 | struct bfi_ioc_ctrl_reply_s fw_event; |
486 | u32 mboxmsg[BFI_IOC_MSGSZ]; |
487 | }; |
488 | |
489 | |
490 | /* |
491 | *---------------------------------------------------------------------- |
492 | * PBC |
493 | *---------------------------------------------------------------------- |
494 | */ |
495 | |
496 | #define BFI_PBC_MAX_BLUNS 8 |
497 | #define BFI_PBC_MAX_VPORTS 16 |
498 | #define BFI_PBC_PORT_DISABLED 2 |
499 | |
500 | /* |
501 | * PBC boot lun configuration |
502 | */ |
503 | struct bfi_pbc_blun_s { |
504 | wwn_t tgt_pwwn; |
505 | struct scsi_lun tgt_lun; |
506 | }; |
507 | |
508 | /* |
509 | * PBC virtual port configuration |
510 | */ |
511 | struct bfi_pbc_vport_s { |
512 | wwn_t vp_pwwn; |
513 | wwn_t vp_nwwn; |
514 | }; |
515 | |
516 | /* |
517 | * BFI pre-boot configuration information |
518 | */ |
519 | struct bfi_pbc_s { |
520 | u8 port_enabled; |
521 | u8 boot_enabled; |
522 | u8 nbluns; |
523 | u8 nvports; |
524 | u8 port_speed; |
525 | u8 rsvd_a; |
526 | u16 hss; |
527 | wwn_t pbc_pwwn; |
528 | wwn_t pbc_nwwn; |
529 | struct bfi_pbc_blun_s blun[BFI_PBC_MAX_BLUNS]; |
530 | struct bfi_pbc_vport_s vport[BFI_PBC_MAX_VPORTS]; |
531 | }; |
532 | |
533 | /* |
534 | *---------------------------------------------------------------------- |
535 | * MSGQ |
536 | *---------------------------------------------------------------------- |
537 | */ |
538 | #define BFI_MSGQ_FULL(_q) (((_q->pi + 1) % _q->q_depth) == _q->ci) |
539 | #define BFI_MSGQ_EMPTY(_q) (_q->pi == _q->ci) |
540 | #define BFI_MSGQ_UPDATE_CI(_q) (_q->ci = (_q->ci + 1) % _q->q_depth) |
541 | #define BFI_MSGQ_UPDATE_PI(_q) (_q->pi = (_q->pi + 1) % _q->q_depth) |
542 | |
543 | /* q_depth must be power of 2 */ |
544 | #define BFI_MSGQ_FREE_CNT(_q) ((_q->ci - _q->pi - 1) & (_q->q_depth - 1)) |
545 | |
546 | enum bfi_msgq_h2i_msgs_e { |
547 | BFI_MSGQ_H2I_INIT_REQ = 1, |
548 | BFI_MSGQ_H2I_DOORBELL = 2, |
549 | BFI_MSGQ_H2I_SHUTDOWN = 3, |
550 | }; |
551 | |
552 | enum bfi_msgq_i2h_msgs_e { |
553 | BFI_MSGQ_I2H_INIT_RSP = 1, |
554 | BFI_MSGQ_I2H_DOORBELL = 2, |
555 | }; |
556 | |
557 | |
558 | /* Messages(commands/responsed/AENS will have the following header */ |
559 | struct bfi_msgq_mhdr_s { |
560 | u8 msg_class; |
561 | u8 msg_id; |
562 | u16 msg_token; |
563 | u16 num_entries; |
564 | u8 enet_id; |
565 | u8 rsvd[1]; |
566 | }; |
567 | |
568 | #define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \ |
569 | (_mh).msg_class = (_mc); \ |
570 | (_mh).msg_id = (_mid); \ |
571 | (_mh).msg_token = (_tok); \ |
572 | (_mh).enet_id = (_enet_id); \ |
573 | } while (0) |
574 | |
575 | /* |
576 | * Mailbox for messaging interface |
577 | * |
578 | */ |
579 | #define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */ |
580 | #define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */ |
581 | #define BFI_MSGQ_MSG_SIZE_MAX (2048) /* TBD */ |
582 | |
583 | struct bfi_msgq_s { |
584 | union bfi_addr_u addr; |
585 | u16 q_depth; /* Total num of entries in the queue */ |
586 | u8 rsvd[2]; |
587 | }; |
588 | |
589 | /* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */ |
590 | struct bfi_msgq_cfg_req_s { |
591 | struct bfi_mhdr_s mh; |
592 | struct bfi_msgq_s cmdq; |
593 | struct bfi_msgq_s rspq; |
594 | }; |
595 | |
596 | /* BFI_ENET_MSGQ_CFG_RSP */ |
597 | struct bfi_msgq_cfg_rsp_s { |
598 | struct bfi_mhdr_s mh; |
599 | u8 cmd_status; |
600 | u8 rsvd[3]; |
601 | }; |
602 | |
603 | |
604 | /* BFI_MSGQ_H2I_DOORBELL */ |
605 | struct bfi_msgq_h2i_db_s { |
606 | struct bfi_mhdr_s mh; |
607 | u16 cmdq_pi; |
608 | u16 rspq_ci; |
609 | }; |
610 | |
611 | /* BFI_MSGQ_I2H_DOORBELL */ |
612 | struct bfi_msgq_i2h_db_s { |
613 | struct bfi_mhdr_s mh; |
614 | u16 rspq_pi; |
615 | u16 cmdq_ci; |
616 | }; |
617 | |
618 | #pragma pack() |
619 | |
620 | /* BFI port specific */ |
621 | #pragma pack(1) |
622 | |
623 | enum bfi_port_h2i { |
624 | BFI_PORT_H2I_ENABLE_REQ = (1), |
625 | BFI_PORT_H2I_DISABLE_REQ = (2), |
626 | BFI_PORT_H2I_GET_STATS_REQ = (3), |
627 | BFI_PORT_H2I_CLEAR_STATS_REQ = (4), |
628 | }; |
629 | |
630 | enum bfi_port_i2h { |
631 | BFI_PORT_I2H_ENABLE_RSP = BFA_I2HM(1), |
632 | BFI_PORT_I2H_DISABLE_RSP = BFA_I2HM(2), |
633 | BFI_PORT_I2H_GET_STATS_RSP = BFA_I2HM(3), |
634 | BFI_PORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(4), |
635 | }; |
636 | |
637 | /* |
638 | * Generic REQ type |
639 | */ |
640 | struct bfi_port_generic_req_s { |
641 | struct bfi_mhdr_s mh; /* msg header */ |
642 | u32 msgtag; /* msgtag for reply */ |
643 | u32 rsvd; |
644 | }; |
645 | |
646 | /* |
647 | * Generic RSP type |
648 | */ |
649 | struct bfi_port_generic_rsp_s { |
650 | struct bfi_mhdr_s mh; /* common msg header */ |
651 | u8 status; /* port enable status */ |
652 | u8 rsvd[3]; |
653 | u32 msgtag; /* msgtag for reply */ |
654 | }; |
655 | |
656 | /* |
657 | * BFI_PORT_H2I_GET_STATS_REQ |
658 | */ |
659 | struct bfi_port_get_stats_req_s { |
660 | struct bfi_mhdr_s mh; /* common msg header */ |
661 | union bfi_addr_u dma_addr; |
662 | }; |
663 | |
664 | union bfi_port_h2i_msg_u { |
665 | struct bfi_mhdr_s mh; |
666 | struct bfi_port_generic_req_s enable_req; |
667 | struct bfi_port_generic_req_s disable_req; |
668 | struct bfi_port_get_stats_req_s getstats_req; |
669 | struct bfi_port_generic_req_s clearstats_req; |
670 | }; |
671 | |
672 | union bfi_port_i2h_msg_u { |
673 | struct bfi_mhdr_s mh; |
674 | struct bfi_port_generic_rsp_s enable_rsp; |
675 | struct bfi_port_generic_rsp_s disable_rsp; |
676 | struct bfi_port_generic_rsp_s getstats_rsp; |
677 | struct bfi_port_generic_rsp_s clearstats_rsp; |
678 | }; |
679 | |
680 | /* |
681 | *---------------------------------------------------------------------- |
682 | * ABLK |
683 | *---------------------------------------------------------------------- |
684 | */ |
685 | enum bfi_ablk_h2i_msgs_e { |
686 | BFI_ABLK_H2I_QUERY = 1, |
687 | BFI_ABLK_H2I_ADPT_CONFIG = 2, |
688 | BFI_ABLK_H2I_PORT_CONFIG = 3, |
689 | BFI_ABLK_H2I_PF_CREATE = 4, |
690 | BFI_ABLK_H2I_PF_DELETE = 5, |
691 | BFI_ABLK_H2I_PF_UPDATE = 6, |
692 | BFI_ABLK_H2I_OPTROM_ENABLE = 7, |
693 | BFI_ABLK_H2I_OPTROM_DISABLE = 8, |
694 | }; |
695 | |
696 | enum bfi_ablk_i2h_msgs_e { |
697 | BFI_ABLK_I2H_QUERY = BFA_I2HM(BFI_ABLK_H2I_QUERY), |
698 | BFI_ABLK_I2H_ADPT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_ADPT_CONFIG), |
699 | BFI_ABLK_I2H_PORT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_PORT_CONFIG), |
700 | BFI_ABLK_I2H_PF_CREATE = BFA_I2HM(BFI_ABLK_H2I_PF_CREATE), |
701 | BFI_ABLK_I2H_PF_DELETE = BFA_I2HM(BFI_ABLK_H2I_PF_DELETE), |
702 | BFI_ABLK_I2H_PF_UPDATE = BFA_I2HM(BFI_ABLK_H2I_PF_UPDATE), |
703 | BFI_ABLK_I2H_OPTROM_ENABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_ENABLE), |
704 | BFI_ABLK_I2H_OPTROM_DISABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_DISABLE), |
705 | }; |
706 | |
707 | /* BFI_ABLK_H2I_QUERY */ |
708 | struct bfi_ablk_h2i_query_s { |
709 | struct bfi_mhdr_s mh; |
710 | union bfi_addr_u addr; |
711 | }; |
712 | |
713 | /* BFI_ABL_H2I_ADPT_CONFIG, BFI_ABLK_H2I_PORT_CONFIG */ |
714 | struct bfi_ablk_h2i_cfg_req_s { |
715 | struct bfi_mhdr_s mh; |
716 | u8 mode; |
717 | u8 port; |
718 | u8 max_pf; |
719 | u8 max_vf; |
720 | }; |
721 | |
722 | /* |
723 | * BFI_ABLK_H2I_PF_CREATE, BFI_ABLK_H2I_PF_DELETE, |
724 | */ |
725 | struct bfi_ablk_h2i_pf_req_s { |
726 | struct bfi_mhdr_s mh; |
727 | u8 pcifn; |
728 | u8 port; |
729 | u16 pers; |
730 | u16 bw_min; /* percent BW @ max speed */ |
731 | u16 bw_max; /* percent BW @ max speed */ |
732 | }; |
733 | |
734 | /* BFI_ABLK_H2I_OPTROM_ENABLE, BFI_ABLK_H2I_OPTROM_DISABLE */ |
735 | struct bfi_ablk_h2i_optrom_s { |
736 | struct bfi_mhdr_s mh; |
737 | }; |
738 | |
739 | /* |
740 | * BFI_ABLK_I2H_QUERY |
741 | * BFI_ABLK_I2H_PORT_CONFIG |
742 | * BFI_ABLK_I2H_PF_CREATE |
743 | * BFI_ABLK_I2H_PF_DELETE |
744 | * BFI_ABLK_I2H_PF_UPDATE |
745 | * BFI_ABLK_I2H_OPTROM_ENABLE |
746 | * BFI_ABLK_I2H_OPTROM_DISABLE |
747 | */ |
748 | struct bfi_ablk_i2h_rsp_s { |
749 | struct bfi_mhdr_s mh; |
750 | u8 status; |
751 | u8 pcifn; |
752 | u8 port_mode; |
753 | }; |
754 | |
755 | |
756 | /* |
757 | * CEE module specific messages |
758 | */ |
759 | |
760 | /* Mailbox commands from host to firmware */ |
761 | enum bfi_cee_h2i_msgs_e { |
762 | BFI_CEE_H2I_GET_CFG_REQ = 1, |
763 | BFI_CEE_H2I_RESET_STATS = 2, |
764 | BFI_CEE_H2I_GET_STATS_REQ = 3, |
765 | }; |
766 | |
767 | enum bfi_cee_i2h_msgs_e { |
768 | BFI_CEE_I2H_GET_CFG_RSP = BFA_I2HM(1), |
769 | BFI_CEE_I2H_RESET_STATS_RSP = BFA_I2HM(2), |
770 | BFI_CEE_I2H_GET_STATS_RSP = BFA_I2HM(3), |
771 | }; |
772 | |
773 | /* |
774 | * H2I command structure for resetting the stats |
775 | */ |
776 | struct bfi_cee_reset_stats_s { |
777 | struct bfi_mhdr_s mh; |
778 | }; |
779 | |
780 | /* |
781 | * Get configuration command from host |
782 | */ |
783 | struct bfi_cee_get_req_s { |
784 | struct bfi_mhdr_s mh; |
785 | union bfi_addr_u dma_addr; |
786 | }; |
787 | |
788 | /* |
789 | * Reply message from firmware |
790 | */ |
791 | struct bfi_cee_get_rsp_s { |
792 | struct bfi_mhdr_s mh; |
793 | u8 cmd_status; |
794 | u8 rsvd[3]; |
795 | }; |
796 | |
797 | /* |
798 | * Reply message from firmware |
799 | */ |
800 | struct bfi_cee_stats_rsp_s { |
801 | struct bfi_mhdr_s mh; |
802 | u8 cmd_status; |
803 | u8 rsvd[3]; |
804 | }; |
805 | |
806 | /* Mailbox message structures from firmware to host */ |
807 | union bfi_cee_i2h_msg_u { |
808 | struct bfi_mhdr_s mh; |
809 | struct bfi_cee_get_rsp_s get_rsp; |
810 | struct bfi_cee_stats_rsp_s stats_rsp; |
811 | }; |
812 | |
813 | /* |
814 | * SFP related |
815 | */ |
816 | |
817 | enum bfi_sfp_h2i_e { |
818 | BFI_SFP_H2I_SHOW = 1, |
819 | BFI_SFP_H2I_SCN = 2, |
820 | }; |
821 | |
822 | enum bfi_sfp_i2h_e { |
823 | BFI_SFP_I2H_SHOW = BFA_I2HM(BFI_SFP_H2I_SHOW), |
824 | BFI_SFP_I2H_SCN = BFA_I2HM(BFI_SFP_H2I_SCN), |
825 | }; |
826 | |
827 | /* |
828 | * SFP state change notification |
829 | */ |
830 | struct bfi_sfp_scn_s { |
831 | struct bfi_mhdr_s mhr; /* host msg header */ |
832 | u8 event; |
833 | u8 sfpid; |
834 | u8 pomlvl; /* pom level: normal/warning/alarm */ |
835 | u8 is_elb; /* e-loopback */ |
836 | }; |
837 | |
838 | /* |
839 | * SFP state |
840 | */ |
841 | enum bfa_sfp_stat_e { |
842 | BFA_SFP_STATE_INIT = 0, /* SFP state is uninit */ |
843 | BFA_SFP_STATE_REMOVED = 1, /* SFP is removed */ |
844 | BFA_SFP_STATE_INSERTED = 2, /* SFP is inserted */ |
845 | BFA_SFP_STATE_VALID = 3, /* SFP is valid */ |
846 | BFA_SFP_STATE_UNSUPPORT = 4, /* SFP is unsupport */ |
847 | BFA_SFP_STATE_FAILED = 5, /* SFP i2c read fail */ |
848 | }; |
849 | |
850 | /* |
851 | * SFP memory access type |
852 | */ |
853 | enum bfi_sfp_mem_e { |
854 | BFI_SFP_MEM_ALL = 0x1, /* access all data field */ |
855 | BFI_SFP_MEM_DIAGEXT = 0x2, /* access diag ext data field only */ |
856 | }; |
857 | |
858 | struct bfi_sfp_req_s { |
859 | struct bfi_mhdr_s mh; |
860 | u8 memtype; |
861 | u8 rsvd[3]; |
862 | struct bfi_alen_s alen; |
863 | }; |
864 | |
865 | struct bfi_sfp_rsp_s { |
866 | struct bfi_mhdr_s mh; |
867 | u8 status; |
868 | u8 state; |
869 | u8 rsvd[2]; |
870 | }; |
871 | |
872 | /* |
873 | * FLASH module specific |
874 | */ |
875 | enum bfi_flash_h2i_msgs { |
876 | BFI_FLASH_H2I_QUERY_REQ = 1, |
877 | BFI_FLASH_H2I_ERASE_REQ = 2, |
878 | BFI_FLASH_H2I_WRITE_REQ = 3, |
879 | BFI_FLASH_H2I_READ_REQ = 4, |
880 | BFI_FLASH_H2I_BOOT_VER_REQ = 5, |
881 | }; |
882 | |
883 | enum bfi_flash_i2h_msgs { |
884 | BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1), |
885 | BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2), |
886 | BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3), |
887 | BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4), |
888 | BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5), |
889 | BFI_FLASH_I2H_EVENT = BFA_I2HM(127), |
890 | }; |
891 | |
892 | /* |
893 | * Flash query request |
894 | */ |
895 | struct bfi_flash_query_req_s { |
896 | struct bfi_mhdr_s mh; /* Common msg header */ |
897 | struct bfi_alen_s alen; |
898 | }; |
899 | |
900 | /* |
901 | * Flash erase request |
902 | */ |
903 | struct bfi_flash_erase_req_s { |
904 | struct bfi_mhdr_s mh; /* Common msg header */ |
905 | u32 type; /* partition type */ |
906 | u8 instance; /* partition instance */ |
907 | u8 rsv[3]; |
908 | }; |
909 | |
910 | /* |
911 | * Flash write request |
912 | */ |
913 | struct bfi_flash_write_req_s { |
914 | struct bfi_mhdr_s mh; /* Common msg header */ |
915 | struct bfi_alen_s alen; |
916 | u32 type; /* partition type */ |
917 | u8 instance; /* partition instance */ |
918 | u8 last; |
919 | u8 rsv[2]; |
920 | u32 offset; |
921 | u32 length; |
922 | }; |
923 | |
924 | /* |
925 | * Flash read request |
926 | */ |
927 | struct bfi_flash_read_req_s { |
928 | struct bfi_mhdr_s mh; /* Common msg header */ |
929 | u32 type; /* partition type */ |
930 | u8 instance; /* partition instance */ |
931 | u8 rsv[3]; |
932 | u32 offset; |
933 | u32 length; |
934 | struct bfi_alen_s alen; |
935 | }; |
936 | |
937 | /* |
938 | * Flash query response |
939 | */ |
940 | struct bfi_flash_query_rsp_s { |
941 | struct bfi_mhdr_s mh; /* Common msg header */ |
942 | u32 status; |
943 | }; |
944 | |
945 | /* |
946 | * Flash read response |
947 | */ |
948 | struct bfi_flash_read_rsp_s { |
949 | struct bfi_mhdr_s mh; /* Common msg header */ |
950 | u32 type; /* partition type */ |
951 | u8 instance; /* partition instance */ |
952 | u8 rsv[3]; |
953 | u32 status; |
954 | u32 length; |
955 | }; |
956 | |
957 | /* |
958 | * Flash write response |
959 | */ |
960 | struct bfi_flash_write_rsp_s { |
961 | struct bfi_mhdr_s mh; /* Common msg header */ |
962 | u32 type; /* partition type */ |
963 | u8 instance; /* partition instance */ |
964 | u8 rsv[3]; |
965 | u32 status; |
966 | u32 length; |
967 | }; |
968 | |
969 | /* |
970 | * Flash erase response |
971 | */ |
972 | struct bfi_flash_erase_rsp_s { |
973 | struct bfi_mhdr_s mh; /* Common msg header */ |
974 | u32 type; /* partition type */ |
975 | u8 instance; /* partition instance */ |
976 | u8 rsv[3]; |
977 | u32 status; |
978 | }; |
979 | |
980 | /* |
981 | * Flash event notification |
982 | */ |
983 | struct bfi_flash_event_s { |
984 | struct bfi_mhdr_s mh; /* Common msg header */ |
985 | bfa_status_t status; |
986 | u32 param; |
987 | }; |
988 | |
989 | /* |
990 | *---------------------------------------------------------------------- |
991 | * DIAG |
992 | *---------------------------------------------------------------------- |
993 | */ |
994 | enum bfi_diag_h2i { |
995 | BFI_DIAG_H2I_PORTBEACON = 1, |
996 | BFI_DIAG_H2I_LOOPBACK = 2, |
997 | BFI_DIAG_H2I_FWPING = 3, |
998 | BFI_DIAG_H2I_TEMPSENSOR = 4, |
999 | BFI_DIAG_H2I_LEDTEST = 5, |
1000 | BFI_DIAG_H2I_QTEST = 6, |
1001 | BFI_DIAG_H2I_DPORT = 7, |
1002 | }; |
1003 | |
1004 | enum bfi_diag_i2h { |
1005 | BFI_DIAG_I2H_PORTBEACON = BFA_I2HM(BFI_DIAG_H2I_PORTBEACON), |
1006 | BFI_DIAG_I2H_LOOPBACK = BFA_I2HM(BFI_DIAG_H2I_LOOPBACK), |
1007 | BFI_DIAG_I2H_FWPING = BFA_I2HM(BFI_DIAG_H2I_FWPING), |
1008 | BFI_DIAG_I2H_TEMPSENSOR = BFA_I2HM(BFI_DIAG_H2I_TEMPSENSOR), |
1009 | BFI_DIAG_I2H_LEDTEST = BFA_I2HM(BFI_DIAG_H2I_LEDTEST), |
1010 | BFI_DIAG_I2H_QTEST = BFA_I2HM(BFI_DIAG_H2I_QTEST), |
1011 | BFI_DIAG_I2H_DPORT = BFA_I2HM(BFI_DIAG_H2I_DPORT), |
1012 | BFI_DIAG_I2H_DPORT_SCN = BFA_I2HM(8), |
1013 | }; |
1014 | |
1015 | #define BFI_DIAG_MAX_SGES 2 |
1016 | #define BFI_DIAG_DMA_BUF_SZ (2 * 1024) |
1017 | #define BFI_BOOT_MEMTEST_RES_ADDR 0x900 |
1018 | #define BFI_BOOT_MEMTEST_RES_SIG 0xA0A1A2A3 |
1019 | |
1020 | struct bfi_diag_lb_req_s { |
1021 | struct bfi_mhdr_s mh; |
1022 | u32 loopcnt; |
1023 | u32 pattern; |
1024 | u8 lb_mode; /*!< bfa_port_opmode_t */ |
1025 | u8 speed; /*!< bfa_port_speed_t */ |
1026 | u8 rsvd[2]; |
1027 | }; |
1028 | |
1029 | struct bfi_diag_lb_rsp_s { |
1030 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1031 | struct bfa_diag_loopback_result_s res; /* 16 bytes */ |
1032 | }; |
1033 | |
1034 | struct bfi_diag_fwping_req_s { |
1035 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1036 | struct bfi_alen_s alen; /* 12 bytes */ |
1037 | u32 data; /* user input data pattern */ |
1038 | u32 count; /* user input dma count */ |
1039 | u8 qtag; /* track CPE vc */ |
1040 | u8 rsv[3]; |
1041 | }; |
1042 | |
1043 | struct bfi_diag_fwping_rsp_s { |
1044 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1045 | u32 data; /* user input data pattern */ |
1046 | u8 qtag; /* track CPE vc */ |
1047 | u8 dma_status; /* dma status */ |
1048 | u8 rsv[2]; |
1049 | }; |
1050 | |
1051 | /* |
1052 | * Temperature Sensor |
1053 | */ |
1054 | struct bfi_diag_ts_req_s { |
1055 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1056 | u16 temp; /* 10-bit A/D value */ |
1057 | u16 brd_temp; /* 9-bit board temp */ |
1058 | u8 status; |
1059 | u8 ts_junc; /* show junction tempsensor */ |
1060 | u8 ts_brd; /* show board tempsensor */ |
1061 | u8 rsv; |
1062 | }; |
1063 | #define bfi_diag_ts_rsp_t struct bfi_diag_ts_req_s |
1064 | |
1065 | struct bfi_diag_ledtest_req_s { |
1066 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1067 | u8 cmd; |
1068 | u8 color; |
1069 | u8 portid; |
1070 | u8 led; /* bitmap of LEDs to be tested */ |
1071 | u16 freq; /* no. of blinks every 10 secs */ |
1072 | u8 rsv[2]; |
1073 | }; |
1074 | |
1075 | /* notify host led operation is done */ |
1076 | struct bfi_diag_ledtest_rsp_s { |
1077 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1078 | }; |
1079 | |
1080 | struct bfi_diag_portbeacon_req_s { |
1081 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1082 | u32 period; /* beaconing period */ |
1083 | u8 beacon; /* 1: beacon on */ |
1084 | u8 rsvd[3]; |
1085 | }; |
1086 | |
1087 | /* notify host the beacon is off */ |
1088 | struct bfi_diag_portbeacon_rsp_s { |
1089 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1090 | }; |
1091 | |
1092 | struct bfi_diag_qtest_req_s { |
1093 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1094 | u32 data[BFI_LMSG_PL_WSZ]; /* fill up tcm prefetch area */ |
1095 | }; |
1096 | #define bfi_diag_qtest_rsp_t struct bfi_diag_qtest_req_s |
1097 | |
1098 | /* |
1099 | * D-port test |
1100 | */ |
1101 | enum bfi_dport_req { |
1102 | BFI_DPORT_DISABLE = 0, /* disable dport request */ |
1103 | BFI_DPORT_ENABLE = 1, /* enable dport request */ |
1104 | BFI_DPORT_START = 2, /* start dport request */ |
1105 | BFI_DPORT_SHOW = 3, /* show dport request */ |
1106 | BFI_DPORT_DYN_DISABLE = 4, /* disable dynamic dport request */ |
1107 | }; |
1108 | |
1109 | enum bfi_dport_scn { |
1110 | BFI_DPORT_SCN_TESTSTART = 1, |
1111 | BFI_DPORT_SCN_TESTCOMP = 2, |
1112 | BFI_DPORT_SCN_SFP_REMOVED = 3, |
1113 | BFI_DPORT_SCN_DDPORT_ENABLE = 4, |
1114 | BFI_DPORT_SCN_DDPORT_DISABLE = 5, |
1115 | BFI_DPORT_SCN_FCPORT_DISABLE = 6, |
1116 | BFI_DPORT_SCN_SUBTESTSTART = 7, |
1117 | BFI_DPORT_SCN_TESTSKIP = 8, |
1118 | BFI_DPORT_SCN_DDPORT_DISABLED = 9, |
1119 | }; |
1120 | |
1121 | struct bfi_diag_dport_req_s { |
1122 | struct bfi_mhdr_s mh; /* 4 bytes */ |
1123 | u8 req; /* request 1: enable 0: disable */ |
1124 | u8 rsvd[3]; |
1125 | u32 lpcnt; |
1126 | u32 payload; |
1127 | }; |
1128 | |
1129 | struct bfi_diag_dport_rsp_s { |
1130 | struct bfi_mhdr_s mh; /* header 4 bytes */ |
1131 | bfa_status_t status; /* reply status */ |
1132 | wwn_t pwwn; /* switch port wwn. 8 bytes */ |
1133 | wwn_t nwwn; /* switch node wwn. 8 bytes */ |
1134 | }; |
1135 | |
1136 | struct bfi_diag_dport_scn_teststart_s { |
1137 | wwn_t pwwn; /* switch port wwn. 8 bytes */ |
1138 | wwn_t nwwn; /* switch node wwn. 8 bytes */ |
1139 | u8 type; /* bfa_diag_dport_test_type_e */ |
1140 | u8 mode; /* bfa_diag_dport_test_opmode */ |
1141 | u8 rsvd[2]; |
1142 | u32 numfrm; /* from switch uint in 1M */ |
1143 | }; |
1144 | |
1145 | struct bfi_diag_dport_scn_testcomp_s { |
1146 | u8 status; /* bfa_diag_dport_test_status_e */ |
1147 | u8 speed; /* bfa_port_speed_t */ |
1148 | u16 numbuffer; /* from switch */ |
1149 | u8 subtest_status[DPORT_TEST_MAX]; /* 4 bytes */ |
1150 | u32 latency; /* from switch */ |
1151 | u32 distance; /* from swtich unit in meters */ |
1152 | /* Buffers required to saturate the link */ |
1153 | u16 frm_sz; /* from switch for buf_reqd */ |
1154 | u8 rsvd[2]; |
1155 | }; |
1156 | |
1157 | struct bfi_diag_dport_scn_s { /* max size == RDS_RMESZ */ |
1158 | struct bfi_mhdr_s mh; /* header 4 bytes */ |
1159 | u8 state; /* new state */ |
1160 | u8 rsvd[3]; |
1161 | union { |
1162 | struct bfi_diag_dport_scn_teststart_s teststart; |
1163 | struct bfi_diag_dport_scn_testcomp_s testcomp; |
1164 | } info; |
1165 | }; |
1166 | |
1167 | union bfi_diag_dport_msg_u { |
1168 | struct bfi_diag_dport_req_s req; |
1169 | struct bfi_diag_dport_rsp_s rsp; |
1170 | struct bfi_diag_dport_scn_s scn; |
1171 | }; |
1172 | |
1173 | /* |
1174 | * PHY module specific |
1175 | */ |
1176 | enum bfi_phy_h2i_msgs_e { |
1177 | BFI_PHY_H2I_QUERY_REQ = 1, |
1178 | BFI_PHY_H2I_STATS_REQ = 2, |
1179 | BFI_PHY_H2I_WRITE_REQ = 3, |
1180 | BFI_PHY_H2I_READ_REQ = 4, |
1181 | }; |
1182 | |
1183 | enum bfi_phy_i2h_msgs_e { |
1184 | BFI_PHY_I2H_QUERY_RSP = BFA_I2HM(1), |
1185 | BFI_PHY_I2H_STATS_RSP = BFA_I2HM(2), |
1186 | BFI_PHY_I2H_WRITE_RSP = BFA_I2HM(3), |
1187 | BFI_PHY_I2H_READ_RSP = BFA_I2HM(4), |
1188 | }; |
1189 | |
1190 | /* |
1191 | * External PHY query request |
1192 | */ |
1193 | struct bfi_phy_query_req_s { |
1194 | struct bfi_mhdr_s mh; /* Common msg header */ |
1195 | u8 instance; |
1196 | u8 rsv[3]; |
1197 | struct bfi_alen_s alen; |
1198 | }; |
1199 | |
1200 | /* |
1201 | * External PHY stats request |
1202 | */ |
1203 | struct bfi_phy_stats_req_s { |
1204 | struct bfi_mhdr_s mh; /* Common msg header */ |
1205 | u8 instance; |
1206 | u8 rsv[3]; |
1207 | struct bfi_alen_s alen; |
1208 | }; |
1209 | |
1210 | /* |
1211 | * External PHY write request |
1212 | */ |
1213 | struct bfi_phy_write_req_s { |
1214 | struct bfi_mhdr_s mh; /* Common msg header */ |
1215 | u8 instance; |
1216 | u8 last; |
1217 | u8 rsv[2]; |
1218 | u32 offset; |
1219 | u32 length; |
1220 | struct bfi_alen_s alen; |
1221 | }; |
1222 | |
1223 | /* |
1224 | * External PHY read request |
1225 | */ |
1226 | struct bfi_phy_read_req_s { |
1227 | struct bfi_mhdr_s mh; /* Common msg header */ |
1228 | u8 instance; |
1229 | u8 rsv[3]; |
1230 | u32 offset; |
1231 | u32 length; |
1232 | struct bfi_alen_s alen; |
1233 | }; |
1234 | |
1235 | /* |
1236 | * External PHY query response |
1237 | */ |
1238 | struct bfi_phy_query_rsp_s { |
1239 | struct bfi_mhdr_s mh; /* Common msg header */ |
1240 | u32 status; |
1241 | }; |
1242 | |
1243 | /* |
1244 | * External PHY stats response |
1245 | */ |
1246 | struct bfi_phy_stats_rsp_s { |
1247 | struct bfi_mhdr_s mh; /* Common msg header */ |
1248 | u32 status; |
1249 | }; |
1250 | |
1251 | /* |
1252 | * External PHY read response |
1253 | */ |
1254 | struct bfi_phy_read_rsp_s { |
1255 | struct bfi_mhdr_s mh; /* Common msg header */ |
1256 | u32 status; |
1257 | u32 length; |
1258 | }; |
1259 | |
1260 | /* |
1261 | * External PHY write response |
1262 | */ |
1263 | struct bfi_phy_write_rsp_s { |
1264 | struct bfi_mhdr_s mh; /* Common msg header */ |
1265 | u32 status; |
1266 | u32 length; |
1267 | }; |
1268 | |
1269 | enum bfi_fru_h2i_msgs { |
1270 | BFI_FRUVPD_H2I_WRITE_REQ = 1, |
1271 | BFI_FRUVPD_H2I_READ_REQ = 2, |
1272 | BFI_TFRU_H2I_WRITE_REQ = 3, |
1273 | BFI_TFRU_H2I_READ_REQ = 4, |
1274 | }; |
1275 | |
1276 | enum bfi_fru_i2h_msgs { |
1277 | BFI_FRUVPD_I2H_WRITE_RSP = BFA_I2HM(1), |
1278 | BFI_FRUVPD_I2H_READ_RSP = BFA_I2HM(2), |
1279 | BFI_TFRU_I2H_WRITE_RSP = BFA_I2HM(3), |
1280 | BFI_TFRU_I2H_READ_RSP = BFA_I2HM(4), |
1281 | }; |
1282 | |
1283 | /* |
1284 | * FRU write request |
1285 | */ |
1286 | struct bfi_fru_write_req_s { |
1287 | struct bfi_mhdr_s mh; /* Common msg header */ |
1288 | u8 last; |
1289 | u8 rsv_1[3]; |
1290 | u8 trfr_cmpl; |
1291 | u8 rsv_2[3]; |
1292 | u32 offset; |
1293 | u32 length; |
1294 | struct bfi_alen_s alen; |
1295 | }; |
1296 | |
1297 | /* |
1298 | * FRU read request |
1299 | */ |
1300 | struct bfi_fru_read_req_s { |
1301 | struct bfi_mhdr_s mh; /* Common msg header */ |
1302 | u32 offset; |
1303 | u32 length; |
1304 | struct bfi_alen_s alen; |
1305 | }; |
1306 | |
1307 | /* |
1308 | * FRU response |
1309 | */ |
1310 | struct bfi_fru_rsp_s { |
1311 | struct bfi_mhdr_s mh; /* Common msg header */ |
1312 | u32 status; |
1313 | u32 length; |
1314 | }; |
1315 | #pragma pack() |
1316 | |
1317 | #endif /* __BFI_H__ */ |
1318 | |