1 | /******************************************************************* |
2 | * This file is part of the Emulex Linux Device Driver for * |
3 | * Fibre Channel Host Bus Adapters. * |
4 | * Copyright (C) 2017-2023 Broadcom. All Rights Reserved. The term * |
5 | * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * |
6 | * Copyright (C) 2004-2016 Emulex. All rights reserved. * |
7 | * EMULEX and SLI are trademarks of Emulex. * |
8 | * www.broadcom.com * |
9 | * * |
10 | * This program is free software; you can redistribute it and/or * |
11 | * modify it under the terms of version 2 of the GNU General * |
12 | * Public License as published by the Free Software Foundation. * |
13 | * This program is distributed in the hope that it will be useful. * |
14 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * |
15 | * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * |
16 | * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * |
17 | * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * |
18 | * TO BE LEGALLY INVALID. See the GNU General Public License for * |
19 | * more details, a copy of which can be found in the file COPYING * |
20 | * included with this package. * |
21 | *******************************************************************/ |
22 | |
23 | #define FDMI_DID 0xfffffaU |
24 | #define NameServer_DID 0xfffffcU |
25 | #define Fabric_Cntl_DID 0xfffffdU |
26 | #define Fabric_DID 0xfffffeU |
27 | #define Bcast_DID 0xffffffU |
28 | #define Mask_DID 0xffffffU |
29 | #define CT_DID_MASK 0xffff00U |
30 | #define Fabric_DID_MASK 0xfff000U |
31 | #define WELL_KNOWN_DID_MASK 0xfffff0U |
32 | |
33 | #define PT2PT_LocalID 1 |
34 | #define PT2PT_RemoteID 2 |
35 | |
36 | #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ |
37 | #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ |
38 | #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ |
39 | #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ |
40 | |
41 | #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING |
42 | 0 */ |
43 | |
44 | #define FCELSSIZE 1024 /* maximum ELS transfer size */ |
45 | |
46 | #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ |
47 | #define 1 /* ring 1 for other protocols */ |
48 | #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ |
49 | |
50 | #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ |
51 | #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ |
52 | #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ |
53 | #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ |
54 | #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ |
55 | #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ |
56 | #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ |
57 | #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ |
58 | #define SLI2_IOCB_CMD_R3_ENTRIES 0 |
59 | #define SLI2_IOCB_RSP_R3_ENTRIES 0 |
60 | #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 |
61 | #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 |
62 | |
63 | #define SLI2_IOCB_CMD_SIZE 32 |
64 | #define SLI2_IOCB_RSP_SIZE 32 |
65 | #define SLI3_IOCB_CMD_SIZE 128 |
66 | #define SLI3_IOCB_RSP_SIZE 64 |
67 | |
68 | #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff |
69 | #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff |
70 | |
71 | /* vendor ID used in SCSI netlink calls */ |
72 | #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) |
73 | |
74 | #define FW_REV_STR_SIZE 32 |
75 | /* Common Transport structures and definitions */ |
76 | |
77 | union CtRevisionId { |
78 | /* Structure is in Big Endian format */ |
79 | struct { |
80 | uint32_t Revision:8; |
81 | uint32_t InId:24; |
82 | } bits; |
83 | uint32_t word; |
84 | }; |
85 | |
86 | union CtCommandResponse { |
87 | /* Structure is in Big Endian format */ |
88 | struct { |
89 | __be16 CmdRsp; |
90 | __be16 Size; |
91 | } bits; |
92 | uint32_t word; |
93 | }; |
94 | |
95 | /* FC4 Feature bits for RFF_ID */ |
96 | #define FC4_FEATURE_TARGET 0x1 |
97 | #define FC4_FEATURE_INIT 0x2 |
98 | #define FC4_FEATURE_NVME_DISC 0x4 |
99 | |
100 | enum rft_word0 { |
101 | RFT_FCP_REG = (0x1 << 8), |
102 | }; |
103 | |
104 | enum rft_word1 { |
105 | RFT_NVME_REG = (0x1 << 8), |
106 | }; |
107 | |
108 | enum rft_word3 { |
109 | RFT_APP_SERV_REG = (0x1 << 0), |
110 | }; |
111 | |
112 | struct lpfc_sli_ct_request { |
113 | /* Structure is in Big Endian format */ |
114 | union CtRevisionId RevisionId; |
115 | uint8_t FsType; |
116 | uint8_t FsSubType; |
117 | uint8_t Options; |
118 | uint8_t Rsrvd1; |
119 | union CtCommandResponse CommandResponse; |
120 | uint8_t Rsrvd2; |
121 | uint8_t ReasonCode; |
122 | uint8_t Explanation; |
123 | uint8_t VendorUnique; |
124 | #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ |
125 | |
126 | union { |
127 | __be32 PortID; |
128 | struct gid { |
129 | uint8_t PortType; /* for GID_PT requests */ |
130 | #define GID_PT_N_PORT 1 |
131 | uint8_t DomainScope; |
132 | uint8_t AreaScope; |
133 | uint8_t Fc4Type; /* for GID_FT requests */ |
134 | } gid; |
135 | struct gid_ff { |
136 | uint8_t Flags; |
137 | uint8_t DomainScope; |
138 | uint8_t AreaScope; |
139 | uint8_t rsvd1; |
140 | uint8_t rsvd2; |
141 | uint8_t rsvd3; |
142 | uint8_t Fc4FBits; |
143 | uint8_t Fc4Type; |
144 | } gid_ff; |
145 | struct rft { |
146 | __be32 port_id; /* For RFT_ID requests */ |
147 | |
148 | __be32 fcp_reg; /* rsvd 31:9, fcp_reg 8, rsvd 7:0 */ |
149 | __be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */ |
150 | __be32 word2; |
151 | __be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */ |
152 | __be32 word[4]; |
153 | } rft; |
154 | struct rnn { |
155 | uint32_t PortId; /* For RNN_ID requests */ |
156 | uint8_t wwnn[8]; |
157 | } rnn; |
158 | struct rsnn { /* For RSNN_ID requests */ |
159 | uint8_t wwnn[8]; |
160 | uint8_t len; |
161 | uint8_t symbname[255]; |
162 | } rsnn; |
163 | struct da_id { /* For DA_ID requests */ |
164 | uint32_t port_id; |
165 | } da_id; |
166 | struct rspn { /* For RSPN_ID requests */ |
167 | uint32_t PortId; |
168 | uint8_t len; |
169 | uint8_t symbname[255]; |
170 | } rspn; |
171 | struct gff { |
172 | uint32_t PortId; |
173 | } gff; |
174 | struct gff_acc { |
175 | uint8_t fbits[128]; |
176 | } gff_acc; |
177 | struct gft { |
178 | uint32_t PortId; |
179 | } gft; |
180 | struct gft_acc { |
181 | uint32_t fc4_types[8]; |
182 | } gft_acc; |
183 | #define FCP_TYPE_FEATURE_OFFSET 7 |
184 | struct rff { |
185 | uint32_t PortId; |
186 | uint8_t reserved[2]; |
187 | uint8_t fbits; |
188 | uint8_t type_code; /* type=8 for FCP */ |
189 | } rff; |
190 | } un; |
191 | }; |
192 | |
193 | #define LPFC_MAX_CT_SIZE (60 * 4096) |
194 | |
195 | #define SLI_CT_REVISION 1 |
196 | #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
197 | sizeof(struct gid)) |
198 | #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
199 | sizeof(struct gid_ff)) |
200 | #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
201 | sizeof(struct gff)) |
202 | #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
203 | sizeof(struct gft)) |
204 | #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
205 | sizeof(struct rft)) |
206 | #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
207 | sizeof(struct rff)) |
208 | #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
209 | sizeof(struct rnn)) |
210 | #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
211 | sizeof(struct rsnn)) |
212 | #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
213 | sizeof(struct da_id)) |
214 | #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ |
215 | sizeof(struct rspn)) |
216 | |
217 | /* |
218 | * FsType Definitions |
219 | */ |
220 | |
221 | #define SLI_CT_MANAGEMENT_SERVICE 0xFA |
222 | #define SLI_CT_TIME_SERVICE 0xFB |
223 | #define SLI_CT_DIRECTORY_SERVICE 0xFC |
224 | #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD |
225 | |
226 | /* |
227 | * Directory Service Subtypes |
228 | */ |
229 | |
230 | #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 |
231 | |
232 | /* |
233 | * Response Codes |
234 | */ |
235 | |
236 | #define SLI_CT_RESPONSE_FS_RJT 0x8001 |
237 | #define SLI_CT_RESPONSE_FS_ACC 0x8002 |
238 | |
239 | /* |
240 | * Reason Codes |
241 | */ |
242 | |
243 | #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 |
244 | #define SLI_CT_INVALID_COMMAND 0x01 |
245 | #define SLI_CT_INVALID_VERSION 0x02 |
246 | #define SLI_CT_LOGICAL_ERROR 0x03 |
247 | #define SLI_CT_INVALID_IU_SIZE 0x04 |
248 | #define SLI_CT_LOGICAL_BUSY 0x05 |
249 | #define SLI_CT_PROTOCOL_ERROR 0x07 |
250 | #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 |
251 | #define SLI_CT_REQ_NOT_SUPPORTED 0x0b |
252 | #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 |
253 | #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 |
254 | #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 |
255 | #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 |
256 | #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 |
257 | #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 |
258 | #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 |
259 | #define SLI_CT_VENDOR_UNIQUE 0xff |
260 | |
261 | /* |
262 | * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations |
263 | */ |
264 | |
265 | #define SLI_CT_NO_PORT_ID 0x01 |
266 | #define SLI_CT_NO_PORT_NAME 0x02 |
267 | #define SLI_CT_NO_NODE_NAME 0x03 |
268 | #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 |
269 | #define SLI_CT_NO_IP_ADDRESS 0x05 |
270 | #define SLI_CT_NO_IPA 0x06 |
271 | #define SLI_CT_NO_FC4_TYPES 0x07 |
272 | #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 |
273 | #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 |
274 | #define SLI_CT_NO_PORT_TYPE 0x0A |
275 | #define SLI_CT_ACCESS_DENIED 0x10 |
276 | #define SLI_CT_INVALID_PORT_ID 0x11 |
277 | #define SLI_CT_DATABASE_EMPTY 0x12 |
278 | #define SLI_CT_APP_ID_NOT_AVAILABLE 0x40 |
279 | |
280 | /* |
281 | * Name Server Command Codes |
282 | */ |
283 | |
284 | #define SLI_CTNS_GA_NXT 0x0100 |
285 | #define SLI_CTNS_GPN_ID 0x0112 |
286 | #define SLI_CTNS_GNN_ID 0x0113 |
287 | #define SLI_CTNS_GCS_ID 0x0114 |
288 | #define SLI_CTNS_GFT_ID 0x0117 |
289 | #define SLI_CTNS_GSPN_ID 0x0118 |
290 | #define SLI_CTNS_GPT_ID 0x011A |
291 | #define SLI_CTNS_GFF_ID 0x011F |
292 | #define SLI_CTNS_GID_PN 0x0121 |
293 | #define SLI_CTNS_GID_NN 0x0131 |
294 | #define SLI_CTNS_GIP_NN 0x0135 |
295 | #define SLI_CTNS_GIPA_NN 0x0136 |
296 | #define SLI_CTNS_GSNN_NN 0x0139 |
297 | #define SLI_CTNS_GNN_IP 0x0153 |
298 | #define SLI_CTNS_GIPA_IP 0x0156 |
299 | #define SLI_CTNS_GID_FT 0x0171 |
300 | #define SLI_CTNS_GID_FF 0x01F1 |
301 | #define SLI_CTNS_GID_PT 0x01A1 |
302 | #define SLI_CTNS_RPN_ID 0x0212 |
303 | #define SLI_CTNS_RNN_ID 0x0213 |
304 | #define SLI_CTNS_RCS_ID 0x0214 |
305 | #define SLI_CTNS_RFT_ID 0x0217 |
306 | #define SLI_CTNS_RSPN_ID 0x0218 |
307 | #define SLI_CTNS_RPT_ID 0x021A |
308 | #define SLI_CTNS_RFF_ID 0x021F |
309 | #define SLI_CTNS_RIP_NN 0x0235 |
310 | #define SLI_CTNS_RIPA_NN 0x0236 |
311 | #define SLI_CTNS_RSNN_NN 0x0239 |
312 | #define SLI_CTNS_DA_ID 0x0300 |
313 | |
314 | /* |
315 | * Port Types |
316 | */ |
317 | |
318 | #define SLI_CTPT_N_PORT 0x01 |
319 | #define SLI_CTPT_NL_PORT 0x02 |
320 | #define SLI_CTPT_FNL_PORT 0x03 |
321 | #define SLI_CTPT_IP 0x04 |
322 | #define SLI_CTPT_FCP 0x08 |
323 | #define SLI_CTPT_NVME 0x28 |
324 | #define SLI_CTPT_NX_PORT 0x7F |
325 | #define SLI_CTPT_F_PORT 0x81 |
326 | #define SLI_CTPT_FL_PORT 0x82 |
327 | #define SLI_CTPT_E_PORT 0x84 |
328 | |
329 | #define SLI_CT_LAST_ENTRY 0x80000000 |
330 | |
331 | /* Fibre Channel Service Parameter definitions */ |
332 | |
333 | #define FC_PH_4_0 6 /* FC-PH version 4.0 */ |
334 | #define FC_PH_4_1 7 /* FC-PH version 4.1 */ |
335 | #define FC_PH_4_2 8 /* FC-PH version 4.2 */ |
336 | #define FC_PH_4_3 9 /* FC-PH version 4.3 */ |
337 | |
338 | #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ |
339 | #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ |
340 | #define FC_PH3 0x20 /* FC-PH-3 version */ |
341 | |
342 | #define FF_FRAME_SIZE 2048 |
343 | |
344 | struct lpfc_name { |
345 | union { |
346 | struct { |
347 | #ifdef __BIG_ENDIAN_BITFIELD |
348 | uint8_t nameType:4; /* FC Word 0, bit 28:31 */ |
349 | uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit |
350 | 8:11 of IEEE ext */ |
351 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
352 | uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit |
353 | 8:11 of IEEE ext */ |
354 | uint8_t nameType:4; /* FC Word 0, bit 28:31 */ |
355 | #endif |
356 | |
357 | #define NAME_IEEE 0x1 /* IEEE name - nameType */ |
358 | #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ |
359 | #define NAME_FC_TYPE 0x3 /* FC native name type */ |
360 | #define NAME_IP_TYPE 0x4 /* IP address */ |
361 | #define NAME_CCITT_TYPE 0xC |
362 | #define NAME_CCITT_GR_TYPE 0xE |
363 | uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE |
364 | extended Lsb */ |
365 | uint8_t IEEE[6]; /* FC IEEE address */ |
366 | } s; |
367 | uint8_t wwn[8]; |
368 | uint64_t name __packed __aligned(4); |
369 | } u; |
370 | }; |
371 | |
372 | struct csp { |
373 | uint8_t fcphHigh; /* FC Word 0, byte 0 */ |
374 | uint8_t fcphLow; |
375 | uint8_t bbCreditMsb; |
376 | uint8_t bbCreditLsb; /* FC Word 0, byte 3 */ |
377 | |
378 | /* |
379 | * Word 1 Bit 31 in common service parameter is overloaded. |
380 | * Word 1 Bit 31 in FLOGI request is multiple NPort request |
381 | * Word 1 Bit 31 in FLOGI response is clean address bit |
382 | */ |
383 | #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ |
384 | /* |
385 | * Word 1 Bit 30 in common service parameter is overloaded. |
386 | * Word 1 Bit 30 in FLOGI request is Virtual Fabrics |
387 | * Word 1 Bit 30 in PLOGI request is random offset |
388 | */ |
389 | #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ |
390 | /* |
391 | * Word 1 Bit 29 in common service parameter is overloaded. |
392 | * Word 1 Bit 29 in FLOGI response is multiple NPort assignment |
393 | * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level |
394 | */ |
395 | #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */ |
396 | #ifdef __BIG_ENDIAN_BITFIELD |
397 | uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ |
398 | uint16_t randomOffset:1; /* FC Word 1, bit 30 */ |
399 | uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ |
400 | uint16_t fPort:1; /* FC Word 1, bit 28 */ |
401 | uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ |
402 | uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ |
403 | uint16_t multicast:1; /* FC Word 1, bit 25 */ |
404 | uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ |
405 | |
406 | uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ |
407 | uint16_t simplex:1; /* FC Word 1, bit 22 */ |
408 | uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ |
409 | uint16_t dhd:1; /* FC Word 1, bit 18 */ |
410 | uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ |
411 | uint16_t payloadlength:1; /* FC Word 1, bit 16 */ |
412 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
413 | uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ |
414 | uint16_t multicast:1; /* FC Word 1, bit 25 */ |
415 | uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ |
416 | uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ |
417 | uint16_t fPort:1; /* FC Word 1, bit 28 */ |
418 | uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ |
419 | uint16_t randomOffset:1; /* FC Word 1, bit 30 */ |
420 | uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ |
421 | |
422 | uint16_t payloadlength:1; /* FC Word 1, bit 16 */ |
423 | uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ |
424 | uint16_t dhd:1; /* FC Word 1, bit 18 */ |
425 | uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ |
426 | uint16_t simplex:1; /* FC Word 1, bit 22 */ |
427 | uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ |
428 | #endif |
429 | |
430 | uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ |
431 | uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ |
432 | union { |
433 | struct { |
434 | uint8_t word2Reserved1; /* FC Word 2 byte 0 */ |
435 | |
436 | uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ |
437 | uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ |
438 | |
439 | uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ |
440 | } nPort; |
441 | uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ |
442 | } w2; |
443 | |
444 | uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ |
445 | }; |
446 | |
447 | struct class_parms { |
448 | #ifdef __BIG_ENDIAN_BITFIELD |
449 | uint8_t classValid:1; /* FC Word 0, bit 31 */ |
450 | uint8_t intermix:1; /* FC Word 0, bit 30 */ |
451 | uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ |
452 | uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ |
453 | uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ |
454 | uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ |
455 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
456 | uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ |
457 | uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ |
458 | uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ |
459 | uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ |
460 | uint8_t intermix:1; /* FC Word 0, bit 30 */ |
461 | uint8_t classValid:1; /* FC Word 0, bit 31 */ |
462 | |
463 | #endif |
464 | |
465 | uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ |
466 | |
467 | #ifdef __BIG_ENDIAN_BITFIELD |
468 | uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ |
469 | uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ |
470 | uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ |
471 | uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ |
472 | uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ |
473 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
474 | uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ |
475 | uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ |
476 | uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ |
477 | uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ |
478 | uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ |
479 | #endif |
480 | |
481 | uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ |
482 | |
483 | #ifdef __BIG_ENDIAN_BITFIELD |
484 | uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ |
485 | uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ |
486 | uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ |
487 | uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ |
488 | uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ |
489 | uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ |
490 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
491 | uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ |
492 | uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ |
493 | uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ |
494 | uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ |
495 | uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ |
496 | uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ |
497 | #endif |
498 | |
499 | uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ |
500 | uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ |
501 | uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ |
502 | |
503 | uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ |
504 | uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ |
505 | uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ |
506 | uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ |
507 | |
508 | uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ |
509 | uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ |
510 | uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ |
511 | uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ |
512 | }; |
513 | |
514 | struct serv_parm { /* Structure is in Big Endian format */ |
515 | struct csp cmn; |
516 | struct lpfc_name portName; |
517 | struct lpfc_name nodeName; |
518 | struct class_parms cls1; |
519 | struct class_parms cls2; |
520 | struct class_parms cls3; |
521 | struct class_parms cls4; |
522 | union { |
523 | uint8_t vendorVersion[16]; |
524 | struct { |
525 | uint32_t vid; |
526 | #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */ |
527 | uint32_t flags; |
528 | #define LPFC_VV_SUPPRESS_RSP 1 |
529 | } vv; |
530 | } un; |
531 | }; |
532 | |
533 | /* |
534 | * Virtual Fabric Tagging Header |
535 | */ |
536 | struct { |
537 | uint32_t ; |
538 | #define fc_vft_hdr_r_ctl_SHIFT 24 |
539 | #define fc_vft_hdr_r_ctl_MASK 0xFF |
540 | #define fc_vft_hdr_r_ctl_WORD word0 |
541 | #define fc_vft_hdr_ver_SHIFT 22 |
542 | #define fc_vft_hdr_ver_MASK 0x3 |
543 | #define fc_vft_hdr_ver_WORD word0 |
544 | #define fc_vft_hdr_type_SHIFT 18 |
545 | #define fc_vft_hdr_type_MASK 0xF |
546 | #define fc_vft_hdr_type_WORD word0 |
547 | #define fc_vft_hdr_e_SHIFT 16 |
548 | #define fc_vft_hdr_e_MASK 0x1 |
549 | #define fc_vft_hdr_e_WORD word0 |
550 | #define fc_vft_hdr_priority_SHIFT 13 |
551 | #define fc_vft_hdr_priority_MASK 0x7 |
552 | #define fc_vft_hdr_priority_WORD word0 |
553 | #define fc_vft_hdr_vf_id_SHIFT 1 |
554 | #define fc_vft_hdr_vf_id_MASK 0xFFF |
555 | #define fc_vft_hdr_vf_id_WORD word0 |
556 | uint32_t ; |
557 | #define fc_vft_hdr_hopct_SHIFT 24 |
558 | #define fc_vft_hdr_hopct_MASK 0xFF |
559 | #define fc_vft_hdr_hopct_WORD word1 |
560 | }; |
561 | |
562 | #include <uapi/scsi/fc/fc_els.h> |
563 | |
564 | /* |
565 | * Extended Link Service LS_COMMAND codes (Payload Word 0) |
566 | */ |
567 | #ifdef __BIG_ENDIAN_BITFIELD |
568 | #define ELS_CMD_MASK 0xffff0000 |
569 | #define ELS_RSP_MASK 0xff000000 |
570 | #define ELS_CMD_LS_RJT 0x01000000 |
571 | #define ELS_CMD_ACC 0x02000000 |
572 | #define ELS_CMD_PLOGI 0x03000000 |
573 | #define ELS_CMD_FLOGI 0x04000000 |
574 | #define ELS_CMD_LOGO 0x05000000 |
575 | #define ELS_CMD_ABTX 0x06000000 |
576 | #define ELS_CMD_RCS 0x07000000 |
577 | #define ELS_CMD_RES 0x08000000 |
578 | #define ELS_CMD_RSS 0x09000000 |
579 | #define ELS_CMD_RSI 0x0A000000 |
580 | #define ELS_CMD_ESTS 0x0B000000 |
581 | #define ELS_CMD_ESTC 0x0C000000 |
582 | #define ELS_CMD_ADVC 0x0D000000 |
583 | #define ELS_CMD_RTV 0x0E000000 |
584 | #define ELS_CMD_RLS 0x0F000000 |
585 | #define ELS_CMD_ECHO 0x10000000 |
586 | #define ELS_CMD_TEST 0x11000000 |
587 | #define ELS_CMD_RRQ 0x12000000 |
588 | #define ELS_CMD_REC 0x13000000 |
589 | #define ELS_CMD_RDP 0x18000000 |
590 | #define ELS_CMD_RDF 0x19000000 |
591 | #define ELS_CMD_PRLI 0x20100014 |
592 | #define ELS_CMD_NVMEPRLI 0x20140018 |
593 | #define ELS_CMD_PRLO 0x21100014 |
594 | #define ELS_CMD_PRLO_ACC 0x02100014 |
595 | #define ELS_CMD_PDISC 0x50000000 |
596 | #define ELS_CMD_FDISC 0x51000000 |
597 | #define ELS_CMD_ADISC 0x52000000 |
598 | #define ELS_CMD_FARP 0x54000000 |
599 | #define ELS_CMD_FARPR 0x55000000 |
600 | #define ELS_CMD_RPL 0x57000000 |
601 | #define ELS_CMD_FAN 0x60000000 |
602 | #define ELS_CMD_RSCN 0x61040000 |
603 | #define ELS_CMD_RSCN_XMT 0x61040008 |
604 | #define ELS_CMD_SCR 0x62000000 |
605 | #define ELS_CMD_RNID 0x78000000 |
606 | #define ELS_CMD_LIRR 0x7A000000 |
607 | #define ELS_CMD_LCB 0x81000000 |
608 | #define ELS_CMD_FPIN 0x16000000 |
609 | #define ELS_CMD_EDC 0x17000000 |
610 | #define ELS_CMD_QFPA 0xB0000000 |
611 | #define ELS_CMD_UVEM 0xB1000000 |
612 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
613 | #define ELS_CMD_MASK 0xffff |
614 | #define ELS_RSP_MASK 0xff |
615 | #define ELS_CMD_LS_RJT 0x01 |
616 | #define ELS_CMD_ACC 0x02 |
617 | #define ELS_CMD_PLOGI 0x03 |
618 | #define ELS_CMD_FLOGI 0x04 |
619 | #define ELS_CMD_LOGO 0x05 |
620 | #define ELS_CMD_ABTX 0x06 |
621 | #define ELS_CMD_RCS 0x07 |
622 | #define ELS_CMD_RES 0x08 |
623 | #define 0x09 |
624 | #define ELS_CMD_RSI 0x0A |
625 | #define ELS_CMD_ESTS 0x0B |
626 | #define ELS_CMD_ESTC 0x0C |
627 | #define ELS_CMD_ADVC 0x0D |
628 | #define ELS_CMD_RTV 0x0E |
629 | #define ELS_CMD_RLS 0x0F |
630 | #define ELS_CMD_ECHO 0x10 |
631 | #define ELS_CMD_TEST 0x11 |
632 | #define ELS_CMD_RRQ 0x12 |
633 | #define ELS_CMD_REC 0x13 |
634 | #define ELS_CMD_RDP 0x18 |
635 | #define ELS_CMD_RDF 0x19 |
636 | #define ELS_CMD_PRLI 0x14001020 |
637 | #define ELS_CMD_NVMEPRLI 0x18001420 |
638 | #define ELS_CMD_PRLO 0x14001021 |
639 | #define ELS_CMD_PRLO_ACC 0x14001002 |
640 | #define ELS_CMD_PDISC 0x50 |
641 | #define ELS_CMD_FDISC 0x51 |
642 | #define ELS_CMD_ADISC 0x52 |
643 | #define ELS_CMD_FARP 0x54 |
644 | #define ELS_CMD_FARPR 0x55 |
645 | #define ELS_CMD_RPL 0x57 |
646 | #define ELS_CMD_FAN 0x60 |
647 | #define ELS_CMD_RSCN 0x0461 |
648 | #define ELS_CMD_RSCN_XMT 0x08000461 |
649 | #define ELS_CMD_SCR 0x62 |
650 | #define ELS_CMD_RNID 0x78 |
651 | #define ELS_CMD_LIRR 0x7A |
652 | #define ELS_CMD_LCB 0x81 |
653 | #define ELS_CMD_FPIN ELS_FPIN |
654 | #define ELS_CMD_EDC ELS_EDC |
655 | #define ELS_CMD_QFPA 0xB0 |
656 | #define ELS_CMD_UVEM 0xB1 |
657 | #endif |
658 | |
659 | /* |
660 | * LS_RJT Payload Definition |
661 | */ |
662 | |
663 | struct ls_rjt { /* Structure is in Big Endian format */ |
664 | union { |
665 | __be32 ls_rjt_error_be; |
666 | uint32_t lsRjtError; |
667 | struct { |
668 | uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ |
669 | |
670 | uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ |
671 | /* LS_RJT reason codes */ |
672 | #define LSRJT_INVALID_CMD 0x01 |
673 | #define LSRJT_LOGICAL_ERR 0x03 |
674 | #define LSRJT_LOGICAL_BSY 0x05 |
675 | #define LSRJT_PROTOCOL_ERR 0x07 |
676 | #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ |
677 | #define LSRJT_CMD_UNSUPPORTED 0x0B |
678 | #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ |
679 | |
680 | uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ |
681 | /* LS_RJT reason explanation */ |
682 | #define LSEXP_NOTHING_MORE 0x00 |
683 | #define LSEXP_SPARM_OPTIONS 0x01 |
684 | #define LSEXP_SPARM_ICTL 0x03 |
685 | #define LSEXP_SPARM_RCTL 0x05 |
686 | #define LSEXP_SPARM_RCV_SIZE 0x07 |
687 | #define LSEXP_SPARM_CONCUR_SEQ 0x09 |
688 | #define LSEXP_SPARM_CREDIT 0x0B |
689 | #define LSEXP_INVALID_PNAME 0x0D |
690 | #define LSEXP_INVALID_NNAME 0x0E |
691 | #define LSEXP_INVALID_CSP 0x0F |
692 | #define LSEXP_INVALID_ASSOC_HDR 0x11 |
693 | #define LSEXP_ASSOC_HDR_REQ 0x13 |
694 | #define LSEXP_INVALID_O_SID 0x15 |
695 | #define LSEXP_INVALID_OX_RX 0x17 |
696 | #define LSEXP_CMD_IN_PROGRESS 0x19 |
697 | #define LSEXP_PORT_LOGIN_REQ 0x1E |
698 | #define LSEXP_INVALID_NPORT_ID 0x1F |
699 | #define LSEXP_INVALID_SEQ_ID 0x21 |
700 | #define LSEXP_INVALID_XCHG 0x23 |
701 | #define LSEXP_INACTIVE_XCHG 0x25 |
702 | #define LSEXP_RQ_REQUIRED 0x27 |
703 | #define LSEXP_OUT_OF_RESOURCE 0x29 |
704 | #define LSEXP_CANT_GIVE_DATA 0x2A |
705 | #define LSEXP_REQ_UNSUPPORTED 0x2C |
706 | #define LSEXP_NO_RSRC_ASSIGN 0x52 |
707 | uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ |
708 | } b; |
709 | } un; |
710 | }; |
711 | |
712 | /* |
713 | * N_Port Login (FLOGO/PLOGO Request) Payload Definition |
714 | */ |
715 | |
716 | typedef struct _LOGO { /* Structure is in Big Endian format */ |
717 | union { |
718 | uint32_t nPortId32; /* Access nPortId as a word */ |
719 | struct { |
720 | uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ |
721 | uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ |
722 | uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ |
723 | uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ |
724 | } b; |
725 | } un; |
726 | struct lpfc_name portName; /* N_port name field */ |
727 | } LOGO; |
728 | |
729 | /* |
730 | * FCP Login (PRLI Request / ACC) Payload Definition |
731 | */ |
732 | |
733 | #define PRLX_PAGE_LEN 0x10 |
734 | #define TPRLO_PAGE_LEN 0x14 |
735 | |
736 | typedef struct _PRLI { /* Structure is in Big Endian format */ |
737 | uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ |
738 | |
739 | #define PRLI_FCP_TYPE 0x08 |
740 | #define PRLI_NVME_TYPE 0x28 |
741 | uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ |
742 | |
743 | #ifdef __BIG_ENDIAN_BITFIELD |
744 | uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ |
745 | uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ |
746 | uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ |
747 | |
748 | /* ACC = imagePairEstablished */ |
749 | uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ |
750 | uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ |
751 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
752 | uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ |
753 | uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ |
754 | uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ |
755 | uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ |
756 | uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ |
757 | /* ACC = imagePairEstablished */ |
758 | #endif |
759 | |
760 | #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ |
761 | #define PRLI_NO_RESOURCES 0x2 |
762 | #define PRLI_INIT_INCOMPLETE 0x3 |
763 | #define PRLI_NO_SUCH_PA 0x4 |
764 | #define PRLI_PREDEF_CONFIG 0x5 |
765 | #define PRLI_PARTIAL_SUCCESS 0x6 |
766 | #define PRLI_INVALID_PAGE_CNT 0x7 |
767 | #define PRLI_INV_SRV_PARM 0x8 |
768 | |
769 | uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ |
770 | |
771 | uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ |
772 | |
773 | uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ |
774 | |
775 | uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ |
776 | uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ |
777 | |
778 | #ifdef __BIG_ENDIAN_BITFIELD |
779 | uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ |
780 | uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ |
781 | uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ |
782 | uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ |
783 | uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ |
784 | uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ |
785 | uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ |
786 | uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ |
787 | uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ |
788 | uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ |
789 | uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ |
790 | uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ |
791 | uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ |
792 | uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ |
793 | uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ |
794 | uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ |
795 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
796 | uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ |
797 | uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ |
798 | uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ |
799 | uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ |
800 | uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ |
801 | uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ |
802 | uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ |
803 | uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ |
804 | uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ |
805 | uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ |
806 | uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ |
807 | uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ |
808 | uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ |
809 | uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ |
810 | uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ |
811 | uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ |
812 | #endif |
813 | } PRLI; |
814 | |
815 | /* |
816 | * FCP Logout (PRLO Request / ACC) Payload Definition |
817 | */ |
818 | |
819 | typedef struct _PRLO { /* Structure is in Big Endian format */ |
820 | uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ |
821 | |
822 | #define PRLO_FCP_TYPE 0x08 |
823 | uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ |
824 | |
825 | #ifdef __BIG_ENDIAN_BITFIELD |
826 | uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ |
827 | uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ |
828 | uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ |
829 | uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ |
830 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
831 | uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ |
832 | uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ |
833 | uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ |
834 | uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ |
835 | #endif |
836 | |
837 | #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ |
838 | #define PRLO_NO_SUCH_IMAGE 0x4 |
839 | #define PRLO_INVALID_PAGE_CNT 0x7 |
840 | |
841 | uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ |
842 | |
843 | uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ |
844 | |
845 | uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ |
846 | |
847 | uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ |
848 | } PRLO; |
849 | |
850 | typedef struct _ADISC { /* Structure is in Big Endian format */ |
851 | uint32_t hardAL_PA; |
852 | struct lpfc_name portName; |
853 | struct lpfc_name nodeName; |
854 | uint32_t DID; |
855 | } ADISC; |
856 | |
857 | typedef struct _FARP { /* Structure is in Big Endian format */ |
858 | uint32_t Mflags:8; |
859 | uint32_t Odid:24; |
860 | #define FARP_NO_ACTION 0 /* FARP information enclosed, no |
861 | action */ |
862 | #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ |
863 | #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ |
864 | #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ |
865 | #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not |
866 | supported */ |
867 | #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not |
868 | supported */ |
869 | uint32_t Rflags:8; |
870 | uint32_t Rdid:24; |
871 | #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ |
872 | #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ |
873 | struct lpfc_name OportName; |
874 | struct lpfc_name OnodeName; |
875 | struct lpfc_name RportName; |
876 | struct lpfc_name RnodeName; |
877 | uint8_t Oipaddr[16]; |
878 | uint8_t Ripaddr[16]; |
879 | } FARP; |
880 | |
881 | typedef struct _FAN { /* Structure is in Big Endian format */ |
882 | uint32_t Fdid; |
883 | struct lpfc_name FportName; |
884 | struct lpfc_name FnodeName; |
885 | } FAN; |
886 | |
887 | typedef struct _SCR { /* Structure is in Big Endian format */ |
888 | uint8_t resvd1; |
889 | uint8_t resvd2; |
890 | uint8_t resvd3; |
891 | uint8_t Function; |
892 | #define SCR_FUNC_FABRIC 0x01 |
893 | #define SCR_FUNC_NPORT 0x02 |
894 | #define SCR_FUNC_FULL 0x03 |
895 | #define SCR_CLEAR 0xff |
896 | } SCR; |
897 | |
898 | typedef struct _RNID_TOP_DISC { |
899 | struct lpfc_name portName; |
900 | uint8_t resvd[8]; |
901 | uint32_t unitType; |
902 | #define RNID_HBA 0x7 |
903 | #define RNID_HOST 0xa |
904 | #define RNID_DRIVER 0xd |
905 | uint32_t physPort; |
906 | uint32_t attachedNodes; |
907 | uint16_t ipVersion; |
908 | #define RNID_IPV4 0x1 |
909 | #define RNID_IPV6 0x2 |
910 | uint16_t UDPport; |
911 | uint8_t ipAddr[16]; |
912 | uint16_t resvd1; |
913 | uint16_t flags; |
914 | #define RNID_TD_SUPPORT 0x1 |
915 | #define RNID_LP_VALID 0x2 |
916 | } RNID_TOP_DISC; |
917 | |
918 | typedef struct _RNID { /* Structure is in Big Endian format */ |
919 | uint8_t Format; |
920 | #define RNID_TOPOLOGY_DISC 0xdf |
921 | uint8_t CommonLen; |
922 | uint8_t resvd1; |
923 | uint8_t SpecificLen; |
924 | struct lpfc_name portName; |
925 | struct lpfc_name nodeName; |
926 | union { |
927 | RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ |
928 | } un; |
929 | } RNID; |
930 | |
931 | struct RLS { /* Structure is in Big Endian format */ |
932 | uint32_t rls; |
933 | #define rls_rsvd_SHIFT 24 |
934 | #define rls_rsvd_MASK 0x000000ff |
935 | #define rls_rsvd_WORD rls |
936 | #define rls_did_SHIFT 0 |
937 | #define rls_did_MASK 0x00ffffff |
938 | #define rls_did_WORD rls |
939 | }; |
940 | |
941 | struct RLS_RSP { /* Structure is in Big Endian format */ |
942 | uint32_t linkFailureCnt; |
943 | uint32_t lossSyncCnt; |
944 | uint32_t lossSignalCnt; |
945 | uint32_t primSeqErrCnt; |
946 | uint32_t invalidXmitWord; |
947 | uint32_t crcCnt; |
948 | }; |
949 | |
950 | struct RRQ { /* Structure is in Big Endian format */ |
951 | uint32_t rrq; |
952 | #define rrq_rsvd_SHIFT 24 |
953 | #define rrq_rsvd_MASK 0x000000ff |
954 | #define rrq_rsvd_WORD rrq |
955 | #define rrq_did_SHIFT 0 |
956 | #define rrq_did_MASK 0x00ffffff |
957 | #define rrq_did_WORD rrq |
958 | uint32_t rrq_exchg; |
959 | #define rrq_oxid_SHIFT 16 |
960 | #define rrq_oxid_MASK 0xffff |
961 | #define rrq_oxid_WORD rrq_exchg |
962 | #define rrq_rxid_SHIFT 0 |
963 | #define rrq_rxid_MASK 0xffff |
964 | #define rrq_rxid_WORD rrq_exchg |
965 | }; |
966 | |
967 | #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ |
968 | #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ |
969 | |
970 | struct RTV_RSP { /* Structure is in Big Endian format */ |
971 | uint32_t ratov; |
972 | uint32_t edtov; |
973 | uint32_t qtov; |
974 | #define qtov_rsvd0_SHIFT 28 |
975 | #define qtov_rsvd0_MASK 0x0000000f |
976 | #define qtov_rsvd0_WORD qtov /* reserved */ |
977 | #define qtov_edtovres_SHIFT 27 |
978 | #define qtov_edtovres_MASK 0x00000001 |
979 | #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ |
980 | #define qtov__rsvd1_SHIFT 19 |
981 | #define qtov_rsvd1_MASK 0x0000003f |
982 | #define qtov_rsvd1_WORD qtov /* reserved */ |
983 | #define qtov_rttov_SHIFT 18 |
984 | #define qtov_rttov_MASK 0x00000001 |
985 | #define qtov_rttov_WORD qtov /* R_T_TOV value */ |
986 | #define qtov_rsvd2_SHIFT 0 |
987 | #define qtov_rsvd2_MASK 0x0003ffff |
988 | #define qtov_rsvd2_WORD qtov /* reserved */ |
989 | }; |
990 | |
991 | |
992 | typedef struct _RPL { /* Structure is in Big Endian format */ |
993 | uint32_t maxsize; |
994 | uint32_t index; |
995 | } RPL; |
996 | |
997 | typedef struct _PORT_NUM_BLK { |
998 | uint32_t portNum; |
999 | uint32_t portID; |
1000 | struct lpfc_name portName; |
1001 | } PORT_NUM_BLK; |
1002 | |
1003 | typedef struct _RPL_RSP { /* Structure is in Big Endian format */ |
1004 | uint32_t listLen; |
1005 | uint32_t index; |
1006 | PORT_NUM_BLK port_num_blk; |
1007 | } RPL_RSP; |
1008 | |
1009 | /* This is used for RSCN command */ |
1010 | typedef struct _D_ID { /* Structure is in Big Endian format */ |
1011 | union { |
1012 | uint32_t word; |
1013 | struct { |
1014 | #ifdef __BIG_ENDIAN_BITFIELD |
1015 | uint8_t resv; |
1016 | uint8_t domain; |
1017 | uint8_t area; |
1018 | uint8_t id; |
1019 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
1020 | uint8_t id; |
1021 | uint8_t area; |
1022 | uint8_t domain; |
1023 | uint8_t resv; |
1024 | #endif |
1025 | } b; |
1026 | } un; |
1027 | } D_ID; |
1028 | |
1029 | #define RSCN_ADDRESS_FORMAT_PORT 0x0 |
1030 | #define RSCN_ADDRESS_FORMAT_AREA 0x1 |
1031 | #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 |
1032 | #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 |
1033 | #define RSCN_ADDRESS_FORMAT_MASK 0x3 |
1034 | |
1035 | /* |
1036 | * Structure to define all ELS Payload types |
1037 | */ |
1038 | |
1039 | typedef struct _ELS_PKT { /* Structure is in Big Endian format */ |
1040 | uint8_t elsCode; /* FC Word 0, bit 24:31 */ |
1041 | uint8_t elsByte1; |
1042 | uint8_t elsByte2; |
1043 | uint8_t elsByte3; |
1044 | union { |
1045 | struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ |
1046 | struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ |
1047 | LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ |
1048 | PRLI prli; /* Payload for PRLI/ACC */ |
1049 | PRLO prlo; /* Payload for PRLO/ACC */ |
1050 | ADISC adisc; /* Payload for ADISC/ACC */ |
1051 | FARP farp; /* Payload for FARP/ACC */ |
1052 | FAN fan; /* Payload for FAN */ |
1053 | SCR scr; /* Payload for SCR/ACC */ |
1054 | RNID rnid; /* Payload for RNID */ |
1055 | uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ |
1056 | } un; |
1057 | } ELS_PKT; |
1058 | |
1059 | /* |
1060 | * Link Cable Beacon (LCB) ELS Frame |
1061 | */ |
1062 | |
1063 | struct fc_lcb_request_frame { |
1064 | uint32_t lcb_command; /* ELS command opcode (0x81) */ |
1065 | uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ |
1066 | #define LPFC_LCB_ON 0x1 |
1067 | #define LPFC_LCB_OFF 0x2 |
1068 | uint8_t reserved[2]; |
1069 | uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ |
1070 | uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ |
1071 | #define LPFC_LCB_GREEN 0x1 |
1072 | #define LPFC_LCB_AMBER 0x2 |
1073 | uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ |
1074 | #define LCB_CAPABILITY_DURATION 1 |
1075 | #define BEACON_VERSION_V1 1 |
1076 | #define BEACON_VERSION_V0 0 |
1077 | uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ |
1078 | }; |
1079 | |
1080 | /* |
1081 | * Link Cable Beacon (LCB) ELS Response Frame |
1082 | */ |
1083 | struct fc_lcb_res_frame { |
1084 | uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ |
1085 | uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ |
1086 | uint8_t reserved[2]; |
1087 | uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ |
1088 | uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ |
1089 | uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ |
1090 | uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ |
1091 | }; |
1092 | |
1093 | /* |
1094 | * Read Diagnostic Parameters (RDP) ELS frame. |
1095 | */ |
1096 | #define SFF_PG0_IDENT_SFP 0x3 |
1097 | |
1098 | #define SFP_FLAG_PT_OPTICAL 0x0 |
1099 | #define SFP_FLAG_PT_SWLASER 0x01 |
1100 | #define SFP_FLAG_PT_LWLASER_LC1310 0x02 |
1101 | #define SFP_FLAG_PT_LWLASER_LL1550 0x03 |
1102 | #define SFP_FLAG_PT_MASK 0x0F |
1103 | #define SFP_FLAG_PT_SHIFT 0 |
1104 | |
1105 | #define SFP_FLAG_IS_OPTICAL_PORT 0x01 |
1106 | #define SFP_FLAG_IS_OPTICAL_MASK 0x010 |
1107 | #define SFP_FLAG_IS_OPTICAL_SHIFT 4 |
1108 | |
1109 | #define SFP_FLAG_IS_DESC_VALID 0x01 |
1110 | #define SFP_FLAG_IS_DESC_VALID_MASK 0x020 |
1111 | #define SFP_FLAG_IS_DESC_VALID_SHIFT 5 |
1112 | |
1113 | #define SFP_FLAG_CT_UNKNOWN 0x0 |
1114 | #define SFP_FLAG_CT_SFP_PLUS 0x01 |
1115 | #define SFP_FLAG_CT_MASK 0x3C |
1116 | #define SFP_FLAG_CT_SHIFT 6 |
1117 | |
1118 | struct fc_rdp_port_name_info { |
1119 | uint8_t wwnn[8]; |
1120 | uint8_t wwpn[8]; |
1121 | }; |
1122 | |
1123 | |
1124 | /* |
1125 | * Link Error Status Block Structure (FC-FS-3) for RDP |
1126 | * This similar to RPS ELS |
1127 | */ |
1128 | struct fc_link_status { |
1129 | uint32_t link_failure_cnt; |
1130 | uint32_t loss_of_synch_cnt; |
1131 | uint32_t loss_of_signal_cnt; |
1132 | uint32_t primitive_seq_proto_err; |
1133 | uint32_t invalid_trans_word; |
1134 | uint32_t invalid_crc_cnt; |
1135 | |
1136 | }; |
1137 | |
1138 | #define RDP_PORT_NAMES_DESC_TAG 0x00010003 |
1139 | struct fc_rdp_port_name_desc { |
1140 | uint32_t tag; /* 0001 0003h */ |
1141 | uint32_t length; /* set to size of payload struct */ |
1142 | struct fc_rdp_port_name_info port_names; |
1143 | }; |
1144 | |
1145 | |
1146 | struct fc_rdp_fec_info { |
1147 | uint32_t CorrectedBlocks; |
1148 | uint32_t UncorrectableBlocks; |
1149 | }; |
1150 | |
1151 | #define RDP_FEC_DESC_TAG 0x00010005 |
1152 | struct fc_fec_rdp_desc { |
1153 | uint32_t tag; |
1154 | uint32_t length; |
1155 | struct fc_rdp_fec_info info; |
1156 | }; |
1157 | |
1158 | struct fc_rdp_link_error_status_payload_info { |
1159 | struct fc_link_status link_status; /* 24 bytes */ |
1160 | uint32_t port_type; /* bits 31-30 only */ |
1161 | }; |
1162 | |
1163 | #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002 |
1164 | struct fc_rdp_link_error_status_desc { |
1165 | uint32_t tag; /* 0001 0002h */ |
1166 | uint32_t length; /* set to size of payload struct */ |
1167 | struct fc_rdp_link_error_status_payload_info info; |
1168 | }; |
1169 | |
1170 | #define VN_PT_PHY_UNKNOWN 0x00 |
1171 | #define VN_PT_PHY_PF_PORT 0x01 |
1172 | #define VN_PT_PHY_ETH_MAC 0x10 |
1173 | #define VN_PT_PHY_SHIFT 30 |
1174 | |
1175 | #define RDP_PS_1GB 0x8000 |
1176 | #define RDP_PS_2GB 0x4000 |
1177 | #define RDP_PS_4GB 0x2000 |
1178 | #define RDP_PS_10GB 0x1000 |
1179 | #define RDP_PS_8GB 0x0800 |
1180 | #define RDP_PS_16GB 0x0400 |
1181 | #define RDP_PS_32GB 0x0200 |
1182 | #define RDP_PS_64GB 0x0100 |
1183 | #define RDP_PS_128GB 0x0080 |
1184 | #define RDP_PS_256GB 0x0040 |
1185 | |
1186 | #define RDP_CAP_USER_CONFIGURED 0x0002 |
1187 | #define RDP_CAP_UNKNOWN 0x0001 |
1188 | #define RDP_PS_UNKNOWN 0x0002 |
1189 | #define RDP_PS_NOT_ESTABLISHED 0x0001 |
1190 | |
1191 | struct fc_rdp_port_speed { |
1192 | uint16_t capabilities; |
1193 | uint16_t speed; |
1194 | }; |
1195 | |
1196 | struct fc_rdp_port_speed_info { |
1197 | struct fc_rdp_port_speed port_speed; |
1198 | }; |
1199 | |
1200 | #define RDP_PORT_SPEED_DESC_TAG 0x00010001 |
1201 | struct fc_rdp_port_speed_desc { |
1202 | uint32_t tag; /* 00010001h */ |
1203 | uint32_t length; /* set to size of payload struct */ |
1204 | struct fc_rdp_port_speed_info info; |
1205 | }; |
1206 | |
1207 | #define RDP_NPORT_ID_SIZE 4 |
1208 | #define RDP_N_PORT_DESC_TAG 0x00000003 |
1209 | struct fc_rdp_nport_desc { |
1210 | uint32_t tag; /* 0000 0003h, big endian */ |
1211 | uint32_t length; /* size of RDP_N_PORT_ID struct */ |
1212 | uint32_t nport_id : 12; |
1213 | uint32_t reserved : 8; |
1214 | }; |
1215 | |
1216 | |
1217 | struct fc_rdp_link_service_info { |
1218 | uint32_t els_req; /* Request payload word 0 value.*/ |
1219 | }; |
1220 | |
1221 | #define RDP_LINK_SERVICE_DESC_TAG 0x00000001 |
1222 | struct fc_rdp_link_service_desc { |
1223 | uint32_t tag; /* Descriptor tag 1 */ |
1224 | uint32_t length; /* set to size of payload struct. */ |
1225 | struct fc_rdp_link_service_info payload; |
1226 | /* must be ELS req Word 0(0x18) */ |
1227 | }; |
1228 | |
1229 | struct fc_rdp_sfp_info { |
1230 | uint16_t temperature; |
1231 | uint16_t vcc; |
1232 | uint16_t tx_bias; |
1233 | uint16_t tx_power; |
1234 | uint16_t rx_power; |
1235 | uint16_t flags; |
1236 | }; |
1237 | |
1238 | #define RDP_SFP_DESC_TAG 0x00010000 |
1239 | struct fc_rdp_sfp_desc { |
1240 | uint32_t tag; |
1241 | uint32_t length; /* set to size of sfp_info struct */ |
1242 | struct fc_rdp_sfp_info sfp_info; |
1243 | }; |
1244 | |
1245 | /* Buffer Credit Descriptor */ |
1246 | struct fc_rdp_bbc_info { |
1247 | uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ |
1248 | uint32_t attached_port_bbc; |
1249 | uint32_t rtt; /* Round trip time */ |
1250 | }; |
1251 | #define RDP_BBC_DESC_TAG 0x00010006 |
1252 | struct fc_rdp_bbc_desc { |
1253 | uint32_t tag; |
1254 | uint32_t length; |
1255 | struct fc_rdp_bbc_info bbc_info; |
1256 | }; |
1257 | |
1258 | /* Optical Element Type Transgression Flags */ |
1259 | #define RDP_OET_LOW_WARNING 0x1 |
1260 | #define RDP_OET_HIGH_WARNING 0x2 |
1261 | #define RDP_OET_LOW_ALARM 0x4 |
1262 | #define RDP_OET_HIGH_ALARM 0x8 |
1263 | |
1264 | #define RDP_OED_TEMPERATURE 0x1 |
1265 | #define RDP_OED_VOLTAGE 0x2 |
1266 | #define RDP_OED_TXBIAS 0x3 |
1267 | #define RDP_OED_TXPOWER 0x4 |
1268 | #define RDP_OED_RXPOWER 0x5 |
1269 | |
1270 | #define RDP_OED_TYPE_SHIFT 28 |
1271 | /* Optical Element Data descriptor */ |
1272 | struct fc_rdp_oed_info { |
1273 | uint16_t hi_alarm; |
1274 | uint16_t lo_alarm; |
1275 | uint16_t hi_warning; |
1276 | uint16_t lo_warning; |
1277 | uint32_t function_flags; |
1278 | }; |
1279 | #define RDP_OED_DESC_TAG 0x00010007 |
1280 | struct fc_rdp_oed_sfp_desc { |
1281 | uint32_t tag; |
1282 | uint32_t length; |
1283 | struct fc_rdp_oed_info oed_info; |
1284 | }; |
1285 | |
1286 | /* Optical Product Data descriptor */ |
1287 | struct fc_rdp_opd_sfp_info { |
1288 | uint8_t vendor_name[16]; |
1289 | uint8_t model_number[16]; |
1290 | uint8_t serial_number[16]; |
1291 | uint8_t revision[4]; |
1292 | uint8_t date[8]; |
1293 | }; |
1294 | |
1295 | #define RDP_OPD_DESC_TAG 0x00010008 |
1296 | struct fc_rdp_opd_sfp_desc { |
1297 | uint32_t tag; |
1298 | uint32_t length; |
1299 | struct fc_rdp_opd_sfp_info opd_info; |
1300 | }; |
1301 | |
1302 | struct fc_rdp_req_frame { |
1303 | uint32_t rdp_command; /* ELS command opcode (0x18)*/ |
1304 | uint32_t rdp_des_length; /* RDP Payload Word 1 */ |
1305 | struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */ |
1306 | }; |
1307 | |
1308 | |
1309 | struct fc_rdp_res_frame { |
1310 | uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ |
1311 | uint32_t length; /* FC Word 1 */ |
1312 | struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */ |
1313 | struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */ |
1314 | struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */ |
1315 | struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */ |
1316 | struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */ |
1317 | struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */ |
1318 | struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/ |
1319 | struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/ |
1320 | struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/ |
1321 | struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/ |
1322 | struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/ |
1323 | struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/ |
1324 | struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/ |
1325 | struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/ |
1326 | }; |
1327 | |
1328 | |
1329 | /* UVEM */ |
1330 | |
1331 | #define LPFC_UVEM_SIZE 60 |
1332 | #define LPFC_UVEM_VEM_ID_DESC_SIZE 16 |
1333 | #define LPFC_UVEM_VE_MAP_DESC_SIZE 20 |
1334 | |
1335 | #define VEM_ID_DESC_TAG 0x0001000A |
1336 | struct lpfc_vem_id_desc { |
1337 | uint32_t tag; |
1338 | uint32_t length; |
1339 | uint8_t vem_id[16]; |
1340 | }; |
1341 | |
1342 | #define LPFC_QFPA_SIZE 4 |
1343 | |
1344 | #define INSTANTIATED_VE_DESC_TAG 0x0001000B |
1345 | struct instantiated_ve_desc { |
1346 | uint32_t tag; |
1347 | uint32_t length; |
1348 | uint8_t global_vem_id[16]; |
1349 | uint32_t word6; |
1350 | #define lpfc_instantiated_local_id_SHIFT 0 |
1351 | #define lpfc_instantiated_local_id_MASK 0x000000ff |
1352 | #define lpfc_instantiated_local_id_WORD word6 |
1353 | #define lpfc_instantiated_nport_id_SHIFT 8 |
1354 | #define lpfc_instantiated_nport_id_MASK 0x00ffffff |
1355 | #define lpfc_instantiated_nport_id_WORD word6 |
1356 | }; |
1357 | |
1358 | #define DEINSTANTIATED_VE_DESC_TAG 0x0001000C |
1359 | struct deinstantiated_ve_desc { |
1360 | uint32_t tag; |
1361 | uint32_t length; |
1362 | uint8_t global_vem_id[16]; |
1363 | uint32_t word6; |
1364 | #define lpfc_deinstantiated_nport_id_SHIFT 0 |
1365 | #define lpfc_deinstantiated_nport_id_MASK 0x000000ff |
1366 | #define lpfc_deinstantiated_nport_id_WORD word6 |
1367 | #define lpfc_deinstantiated_local_id_SHIFT 24 |
1368 | #define lpfc_deinstantiated_local_id_MASK 0x00ffffff |
1369 | #define lpfc_deinstantiated_local_id_WORD word6 |
1370 | }; |
1371 | |
1372 | /* Query Fabric Priority Allocation Response */ |
1373 | #define LPFC_PRIORITY_RANGE_DESC_SIZE 12 |
1374 | |
1375 | struct priority_range_desc { |
1376 | uint32_t tag; |
1377 | uint32_t length; |
1378 | uint8_t lo_range; |
1379 | uint8_t hi_range; |
1380 | uint8_t qos_priority; |
1381 | uint8_t local_ve_id; |
1382 | }; |
1383 | |
1384 | struct fc_qfpa_res { |
1385 | uint32_t reply_sequence; /* LS_ACC or LS_RJT */ |
1386 | uint32_t length; /* FC Word 1 */ |
1387 | struct priority_range_desc desc[1]; |
1388 | }; |
1389 | |
1390 | /* Application Server command code */ |
1391 | /* VMID */ |
1392 | |
1393 | #define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */ |
1394 | |
1395 | #define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */ |
1396 | #define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */ |
1397 | #define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */ |
1398 | /* for Nport */ |
1399 | #define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */ |
1400 | /* for Nport */ |
1401 | #define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */ |
1402 | #define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */ |
1403 | /* Identifier */ |
1404 | #define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */ |
1405 | /* Identifier */ |
1406 | |
1407 | struct entity_id_object { |
1408 | uint8_t entity_id_len; |
1409 | uint8_t entity_id[255]; /* VM UUID */ |
1410 | }; |
1411 | |
1412 | struct app_id_object { |
1413 | __be32 port_id; |
1414 | __be32 app_id; |
1415 | struct entity_id_object obj; |
1416 | }; |
1417 | |
1418 | struct lpfc_vmid_rapp_ident_list { |
1419 | __be32 no_of_objects; |
1420 | struct entity_id_object obj[]; |
1421 | }; |
1422 | |
1423 | struct lpfc_vmid_dapp_ident_list { |
1424 | __be32 no_of_objects; |
1425 | struct entity_id_object obj[]; |
1426 | }; |
1427 | |
1428 | #define GALLAPPIA_ID_LAST 0x80 |
1429 | struct lpfc_vmid_gallapp_ident_list { |
1430 | uint8_t control; |
1431 | uint8_t reserved[3]; |
1432 | struct app_id_object app_id; |
1433 | }; |
1434 | |
1435 | #define RAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) |
1436 | #define DAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) |
1437 | #define GALLAPPIA_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) |
1438 | #define DALLAPP_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) |
1439 | |
1440 | /******** FDMI ********/ |
1441 | |
1442 | /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ |
1443 | #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ |
1444 | |
1445 | /* Definitions for HBA / Port attribute entries */ |
1446 | |
1447 | /* Attribute Entry Structures */ |
1448 | |
1449 | struct lpfc_fdmi_attr_u32 { |
1450 | __be16 type; |
1451 | __be16 len; |
1452 | __be32 value_u32; |
1453 | }; |
1454 | |
1455 | struct lpfc_fdmi_attr_wwn { |
1456 | __be16 type; |
1457 | __be16 len; |
1458 | |
1459 | /* Keep as u8[8] instead of __be64 to avoid accidental zero padding |
1460 | * by compiler |
1461 | */ |
1462 | u8 name[8]; |
1463 | }; |
1464 | |
1465 | struct lpfc_fdmi_attr_fullwwn { |
1466 | __be16 type; |
1467 | __be16 len; |
1468 | |
1469 | /* Keep as u8[8] instead of __be64 to avoid accidental zero padding |
1470 | * by compiler |
1471 | */ |
1472 | u8 nname[8]; |
1473 | u8 pname[8]; |
1474 | }; |
1475 | |
1476 | struct lpfc_fdmi_attr_fc4types { |
1477 | __be16 type; |
1478 | __be16 len; |
1479 | u8 value_types[32]; |
1480 | }; |
1481 | |
1482 | struct lpfc_fdmi_attr_string { |
1483 | __be16 type; |
1484 | __be16 len; |
1485 | char value_string[256]; |
1486 | }; |
1487 | |
1488 | /* Maximum FDMI attribute length is Type+Len (4 bytes) + 256 byte string */ |
1489 | #define FDMI_MAX_ATTRLEN sizeof(struct lpfc_fdmi_attr_string) |
1490 | |
1491 | /* |
1492 | * HBA Attribute Block |
1493 | */ |
1494 | struct lpfc_fdmi_attr_block { |
1495 | uint32_t EntryCnt; /* Number of HBA attribute entries */ |
1496 | /* Variable Length Attribute Entry TLV's follow */ |
1497 | }; |
1498 | |
1499 | /* |
1500 | * Port Entry |
1501 | */ |
1502 | struct lpfc_fdmi_port_entry { |
1503 | struct lpfc_name PortName; |
1504 | }; |
1505 | |
1506 | /* |
1507 | * HBA Identifier |
1508 | */ |
1509 | struct lpfc_fdmi_hba_ident { |
1510 | struct lpfc_name PortName; |
1511 | }; |
1512 | |
1513 | /* |
1514 | * Registered Port List Format |
1515 | */ |
1516 | struct lpfc_fdmi_reg_port_list { |
1517 | __be32 EntryCnt; |
1518 | struct lpfc_fdmi_port_entry pe; |
1519 | }; |
1520 | |
1521 | /* |
1522 | * Register HBA(RHBA) |
1523 | */ |
1524 | struct lpfc_fdmi_reg_hba { |
1525 | struct lpfc_fdmi_hba_ident hi; |
1526 | struct lpfc_fdmi_reg_port_list rpl; |
1527 | }; |
1528 | |
1529 | /******** MI MIB ********/ |
1530 | #define SLI_CT_MIB_Subtypes 0x11 |
1531 | |
1532 | /* |
1533 | * Register HBA Attributes (RHAT) |
1534 | */ |
1535 | struct lpfc_fdmi_reg_hbaattr { |
1536 | struct lpfc_name HBA_PortName; |
1537 | struct lpfc_fdmi_attr_block ab; |
1538 | }; |
1539 | |
1540 | /* |
1541 | * Register Port Attributes (RPA) |
1542 | */ |
1543 | struct lpfc_fdmi_reg_portattr { |
1544 | struct lpfc_name PortName; |
1545 | struct lpfc_fdmi_attr_block ab; |
1546 | }; |
1547 | |
1548 | /* |
1549 | * HBA MAnagement Operations Command Codes |
1550 | */ |
1551 | #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ |
1552 | #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ |
1553 | #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ |
1554 | #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ |
1555 | #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ |
1556 | #define SLI_MGMT_RHBA 0x200 /* Register HBA */ |
1557 | #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ |
1558 | #define SLI_MGMT_RPRT 0x210 /* Register Port */ |
1559 | #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ |
1560 | #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ |
1561 | #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ |
1562 | #define SLI_MGMT_DPRT 0x310 /* De-register Port */ |
1563 | #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ |
1564 | |
1565 | #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */ |
1566 | |
1567 | /* |
1568 | * HBA Attribute Types |
1569 | */ |
1570 | #define RHBA_NODENAME 0x1 /* 8 byte WWNN */ |
1571 | #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ |
1572 | #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ |
1573 | #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ |
1574 | #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ |
1575 | #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ |
1576 | #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ |
1577 | #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ |
1578 | #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ |
1579 | #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ |
1580 | #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ |
1581 | #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ |
1582 | #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */ |
1583 | #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */ |
1584 | #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */ |
1585 | #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */ |
1586 | #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */ |
1587 | #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */ |
1588 | |
1589 | /* Bit mask for all individual HBA attributes */ |
1590 | #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001 |
1591 | #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002 |
1592 | #define LPFC_FDMI_HBA_ATTR_sn 0x00000004 |
1593 | #define LPFC_FDMI_HBA_ATTR_model 0x00000008 |
1594 | #define LPFC_FDMI_HBA_ATTR_description 0x00000010 |
1595 | #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020 |
1596 | #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040 |
1597 | #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080 |
1598 | #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100 |
1599 | #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200 |
1600 | #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400 |
1601 | #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800 |
1602 | #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */ |
1603 | #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000 |
1604 | #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000 |
1605 | #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000 |
1606 | #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */ |
1607 | #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000 |
1608 | |
1609 | /* Bit mask for FDMI-1 defined HBA attributes */ |
1610 | #define LPFC_FDMI1_HBA_ATTR 0x000007ff |
1611 | |
1612 | /* Bit mask for FDMI-2 defined HBA attributes */ |
1613 | /* Skip vendor_info and bios_state */ |
1614 | #define LPFC_FDMI2_HBA_ATTR 0x0002efff |
1615 | |
1616 | /* |
1617 | * Port Attribute Types |
1618 | */ |
1619 | #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ |
1620 | #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ |
1621 | #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ |
1622 | #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ |
1623 | #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ |
1624 | #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ |
1625 | #define RPRT_NODENAME 0x7 /* 8 byte WWNN */ |
1626 | #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */ |
1627 | #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ |
1628 | #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ |
1629 | #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ |
1630 | #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */ |
1631 | #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ |
1632 | #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ |
1633 | #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ |
1634 | #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ |
1635 | #define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */ |
1636 | #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */ |
1637 | #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */ |
1638 | #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */ |
1639 | #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */ |
1640 | #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */ |
1641 | #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */ |
1642 | #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */ |
1643 | |
1644 | /* Bit mask for all individual PORT attributes */ |
1645 | #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001 |
1646 | #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002 |
1647 | #define LPFC_FDMI_PORT_ATTR_speed 0x00000004 |
1648 | #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008 |
1649 | #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010 |
1650 | #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020 |
1651 | #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040 |
1652 | #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080 |
1653 | #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100 |
1654 | #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200 |
1655 | #define LPFC_FDMI_PORT_ATTR_class 0x00000400 |
1656 | #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800 |
1657 | #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000 |
1658 | #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000 |
1659 | #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000 |
1660 | #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000 |
1661 | #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */ |
1662 | #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */ |
1663 | #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */ |
1664 | #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */ |
1665 | #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */ |
1666 | #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */ |
1667 | #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */ |
1668 | #define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */ |
1669 | |
1670 | /* Bit mask for FDMI-1 defined PORT attributes */ |
1671 | #define LPFC_FDMI1_PORT_ATTR 0x0000003f |
1672 | |
1673 | /* Bit mask for FDMI-2 defined PORT attributes */ |
1674 | #define LPFC_FDMI2_PORT_ATTR 0x0000ffff |
1675 | |
1676 | /* Bit mask for Smart SAN defined PORT attributes */ |
1677 | #define LPFC_FDMI2_SMART_ATTR 0x007fffff |
1678 | |
1679 | /* Defines for PORT port state attribute */ |
1680 | #define LPFC_FDMI_PORTSTATE_UNKNOWN 1 |
1681 | #define LPFC_FDMI_PORTSTATE_ONLINE 2 |
1682 | |
1683 | /* Defines for PORT port type attribute */ |
1684 | #define LPFC_FDMI_PORTTYPE_UNKNOWN 0 |
1685 | #define LPFC_FDMI_PORTTYPE_NPORT 1 |
1686 | #define LPFC_FDMI_PORTTYPE_NLPORT 2 |
1687 | |
1688 | /* |
1689 | * Begin HBA configuration parameters. |
1690 | * The PCI configuration register BAR assignments are: |
1691 | * BAR0, offset 0x10 - SLIM base memory address |
1692 | * BAR1, offset 0x14 - SLIM base memory high address |
1693 | * BAR2, offset 0x18 - REGISTER base memory address |
1694 | * BAR3, offset 0x1c - REGISTER base memory high address |
1695 | * BAR4, offset 0x20 - BIU I/O registers |
1696 | * BAR5, offset 0x24 - REGISTER base io high address |
1697 | */ |
1698 | |
1699 | /* Number of rings currently used and available. */ |
1700 | #define MAX_SLI3_CONFIGURED_RINGS 3 |
1701 | #define MAX_SLI3_RINGS 4 |
1702 | |
1703 | /* IOCB / Mailbox is owned by FireFly */ |
1704 | #define OWN_CHIP 1 |
1705 | |
1706 | /* IOCB / Mailbox is owned by Host */ |
1707 | #define OWN_HOST 0 |
1708 | |
1709 | /* Number of 4-byte words in an IOCB. */ |
1710 | #define IOCB_WORD_SZ 8 |
1711 | |
1712 | /* network headers for Dfctl field */ |
1713 | #define FC_NET_HDR 0x20 |
1714 | |
1715 | /* Start FireFly Register definitions */ |
1716 | #define PCI_VENDOR_ID_EMULEX 0x10df |
1717 | #define PCI_DEVICE_ID_FIREFLY 0x1ae5 |
1718 | #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 |
1719 | #define PCI_DEVICE_ID_BALIUS 0xe131 |
1720 | #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 |
1721 | #define PCI_DEVICE_ID_LANCER_FC 0xe200 |
1722 | #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 |
1723 | #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 |
1724 | #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 |
1725 | #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 |
1726 | #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400 |
1727 | #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500 |
1728 | #define PCI_DEVICE_ID_SAT_SMB 0xf011 |
1729 | #define PCI_DEVICE_ID_SAT_MID 0xf015 |
1730 | #define PCI_DEVICE_ID_RFLY 0xf095 |
1731 | #define PCI_DEVICE_ID_PFLY 0xf098 |
1732 | #define PCI_DEVICE_ID_LP101 0xf0a1 |
1733 | #define PCI_DEVICE_ID_TFLY 0xf0a5 |
1734 | #define PCI_DEVICE_ID_BSMB 0xf0d1 |
1735 | #define PCI_DEVICE_ID_BMID 0xf0d5 |
1736 | #define PCI_DEVICE_ID_ZSMB 0xf0e1 |
1737 | #define PCI_DEVICE_ID_ZMID 0xf0e5 |
1738 | #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 |
1739 | #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 |
1740 | #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 |
1741 | #define PCI_DEVICE_ID_SAT 0xf100 |
1742 | #define PCI_DEVICE_ID_SAT_SCSP 0xf111 |
1743 | #define PCI_DEVICE_ID_SAT_DCSP 0xf112 |
1744 | #define PCI_DEVICE_ID_FALCON 0xf180 |
1745 | #define PCI_DEVICE_ID_SUPERFLY 0xf700 |
1746 | #define PCI_DEVICE_ID_DRAGONFLY 0xf800 |
1747 | #define PCI_DEVICE_ID_CENTAUR 0xf900 |
1748 | #define PCI_DEVICE_ID_PEGASUS 0xf980 |
1749 | #define PCI_DEVICE_ID_THOR 0xfa00 |
1750 | #define PCI_DEVICE_ID_VIPER 0xfb00 |
1751 | #define PCI_DEVICE_ID_LP10000S 0xfc00 |
1752 | #define PCI_DEVICE_ID_LP11000S 0xfc10 |
1753 | #define PCI_DEVICE_ID_LPE11000S 0xfc20 |
1754 | #define PCI_DEVICE_ID_SAT_S 0xfc40 |
1755 | #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 |
1756 | #define PCI_DEVICE_ID_HELIOS 0xfd00 |
1757 | #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 |
1758 | #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 |
1759 | #define PCI_DEVICE_ID_ZEPHYR 0xfe00 |
1760 | #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 |
1761 | #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 |
1762 | #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 |
1763 | #define PCI_DEVICE_ID_TIGERSHARK 0x0704 |
1764 | #define PCI_DEVICE_ID_TOMCAT 0x0714 |
1765 | #define PCI_DEVICE_ID_SKYHAWK 0x0724 |
1766 | #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c |
1767 | #define PCI_VENDOR_ID_ATTO 0x117c |
1768 | #define PCI_DEVICE_ID_CLRY_16XE 0x0064 |
1769 | #define PCI_DEVICE_ID_CLRY_161E 0x0063 |
1770 | #define PCI_DEVICE_ID_CLRY_162E 0x0064 |
1771 | #define PCI_DEVICE_ID_CLRY_164E 0x0065 |
1772 | #define PCI_DEVICE_ID_CLRY_16XP 0x0094 |
1773 | #define PCI_DEVICE_ID_CLRY_161P 0x00a0 |
1774 | #define PCI_DEVICE_ID_CLRY_162P 0x0094 |
1775 | #define PCI_DEVICE_ID_CLRY_164P 0x00a1 |
1776 | #define PCI_DEVICE_ID_CLRY_32XE 0x0094 |
1777 | #define PCI_DEVICE_ID_CLRY_321E 0x00a2 |
1778 | #define PCI_DEVICE_ID_CLRY_322E 0x00a3 |
1779 | #define PCI_DEVICE_ID_CLRY_324E 0x00ac |
1780 | #define PCI_DEVICE_ID_CLRY_32XP 0x00bb |
1781 | #define PCI_DEVICE_ID_CLRY_321P 0x00bc |
1782 | #define PCI_DEVICE_ID_CLRY_322P 0x00bd |
1783 | #define PCI_DEVICE_ID_CLRY_324P 0x00be |
1784 | #define PCI_DEVICE_ID_TLFC_2 0x0064 |
1785 | #define PCI_DEVICE_ID_TLFC_2XX2 0x4064 |
1786 | #define PCI_DEVICE_ID_TLFC_3 0x0094 |
1787 | #define PCI_DEVICE_ID_TLFC_3162 0x40a6 |
1788 | #define PCI_DEVICE_ID_TLFC_3322 0x40a7 |
1789 | |
1790 | #define JEDEC_ID_ADDRESS 0x0080001c |
1791 | #define FIREFLY_JEDEC_ID 0x1ACC |
1792 | #define SUPERFLY_JEDEC_ID 0x0020 |
1793 | #define DRAGONFLY_JEDEC_ID 0x0021 |
1794 | #define DRAGONFLY_V2_JEDEC_ID 0x0025 |
1795 | #define CENTAUR_2G_JEDEC_ID 0x0026 |
1796 | #define CENTAUR_1G_JEDEC_ID 0x0028 |
1797 | #define PEGASUS_ORION_JEDEC_ID 0x0036 |
1798 | #define PEGASUS_JEDEC_ID 0x0038 |
1799 | #define THOR_JEDEC_ID 0x0012 |
1800 | #define HELIOS_JEDEC_ID 0x0364 |
1801 | #define ZEPHYR_JEDEC_ID 0x0577 |
1802 | #define VIPER_JEDEC_ID 0x4838 |
1803 | #define SATURN_JEDEC_ID 0x1004 |
1804 | |
1805 | #define JEDEC_ID_MASK 0x0FFFF000 |
1806 | #define JEDEC_ID_SHIFT 12 |
1807 | #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) |
1808 | |
1809 | typedef struct { /* FireFly BIU registers */ |
1810 | uint32_t hostAtt; /* See definitions for Host Attention |
1811 | register */ |
1812 | uint32_t chipAtt; /* See definitions for Chip Attention |
1813 | register */ |
1814 | uint32_t hostStatus; /* See definitions for Host Status register */ |
1815 | uint32_t hostControl; /* See definitions for Host Control register */ |
1816 | uint32_t buiConfig; /* See definitions for BIU configuration |
1817 | register */ |
1818 | } FF_REGS; |
1819 | |
1820 | /* IO Register size in bytes */ |
1821 | #define FF_REG_AREA_SIZE 256 |
1822 | |
1823 | /* Host Attention Register */ |
1824 | |
1825 | #define HA_REG_OFFSET 0 /* Byte offset from register base address */ |
1826 | |
1827 | #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ |
1828 | #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ |
1829 | #define HA_R0ATT 0x00000008 /* Bit 3 */ |
1830 | #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ |
1831 | #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ |
1832 | #define HA_R1ATT 0x00000080 /* Bit 7 */ |
1833 | #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ |
1834 | #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ |
1835 | #define HA_R2ATT 0x00000800 /* Bit 11 */ |
1836 | #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ |
1837 | #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ |
1838 | #define HA_R3ATT 0x00008000 /* Bit 15 */ |
1839 | #define HA_LATT 0x20000000 /* Bit 29 */ |
1840 | #define HA_MBATT 0x40000000 /* Bit 30 */ |
1841 | #define HA_ERATT 0x80000000 /* Bit 31 */ |
1842 | |
1843 | #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ |
1844 | #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ |
1845 | #define HA_RXATT 0x00000008 /* Bit 3 */ |
1846 | #define HA_RXMASK 0x0000000f |
1847 | |
1848 | #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) |
1849 | #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) |
1850 | #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) |
1851 | #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) |
1852 | |
1853 | #define HA_R0_POS 3 |
1854 | #define HA_R1_POS 7 |
1855 | #define HA_R2_POS 11 |
1856 | #define HA_R3_POS 15 |
1857 | #define HA_LE_POS 29 |
1858 | #define HA_MB_POS 30 |
1859 | #define HA_ER_POS 31 |
1860 | /* Chip Attention Register */ |
1861 | |
1862 | #define CA_REG_OFFSET 4 /* Byte offset from register base address */ |
1863 | |
1864 | #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ |
1865 | #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ |
1866 | #define CA_R0ATT 0x00000008 /* Bit 3 */ |
1867 | #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ |
1868 | #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ |
1869 | #define CA_R1ATT 0x00000080 /* Bit 7 */ |
1870 | #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ |
1871 | #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ |
1872 | #define CA_R2ATT 0x00000800 /* Bit 11 */ |
1873 | #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ |
1874 | #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ |
1875 | #define CA_R3ATT 0x00008000 /* Bit 15 */ |
1876 | #define CA_MBATT 0x40000000 /* Bit 30 */ |
1877 | |
1878 | /* Host Status Register */ |
1879 | |
1880 | #define HS_REG_OFFSET 8 /* Byte offset from register base address */ |
1881 | |
1882 | #define HS_MBRDY 0x00400000 /* Bit 22 */ |
1883 | #define HS_FFRDY 0x00800000 /* Bit 23 */ |
1884 | #define HS_FFER8 0x01000000 /* Bit 24 */ |
1885 | #define HS_FFER7 0x02000000 /* Bit 25 */ |
1886 | #define HS_FFER6 0x04000000 /* Bit 26 */ |
1887 | #define HS_FFER5 0x08000000 /* Bit 27 */ |
1888 | #define HS_FFER4 0x10000000 /* Bit 28 */ |
1889 | #define HS_FFER3 0x20000000 /* Bit 29 */ |
1890 | #define HS_FFER2 0x40000000 /* Bit 30 */ |
1891 | #define HS_FFER1 0x80000000 /* Bit 31 */ |
1892 | #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ |
1893 | #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ |
1894 | #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ |
1895 | /* Host Control Register */ |
1896 | |
1897 | #define HC_REG_OFFSET 12 /* Byte offset from register base address */ |
1898 | |
1899 | #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ |
1900 | #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ |
1901 | #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ |
1902 | #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ |
1903 | #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ |
1904 | #define HC_INITHBI 0x02000000 /* Bit 25 */ |
1905 | #define HC_INITMB 0x04000000 /* Bit 26 */ |
1906 | #define HC_INITFF 0x08000000 /* Bit 27 */ |
1907 | #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ |
1908 | #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ |
1909 | |
1910 | /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ |
1911 | #define MSIX_DFLT_ID 0 |
1912 | #define MSIX_RNG0_ID 0 |
1913 | #define MSIX_RNG1_ID 1 |
1914 | #define MSIX_RNG2_ID 2 |
1915 | #define MSIX_RNG3_ID 3 |
1916 | |
1917 | #define MSIX_LINK_ID 4 |
1918 | #define MSIX_MBOX_ID 5 |
1919 | |
1920 | #define MSIX_SPARE0_ID 6 |
1921 | #define MSIX_SPARE1_ID 7 |
1922 | |
1923 | /* Mailbox Commands */ |
1924 | #define MBX_SHUTDOWN 0x00 /* terminate testing */ |
1925 | #define MBX_LOAD_SM 0x01 |
1926 | #define MBX_READ_NV 0x02 |
1927 | #define MBX_WRITE_NV 0x03 |
1928 | #define MBX_RUN_BIU_DIAG 0x04 |
1929 | #define MBX_INIT_LINK 0x05 |
1930 | #define MBX_DOWN_LINK 0x06 |
1931 | #define MBX_CONFIG_LINK 0x07 |
1932 | #define MBX_CONFIG_RING 0x09 |
1933 | #define MBX_RESET_RING 0x0A |
1934 | #define MBX_READ_CONFIG 0x0B |
1935 | #define MBX_READ_RCONFIG 0x0C |
1936 | #define MBX_READ_SPARM 0x0D |
1937 | #define MBX_READ_STATUS 0x0E |
1938 | #define MBX_READ_RPI 0x0F |
1939 | #define MBX_READ_XRI 0x10 |
1940 | #define MBX_READ_REV 0x11 |
1941 | #define MBX_READ_LNK_STAT 0x12 |
1942 | #define MBX_REG_LOGIN 0x13 |
1943 | #define MBX_UNREG_LOGIN 0x14 |
1944 | #define MBX_CLEAR_LA 0x16 |
1945 | #define MBX_DUMP_MEMORY 0x17 |
1946 | #define MBX_DUMP_CONTEXT 0x18 |
1947 | #define MBX_RUN_DIAGS 0x19 |
1948 | #define MBX_RESTART 0x1A |
1949 | #define MBX_UPDATE_CFG 0x1B |
1950 | #define MBX_DOWN_LOAD 0x1C |
1951 | #define MBX_DEL_LD_ENTRY 0x1D |
1952 | #define MBX_RUN_PROGRAM 0x1E |
1953 | #define MBX_SET_MASK 0x20 |
1954 | #define MBX_SET_VARIABLE 0x21 |
1955 | #define MBX_UNREG_D_ID 0x23 |
1956 | #define MBX_KILL_BOARD 0x24 |
1957 | #define MBX_CONFIG_FARP 0x25 |
1958 | #define MBX_BEACON 0x2A |
1959 | #define MBX_CONFIG_MSI 0x30 |
1960 | #define MBX_HEARTBEAT 0x31 |
1961 | #define MBX_WRITE_VPARMS 0x32 |
1962 | #define MBX_ASYNCEVT_ENABLE 0x33 |
1963 | #define MBX_READ_EVENT_LOG_STATUS 0x37 |
1964 | #define MBX_READ_EVENT_LOG 0x38 |
1965 | #define MBX_WRITE_EVENT_LOG 0x39 |
1966 | |
1967 | #define MBX_PORT_CAPABILITIES 0x3B |
1968 | #define MBX_PORT_IOV_CONTROL 0x3C |
1969 | |
1970 | #define MBX_CONFIG_HBQ 0x7C |
1971 | #define MBX_LOAD_AREA 0x81 |
1972 | #define MBX_RUN_BIU_DIAG64 0x84 |
1973 | #define MBX_CONFIG_PORT 0x88 |
1974 | #define MBX_READ_SPARM64 0x8D |
1975 | #define MBX_READ_RPI64 0x8F |
1976 | #define MBX_REG_LOGIN64 0x93 |
1977 | #define MBX_READ_TOPOLOGY 0x95 |
1978 | #define MBX_REG_VPI 0x96 |
1979 | #define MBX_UNREG_VPI 0x97 |
1980 | |
1981 | #define MBX_WRITE_WWN 0x98 |
1982 | #define MBX_SET_DEBUG 0x99 |
1983 | #define MBX_LOAD_EXP_ROM 0x9C |
1984 | #define MBX_SLI4_CONFIG 0x9B |
1985 | #define MBX_SLI4_REQ_FTRS 0x9D |
1986 | #define MBX_MAX_CMDS 0x9E |
1987 | #define MBX_RESUME_RPI 0x9E |
1988 | #define MBX_SLI2_CMD_MASK 0x80 |
1989 | #define MBX_REG_VFI 0x9F |
1990 | #define MBX_REG_FCFI 0xA0 |
1991 | #define MBX_UNREG_VFI 0xA1 |
1992 | #define MBX_UNREG_FCFI 0xA2 |
1993 | #define MBX_INIT_VFI 0xA3 |
1994 | #define MBX_INIT_VPI 0xA4 |
1995 | #define MBX_ACCESS_VDATA 0xA5 |
1996 | #define MBX_REG_FCFI_MRQ 0xAF |
1997 | |
1998 | #define MBX_AUTH_PORT 0xF8 |
1999 | #define MBX_SECURITY_MGMT 0xF9 |
2000 | |
2001 | /* IOCB Commands */ |
2002 | |
2003 | #define CMD_RCV_SEQUENCE_CX 0x01 |
2004 | #define CMD_XMIT_SEQUENCE_CR 0x02 |
2005 | #define CMD_XMIT_SEQUENCE_CX 0x03 |
2006 | #define CMD_XMIT_BCAST_CN 0x04 |
2007 | #define CMD_XMIT_BCAST_CX 0x05 |
2008 | #define CMD_QUE_RING_BUF_CN 0x06 |
2009 | #define CMD_QUE_XRI_BUF_CX 0x07 |
2010 | #define CMD_IOCB_CONTINUE_CN 0x08 |
2011 | #define CMD_RET_XRI_BUF_CX 0x09 |
2012 | #define CMD_ELS_REQUEST_CR 0x0A |
2013 | #define CMD_ELS_REQUEST_CX 0x0B |
2014 | #define CMD_RCV_ELS_REQ_CX 0x0D |
2015 | #define CMD_ABORT_XRI_CN 0x0E |
2016 | #define CMD_ABORT_XRI_CX 0x0F |
2017 | #define CMD_CLOSE_XRI_CN 0x10 |
2018 | #define CMD_CLOSE_XRI_CX 0x11 |
2019 | #define CMD_CREATE_XRI_CR 0x12 |
2020 | #define CMD_CREATE_XRI_CX 0x13 |
2021 | #define CMD_GET_RPI_CN 0x14 |
2022 | #define CMD_XMIT_ELS_RSP_CX 0x15 |
2023 | #define CMD_GET_RPI_CR 0x16 |
2024 | #define CMD_XRI_ABORTED_CX 0x17 |
2025 | #define CMD_FCP_IWRITE_CR 0x18 |
2026 | #define CMD_FCP_IWRITE_CX 0x19 |
2027 | #define CMD_FCP_IREAD_CR 0x1A |
2028 | #define CMD_FCP_IREAD_CX 0x1B |
2029 | #define CMD_FCP_ICMND_CR 0x1C |
2030 | #define CMD_FCP_ICMND_CX 0x1D |
2031 | #define CMD_FCP_TSEND_CX 0x1F |
2032 | #define CMD_FCP_TRECEIVE_CX 0x21 |
2033 | #define CMD_FCP_TRSP_CX 0x23 |
2034 | #define CMD_FCP_AUTO_TRSP_CX 0x29 |
2035 | |
2036 | #define CMD_ADAPTER_MSG 0x20 |
2037 | #define CMD_ADAPTER_DUMP 0x22 |
2038 | |
2039 | /* SLI_2 IOCB Command Set */ |
2040 | |
2041 | #define CMD_ASYNC_STATUS 0x7C |
2042 | #define CMD_RCV_SEQUENCE64_CX 0x81 |
2043 | #define CMD_XMIT_SEQUENCE64_CR 0x82 |
2044 | #define CMD_XMIT_SEQUENCE64_CX 0x83 |
2045 | #define CMD_XMIT_BCAST64_CN 0x84 |
2046 | #define CMD_XMIT_BCAST64_CX 0x85 |
2047 | #define CMD_QUE_RING_BUF64_CN 0x86 |
2048 | #define CMD_QUE_XRI_BUF64_CX 0x87 |
2049 | #define CMD_IOCB_CONTINUE64_CN 0x88 |
2050 | #define CMD_RET_XRI_BUF64_CX 0x89 |
2051 | #define CMD_ELS_REQUEST64_CR 0x8A |
2052 | #define CMD_ELS_REQUEST64_CX 0x8B |
2053 | #define CMD_ABORT_MXRI64_CN 0x8C |
2054 | #define CMD_RCV_ELS_REQ64_CX 0x8D |
2055 | #define CMD_XMIT_ELS_RSP64_CX 0x95 |
2056 | #define CMD_XMIT_BLS_RSP64_CX 0x97 |
2057 | #define CMD_FCP_IWRITE64_CR 0x98 |
2058 | #define CMD_FCP_IWRITE64_CX 0x99 |
2059 | #define CMD_FCP_IREAD64_CR 0x9A |
2060 | #define CMD_FCP_IREAD64_CX 0x9B |
2061 | #define CMD_FCP_ICMND64_CR 0x9C |
2062 | #define CMD_FCP_ICMND64_CX 0x9D |
2063 | #define CMD_FCP_TSEND64_CX 0x9F |
2064 | #define CMD_FCP_TRECEIVE64_CX 0xA1 |
2065 | #define CMD_FCP_TRSP64_CX 0xA3 |
2066 | |
2067 | #define CMD_QUE_XRI64_CX 0xB3 |
2068 | #define CMD_IOCB_RCV_SEQ64_CX 0xB5 |
2069 | #define CMD_IOCB_RCV_ELS64_CX 0xB7 |
2070 | #define CMD_IOCB_RET_XRI64_CX 0xB9 |
2071 | #define CMD_IOCB_RCV_CONT64_CX 0xBB |
2072 | |
2073 | #define CMD_GEN_REQUEST64_CR 0xC2 |
2074 | #define CMD_GEN_REQUEST64_CX 0xC3 |
2075 | |
2076 | /* Unhandled SLI-3 Commands */ |
2077 | #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 |
2078 | #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 |
2079 | #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 |
2080 | #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD |
2081 | #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 |
2082 | #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA |
2083 | #define CMD_IOCB_RET_HBQE64_CN 0xCA |
2084 | #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC |
2085 | #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD |
2086 | #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF |
2087 | #define CMD_IOCB_LOGENTRY_CN 0x94 |
2088 | #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 |
2089 | |
2090 | /* Data Security SLI Commands */ |
2091 | #define DSSCMD_IWRITE64_CR 0xF8 |
2092 | #define DSSCMD_IWRITE64_CX 0xF9 |
2093 | #define DSSCMD_IREAD64_CR 0xFA |
2094 | #define DSSCMD_IREAD64_CX 0xFB |
2095 | |
2096 | #define CMD_MAX_IOCB_CMD 0xFB |
2097 | #define CMD_IOCB_MASK 0xff |
2098 | |
2099 | #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG |
2100 | iocb */ |
2101 | #define LPFC_MAX_ADPTMSG 32 /* max msg data */ |
2102 | /* |
2103 | * Define Status |
2104 | */ |
2105 | #define MBX_SUCCESS 0 |
2106 | #define MBXERR_NUM_RINGS 1 |
2107 | #define MBXERR_NUM_IOCBS 2 |
2108 | #define MBXERR_IOCBS_EXCEEDED 3 |
2109 | #define MBXERR_BAD_RING_NUMBER 4 |
2110 | #define MBXERR_MASK_ENTRIES_RANGE 5 |
2111 | #define MBXERR_MASKS_EXCEEDED 6 |
2112 | #define MBXERR_BAD_PROFILE 7 |
2113 | #define MBXERR_BAD_DEF_CLASS 8 |
2114 | #define MBXERR_BAD_MAX_RESPONDER 9 |
2115 | #define MBXERR_BAD_MAX_ORIGINATOR 10 |
2116 | #define MBXERR_RPI_REGISTERED 11 |
2117 | #define MBXERR_RPI_FULL 12 |
2118 | #define MBXERR_NO_RESOURCES 13 |
2119 | #define MBXERR_BAD_RCV_LENGTH 14 |
2120 | #define MBXERR_DMA_ERROR 15 |
2121 | #define MBXERR_ERROR 16 |
2122 | #define MBXERR_LINK_DOWN 0x33 |
2123 | #define MBXERR_SEC_NO_PERMISSION 0xF02 |
2124 | #define MBX_NOT_FINISHED 255 |
2125 | |
2126 | #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ |
2127 | #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ |
2128 | |
2129 | #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ |
2130 | |
2131 | /* |
2132 | * return code Fail |
2133 | */ |
2134 | #define FAILURE 1 |
2135 | |
2136 | /* |
2137 | * Begin Structure Definitions for Mailbox Commands |
2138 | */ |
2139 | |
2140 | typedef struct { |
2141 | #ifdef __BIG_ENDIAN_BITFIELD |
2142 | uint8_t tval; |
2143 | uint8_t tmask; |
2144 | uint8_t rval; |
2145 | uint8_t rmask; |
2146 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2147 | uint8_t rmask; |
2148 | uint8_t rval; |
2149 | uint8_t tmask; |
2150 | uint8_t tval; |
2151 | #endif |
2152 | } RR_REG; |
2153 | |
2154 | struct ulp_bde { |
2155 | uint32_t bdeAddress; |
2156 | #ifdef __BIG_ENDIAN_BITFIELD |
2157 | uint32_t bdeReserved:4; |
2158 | uint32_t bdeAddrHigh:4; |
2159 | uint32_t bdeSize:24; |
2160 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2161 | uint32_t bdeSize:24; |
2162 | uint32_t bdeAddrHigh:4; |
2163 | uint32_t bdeReserved:4; |
2164 | #endif |
2165 | }; |
2166 | |
2167 | typedef struct ULP_BDL { /* SLI-2 */ |
2168 | #ifdef __BIG_ENDIAN_BITFIELD |
2169 | uint32_t bdeFlags:8; /* BDL Flags */ |
2170 | uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ |
2171 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2172 | uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ |
2173 | uint32_t bdeFlags:8; /* BDL Flags */ |
2174 | #endif |
2175 | |
2176 | uint32_t addrLow; /* Address 0:31 */ |
2177 | uint32_t addrHigh; /* Address 32:63 */ |
2178 | uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ |
2179 | } ULP_BDL; |
2180 | |
2181 | /* |
2182 | * BlockGuard Definitions |
2183 | */ |
2184 | |
2185 | enum lpfc_protgrp_type { |
2186 | LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ |
2187 | LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ |
2188 | LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ |
2189 | LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ |
2190 | }; |
2191 | |
2192 | /* PDE Descriptors */ |
2193 | #define LPFC_PDE5_DESCRIPTOR 0x85 |
2194 | #define LPFC_PDE6_DESCRIPTOR 0x86 |
2195 | #define LPFC_PDE7_DESCRIPTOR 0x87 |
2196 | |
2197 | /* BlockGuard Opcodes */ |
2198 | #define BG_OP_IN_NODIF_OUT_CRC 0x0 |
2199 | #define BG_OP_IN_CRC_OUT_NODIF 0x1 |
2200 | #define BG_OP_IN_NODIF_OUT_CSUM 0x2 |
2201 | #define BG_OP_IN_CSUM_OUT_NODIF 0x3 |
2202 | #define BG_OP_IN_CRC_OUT_CRC 0x4 |
2203 | #define BG_OP_IN_CSUM_OUT_CSUM 0x5 |
2204 | #define BG_OP_IN_CRC_OUT_CSUM 0x6 |
2205 | #define BG_OP_IN_CSUM_OUT_CRC 0x7 |
2206 | #define BG_OP_RAW_MODE 0x8 |
2207 | |
2208 | struct lpfc_pde5 { |
2209 | uint32_t word0; |
2210 | #define pde5_type_SHIFT 24 |
2211 | #define pde5_type_MASK 0x000000ff |
2212 | #define pde5_type_WORD word0 |
2213 | #define pde5_rsvd0_SHIFT 0 |
2214 | #define pde5_rsvd0_MASK 0x00ffffff |
2215 | #define pde5_rsvd0_WORD word0 |
2216 | uint32_t reftag; /* Reference Tag Value */ |
2217 | uint32_t reftagtr; /* Reference Tag Translation Value */ |
2218 | }; |
2219 | |
2220 | struct lpfc_pde6 { |
2221 | uint32_t word0; |
2222 | #define pde6_type_SHIFT 24 |
2223 | #define pde6_type_MASK 0x000000ff |
2224 | #define pde6_type_WORD word0 |
2225 | #define pde6_rsvd0_SHIFT 0 |
2226 | #define pde6_rsvd0_MASK 0x00ffffff |
2227 | #define pde6_rsvd0_WORD word0 |
2228 | uint32_t word1; |
2229 | #define pde6_rsvd1_SHIFT 26 |
2230 | #define pde6_rsvd1_MASK 0x0000003f |
2231 | #define pde6_rsvd1_WORD word1 |
2232 | #define pde6_na_SHIFT 25 |
2233 | #define pde6_na_MASK 0x00000001 |
2234 | #define pde6_na_WORD word1 |
2235 | #define pde6_rsvd2_SHIFT 16 |
2236 | #define pde6_rsvd2_MASK 0x000001FF |
2237 | #define pde6_rsvd2_WORD word1 |
2238 | #define pde6_apptagtr_SHIFT 0 |
2239 | #define pde6_apptagtr_MASK 0x0000ffff |
2240 | #define pde6_apptagtr_WORD word1 |
2241 | uint32_t word2; |
2242 | #define pde6_optx_SHIFT 28 |
2243 | #define pde6_optx_MASK 0x0000000f |
2244 | #define pde6_optx_WORD word2 |
2245 | #define pde6_oprx_SHIFT 24 |
2246 | #define pde6_oprx_MASK 0x0000000f |
2247 | #define pde6_oprx_WORD word2 |
2248 | #define pde6_nr_SHIFT 23 |
2249 | #define pde6_nr_MASK 0x00000001 |
2250 | #define pde6_nr_WORD word2 |
2251 | #define pde6_ce_SHIFT 22 |
2252 | #define pde6_ce_MASK 0x00000001 |
2253 | #define pde6_ce_WORD word2 |
2254 | #define pde6_re_SHIFT 21 |
2255 | #define pde6_re_MASK 0x00000001 |
2256 | #define pde6_re_WORD word2 |
2257 | #define pde6_ae_SHIFT 20 |
2258 | #define pde6_ae_MASK 0x00000001 |
2259 | #define pde6_ae_WORD word2 |
2260 | #define pde6_ai_SHIFT 19 |
2261 | #define pde6_ai_MASK 0x00000001 |
2262 | #define pde6_ai_WORD word2 |
2263 | #define pde6_bs_SHIFT 16 |
2264 | #define pde6_bs_MASK 0x00000007 |
2265 | #define pde6_bs_WORD word2 |
2266 | #define pde6_apptagval_SHIFT 0 |
2267 | #define pde6_apptagval_MASK 0x0000ffff |
2268 | #define pde6_apptagval_WORD word2 |
2269 | }; |
2270 | |
2271 | struct lpfc_pde7 { |
2272 | uint32_t word0; |
2273 | #define pde7_type_SHIFT 24 |
2274 | #define pde7_type_MASK 0x000000ff |
2275 | #define pde7_type_WORD word0 |
2276 | #define pde7_rsvd0_SHIFT 0 |
2277 | #define pde7_rsvd0_MASK 0x00ffffff |
2278 | #define pde7_rsvd0_WORD word0 |
2279 | uint32_t addrHigh; |
2280 | uint32_t addrLow; |
2281 | }; |
2282 | |
2283 | /* Structure for MB Command LOAD_SM and DOWN_LOAD */ |
2284 | |
2285 | typedef struct { |
2286 | #ifdef __BIG_ENDIAN_BITFIELD |
2287 | uint32_t rsvd2:25; |
2288 | uint32_t acknowledgment:1; |
2289 | uint32_t version:1; |
2290 | uint32_t erase_or_prog:1; |
2291 | uint32_t update_flash:1; |
2292 | uint32_t update_ram:1; |
2293 | uint32_t method:1; |
2294 | uint32_t load_cmplt:1; |
2295 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2296 | uint32_t load_cmplt:1; |
2297 | uint32_t method:1; |
2298 | uint32_t update_ram:1; |
2299 | uint32_t update_flash:1; |
2300 | uint32_t erase_or_prog:1; |
2301 | uint32_t version:1; |
2302 | uint32_t acknowledgment:1; |
2303 | uint32_t rsvd2:25; |
2304 | #endif |
2305 | |
2306 | uint32_t dl_to_adr_low; |
2307 | uint32_t dl_to_adr_high; |
2308 | uint32_t dl_len; |
2309 | union { |
2310 | uint32_t dl_from_mbx_offset; |
2311 | struct ulp_bde dl_from_bde; |
2312 | struct ulp_bde64 dl_from_bde64; |
2313 | } un; |
2314 | |
2315 | } LOAD_SM_VAR; |
2316 | |
2317 | /* Structure for MB Command READ_NVPARM (02) */ |
2318 | |
2319 | typedef struct { |
2320 | uint32_t rsvd1[3]; /* Read as all one's */ |
2321 | uint32_t rsvd2; /* Read as all zero's */ |
2322 | uint32_t portname[2]; /* N_PORT name */ |
2323 | uint32_t nodename[2]; /* NODE name */ |
2324 | |
2325 | #ifdef __BIG_ENDIAN_BITFIELD |
2326 | uint32_t pref_DID:24; |
2327 | uint32_t hardAL_PA:8; |
2328 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2329 | uint32_t hardAL_PA:8; |
2330 | uint32_t pref_DID:24; |
2331 | #endif |
2332 | |
2333 | uint32_t rsvd3[21]; /* Read as all one's */ |
2334 | } READ_NV_VAR; |
2335 | |
2336 | /* Structure for MB Command WRITE_NVPARMS (03) */ |
2337 | |
2338 | typedef struct { |
2339 | uint32_t rsvd1[3]; /* Must be all one's */ |
2340 | uint32_t rsvd2; /* Must be all zero's */ |
2341 | uint32_t portname[2]; /* N_PORT name */ |
2342 | uint32_t nodename[2]; /* NODE name */ |
2343 | |
2344 | #ifdef __BIG_ENDIAN_BITFIELD |
2345 | uint32_t pref_DID:24; |
2346 | uint32_t hardAL_PA:8; |
2347 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2348 | uint32_t hardAL_PA:8; |
2349 | uint32_t pref_DID:24; |
2350 | #endif |
2351 | |
2352 | uint32_t rsvd3[21]; /* Must be all one's */ |
2353 | } WRITE_NV_VAR; |
2354 | |
2355 | /* Structure for MB Command RUN_BIU_DIAG (04) */ |
2356 | /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ |
2357 | |
2358 | typedef struct { |
2359 | uint32_t rsvd1; |
2360 | union { |
2361 | struct { |
2362 | struct ulp_bde xmit_bde; |
2363 | struct ulp_bde rcv_bde; |
2364 | } s1; |
2365 | struct { |
2366 | struct ulp_bde64 xmit_bde64; |
2367 | struct ulp_bde64 rcv_bde64; |
2368 | } s2; |
2369 | } un; |
2370 | } BIU_DIAG_VAR; |
2371 | |
2372 | /* Structure for MB command READ_EVENT_LOG (0x38) */ |
2373 | struct READ_EVENT_LOG_VAR { |
2374 | uint32_t word1; |
2375 | #define lpfc_event_log_SHIFT 29 |
2376 | #define lpfc_event_log_MASK 0x00000001 |
2377 | #define lpfc_event_log_WORD word1 |
2378 | #define USE_MAILBOX_RESPONSE 1 |
2379 | uint32_t offset; |
2380 | struct ulp_bde64 rcv_bde64; |
2381 | }; |
2382 | |
2383 | /* Structure for MB Command INIT_LINK (05) */ |
2384 | |
2385 | typedef struct { |
2386 | #ifdef __BIG_ENDIAN_BITFIELD |
2387 | uint32_t rsvd1:24; |
2388 | uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ |
2389 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2390 | uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ |
2391 | uint32_t rsvd1:24; |
2392 | #endif |
2393 | |
2394 | #ifdef __BIG_ENDIAN_BITFIELD |
2395 | uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ |
2396 | uint8_t rsvd2; |
2397 | uint16_t link_flags; |
2398 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2399 | uint16_t link_flags; |
2400 | uint8_t rsvd2; |
2401 | uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ |
2402 | #endif |
2403 | |
2404 | #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ |
2405 | #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ |
2406 | #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ |
2407 | #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ |
2408 | #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ |
2409 | #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ |
2410 | #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ |
2411 | |
2412 | #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ |
2413 | #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ |
2414 | #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ |
2415 | |
2416 | uint32_t link_speed; |
2417 | #define LINK_SPEED_AUTO 0x0 /* Auto selection */ |
2418 | #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ |
2419 | #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ |
2420 | #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ |
2421 | #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ |
2422 | #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ |
2423 | #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ |
2424 | #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ |
2425 | #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */ |
2426 | #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */ |
2427 | #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */ |
2428 | |
2429 | } INIT_LINK_VAR; |
2430 | |
2431 | /* Structure for MB Command DOWN_LINK (06) */ |
2432 | |
2433 | typedef struct { |
2434 | uint32_t rsvd1; |
2435 | } DOWN_LINK_VAR; |
2436 | |
2437 | /* Structure for MB Command CONFIG_LINK (07) */ |
2438 | |
2439 | typedef struct { |
2440 | #ifdef __BIG_ENDIAN_BITFIELD |
2441 | uint32_t cr:1; |
2442 | uint32_t ci:1; |
2443 | uint32_t cr_delay:6; |
2444 | uint32_t cr_count:8; |
2445 | uint32_t rsvd1:8; |
2446 | uint32_t MaxBBC:8; |
2447 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2448 | uint32_t MaxBBC:8; |
2449 | uint32_t rsvd1:8; |
2450 | uint32_t cr_count:8; |
2451 | uint32_t cr_delay:6; |
2452 | uint32_t ci:1; |
2453 | uint32_t cr:1; |
2454 | #endif |
2455 | |
2456 | uint32_t myId; |
2457 | uint32_t rsvd2; |
2458 | uint32_t edtov; |
2459 | uint32_t arbtov; |
2460 | uint32_t ratov; |
2461 | uint32_t rttov; |
2462 | uint32_t altov; |
2463 | uint32_t crtov; |
2464 | |
2465 | #ifdef __BIG_ENDIAN_BITFIELD |
2466 | uint32_t rsvd4:19; |
2467 | uint32_t cscn:1; |
2468 | uint32_t bbscn:4; |
2469 | uint32_t rsvd3:8; |
2470 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2471 | uint32_t rsvd3:8; |
2472 | uint32_t bbscn:4; |
2473 | uint32_t cscn:1; |
2474 | uint32_t rsvd4:19; |
2475 | #endif |
2476 | |
2477 | #ifdef __BIG_ENDIAN_BITFIELD |
2478 | uint32_t rrq_enable:1; |
2479 | uint32_t rrq_immed:1; |
2480 | uint32_t rsvd5:29; |
2481 | uint32_t ack0_enable:1; |
2482 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2483 | uint32_t ack0_enable:1; |
2484 | uint32_t rsvd5:29; |
2485 | uint32_t rrq_immed:1; |
2486 | uint32_t rrq_enable:1; |
2487 | #endif |
2488 | } CONFIG_LINK; |
2489 | |
2490 | /* Structure for MB Command PART_SLIM (08) |
2491 | * will be removed since SLI1 is no longer supported! |
2492 | */ |
2493 | typedef struct { |
2494 | #ifdef __BIG_ENDIAN_BITFIELD |
2495 | uint16_t offCiocb; |
2496 | uint16_t numCiocb; |
2497 | uint16_t offRiocb; |
2498 | uint16_t numRiocb; |
2499 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2500 | uint16_t numCiocb; |
2501 | uint16_t offCiocb; |
2502 | uint16_t numRiocb; |
2503 | uint16_t offRiocb; |
2504 | #endif |
2505 | } RING_DEF; |
2506 | |
2507 | typedef struct { |
2508 | #ifdef __BIG_ENDIAN_BITFIELD |
2509 | uint32_t unused1:24; |
2510 | uint32_t numRing:8; |
2511 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2512 | uint32_t numRing:8; |
2513 | uint32_t unused1:24; |
2514 | #endif |
2515 | |
2516 | RING_DEF ringdef[4]; |
2517 | uint32_t hbainit; |
2518 | } PART_SLIM_VAR; |
2519 | |
2520 | /* Structure for MB Command CONFIG_RING (09) */ |
2521 | |
2522 | typedef struct { |
2523 | #ifdef __BIG_ENDIAN_BITFIELD |
2524 | uint32_t unused2:6; |
2525 | uint32_t recvSeq:1; |
2526 | uint32_t recvNotify:1; |
2527 | uint32_t numMask:8; |
2528 | uint32_t profile:8; |
2529 | uint32_t unused1:4; |
2530 | uint32_t ring:4; |
2531 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2532 | uint32_t ring:4; |
2533 | uint32_t unused1:4; |
2534 | uint32_t profile:8; |
2535 | uint32_t numMask:8; |
2536 | uint32_t recvNotify:1; |
2537 | uint32_t recvSeq:1; |
2538 | uint32_t unused2:6; |
2539 | #endif |
2540 | |
2541 | #ifdef __BIG_ENDIAN_BITFIELD |
2542 | uint16_t maxRespXchg; |
2543 | uint16_t maxOrigXchg; |
2544 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2545 | uint16_t maxOrigXchg; |
2546 | uint16_t maxRespXchg; |
2547 | #endif |
2548 | |
2549 | RR_REG rrRegs[6]; |
2550 | } CONFIG_RING_VAR; |
2551 | |
2552 | /* Structure for MB Command RESET_RING (10) */ |
2553 | |
2554 | typedef struct { |
2555 | uint32_t ring_no; |
2556 | } RESET_RING_VAR; |
2557 | |
2558 | /* Structure for MB Command READ_CONFIG (11) */ |
2559 | |
2560 | typedef struct { |
2561 | #ifdef __BIG_ENDIAN_BITFIELD |
2562 | uint32_t cr:1; |
2563 | uint32_t ci:1; |
2564 | uint32_t cr_delay:6; |
2565 | uint32_t cr_count:8; |
2566 | uint32_t InitBBC:8; |
2567 | uint32_t MaxBBC:8; |
2568 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2569 | uint32_t MaxBBC:8; |
2570 | uint32_t InitBBC:8; |
2571 | uint32_t cr_count:8; |
2572 | uint32_t cr_delay:6; |
2573 | uint32_t ci:1; |
2574 | uint32_t cr:1; |
2575 | #endif |
2576 | |
2577 | #ifdef __BIG_ENDIAN_BITFIELD |
2578 | uint32_t topology:8; |
2579 | uint32_t myDid:24; |
2580 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2581 | uint32_t myDid:24; |
2582 | uint32_t topology:8; |
2583 | #endif |
2584 | |
2585 | /* Defines for topology (defined previously) */ |
2586 | #ifdef __BIG_ENDIAN_BITFIELD |
2587 | uint32_t AR:1; |
2588 | uint32_t IR:1; |
2589 | uint32_t rsvd1:29; |
2590 | uint32_t ack0:1; |
2591 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2592 | uint32_t ack0:1; |
2593 | uint32_t rsvd1:29; |
2594 | uint32_t IR:1; |
2595 | uint32_t AR:1; |
2596 | #endif |
2597 | |
2598 | uint32_t edtov; |
2599 | uint32_t arbtov; |
2600 | uint32_t ratov; |
2601 | uint32_t rttov; |
2602 | uint32_t altov; |
2603 | uint32_t lmt; |
2604 | #define LMT_RESERVED 0x000 /* Not used */ |
2605 | #define LMT_1Gb 0x004 |
2606 | #define LMT_2Gb 0x008 |
2607 | #define LMT_4Gb 0x040 |
2608 | #define LMT_8Gb 0x080 |
2609 | #define LMT_10Gb 0x100 |
2610 | #define LMT_16Gb 0x200 |
2611 | #define LMT_32Gb 0x400 |
2612 | #define LMT_64Gb 0x800 |
2613 | #define LMT_128Gb 0x1000 |
2614 | #define LMT_256Gb 0x2000 |
2615 | uint32_t rsvd2; |
2616 | uint32_t rsvd3; |
2617 | uint32_t max_xri; |
2618 | uint32_t max_iocb; |
2619 | uint32_t max_rpi; |
2620 | uint32_t avail_xri; |
2621 | uint32_t avail_iocb; |
2622 | uint32_t avail_rpi; |
2623 | uint32_t max_vpi; |
2624 | uint32_t rsvd4; |
2625 | uint32_t rsvd5; |
2626 | uint32_t avail_vpi; |
2627 | } READ_CONFIG_VAR; |
2628 | |
2629 | /* Structure for MB Command READ_RCONFIG (12) */ |
2630 | |
2631 | typedef struct { |
2632 | #ifdef __BIG_ENDIAN_BITFIELD |
2633 | uint32_t rsvd2:7; |
2634 | uint32_t recvNotify:1; |
2635 | uint32_t numMask:8; |
2636 | uint32_t profile:8; |
2637 | uint32_t rsvd1:4; |
2638 | uint32_t ring:4; |
2639 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2640 | uint32_t ring:4; |
2641 | uint32_t rsvd1:4; |
2642 | uint32_t profile:8; |
2643 | uint32_t numMask:8; |
2644 | uint32_t recvNotify:1; |
2645 | uint32_t rsvd2:7; |
2646 | #endif |
2647 | |
2648 | #ifdef __BIG_ENDIAN_BITFIELD |
2649 | uint16_t maxResp; |
2650 | uint16_t maxOrig; |
2651 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2652 | uint16_t maxOrig; |
2653 | uint16_t maxResp; |
2654 | #endif |
2655 | |
2656 | RR_REG rrRegs[6]; |
2657 | |
2658 | #ifdef __BIG_ENDIAN_BITFIELD |
2659 | uint16_t cmdRingOffset; |
2660 | uint16_t cmdEntryCnt; |
2661 | uint16_t rspRingOffset; |
2662 | uint16_t rspEntryCnt; |
2663 | uint16_t nextCmdOffset; |
2664 | uint16_t rsvd3; |
2665 | uint16_t nextRspOffset; |
2666 | uint16_t rsvd4; |
2667 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2668 | uint16_t cmdEntryCnt; |
2669 | uint16_t cmdRingOffset; |
2670 | uint16_t rspEntryCnt; |
2671 | uint16_t rspRingOffset; |
2672 | uint16_t rsvd3; |
2673 | uint16_t nextCmdOffset; |
2674 | uint16_t rsvd4; |
2675 | uint16_t nextRspOffset; |
2676 | #endif |
2677 | } READ_RCONF_VAR; |
2678 | |
2679 | /* Structure for MB Command READ_SPARM (13) */ |
2680 | /* Structure for MB Command READ_SPARM64 (0x8D) */ |
2681 | |
2682 | typedef struct { |
2683 | uint32_t rsvd1; |
2684 | uint32_t rsvd2; |
2685 | union { |
2686 | struct ulp_bde sp; /* This BDE points to struct serv_parm |
2687 | structure */ |
2688 | struct ulp_bde64 sp64; |
2689 | } un; |
2690 | #ifdef __BIG_ENDIAN_BITFIELD |
2691 | uint16_t rsvd3; |
2692 | uint16_t vpi; |
2693 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2694 | uint16_t vpi; |
2695 | uint16_t rsvd3; |
2696 | #endif |
2697 | } READ_SPARM_VAR; |
2698 | |
2699 | /* Structure for MB Command READ_STATUS (14) */ |
2700 | enum read_status_word1 { |
2701 | RD_ST_CC = 0x01, |
2702 | RD_ST_XKB = 0x80, |
2703 | }; |
2704 | |
2705 | enum read_status_word17 { |
2706 | RD_ST_XMIT_XKB_MASK = 0x3fffff, |
2707 | }; |
2708 | |
2709 | enum read_status_word18 { |
2710 | RD_ST_RCV_XKB_MASK = 0x3fffff, |
2711 | }; |
2712 | |
2713 | typedef struct { |
2714 | u8 clear_counters; /* rsvd 7:1, cc 0 */ |
2715 | u8 rsvd5; |
2716 | u8 rsvd6; |
2717 | u8 xkb; /* xkb 7, rsvd 6:0 */ |
2718 | |
2719 | u32 rsvd8; |
2720 | |
2721 | uint32_t xmitByteCnt; |
2722 | uint32_t rcvByteCnt; |
2723 | uint32_t xmitFrameCnt; |
2724 | uint32_t rcvFrameCnt; |
2725 | uint32_t xmitSeqCnt; |
2726 | uint32_t rcvSeqCnt; |
2727 | uint32_t totalOrigExchanges; |
2728 | uint32_t totalRespExchanges; |
2729 | uint32_t rcvPbsyCnt; |
2730 | uint32_t rcvFbsyCnt; |
2731 | |
2732 | u32 drop_frame_no_rq; |
2733 | u32 empty_rq; |
2734 | u32 drop_frame_no_xri; |
2735 | u32 empty_xri; |
2736 | |
2737 | u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */ |
2738 | u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */ |
2739 | } READ_STATUS_VAR; |
2740 | |
2741 | /* Structure for MB Command READ_RPI (15) */ |
2742 | /* Structure for MB Command READ_RPI64 (0x8F) */ |
2743 | |
2744 | typedef struct { |
2745 | #ifdef __BIG_ENDIAN_BITFIELD |
2746 | uint16_t nextRpi; |
2747 | uint16_t reqRpi; |
2748 | uint32_t rsvd2:8; |
2749 | uint32_t DID:24; |
2750 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2751 | uint16_t reqRpi; |
2752 | uint16_t nextRpi; |
2753 | uint32_t DID:24; |
2754 | uint32_t rsvd2:8; |
2755 | #endif |
2756 | |
2757 | union { |
2758 | struct ulp_bde sp; |
2759 | struct ulp_bde64 sp64; |
2760 | } un; |
2761 | |
2762 | } READ_RPI_VAR; |
2763 | |
2764 | /* Structure for MB Command READ_XRI (16) */ |
2765 | |
2766 | typedef struct { |
2767 | #ifdef __BIG_ENDIAN_BITFIELD |
2768 | uint16_t nextXri; |
2769 | uint16_t reqXri; |
2770 | uint16_t rsvd1; |
2771 | uint16_t rpi; |
2772 | uint32_t rsvd2:8; |
2773 | uint32_t DID:24; |
2774 | uint32_t rsvd3:8; |
2775 | uint32_t SID:24; |
2776 | uint32_t rsvd4; |
2777 | uint8_t seqId; |
2778 | uint8_t rsvd5; |
2779 | uint16_t seqCount; |
2780 | uint16_t oxId; |
2781 | uint16_t rxId; |
2782 | uint32_t rsvd6:30; |
2783 | uint32_t si:1; |
2784 | uint32_t exchOrig:1; |
2785 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2786 | uint16_t reqXri; |
2787 | uint16_t nextXri; |
2788 | uint16_t rpi; |
2789 | uint16_t rsvd1; |
2790 | uint32_t DID:24; |
2791 | uint32_t rsvd2:8; |
2792 | uint32_t SID:24; |
2793 | uint32_t rsvd3:8; |
2794 | uint32_t rsvd4; |
2795 | uint16_t seqCount; |
2796 | uint8_t rsvd5; |
2797 | uint8_t seqId; |
2798 | uint16_t rxId; |
2799 | uint16_t oxId; |
2800 | uint32_t exchOrig:1; |
2801 | uint32_t si:1; |
2802 | uint32_t rsvd6:30; |
2803 | #endif |
2804 | } READ_XRI_VAR; |
2805 | |
2806 | /* Structure for MB Command READ_REV (17) */ |
2807 | |
2808 | typedef struct { |
2809 | #ifdef __BIG_ENDIAN_BITFIELD |
2810 | uint32_t cv:1; |
2811 | uint32_t rr:1; |
2812 | uint32_t rsvd2:2; |
2813 | uint32_t v3req:1; |
2814 | uint32_t v3rsp:1; |
2815 | uint32_t rsvd1:25; |
2816 | uint32_t rv:1; |
2817 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2818 | uint32_t rv:1; |
2819 | uint32_t rsvd1:25; |
2820 | uint32_t v3rsp:1; |
2821 | uint32_t v3req:1; |
2822 | uint32_t rsvd2:2; |
2823 | uint32_t rr:1; |
2824 | uint32_t cv:1; |
2825 | #endif |
2826 | |
2827 | uint32_t biuRev; |
2828 | uint32_t smRev; |
2829 | union { |
2830 | uint32_t smFwRev; |
2831 | struct { |
2832 | #ifdef __BIG_ENDIAN_BITFIELD |
2833 | uint8_t ProgType; |
2834 | uint8_t ProgId; |
2835 | uint16_t ProgVer:4; |
2836 | uint16_t ProgRev:4; |
2837 | uint16_t ProgFixLvl:2; |
2838 | uint16_t ProgDistType:2; |
2839 | uint16_t DistCnt:4; |
2840 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2841 | uint16_t DistCnt:4; |
2842 | uint16_t ProgDistType:2; |
2843 | uint16_t ProgFixLvl:2; |
2844 | uint16_t ProgRev:4; |
2845 | uint16_t ProgVer:4; |
2846 | uint8_t ProgId; |
2847 | uint8_t ProgType; |
2848 | #endif |
2849 | |
2850 | } b; |
2851 | } un; |
2852 | uint32_t endecRev; |
2853 | #ifdef __BIG_ENDIAN_BITFIELD |
2854 | uint8_t feaLevelHigh; |
2855 | uint8_t feaLevelLow; |
2856 | uint8_t fcphHigh; |
2857 | uint8_t fcphLow; |
2858 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2859 | uint8_t fcphLow; |
2860 | uint8_t fcphHigh; |
2861 | uint8_t feaLevelLow; |
2862 | uint8_t feaLevelHigh; |
2863 | #endif |
2864 | |
2865 | uint32_t postKernRev; |
2866 | uint32_t opFwRev; |
2867 | uint8_t opFwName[16]; |
2868 | uint32_t sli1FwRev; |
2869 | uint8_t sli1FwName[16]; |
2870 | uint32_t sli2FwRev; |
2871 | uint8_t sli2FwName[16]; |
2872 | uint32_t sli3Feat; |
2873 | uint32_t RandomData[6]; |
2874 | } READ_REV_VAR; |
2875 | |
2876 | /* Structure for MB Command READ_LINK_STAT (18) */ |
2877 | |
2878 | typedef struct { |
2879 | uint32_t word0; |
2880 | |
2881 | #define lpfc_read_link_stat_rec_SHIFT 0 |
2882 | #define lpfc_read_link_stat_rec_MASK 0x1 |
2883 | #define lpfc_read_link_stat_rec_WORD word0 |
2884 | |
2885 | #define lpfc_read_link_stat_gec_SHIFT 1 |
2886 | #define lpfc_read_link_stat_gec_MASK 0x1 |
2887 | #define lpfc_read_link_stat_gec_WORD word0 |
2888 | |
2889 | #define lpfc_read_link_stat_w02oftow23of_SHIFT 2 |
2890 | #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF |
2891 | #define lpfc_read_link_stat_w02oftow23of_WORD word0 |
2892 | |
2893 | #define lpfc_read_link_stat_rsvd_SHIFT 24 |
2894 | #define lpfc_read_link_stat_rsvd_MASK 0x1F |
2895 | #define lpfc_read_link_stat_rsvd_WORD word0 |
2896 | |
2897 | #define lpfc_read_link_stat_gec2_SHIFT 29 |
2898 | #define lpfc_read_link_stat_gec2_MASK 0x1 |
2899 | #define lpfc_read_link_stat_gec2_WORD word0 |
2900 | |
2901 | #define lpfc_read_link_stat_clrc_SHIFT 30 |
2902 | #define lpfc_read_link_stat_clrc_MASK 0x1 |
2903 | #define lpfc_read_link_stat_clrc_WORD word0 |
2904 | |
2905 | #define lpfc_read_link_stat_clof_SHIFT 31 |
2906 | #define lpfc_read_link_stat_clof_MASK 0x1 |
2907 | #define lpfc_read_link_stat_clof_WORD word0 |
2908 | |
2909 | uint32_t linkFailureCnt; |
2910 | uint32_t lossSyncCnt; |
2911 | uint32_t lossSignalCnt; |
2912 | uint32_t primSeqErrCnt; |
2913 | uint32_t invalidXmitWord; |
2914 | uint32_t crcCnt; |
2915 | uint32_t primSeqTimeout; |
2916 | uint32_t elasticOverrun; |
2917 | uint32_t arbTimeout; |
2918 | uint32_t advRecBufCredit; |
2919 | uint32_t curRecBufCredit; |
2920 | uint32_t advTransBufCredit; |
2921 | uint32_t curTransBufCredit; |
2922 | uint32_t recEofCount; |
2923 | uint32_t recEofdtiCount; |
2924 | uint32_t recEofniCount; |
2925 | uint32_t recSofcount; |
2926 | uint32_t rsvd1; |
2927 | uint32_t rsvd2; |
2928 | uint32_t recDrpXriCount; |
2929 | uint32_t fecCorrBlkCount; |
2930 | uint32_t fecUncorrBlkCount; |
2931 | } READ_LNK_VAR; |
2932 | |
2933 | /* Structure for MB Command REG_LOGIN (19) */ |
2934 | /* Structure for MB Command REG_LOGIN64 (0x93) */ |
2935 | |
2936 | typedef struct { |
2937 | #ifdef __BIG_ENDIAN_BITFIELD |
2938 | uint16_t rsvd1; |
2939 | uint16_t rpi; |
2940 | uint32_t rsvd2:8; |
2941 | uint32_t did:24; |
2942 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2943 | uint16_t rpi; |
2944 | uint16_t rsvd1; |
2945 | uint32_t did:24; |
2946 | uint32_t rsvd2:8; |
2947 | #endif |
2948 | |
2949 | union { |
2950 | struct ulp_bde sp; |
2951 | struct ulp_bde64 sp64; |
2952 | } un; |
2953 | |
2954 | #ifdef __BIG_ENDIAN_BITFIELD |
2955 | uint16_t rsvd6; |
2956 | uint16_t vpi; |
2957 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2958 | uint16_t vpi; |
2959 | uint16_t rsvd6; |
2960 | #endif |
2961 | |
2962 | } REG_LOGIN_VAR; |
2963 | |
2964 | /* Word 30 contents for REG_LOGIN */ |
2965 | typedef union { |
2966 | struct { |
2967 | #ifdef __BIG_ENDIAN_BITFIELD |
2968 | uint16_t rsvd1:12; |
2969 | uint16_t wd30_class:4; |
2970 | uint16_t xri; |
2971 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2972 | uint16_t xri; |
2973 | uint16_t wd30_class:4; |
2974 | uint16_t rsvd1:12; |
2975 | #endif |
2976 | } f; |
2977 | uint32_t word; |
2978 | } REG_WD30; |
2979 | |
2980 | /* Structure for MB Command UNREG_LOGIN (20) */ |
2981 | |
2982 | typedef struct { |
2983 | #ifdef __BIG_ENDIAN_BITFIELD |
2984 | uint16_t rsvd1; |
2985 | uint16_t rpi; |
2986 | uint32_t rsvd2; |
2987 | uint32_t rsvd3; |
2988 | uint32_t rsvd4; |
2989 | uint32_t rsvd5; |
2990 | uint16_t rsvd6; |
2991 | uint16_t vpi; |
2992 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
2993 | uint16_t rpi; |
2994 | uint16_t rsvd1; |
2995 | uint32_t rsvd2; |
2996 | uint32_t rsvd3; |
2997 | uint32_t rsvd4; |
2998 | uint32_t rsvd5; |
2999 | uint16_t vpi; |
3000 | uint16_t rsvd6; |
3001 | #endif |
3002 | } UNREG_LOGIN_VAR; |
3003 | |
3004 | /* Structure for MB Command REG_VPI (0x96) */ |
3005 | typedef struct { |
3006 | #ifdef __BIG_ENDIAN_BITFIELD |
3007 | uint32_t rsvd1; |
3008 | uint32_t rsvd2:7; |
3009 | uint32_t upd:1; |
3010 | uint32_t sid:24; |
3011 | uint32_t wwn[2]; |
3012 | uint32_t rsvd5; |
3013 | uint16_t vfi; |
3014 | uint16_t vpi; |
3015 | #else /* __LITTLE_ENDIAN */ |
3016 | uint32_t rsvd1; |
3017 | uint32_t sid:24; |
3018 | uint32_t upd:1; |
3019 | uint32_t rsvd2:7; |
3020 | uint32_t wwn[2]; |
3021 | uint32_t rsvd5; |
3022 | uint16_t vpi; |
3023 | uint16_t vfi; |
3024 | #endif |
3025 | } REG_VPI_VAR; |
3026 | |
3027 | /* Structure for MB Command UNREG_VPI (0x97) */ |
3028 | typedef struct { |
3029 | uint32_t rsvd1; |
3030 | #ifdef __BIG_ENDIAN_BITFIELD |
3031 | uint16_t rsvd2; |
3032 | uint16_t sli4_vpi; |
3033 | #else /* __LITTLE_ENDIAN */ |
3034 | uint16_t sli4_vpi; |
3035 | uint16_t rsvd2; |
3036 | #endif |
3037 | uint32_t rsvd3; |
3038 | uint32_t rsvd4; |
3039 | uint32_t rsvd5; |
3040 | #ifdef __BIG_ENDIAN_BITFIELD |
3041 | uint16_t rsvd6; |
3042 | uint16_t vpi; |
3043 | #else /* __LITTLE_ENDIAN */ |
3044 | uint16_t vpi; |
3045 | uint16_t rsvd6; |
3046 | #endif |
3047 | } UNREG_VPI_VAR; |
3048 | |
3049 | /* Structure for MB Command UNREG_D_ID (0x23) */ |
3050 | |
3051 | typedef struct { |
3052 | uint32_t did; |
3053 | uint32_t rsvd2; |
3054 | uint32_t rsvd3; |
3055 | uint32_t rsvd4; |
3056 | uint32_t rsvd5; |
3057 | #ifdef __BIG_ENDIAN_BITFIELD |
3058 | uint16_t rsvd6; |
3059 | uint16_t vpi; |
3060 | #else |
3061 | uint16_t vpi; |
3062 | uint16_t rsvd6; |
3063 | #endif |
3064 | } UNREG_D_ID_VAR; |
3065 | |
3066 | /* Structure for MB Command READ_TOPOLOGY (0x95) */ |
3067 | struct lpfc_mbx_read_top { |
3068 | uint32_t eventTag; /* Event tag */ |
3069 | uint32_t word2; |
3070 | #define lpfc_mbx_read_top_fa_SHIFT 12 |
3071 | #define lpfc_mbx_read_top_fa_MASK 0x00000001 |
3072 | #define lpfc_mbx_read_top_fa_WORD word2 |
3073 | #define lpfc_mbx_read_top_mm_SHIFT 11 |
3074 | #define lpfc_mbx_read_top_mm_MASK 0x00000001 |
3075 | #define lpfc_mbx_read_top_mm_WORD word2 |
3076 | #define lpfc_mbx_read_top_pb_SHIFT 9 |
3077 | #define lpfc_mbx_read_top_pb_MASK 0X00000001 |
3078 | #define lpfc_mbx_read_top_pb_WORD word2 |
3079 | #define lpfc_mbx_read_top_il_SHIFT 8 |
3080 | #define lpfc_mbx_read_top_il_MASK 0x00000001 |
3081 | #define lpfc_mbx_read_top_il_WORD word2 |
3082 | #define lpfc_mbx_read_top_att_type_SHIFT 0 |
3083 | #define lpfc_mbx_read_top_att_type_MASK 0x000000FF |
3084 | #define lpfc_mbx_read_top_att_type_WORD word2 |
3085 | #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ |
3086 | #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ |
3087 | #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ |
3088 | #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */ |
3089 | uint32_t word3; |
3090 | #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 |
3091 | #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF |
3092 | #define lpfc_mbx_read_top_alpa_granted_WORD word3 |
3093 | #define lpfc_mbx_read_top_lip_alps_SHIFT 16 |
3094 | #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF |
3095 | #define lpfc_mbx_read_top_lip_alps_WORD word3 |
3096 | #define lpfc_mbx_read_top_lip_type_SHIFT 8 |
3097 | #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF |
3098 | #define lpfc_mbx_read_top_lip_type_WORD word3 |
3099 | #define lpfc_mbx_read_top_topology_SHIFT 0 |
3100 | #define lpfc_mbx_read_top_topology_MASK 0x000000FF |
3101 | #define lpfc_mbx_read_top_topology_WORD word3 |
3102 | #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ |
3103 | #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ |
3104 | /* store the LILP AL_PA position map into */ |
3105 | struct ulp_bde64 lilpBde64; |
3106 | #define LPFC_ALPA_MAP_SIZE 128 |
3107 | uint32_t word7; |
3108 | #define lpfc_mbx_read_top_ld_lu_SHIFT 31 |
3109 | #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 |
3110 | #define lpfc_mbx_read_top_ld_lu_WORD word7 |
3111 | #define lpfc_mbx_read_top_ld_tf_SHIFT 30 |
3112 | #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 |
3113 | #define lpfc_mbx_read_top_ld_tf_WORD word7 |
3114 | #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 |
3115 | #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF |
3116 | #define lpfc_mbx_read_top_ld_link_spd_WORD word7 |
3117 | #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 |
3118 | #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F |
3119 | #define lpfc_mbx_read_top_ld_nl_port_WORD word7 |
3120 | #define lpfc_mbx_read_top_ld_tx_SHIFT 2 |
3121 | #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 |
3122 | #define lpfc_mbx_read_top_ld_tx_WORD word7 |
3123 | #define lpfc_mbx_read_top_ld_rx_SHIFT 0 |
3124 | #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 |
3125 | #define lpfc_mbx_read_top_ld_rx_WORD word7 |
3126 | uint32_t word8; |
3127 | #define lpfc_mbx_read_top_lu_SHIFT 31 |
3128 | #define lpfc_mbx_read_top_lu_MASK 0x00000001 |
3129 | #define lpfc_mbx_read_top_lu_WORD word8 |
3130 | #define lpfc_mbx_read_top_tf_SHIFT 30 |
3131 | #define lpfc_mbx_read_top_tf_MASK 0x00000001 |
3132 | #define lpfc_mbx_read_top_tf_WORD word8 |
3133 | #define lpfc_mbx_read_top_link_spd_SHIFT 8 |
3134 | #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF |
3135 | #define lpfc_mbx_read_top_link_spd_WORD word8 |
3136 | #define lpfc_mbx_read_top_nl_port_SHIFT 4 |
3137 | #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F |
3138 | #define lpfc_mbx_read_top_nl_port_WORD word8 |
3139 | #define lpfc_mbx_read_top_tx_SHIFT 2 |
3140 | #define lpfc_mbx_read_top_tx_MASK 0x00000003 |
3141 | #define lpfc_mbx_read_top_tx_WORD word8 |
3142 | #define lpfc_mbx_read_top_rx_SHIFT 0 |
3143 | #define lpfc_mbx_read_top_rx_MASK 0x00000003 |
3144 | #define lpfc_mbx_read_top_rx_WORD word8 |
3145 | #define LPFC_LINK_SPEED_UNKNOWN 0x0 |
3146 | #define LPFC_LINK_SPEED_1GHZ 0x04 |
3147 | #define LPFC_LINK_SPEED_2GHZ 0x08 |
3148 | #define LPFC_LINK_SPEED_4GHZ 0x10 |
3149 | #define LPFC_LINK_SPEED_8GHZ 0x20 |
3150 | #define LPFC_LINK_SPEED_10GHZ 0x40 |
3151 | #define LPFC_LINK_SPEED_16GHZ 0x80 |
3152 | #define LPFC_LINK_SPEED_32GHZ 0x90 |
3153 | #define LPFC_LINK_SPEED_64GHZ 0xA0 |
3154 | #define LPFC_LINK_SPEED_128GHZ 0xB0 |
3155 | #define LPFC_LINK_SPEED_256GHZ 0xC0 |
3156 | }; |
3157 | |
3158 | /* Structure for MB Command CLEAR_LA (22) */ |
3159 | |
3160 | typedef struct { |
3161 | uint32_t eventTag; /* Event tag */ |
3162 | uint32_t rsvd1; |
3163 | } CLEAR_LA_VAR; |
3164 | |
3165 | /* Structure for MB Command DUMP */ |
3166 | |
3167 | typedef struct { |
3168 | #ifdef __BIG_ENDIAN_BITFIELD |
3169 | uint32_t rsvd:25; |
3170 | uint32_t ra:1; |
3171 | uint32_t co:1; |
3172 | uint32_t cv:1; |
3173 | uint32_t type:4; |
3174 | uint32_t entry_index:16; |
3175 | uint32_t region_id:16; |
3176 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3177 | uint32_t type:4; |
3178 | uint32_t cv:1; |
3179 | uint32_t co:1; |
3180 | uint32_t ra:1; |
3181 | uint32_t rsvd:25; |
3182 | uint32_t region_id:16; |
3183 | uint32_t entry_index:16; |
3184 | #endif |
3185 | |
3186 | uint32_t sli4_length; |
3187 | uint32_t word_cnt; |
3188 | uint32_t resp_offset; |
3189 | } DUMP_VAR; |
3190 | |
3191 | #define DMP_MEM_REG 0x1 |
3192 | #define DMP_NV_PARAMS 0x2 |
3193 | #define DMP_LMSD 0x3 /* Link Module Serial Data */ |
3194 | #define DMP_WELL_KNOWN 0x4 |
3195 | |
3196 | #define DMP_REGION_VPD 0xe |
3197 | #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ |
3198 | #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ |
3199 | #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ |
3200 | |
3201 | #define DMP_REGION_VPORT 0x16 /* VPort info region */ |
3202 | #define DMP_VPORT_REGION_SIZE 0x200 |
3203 | #define DMP_MBOX_OFFSET_WORD 0x5 |
3204 | |
3205 | #define DMP_REGION_23 0x17 /* fcoe param and port state region */ |
3206 | #define DMP_RGN23_SIZE 0x400 |
3207 | |
3208 | #define WAKE_UP_PARMS_REGION_ID 4 |
3209 | #define WAKE_UP_PARMS_WORD_SIZE 15 |
3210 | |
3211 | struct vport_rec { |
3212 | uint8_t wwpn[8]; |
3213 | uint8_t wwnn[8]; |
3214 | }; |
3215 | |
3216 | #define VPORT_INFO_SIG 0x32324752 |
3217 | #define VPORT_INFO_REV_MASK 0xff |
3218 | #define VPORT_INFO_REV 0x1 |
3219 | #define MAX_STATIC_VPORT_COUNT 16 |
3220 | struct static_vport_info { |
3221 | uint32_t signature; |
3222 | uint32_t rev; |
3223 | struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; |
3224 | uint32_t resvd[66]; |
3225 | }; |
3226 | |
3227 | /* Option rom version structure */ |
3228 | struct prog_id { |
3229 | #ifdef __BIG_ENDIAN_BITFIELD |
3230 | uint8_t type; |
3231 | uint8_t id; |
3232 | uint32_t ver:4; /* Major Version */ |
3233 | uint32_t rev:4; /* Revision */ |
3234 | uint32_t lev:2; /* Level */ |
3235 | uint32_t dist:2; /* Dist Type */ |
3236 | uint32_t num:4; /* number after dist type */ |
3237 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3238 | uint32_t num:4; /* number after dist type */ |
3239 | uint32_t dist:2; /* Dist Type */ |
3240 | uint32_t lev:2; /* Level */ |
3241 | uint32_t rev:4; /* Revision */ |
3242 | uint32_t ver:4; /* Major Version */ |
3243 | uint8_t id; |
3244 | uint8_t type; |
3245 | #endif |
3246 | }; |
3247 | |
3248 | /* Structure for MB Command UPDATE_CFG (0x1B) */ |
3249 | |
3250 | struct update_cfg_var { |
3251 | #ifdef __BIG_ENDIAN_BITFIELD |
3252 | uint32_t rsvd2:16; |
3253 | uint32_t type:8; |
3254 | uint32_t rsvd:1; |
3255 | uint32_t ra:1; |
3256 | uint32_t co:1; |
3257 | uint32_t cv:1; |
3258 | uint32_t req:4; |
3259 | uint32_t entry_length:16; |
3260 | uint32_t region_id:16; |
3261 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3262 | uint32_t req:4; |
3263 | uint32_t cv:1; |
3264 | uint32_t co:1; |
3265 | uint32_t ra:1; |
3266 | uint32_t rsvd:1; |
3267 | uint32_t type:8; |
3268 | uint32_t rsvd2:16; |
3269 | uint32_t region_id:16; |
3270 | uint32_t entry_length:16; |
3271 | #endif |
3272 | |
3273 | uint32_t resp_info; |
3274 | uint32_t byte_cnt; |
3275 | uint32_t data_offset; |
3276 | }; |
3277 | |
3278 | struct hbq_mask { |
3279 | #ifdef __BIG_ENDIAN_BITFIELD |
3280 | uint8_t tmatch; |
3281 | uint8_t tmask; |
3282 | uint8_t rctlmatch; |
3283 | uint8_t rctlmask; |
3284 | #else /* __LITTLE_ENDIAN */ |
3285 | uint8_t rctlmask; |
3286 | uint8_t rctlmatch; |
3287 | uint8_t tmask; |
3288 | uint8_t tmatch; |
3289 | #endif |
3290 | }; |
3291 | |
3292 | |
3293 | /* Structure for MB Command CONFIG_HBQ (7c) */ |
3294 | |
3295 | struct config_hbq_var { |
3296 | #ifdef __BIG_ENDIAN_BITFIELD |
3297 | uint32_t rsvd1 :7; |
3298 | uint32_t recvNotify :1; /* Receive Notification */ |
3299 | uint32_t numMask :8; /* # Mask Entries */ |
3300 | uint32_t profile :8; /* Selection Profile */ |
3301 | uint32_t rsvd2 :8; |
3302 | #else /* __LITTLE_ENDIAN */ |
3303 | uint32_t rsvd2 :8; |
3304 | uint32_t profile :8; /* Selection Profile */ |
3305 | uint32_t numMask :8; /* # Mask Entries */ |
3306 | uint32_t recvNotify :1; /* Receive Notification */ |
3307 | uint32_t rsvd1 :7; |
3308 | #endif |
3309 | |
3310 | #ifdef __BIG_ENDIAN_BITFIELD |
3311 | uint32_t hbqId :16; |
3312 | uint32_t rsvd3 :12; |
3313 | uint32_t ringMask :4; |
3314 | #else /* __LITTLE_ENDIAN */ |
3315 | uint32_t ringMask :4; |
3316 | uint32_t rsvd3 :12; |
3317 | uint32_t hbqId :16; |
3318 | #endif |
3319 | |
3320 | #ifdef __BIG_ENDIAN_BITFIELD |
3321 | uint32_t entry_count :16; |
3322 | uint32_t rsvd4 :8; |
3323 | uint32_t headerLen :8; |
3324 | #else /* __LITTLE_ENDIAN */ |
3325 | uint32_t :8; |
3326 | uint32_t rsvd4 :8; |
3327 | uint32_t entry_count :16; |
3328 | #endif |
3329 | |
3330 | uint32_t hbqaddrLow; |
3331 | uint32_t hbqaddrHigh; |
3332 | |
3333 | #ifdef __BIG_ENDIAN_BITFIELD |
3334 | uint32_t rsvd5 :31; |
3335 | uint32_t logEntry :1; |
3336 | #else /* __LITTLE_ENDIAN */ |
3337 | uint32_t logEntry :1; |
3338 | uint32_t rsvd5 :31; |
3339 | #endif |
3340 | |
3341 | uint32_t rsvd6; /* w7 */ |
3342 | uint32_t rsvd7; /* w8 */ |
3343 | uint32_t rsvd8; /* w9 */ |
3344 | |
3345 | struct hbq_mask hbqMasks[6]; |
3346 | |
3347 | |
3348 | union { |
3349 | uint32_t allprofiles[12]; |
3350 | |
3351 | struct { |
3352 | #ifdef __BIG_ENDIAN_BITFIELD |
3353 | uint32_t seqlenoff :16; |
3354 | uint32_t maxlen :16; |
3355 | #else /* __LITTLE_ENDIAN */ |
3356 | uint32_t maxlen :16; |
3357 | uint32_t seqlenoff :16; |
3358 | #endif |
3359 | #ifdef __BIG_ENDIAN_BITFIELD |
3360 | uint32_t rsvd1 :28; |
3361 | uint32_t seqlenbcnt :4; |
3362 | #else /* __LITTLE_ENDIAN */ |
3363 | uint32_t seqlenbcnt :4; |
3364 | uint32_t rsvd1 :28; |
3365 | #endif |
3366 | uint32_t rsvd[10]; |
3367 | } profile2; |
3368 | |
3369 | struct { |
3370 | #ifdef __BIG_ENDIAN_BITFIELD |
3371 | uint32_t seqlenoff :16; |
3372 | uint32_t maxlen :16; |
3373 | #else /* __LITTLE_ENDIAN */ |
3374 | uint32_t maxlen :16; |
3375 | uint32_t seqlenoff :16; |
3376 | #endif |
3377 | #ifdef __BIG_ENDIAN_BITFIELD |
3378 | uint32_t cmdcodeoff :28; |
3379 | uint32_t rsvd1 :12; |
3380 | uint32_t seqlenbcnt :4; |
3381 | #else /* __LITTLE_ENDIAN */ |
3382 | uint32_t seqlenbcnt :4; |
3383 | uint32_t rsvd1 :12; |
3384 | uint32_t cmdcodeoff :28; |
3385 | #endif |
3386 | uint32_t cmdmatch[8]; |
3387 | |
3388 | uint32_t rsvd[2]; |
3389 | } profile3; |
3390 | |
3391 | struct { |
3392 | #ifdef __BIG_ENDIAN_BITFIELD |
3393 | uint32_t seqlenoff :16; |
3394 | uint32_t maxlen :16; |
3395 | #else /* __LITTLE_ENDIAN */ |
3396 | uint32_t maxlen :16; |
3397 | uint32_t seqlenoff :16; |
3398 | #endif |
3399 | #ifdef __BIG_ENDIAN_BITFIELD |
3400 | uint32_t cmdcodeoff :28; |
3401 | uint32_t rsvd1 :12; |
3402 | uint32_t seqlenbcnt :4; |
3403 | #else /* __LITTLE_ENDIAN */ |
3404 | uint32_t seqlenbcnt :4; |
3405 | uint32_t rsvd1 :12; |
3406 | uint32_t cmdcodeoff :28; |
3407 | #endif |
3408 | uint32_t cmdmatch[8]; |
3409 | |
3410 | uint32_t rsvd[2]; |
3411 | } profile5; |
3412 | |
3413 | } profiles; |
3414 | |
3415 | }; |
3416 | |
3417 | |
3418 | |
3419 | /* Structure for MB Command CONFIG_PORT (0x88) */ |
3420 | typedef struct { |
3421 | #ifdef __BIG_ENDIAN_BITFIELD |
3422 | uint32_t cBE : 1; |
3423 | uint32_t cET : 1; |
3424 | uint32_t cHpcb : 1; |
3425 | uint32_t cMA : 1; |
3426 | uint32_t sli_mode : 4; |
3427 | uint32_t pcbLen : 24; /* bit 23:0 of memory based port |
3428 | * config block */ |
3429 | #else /* __LITTLE_ENDIAN */ |
3430 | uint32_t pcbLen : 24; /* bit 23:0 of memory based port |
3431 | * config block */ |
3432 | uint32_t sli_mode : 4; |
3433 | uint32_t cMA : 1; |
3434 | uint32_t cHpcb : 1; |
3435 | uint32_t cET : 1; |
3436 | uint32_t cBE : 1; |
3437 | #endif |
3438 | |
3439 | uint32_t pcbLow; /* bit 31:0 of memory based port config block */ |
3440 | uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ |
3441 | uint32_t hbainit[5]; |
3442 | #ifdef __BIG_ENDIAN_BITFIELD |
3443 | uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ |
3444 | uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ |
3445 | #else /* __LITTLE_ENDIAN */ |
3446 | uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ |
3447 | uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ |
3448 | #endif |
3449 | |
3450 | #ifdef __BIG_ENDIAN_BITFIELD |
3451 | uint32_t rsvd1 : 20; /* Reserved */ |
3452 | uint32_t casabt : 1; /* Configure async abts status notice */ |
3453 | uint32_t rsvd2 : 2; /* Reserved */ |
3454 | uint32_t cbg : 1; /* Configure BlockGuard */ |
3455 | uint32_t cmv : 1; /* Configure Max VPIs */ |
3456 | uint32_t ccrp : 1; /* Config Command Ring Polling */ |
3457 | uint32_t csah : 1; /* Configure Synchronous Abort Handling */ |
3458 | uint32_t chbs : 1; /* Cofigure Host Backing store */ |
3459 | uint32_t cinb : 1; /* Enable Interrupt Notification Block */ |
3460 | uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ |
3461 | uint32_t cmx : 1; /* Configure Max XRIs */ |
3462 | uint32_t cmr : 1; /* Configure Max RPIs */ |
3463 | #else /* __LITTLE_ENDIAN */ |
3464 | uint32_t cmr : 1; /* Configure Max RPIs */ |
3465 | uint32_t cmx : 1; /* Configure Max XRIs */ |
3466 | uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ |
3467 | uint32_t cinb : 1; /* Enable Interrupt Notification Block */ |
3468 | uint32_t chbs : 1; /* Cofigure Host Backing store */ |
3469 | uint32_t csah : 1; /* Configure Synchronous Abort Handling */ |
3470 | uint32_t ccrp : 1; /* Config Command Ring Polling */ |
3471 | uint32_t cmv : 1; /* Configure Max VPIs */ |
3472 | uint32_t cbg : 1; /* Configure BlockGuard */ |
3473 | uint32_t rsvd2 : 2; /* Reserved */ |
3474 | uint32_t casabt : 1; /* Configure async abts status notice */ |
3475 | uint32_t rsvd1 : 20; /* Reserved */ |
3476 | #endif |
3477 | #ifdef __BIG_ENDIAN_BITFIELD |
3478 | uint32_t rsvd3 : 20; /* Reserved */ |
3479 | uint32_t gasabt : 1; /* Grant async abts status notice */ |
3480 | uint32_t rsvd4 : 2; /* Reserved */ |
3481 | uint32_t gbg : 1; /* Grant BlockGuard */ |
3482 | uint32_t gmv : 1; /* Grant Max VPIs */ |
3483 | uint32_t gcrp : 1; /* Grant Command Ring Polling */ |
3484 | uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ |
3485 | uint32_t ghbs : 1; /* Grant Host Backing Store */ |
3486 | uint32_t ginb : 1; /* Grant Interrupt Notification Block */ |
3487 | uint32_t gerbm : 1; /* Grant ERBM Request */ |
3488 | uint32_t gmx : 1; /* Grant Max XRIs */ |
3489 | uint32_t gmr : 1; /* Grant Max RPIs */ |
3490 | #else /* __LITTLE_ENDIAN */ |
3491 | uint32_t gmr : 1; /* Grant Max RPIs */ |
3492 | uint32_t gmx : 1; /* Grant Max XRIs */ |
3493 | uint32_t gerbm : 1; /* Grant ERBM Request */ |
3494 | uint32_t ginb : 1; /* Grant Interrupt Notification Block */ |
3495 | uint32_t ghbs : 1; /* Grant Host Backing Store */ |
3496 | uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ |
3497 | uint32_t gcrp : 1; /* Grant Command Ring Polling */ |
3498 | uint32_t gmv : 1; /* Grant Max VPIs */ |
3499 | uint32_t gbg : 1; /* Grant BlockGuard */ |
3500 | uint32_t rsvd4 : 2; /* Reserved */ |
3501 | uint32_t gasabt : 1; /* Grant async abts status notice */ |
3502 | uint32_t rsvd3 : 20; /* Reserved */ |
3503 | #endif |
3504 | |
3505 | #ifdef __BIG_ENDIAN_BITFIELD |
3506 | uint32_t max_rpi : 16; /* Max RPIs Port should configure */ |
3507 | uint32_t max_xri : 16; /* Max XRIs Port should configure */ |
3508 | #else /* __LITTLE_ENDIAN */ |
3509 | uint32_t max_xri : 16; /* Max XRIs Port should configure */ |
3510 | uint32_t max_rpi : 16; /* Max RPIs Port should configure */ |
3511 | #endif |
3512 | |
3513 | #ifdef __BIG_ENDIAN_BITFIELD |
3514 | uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ |
3515 | uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ |
3516 | #else /* __LITTLE_ENDIAN */ |
3517 | uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ |
3518 | uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ |
3519 | #endif |
3520 | |
3521 | uint32_t rsvd6; /* Reserved */ |
3522 | |
3523 | #ifdef __BIG_ENDIAN_BITFIELD |
3524 | uint32_t rsvd7 : 16; |
3525 | uint32_t max_vpi : 16; /* Max number of virt N-Ports */ |
3526 | #else /* __LITTLE_ENDIAN */ |
3527 | uint32_t max_vpi : 16; /* Max number of virt N-Ports */ |
3528 | uint32_t rsvd7 : 16; |
3529 | #endif |
3530 | |
3531 | } CONFIG_PORT_VAR; |
3532 | |
3533 | /* Structure for MB Command CONFIG_MSI (0x30) */ |
3534 | struct config_msi_var { |
3535 | #ifdef __BIG_ENDIAN_BITFIELD |
3536 | uint32_t dfltMsgNum:8; /* Default message number */ |
3537 | uint32_t rsvd1:11; /* Reserved */ |
3538 | uint32_t NID:5; /* Number of secondary attention IDs */ |
3539 | uint32_t rsvd2:5; /* Reserved */ |
3540 | uint32_t dfltPresent:1; /* Default message number present */ |
3541 | uint32_t addFlag:1; /* Add association flag */ |
3542 | uint32_t reportFlag:1; /* Report association flag */ |
3543 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3544 | uint32_t reportFlag:1; /* Report association flag */ |
3545 | uint32_t addFlag:1; /* Add association flag */ |
3546 | uint32_t dfltPresent:1; /* Default message number present */ |
3547 | uint32_t rsvd2:5; /* Reserved */ |
3548 | uint32_t NID:5; /* Number of secondary attention IDs */ |
3549 | uint32_t rsvd1:11; /* Reserved */ |
3550 | uint32_t dfltMsgNum:8; /* Default message number */ |
3551 | #endif |
3552 | uint32_t attentionConditions[2]; |
3553 | uint8_t attentionId[16]; |
3554 | uint8_t messageNumberByHA[64]; |
3555 | uint8_t messageNumberByID[16]; |
3556 | uint32_t autoClearHA[2]; |
3557 | #ifdef __BIG_ENDIAN_BITFIELD |
3558 | uint32_t rsvd3:16; |
3559 | uint32_t autoClearID:16; |
3560 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3561 | uint32_t autoClearID:16; |
3562 | uint32_t rsvd3:16; |
3563 | #endif |
3564 | uint32_t rsvd4; |
3565 | }; |
3566 | |
3567 | /* SLI-2 Port Control Block */ |
3568 | |
3569 | /* SLIM POINTER */ |
3570 | #define SLIMOFF 0x30 /* WORD */ |
3571 | |
3572 | typedef struct _SLI2_RDSC { |
3573 | uint32_t cmdEntries; |
3574 | uint32_t cmdAddrLow; |
3575 | uint32_t cmdAddrHigh; |
3576 | |
3577 | uint32_t rspEntries; |
3578 | uint32_t rspAddrLow; |
3579 | uint32_t rspAddrHigh; |
3580 | } SLI2_RDSC; |
3581 | |
3582 | typedef struct _PCB { |
3583 | #ifdef __BIG_ENDIAN_BITFIELD |
3584 | uint32_t type:8; |
3585 | #define TYPE_NATIVE_SLI2 0x01 |
3586 | uint32_t feature:8; |
3587 | #define FEATURE_INITIAL_SLI2 0x01 |
3588 | uint32_t rsvd:12; |
3589 | uint32_t maxRing:4; |
3590 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3591 | uint32_t maxRing:4; |
3592 | uint32_t rsvd:12; |
3593 | uint32_t feature:8; |
3594 | #define FEATURE_INITIAL_SLI2 0x01 |
3595 | uint32_t type:8; |
3596 | #define TYPE_NATIVE_SLI2 0x01 |
3597 | #endif |
3598 | |
3599 | uint32_t mailBoxSize; |
3600 | uint32_t mbAddrLow; |
3601 | uint32_t mbAddrHigh; |
3602 | |
3603 | uint32_t hgpAddrLow; |
3604 | uint32_t hgpAddrHigh; |
3605 | |
3606 | uint32_t pgpAddrLow; |
3607 | uint32_t pgpAddrHigh; |
3608 | SLI2_RDSC rdsc[MAX_SLI3_RINGS]; |
3609 | } PCB_t; |
3610 | |
3611 | /* NEW_FEATURE */ |
3612 | typedef struct { |
3613 | #ifdef __BIG_ENDIAN_BITFIELD |
3614 | uint32_t rsvd0:27; |
3615 | uint32_t discardFarp:1; |
3616 | uint32_t IPEnable:1; |
3617 | uint32_t nodeName:1; |
3618 | uint32_t portName:1; |
3619 | uint32_t filterEnable:1; |
3620 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3621 | uint32_t filterEnable:1; |
3622 | uint32_t portName:1; |
3623 | uint32_t nodeName:1; |
3624 | uint32_t IPEnable:1; |
3625 | uint32_t discardFarp:1; |
3626 | uint32_t rsvd:27; |
3627 | #endif |
3628 | |
3629 | uint8_t portname[8]; /* Used to be struct lpfc_name */ |
3630 | uint8_t nodename[8]; |
3631 | uint32_t rsvd1; |
3632 | uint32_t rsvd2; |
3633 | uint32_t rsvd3; |
3634 | uint32_t IPAddress; |
3635 | } CONFIG_FARP_VAR; |
3636 | |
3637 | /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ |
3638 | |
3639 | typedef struct { |
3640 | #ifdef __BIG_ENDIAN_BITFIELD |
3641 | uint32_t rsvd:30; |
3642 | uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ |
3643 | #else /* __LITTLE_ENDIAN */ |
3644 | uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ |
3645 | uint32_t rsvd:30; |
3646 | #endif |
3647 | } ASYNCEVT_ENABLE_VAR; |
3648 | |
3649 | /* Union of all Mailbox Command types */ |
3650 | #define MAILBOX_CMD_WSIZE 32 |
3651 | #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) |
3652 | /* ext_wsize times 4 bytes should not be greater than max xmit size */ |
3653 | #define MAILBOX_EXT_WSIZE 512 |
3654 | #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) |
3655 | #define MAILBOX_HBA_EXT_OFFSET 0x100 |
3656 | /* max mbox xmit size is a page size for sysfs IO operations */ |
3657 | #define MAILBOX_SYSFS_MAX 4096 |
3658 | |
3659 | typedef union { |
3660 | uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ |
3661 | * feature/max ring number |
3662 | */ |
3663 | LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ |
3664 | READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ |
3665 | WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ |
3666 | BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ |
3667 | INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ |
3668 | DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ |
3669 | CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ |
3670 | PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ |
3671 | CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ |
3672 | RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ |
3673 | READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ |
3674 | READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ |
3675 | READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ |
3676 | READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ |
3677 | READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ |
3678 | READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ |
3679 | READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ |
3680 | READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ |
3681 | REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ |
3682 | UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ |
3683 | CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ |
3684 | DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ |
3685 | UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ |
3686 | CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) |
3687 | * NEW_FEATURE |
3688 | */ |
3689 | struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ |
3690 | struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ |
3691 | CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ |
3692 | struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ |
3693 | REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ |
3694 | UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ |
3695 | ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ |
3696 | struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 |
3697 | * (READ_EVENT_LOG) |
3698 | */ |
3699 | struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ |
3700 | } MAILVARIANTS; |
3701 | |
3702 | /* |
3703 | * SLI-2 specific structures |
3704 | */ |
3705 | |
3706 | struct lpfc_hgp { |
3707 | __le32 cmdPutInx; |
3708 | __le32 rspGetInx; |
3709 | }; |
3710 | |
3711 | struct lpfc_pgp { |
3712 | __le32 cmdGetInx; |
3713 | __le32 rspPutInx; |
3714 | }; |
3715 | |
3716 | struct sli2_desc { |
3717 | uint32_t unused1[16]; |
3718 | struct lpfc_hgp host[MAX_SLI3_RINGS]; |
3719 | struct lpfc_pgp port[MAX_SLI3_RINGS]; |
3720 | }; |
3721 | |
3722 | struct sli3_desc { |
3723 | struct lpfc_hgp host[MAX_SLI3_RINGS]; |
3724 | uint32_t reserved[8]; |
3725 | uint32_t hbq_put[16]; |
3726 | }; |
3727 | |
3728 | struct sli3_pgp { |
3729 | struct lpfc_pgp port[MAX_SLI3_RINGS]; |
3730 | uint32_t hbq_get[16]; |
3731 | }; |
3732 | |
3733 | union sli_var { |
3734 | struct sli2_desc s2; |
3735 | struct sli3_desc s3; |
3736 | struct sli3_pgp s3_pgp; |
3737 | }; |
3738 | |
3739 | typedef struct { |
3740 | struct_group_tagged(MAILBOX_word0, bits, |
3741 | union { |
3742 | struct { |
3743 | #ifdef __BIG_ENDIAN_BITFIELD |
3744 | uint16_t mbxStatus; |
3745 | uint8_t mbxCommand; |
3746 | uint8_t mbxReserved:6; |
3747 | uint8_t mbxHc:1; |
3748 | uint8_t mbxOwner:1; /* Low order bit first word */ |
3749 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3750 | uint8_t mbxOwner:1; /* Low order bit first word */ |
3751 | uint8_t mbxHc:1; |
3752 | uint8_t mbxReserved:6; |
3753 | uint8_t mbxCommand; |
3754 | uint16_t mbxStatus; |
3755 | #endif |
3756 | }; |
3757 | u32 word0; |
3758 | }; |
3759 | ); |
3760 | |
3761 | MAILVARIANTS un; |
3762 | union sli_var us; |
3763 | } MAILBOX_t; |
3764 | |
3765 | /* |
3766 | * Begin Structure Definitions for IOCB Commands |
3767 | */ |
3768 | |
3769 | typedef struct { |
3770 | #ifdef __BIG_ENDIAN_BITFIELD |
3771 | uint8_t statAction; |
3772 | uint8_t statRsn; |
3773 | uint8_t statBaExp; |
3774 | uint8_t statLocalError; |
3775 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3776 | uint8_t statLocalError; |
3777 | uint8_t statBaExp; |
3778 | uint8_t statRsn; |
3779 | uint8_t statAction; |
3780 | #endif |
3781 | /* statRsn P/F_RJT reason codes */ |
3782 | #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ |
3783 | #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ |
3784 | #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ |
3785 | #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ |
3786 | #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ |
3787 | #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ |
3788 | #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ |
3789 | #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ |
3790 | #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ |
3791 | #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ |
3792 | #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ |
3793 | #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ |
3794 | #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ |
3795 | #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ |
3796 | #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ |
3797 | #define RJT_BAD_PARM 0x10 /* Param. field invalid */ |
3798 | #define RJT_XCHG_ERR 0x11 /* Exchange error */ |
3799 | #define RJT_PROT_ERR 0x12 /* Protocol error */ |
3800 | #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ |
3801 | #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ |
3802 | #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ |
3803 | #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ |
3804 | #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ |
3805 | #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ |
3806 | #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ |
3807 | #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ |
3808 | |
3809 | #define IOERR_SUCCESS 0x00 /* statLocalError */ |
3810 | #define IOERR_MISSING_CONTINUE 0x01 |
3811 | #define IOERR_SEQUENCE_TIMEOUT 0x02 |
3812 | #define IOERR_INTERNAL_ERROR 0x03 |
3813 | #define IOERR_INVALID_RPI 0x04 |
3814 | #define IOERR_NO_XRI 0x05 |
3815 | #define IOERR_ILLEGAL_COMMAND 0x06 |
3816 | #define IOERR_XCHG_DROPPED 0x07 |
3817 | #define IOERR_ILLEGAL_FIELD 0x08 |
3818 | #define IOERR_RPI_SUSPENDED 0x09 |
3819 | #define IOERR_TOO_MANY_BUFFERS 0x0A |
3820 | #define IOERR_RCV_BUFFER_WAITING 0x0B |
3821 | #define IOERR_NO_CONNECTION 0x0C |
3822 | #define IOERR_TX_DMA_FAILED 0x0D |
3823 | #define IOERR_RX_DMA_FAILED 0x0E |
3824 | #define IOERR_ILLEGAL_FRAME 0x0F |
3825 | #define 0x10 |
3826 | #define IOERR_NO_RESOURCES 0x11 |
3827 | #define IOERR_RESERVED 0x12 |
3828 | #define IOERR_ILLEGAL_LENGTH 0x13 |
3829 | #define IOERR_UNSUPPORTED_FEATURE 0x14 |
3830 | #define IOERR_ABORT_IN_PROGRESS 0x15 |
3831 | #define IOERR_ABORT_REQUESTED 0x16 |
3832 | #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 |
3833 | #define IOERR_LOOP_OPEN_FAILURE 0x18 |
3834 | #define IOERR_RING_RESET 0x19 |
3835 | #define IOERR_LINK_DOWN 0x1A |
3836 | #define IOERR_CORRUPTED_DATA 0x1B |
3837 | #define IOERR_CORRUPTED_RPI 0x1C |
3838 | #define IOERR_OUT_OF_ORDER_DATA 0x1D |
3839 | #define IOERR_OUT_OF_ORDER_ACK 0x1E |
3840 | #define IOERR_DUP_FRAME 0x1F |
3841 | #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ |
3842 | #define IOERR_BAD_HOST_ADDRESS 0x21 |
3843 | #define IOERR_RCV_HDRBUF_WAITING 0x22 |
3844 | #define IOERR_MISSING_HDR_BUFFER 0x23 |
3845 | #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 |
3846 | #define IOERR_ABORTMULT_REQUESTED 0x25 |
3847 | #define IOERR_BUFFER_SHORTAGE 0x28 |
3848 | #define IOERR_DEFAULT 0x29 |
3849 | #define IOERR_CNT 0x2A |
3850 | #define IOERR_SLER_FAILURE 0x46 |
3851 | #define IOERR_SLER_CMD_RCV_FAILURE 0x47 |
3852 | #define IOERR_SLER_REC_RJT_ERR 0x48 |
3853 | #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 |
3854 | #define IOERR_SLER_SRR_RJT_ERR 0x4A |
3855 | #define IOERR_SLER_RRQ_RJT_ERR 0x4C |
3856 | #define IOERR_SLER_RRQ_RETRY_ERR 0x4D |
3857 | #define IOERR_SLER_ABTS_ERR 0x4E |
3858 | #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 |
3859 | #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 |
3860 | #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 |
3861 | #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 |
3862 | #define IOERR_DRVR_MASK 0x100 |
3863 | #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ |
3864 | #define IOERR_SLI_BRESET 0x102 |
3865 | #define IOERR_SLI_ABORTED 0x103 |
3866 | #define IOERR_PARAM_MASK 0x1ff |
3867 | } PARM_ERR; |
3868 | |
3869 | typedef union { |
3870 | struct { |
3871 | #ifdef __BIG_ENDIAN_BITFIELD |
3872 | uint8_t Rctl; /* R_CTL field */ |
3873 | uint8_t Type; /* TYPE field */ |
3874 | uint8_t Dfctl; /* DF_CTL field */ |
3875 | uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ |
3876 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3877 | uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ |
3878 | uint8_t Dfctl; /* DF_CTL field */ |
3879 | uint8_t Type; /* TYPE field */ |
3880 | uint8_t Rctl; /* R_CTL field */ |
3881 | #endif |
3882 | |
3883 | #define BC 0x02 /* Broadcast Received - Fctl */ |
3884 | #define SI 0x04 /* Sequence Initiative */ |
3885 | #define LA 0x08 /* Ignore Link Attention state */ |
3886 | #define LS 0x80 /* Last Sequence */ |
3887 | } hcsw; |
3888 | uint32_t reserved; |
3889 | } WORD5; |
3890 | |
3891 | /* IOCB Command template for a generic response */ |
3892 | typedef struct { |
3893 | uint32_t reserved[4]; |
3894 | PARM_ERR perr; |
3895 | } GENERIC_RSP; |
3896 | |
3897 | /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ |
3898 | typedef struct { |
3899 | struct ulp_bde xrsqbde[2]; |
3900 | uint32_t xrsqRo; /* Starting Relative Offset */ |
3901 | WORD5 w5; /* Header control/status word */ |
3902 | } XR_SEQ_FIELDS; |
3903 | |
3904 | /* IOCB Command template for ELS_REQUEST */ |
3905 | typedef struct { |
3906 | struct ulp_bde elsReq; |
3907 | struct ulp_bde elsRsp; |
3908 | |
3909 | #ifdef __BIG_ENDIAN_BITFIELD |
3910 | uint32_t word4Rsvd:7; |
3911 | uint32_t fl:1; |
3912 | uint32_t myID:24; |
3913 | uint32_t word5Rsvd:8; |
3914 | uint32_t remoteID:24; |
3915 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3916 | uint32_t myID:24; |
3917 | uint32_t fl:1; |
3918 | uint32_t word4Rsvd:7; |
3919 | uint32_t remoteID:24; |
3920 | uint32_t word5Rsvd:8; |
3921 | #endif |
3922 | } ELS_REQUEST; |
3923 | |
3924 | /* IOCB Command template for RCV_ELS_REQ */ |
3925 | typedef struct { |
3926 | struct ulp_bde elsReq[2]; |
3927 | uint32_t parmRo; |
3928 | |
3929 | #ifdef __BIG_ENDIAN_BITFIELD |
3930 | uint32_t word5Rsvd:8; |
3931 | uint32_t remoteID:24; |
3932 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3933 | uint32_t remoteID:24; |
3934 | uint32_t word5Rsvd:8; |
3935 | #endif |
3936 | } RCV_ELS_REQ; |
3937 | |
3938 | /* IOCB Command template for ABORT / CLOSE_XRI */ |
3939 | typedef struct { |
3940 | uint32_t rsvd[3]; |
3941 | uint32_t abortType; |
3942 | #define ABORT_TYPE_ABTX 0x00000000 |
3943 | #define ABORT_TYPE_ABTS 0x00000001 |
3944 | uint32_t parm; |
3945 | #ifdef __BIG_ENDIAN_BITFIELD |
3946 | uint16_t abortContextTag; /* ulpContext from command to abort/close */ |
3947 | uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ |
3948 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3949 | uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ |
3950 | uint16_t abortContextTag; /* ulpContext from command to abort/close */ |
3951 | #endif |
3952 | } AC_XRI; |
3953 | |
3954 | /* IOCB Command template for ABORT_MXRI64 */ |
3955 | typedef struct { |
3956 | uint32_t rsvd[3]; |
3957 | uint32_t abortType; |
3958 | uint32_t parm; |
3959 | uint32_t iotag32; |
3960 | } A_MXRI64; |
3961 | |
3962 | /* IOCB Command template for GET_RPI */ |
3963 | typedef struct { |
3964 | uint32_t rsvd[4]; |
3965 | uint32_t parmRo; |
3966 | #ifdef __BIG_ENDIAN_BITFIELD |
3967 | uint32_t word5Rsvd:8; |
3968 | uint32_t remoteID:24; |
3969 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
3970 | uint32_t remoteID:24; |
3971 | uint32_t word5Rsvd:8; |
3972 | #endif |
3973 | } GET_RPI; |
3974 | |
3975 | /* IOCB Command template for all FCP Initiator commands */ |
3976 | typedef struct { |
3977 | struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ |
3978 | struct ulp_bde fcpi_rsp; /* Rcv buffer */ |
3979 | uint32_t fcpi_parm; |
3980 | uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ |
3981 | } FCPI_FIELDS; |
3982 | |
3983 | /* IOCB Command template for all FCP Target commands */ |
3984 | typedef struct { |
3985 | struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ |
3986 | uint32_t fcpt_Offset; |
3987 | uint32_t fcpt_Length; /* transfer ready for IWRITE */ |
3988 | } FCPT_FIELDS; |
3989 | |
3990 | /* SLI-2 IOCB structure definitions */ |
3991 | |
3992 | /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ |
3993 | typedef struct { |
3994 | ULP_BDL bdl; |
3995 | uint32_t xrsqRo; /* Starting Relative Offset */ |
3996 | WORD5 w5; /* Header control/status word */ |
3997 | } XMT_SEQ_FIELDS64; |
3998 | |
3999 | /* This word is remote ports D_ID for XMIT_ELS_RSP64 */ |
4000 | #define xmit_els_remoteID xrsqRo |
4001 | |
4002 | /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ |
4003 | typedef struct { |
4004 | struct ulp_bde64 rcvBde; |
4005 | uint32_t rsvd1; |
4006 | uint32_t xrsqRo; /* Starting Relative Offset */ |
4007 | WORD5 w5; /* Header control/status word */ |
4008 | } RCV_SEQ_FIELDS64; |
4009 | |
4010 | /* IOCB Command template for ELS_REQUEST64 */ |
4011 | typedef struct { |
4012 | ULP_BDL bdl; |
4013 | #ifdef __BIG_ENDIAN_BITFIELD |
4014 | uint32_t word4Rsvd:7; |
4015 | uint32_t fl:1; |
4016 | uint32_t myID:24; |
4017 | uint32_t word5Rsvd:8; |
4018 | uint32_t remoteID:24; |
4019 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
4020 | uint32_t myID:24; |
4021 | uint32_t fl:1; |
4022 | uint32_t word4Rsvd:7; |
4023 | uint32_t remoteID:24; |
4024 | uint32_t word5Rsvd:8; |
4025 | #endif |
4026 | } ELS_REQUEST64; |
4027 | |
4028 | /* IOCB Command template for GEN_REQUEST64 */ |
4029 | typedef struct { |
4030 | ULP_BDL bdl; |
4031 | uint32_t xrsqRo; /* Starting Relative Offset */ |
4032 | WORD5 w5; /* Header control/status word */ |
4033 | } GEN_REQUEST64; |
4034 | |
4035 | /* IOCB Command template for RCV_ELS_REQ64 */ |
4036 | typedef struct { |
4037 | struct ulp_bde64 elsReq; |
4038 | uint32_t rcvd1; |
4039 | uint32_t parmRo; |
4040 | |
4041 | #ifdef __BIG_ENDIAN_BITFIELD |
4042 | uint32_t word5Rsvd:8; |
4043 | uint32_t remoteID:24; |
4044 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
4045 | uint32_t remoteID:24; |
4046 | uint32_t word5Rsvd:8; |
4047 | #endif |
4048 | } RCV_ELS_REQ64; |
4049 | |
4050 | /* IOCB Command template for RCV_SEQ64 */ |
4051 | struct rcv_seq64 { |
4052 | struct ulp_bde64 elsReq; |
4053 | uint32_t hbq_1; |
4054 | uint32_t parmRo; |
4055 | #ifdef __BIG_ENDIAN_BITFIELD |
4056 | uint32_t rctl:8; |
4057 | uint32_t type:8; |
4058 | uint32_t dfctl:8; |
4059 | uint32_t ls:1; |
4060 | uint32_t fs:1; |
4061 | uint32_t rsvd2:3; |
4062 | uint32_t si:1; |
4063 | uint32_t bc:1; |
4064 | uint32_t rsvd3:1; |
4065 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
4066 | uint32_t rsvd3:1; |
4067 | uint32_t bc:1; |
4068 | uint32_t si:1; |
4069 | uint32_t rsvd2:3; |
4070 | uint32_t fs:1; |
4071 | uint32_t ls:1; |
4072 | uint32_t dfctl:8; |
4073 | uint32_t type:8; |
4074 | uint32_t rctl:8; |
4075 | #endif |
4076 | }; |
4077 | |
4078 | /* IOCB Command template for all 64 bit FCP Initiator commands */ |
4079 | typedef struct { |
4080 | ULP_BDL bdl; |
4081 | uint32_t fcpi_parm; |
4082 | uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ |
4083 | } FCPI_FIELDS64; |
4084 | |
4085 | /* IOCB Command template for all 64 bit FCP Target commands */ |
4086 | typedef struct { |
4087 | ULP_BDL bdl; |
4088 | uint32_t fcpt_Offset; |
4089 | uint32_t fcpt_Length; /* transfer ready for IWRITE */ |
4090 | } FCPT_FIELDS64; |
4091 | |
4092 | /* IOCB Command template for Async Status iocb commands */ |
4093 | typedef struct { |
4094 | uint32_t rsvd[4]; |
4095 | uint32_t param; |
4096 | #ifdef __BIG_ENDIAN_BITFIELD |
4097 | uint16_t evt_code; /* High order bits word 5 */ |
4098 | uint16_t sub_ctxt_tag; /* Low order bits word 5 */ |
4099 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
4100 | uint16_t sub_ctxt_tag; /* High order bits word 5 */ |
4101 | uint16_t evt_code; /* Low order bits word 5 */ |
4102 | #endif |
4103 | } ASYNCSTAT_FIELDS; |
4104 | #define ASYNC_TEMP_WARN 0x100 |
4105 | #define ASYNC_TEMP_SAFE 0x101 |
4106 | #define ASYNC_STATUS_CN 0x102 |
4107 | |
4108 | /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) |
4109 | or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ |
4110 | |
4111 | struct rcv_sli3 { |
4112 | #ifdef __BIG_ENDIAN_BITFIELD |
4113 | uint16_t ox_id; |
4114 | uint16_t seq_cnt; |
4115 | |
4116 | uint16_t vpi; |
4117 | uint16_t word9Rsvd; |
4118 | #else /* __LITTLE_ENDIAN */ |
4119 | uint16_t seq_cnt; |
4120 | uint16_t ox_id; |
4121 | |
4122 | uint16_t word9Rsvd; |
4123 | uint16_t vpi; |
4124 | #endif |
4125 | uint32_t word10Rsvd; |
4126 | uint32_t acc_len; /* accumulated length */ |
4127 | struct ulp_bde64 bde2; |
4128 | }; |
4129 | |
4130 | /* Structure used for a single HBQ entry */ |
4131 | struct lpfc_hbq_entry { |
4132 | struct ulp_bde64 bde; |
4133 | uint32_t buffer_tag; |
4134 | }; |
4135 | |
4136 | /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ |
4137 | typedef struct { |
4138 | struct lpfc_hbq_entry buff; |
4139 | uint32_t rsvd; |
4140 | uint32_t rsvd1; |
4141 | } QUE_XRI64_CX_FIELDS; |
4142 | |
4143 | struct que_xri64cx_ext_fields { |
4144 | uint32_t iotag64_low; |
4145 | uint32_t iotag64_high; |
4146 | uint32_t ebde_count; |
4147 | uint32_t rsvd; |
4148 | struct lpfc_hbq_entry buff[5]; |
4149 | }; |
4150 | |
4151 | struct sli3_bg_fields { |
4152 | uint32_t filler[6]; /* word 8-13 in IOCB */ |
4153 | uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ |
4154 | /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ |
4155 | #define BGS_BIDIR_BG_PROF_MASK 0xff000000 |
4156 | #define BGS_BIDIR_BG_PROF_SHIFT 24 |
4157 | #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 |
4158 | #define BGS_BIDIR_ERR_COND_SHIFT 16 |
4159 | #define BGS_BG_PROFILE_MASK 0x0000ff00 |
4160 | #define BGS_BG_PROFILE_SHIFT 8 |
4161 | #define BGS_INVALID_PROF_MASK 0x00000020 |
4162 | #define BGS_INVALID_PROF_SHIFT 5 |
4163 | #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 |
4164 | #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 |
4165 | #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 |
4166 | #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 |
4167 | #define BGS_REFTAG_ERR_MASK 0x00000004 |
4168 | #define BGS_REFTAG_ERR_SHIFT 2 |
4169 | #define BGS_APPTAG_ERR_MASK 0x00000002 |
4170 | #define BGS_APPTAG_ERR_SHIFT 1 |
4171 | #define BGS_GUARD_ERR_MASK 0x00000001 |
4172 | #define BGS_GUARD_ERR_SHIFT 0 |
4173 | uint32_t bgstat; /* word 15 - BlockGuard Status */ |
4174 | }; |
4175 | |
4176 | static inline uint32_t |
4177 | lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) |
4178 | { |
4179 | return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> |
4180 | BGS_BIDIR_BG_PROF_SHIFT; |
4181 | } |
4182 | |
4183 | static inline uint32_t |
4184 | lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) |
4185 | { |
4186 | return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> |
4187 | BGS_BIDIR_ERR_COND_SHIFT; |
4188 | } |
4189 | |
4190 | static inline uint32_t |
4191 | lpfc_bgs_get_bg_prof(uint32_t bgstat) |
4192 | { |
4193 | return (bgstat & BGS_BG_PROFILE_MASK) >> |
4194 | BGS_BG_PROFILE_SHIFT; |
4195 | } |
4196 | |
4197 | static inline uint32_t |
4198 | lpfc_bgs_get_invalid_prof(uint32_t bgstat) |
4199 | { |
4200 | return (bgstat & BGS_INVALID_PROF_MASK) >> |
4201 | BGS_INVALID_PROF_SHIFT; |
4202 | } |
4203 | |
4204 | static inline uint32_t |
4205 | lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) |
4206 | { |
4207 | return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> |
4208 | BGS_UNINIT_DIF_BLOCK_SHIFT; |
4209 | } |
4210 | |
4211 | static inline uint32_t |
4212 | lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) |
4213 | { |
4214 | return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> |
4215 | BGS_HI_WATER_MARK_PRESENT_SHIFT; |
4216 | } |
4217 | |
4218 | static inline uint32_t |
4219 | lpfc_bgs_get_reftag_err(uint32_t bgstat) |
4220 | { |
4221 | return (bgstat & BGS_REFTAG_ERR_MASK) >> |
4222 | BGS_REFTAG_ERR_SHIFT; |
4223 | } |
4224 | |
4225 | static inline uint32_t |
4226 | lpfc_bgs_get_apptag_err(uint32_t bgstat) |
4227 | { |
4228 | return (bgstat & BGS_APPTAG_ERR_MASK) >> |
4229 | BGS_APPTAG_ERR_SHIFT; |
4230 | } |
4231 | |
4232 | static inline uint32_t |
4233 | lpfc_bgs_get_guard_err(uint32_t bgstat) |
4234 | { |
4235 | return (bgstat & BGS_GUARD_ERR_MASK) >> |
4236 | BGS_GUARD_ERR_SHIFT; |
4237 | } |
4238 | |
4239 | #define LPFC_EXT_DATA_BDE_COUNT 3 |
4240 | struct fcp_irw_ext { |
4241 | uint32_t io_tag64_low; |
4242 | uint32_t io_tag64_high; |
4243 | #ifdef __BIG_ENDIAN_BITFIELD |
4244 | uint8_t reserved1; |
4245 | uint8_t reserved2; |
4246 | uint8_t reserved3; |
4247 | uint8_t ebde_count; |
4248 | #else /* __LITTLE_ENDIAN */ |
4249 | uint8_t ebde_count; |
4250 | uint8_t reserved3; |
4251 | uint8_t reserved2; |
4252 | uint8_t reserved1; |
4253 | #endif |
4254 | uint32_t reserved4; |
4255 | struct ulp_bde64 rbde; /* response bde */ |
4256 | struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ |
4257 | uint8_t icd[32]; /* immediate command data (32 bytes) */ |
4258 | }; |
4259 | |
4260 | typedef struct _IOCB { /* IOCB structure */ |
4261 | union { |
4262 | GENERIC_RSP grsp; /* Generic response */ |
4263 | XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ |
4264 | struct ulp_bde cont[3]; /* up to 3 continuation bdes */ |
4265 | RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ |
4266 | AC_XRI acxri; /* ABORT / CLOSE_XRI template */ |
4267 | A_MXRI64 amxri; /* abort multiple xri command overlay */ |
4268 | GET_RPI getrpi; /* GET_RPI template */ |
4269 | FCPI_FIELDS fcpi; /* FCP Initiator template */ |
4270 | FCPT_FIELDS fcpt; /* FCP target template */ |
4271 | |
4272 | /* SLI-2 structures */ |
4273 | |
4274 | struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation |
4275 | * bde_64s */ |
4276 | ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ |
4277 | GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ |
4278 | RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ |
4279 | XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ |
4280 | FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ |
4281 | FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ |
4282 | ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ |
4283 | QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ |
4284 | struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ |
4285 | struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ |
4286 | uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ |
4287 | } un; |
4288 | union { |
4289 | struct { |
4290 | #ifdef __BIG_ENDIAN_BITFIELD |
4291 | uint16_t ulpContext; /* High order bits word 6 */ |
4292 | uint16_t ulpIoTag; /* Low order bits word 6 */ |
4293 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
4294 | uint16_t ulpIoTag; /* Low order bits word 6 */ |
4295 | uint16_t ulpContext; /* High order bits word 6 */ |
4296 | #endif |
4297 | } t1; |
4298 | struct { |
4299 | #ifdef __BIG_ENDIAN_BITFIELD |
4300 | uint16_t ulpContext; /* High order bits word 6 */ |
4301 | uint16_t ulpIoTag1:2; /* Low order bits word 6 */ |
4302 | uint16_t ulpIoTag0:14; /* Low order bits word 6 */ |
4303 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
4304 | uint16_t ulpIoTag0:14; /* Low order bits word 6 */ |
4305 | uint16_t ulpIoTag1:2; /* Low order bits word 6 */ |
4306 | uint16_t ulpContext; /* High order bits word 6 */ |
4307 | #endif |
4308 | } t2; |
4309 | } un1; |
4310 | #define ulpContext un1.t1.ulpContext |
4311 | #define ulpIoTag un1.t1.ulpIoTag |
4312 | #define ulpIoTag0 un1.t2.ulpIoTag0 |
4313 | |
4314 | #ifdef __BIG_ENDIAN_BITFIELD |
4315 | uint32_t ulpTimeout:8; |
4316 | uint32_t ulpXS:1; |
4317 | uint32_t ulpFCP2Rcvy:1; |
4318 | uint32_t ulpPU:2; |
4319 | uint32_t ulpIr:1; |
4320 | uint32_t ulpClass:3; |
4321 | uint32_t ulpCommand:8; |
4322 | uint32_t ulpStatus:4; |
4323 | uint32_t ulpBdeCount:2; |
4324 | uint32_t ulpLe:1; |
4325 | uint32_t ulpOwner:1; /* Low order bit word 7 */ |
4326 | #else /* __LITTLE_ENDIAN_BITFIELD */ |
4327 | uint32_t ulpOwner:1; /* Low order bit word 7 */ |
4328 | uint32_t ulpLe:1; |
4329 | uint32_t ulpBdeCount:2; |
4330 | uint32_t ulpStatus:4; |
4331 | uint32_t ulpCommand:8; |
4332 | uint32_t ulpClass:3; |
4333 | uint32_t ulpIr:1; |
4334 | uint32_t ulpPU:2; |
4335 | uint32_t ulpFCP2Rcvy:1; |
4336 | uint32_t ulpXS:1; |
4337 | uint32_t ulpTimeout:8; |
4338 | #endif |
4339 | |
4340 | union { |
4341 | struct rcv_sli3 rcvsli3; /* words 8 - 15 */ |
4342 | |
4343 | /* words 8-31 used for que_xri_cx iocb */ |
4344 | struct que_xri64cx_ext_fields que_xri64cx_ext_words; |
4345 | struct fcp_irw_ext fcp_ext; |
4346 | uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ |
4347 | |
4348 | /* words 8-15 for BlockGuard */ |
4349 | struct sli3_bg_fields sli3_bg; |
4350 | } unsli3; |
4351 | |
4352 | #define ulpCt_h ulpXS |
4353 | #define ulpCt_l ulpFCP2Rcvy |
4354 | |
4355 | #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ |
4356 | #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ |
4357 | #define PARM_UNUSED 0 /* PU field (Word 4) not used */ |
4358 | #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ |
4359 | #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ |
4360 | #define PARM_NPIV_DID 3 |
4361 | #define CLASS1 0 /* Class 1 */ |
4362 | #define CLASS2 1 /* Class 2 */ |
4363 | #define CLASS3 2 /* Class 3 */ |
4364 | #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ |
4365 | |
4366 | #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ |
4367 | #define IOSTAT_FCP_RSP_ERROR 0x1 |
4368 | #define IOSTAT_REMOTE_STOP 0x2 |
4369 | #define IOSTAT_LOCAL_REJECT 0x3 |
4370 | #define IOSTAT_NPORT_RJT 0x4 |
4371 | #define IOSTAT_FABRIC_RJT 0x5 |
4372 | #define IOSTAT_NPORT_BSY 0x6 |
4373 | #define IOSTAT_FABRIC_BSY 0x7 |
4374 | #define IOSTAT_INTERMED_RSP 0x8 |
4375 | #define IOSTAT_LS_RJT 0x9 |
4376 | #define IOSTAT_BA_RJT 0xA |
4377 | #define IOSTAT_RSVD1 0xB |
4378 | #define IOSTAT_RSVD2 0xC |
4379 | #define IOSTAT_RSVD3 0xD |
4380 | #define IOSTAT_RSVD4 0xE |
4381 | #define IOSTAT_NEED_BUFFER 0xF |
4382 | #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ |
4383 | #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ |
4384 | #define IOSTAT_CNT 0x11 |
4385 | |
4386 | } IOCB_t; |
4387 | |
4388 | |
4389 | #define SLI1_SLIM_SIZE (4 * 1024) |
4390 | |
4391 | /* Up to 498 IOCBs will fit into 16k |
4392 | * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 |
4393 | */ |
4394 | #define SLI2_SLIM_SIZE (64 * 1024) |
4395 | |
4396 | /* Maximum IOCBs that will fit in SLI2 slim */ |
4397 | #define MAX_SLI2_IOCB 498 |
4398 | #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ |
4399 | (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ |
4400 | sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) |
4401 | |
4402 | /* HBQ entries are 4 words each = 4k */ |
4403 | #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ |
4404 | lpfc_sli_hbq_count()) |
4405 | |
4406 | struct lpfc_sli2_slim { |
4407 | MAILBOX_t mbx; |
4408 | uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; |
4409 | PCB_t pcb; |
4410 | IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; |
4411 | }; |
4412 | |
4413 | /* |
4414 | * This function checks PCI device to allow special handling for LC HBAs. |
4415 | * |
4416 | * Parameters: |
4417 | * device : struct pci_dev 's device field |
4418 | * |
4419 | * return 1 => TRUE |
4420 | * 0 => FALSE |
4421 | */ |
4422 | static inline int |
4423 | lpfc_is_LC_HBA(unsigned short device) |
4424 | { |
4425 | if ((device == PCI_DEVICE_ID_TFLY) || |
4426 | (device == PCI_DEVICE_ID_PFLY) || |
4427 | (device == PCI_DEVICE_ID_LP101) || |
4428 | (device == PCI_DEVICE_ID_BMID) || |
4429 | (device == PCI_DEVICE_ID_BSMB) || |
4430 | (device == PCI_DEVICE_ID_ZMID) || |
4431 | (device == PCI_DEVICE_ID_ZSMB) || |
4432 | (device == PCI_DEVICE_ID_SAT_MID) || |
4433 | (device == PCI_DEVICE_ID_SAT_SMB) || |
4434 | (device == PCI_DEVICE_ID_RFLY)) |
4435 | return 1; |
4436 | else |
4437 | return 0; |
4438 | } |
4439 | |
4440 | #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ |
4441 | |