1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2015 Atmel |
4 | * |
5 | * Boris Brezillon <boris.brezillon@free-electrons.com |
6 | */ |
7 | |
8 | #ifndef __AT91_SOC_H |
9 | #define __AT91_SOC_H |
10 | |
11 | #include <linux/sys_soc.h> |
12 | |
13 | struct at91_soc { |
14 | u32 cidr_match; |
15 | u32 cidr_mask; |
16 | u32 version_mask; |
17 | u32 exid_match; |
18 | const char *name; |
19 | const char *family; |
20 | }; |
21 | |
22 | #define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid, \ |
23 | __name, __family) \ |
24 | { \ |
25 | .cidr_match = (__cidr), \ |
26 | .cidr_mask = (__cidr_mask), \ |
27 | .version_mask = (__version_mask), \ |
28 | .exid_match = (__exid), \ |
29 | .name = (__name), \ |
30 | .family = (__family), \ |
31 | } |
32 | |
33 | struct soc_device * __init |
34 | at91_soc_init(const struct at91_soc *socs); |
35 | |
36 | #define AT91RM9200_CIDR_MATCH 0x09290780 |
37 | |
38 | #define AT91SAM9260_CIDR_MATCH 0x019803a0 |
39 | #define AT91SAM9261_CIDR_MATCH 0x019703a0 |
40 | #define AT91SAM9263_CIDR_MATCH 0x019607a0 |
41 | #define AT91SAM9G20_CIDR_MATCH 0x019905a0 |
42 | #define AT91SAM9RL64_CIDR_MATCH 0x019b03a0 |
43 | #define AT91SAM9G45_CIDR_MATCH 0x019b05a0 |
44 | #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 |
45 | #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 |
46 | #define SAM9X60_CIDR_MATCH 0x019b35a0 |
47 | #define SAMA7G5_CIDR_MATCH 0x00162100 |
48 | |
49 | #define AT91SAM9M11_EXID_MATCH 0x00000001 |
50 | #define AT91SAM9M10_EXID_MATCH 0x00000002 |
51 | #define AT91SAM9G46_EXID_MATCH 0x00000003 |
52 | #define AT91SAM9G45_EXID_MATCH 0x00000004 |
53 | |
54 | #define AT91SAM9G15_EXID_MATCH 0x00000000 |
55 | #define AT91SAM9G35_EXID_MATCH 0x00000001 |
56 | #define AT91SAM9X35_EXID_MATCH 0x00000002 |
57 | #define AT91SAM9G25_EXID_MATCH 0x00000003 |
58 | #define AT91SAM9X25_EXID_MATCH 0x00000004 |
59 | |
60 | #define AT91SAM9CN12_EXID_MATCH 0x00000005 |
61 | #define AT91SAM9N12_EXID_MATCH 0x00000006 |
62 | #define AT91SAM9CN11_EXID_MATCH 0x00000009 |
63 | |
64 | #define SAM9X60_EXID_MATCH 0x00000000 |
65 | #define SAM9X60_D5M_EXID_MATCH 0x00000001 |
66 | #define SAM9X60_D1G_EXID_MATCH 0x00000010 |
67 | #define SAM9X60_D6K_EXID_MATCH 0x00000011 |
68 | |
69 | #define SAMA7G51_EXID_MATCH 0x3 |
70 | #define SAMA7G52_EXID_MATCH 0x2 |
71 | #define SAMA7G53_EXID_MATCH 0x1 |
72 | #define SAMA7G54_EXID_MATCH 0x0 |
73 | #define SAMA7G54_D1G_EXID_MATCH 0x00000018 |
74 | #define SAMA7G54_D2G_EXID_MATCH 0x00000020 |
75 | #define SAMA7G54_D4G_EXID_MATCH 0x00000028 |
76 | |
77 | #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 |
78 | #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 |
79 | #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 |
80 | |
81 | #define SAMA5D2_CIDR_MATCH 0x0a5c08c0 |
82 | #define SAMA5D21CU_EXID_MATCH 0x0000005a |
83 | #define SAMA5D225C_D1M_EXID_MATCH 0x00000053 |
84 | #define SAMA5D22CU_EXID_MATCH 0x00000059 |
85 | #define SAMA5D22CN_EXID_MATCH 0x00000069 |
86 | #define SAMA5D23CU_EXID_MATCH 0x00000058 |
87 | #define SAMA5D24CX_EXID_MATCH 0x00000004 |
88 | #define SAMA5D24CU_EXID_MATCH 0x00000014 |
89 | #define SAMA5D26CU_EXID_MATCH 0x00000012 |
90 | #define SAMA5D27C_D1G_EXID_MATCH 0x00000033 |
91 | #define SAMA5D27C_D5M_EXID_MATCH 0x00000032 |
92 | #define SAMA5D27C_LD1G_EXID_MATCH 0x00000061 |
93 | #define SAMA5D27C_LD2G_EXID_MATCH 0x00000062 |
94 | #define SAMA5D27CU_EXID_MATCH 0x00000011 |
95 | #define SAMA5D27CN_EXID_MATCH 0x00000021 |
96 | #define SAMA5D28C_D1G_EXID_MATCH 0x00000013 |
97 | #define SAMA5D28C_LD1G_EXID_MATCH 0x00000071 |
98 | #define SAMA5D28C_LD2G_EXID_MATCH 0x00000072 |
99 | #define SAMA5D28CU_EXID_MATCH 0x00000010 |
100 | #define SAMA5D28CN_EXID_MATCH 0x00000020 |
101 | #define SAMA5D29CN_EXID_MATCH 0x00000023 |
102 | |
103 | #define SAMA5D3_CIDR_MATCH 0x0a5c07c0 |
104 | #define SAMA5D31_EXID_MATCH 0x00444300 |
105 | #define SAMA5D33_EXID_MATCH 0x00414300 |
106 | #define SAMA5D34_EXID_MATCH 0x00414301 |
107 | #define SAMA5D35_EXID_MATCH 0x00584300 |
108 | #define SAMA5D36_EXID_MATCH 0x00004301 |
109 | |
110 | #define SAMA5D4_CIDR_MATCH 0x0a5c07c0 |
111 | #define SAMA5D41_EXID_MATCH 0x00000001 |
112 | #define SAMA5D42_EXID_MATCH 0x00000002 |
113 | #define SAMA5D43_EXID_MATCH 0x00000003 |
114 | #define SAMA5D44_EXID_MATCH 0x00000004 |
115 | |
116 | #define SAME70Q21_CIDR_MATCH 0x21020e00 |
117 | #define SAME70Q21_EXID_MATCH 0x00000002 |
118 | #define SAME70Q20_CIDR_MATCH 0x21020c00 |
119 | #define SAME70Q20_EXID_MATCH 0x00000002 |
120 | #define SAME70Q19_CIDR_MATCH 0x210d0a00 |
121 | #define SAME70Q19_EXID_MATCH 0x00000002 |
122 | |
123 | #define SAMS70Q21_CIDR_MATCH 0x21120e00 |
124 | #define SAMS70Q21_EXID_MATCH 0x00000002 |
125 | #define SAMS70Q20_CIDR_MATCH 0x21120c00 |
126 | #define SAMS70Q20_EXID_MATCH 0x00000002 |
127 | #define SAMS70Q19_CIDR_MATCH 0x211d0a00 |
128 | #define SAMS70Q19_EXID_MATCH 0x00000002 |
129 | |
130 | #define SAMV71Q21_CIDR_MATCH 0x21220e00 |
131 | #define SAMV71Q21_EXID_MATCH 0x00000002 |
132 | #define SAMV71Q20_CIDR_MATCH 0x21220c00 |
133 | #define SAMV71Q20_EXID_MATCH 0x00000002 |
134 | #define SAMV71Q19_CIDR_MATCH 0x212d0a00 |
135 | #define SAMV71Q19_EXID_MATCH 0x00000002 |
136 | |
137 | #define SAMV70Q20_CIDR_MATCH 0x21320c00 |
138 | #define SAMV70Q20_EXID_MATCH 0x00000002 |
139 | #define SAMV70Q19_CIDR_MATCH 0x213d0a00 |
140 | #define SAMV70Q19_EXID_MATCH 0x00000002 |
141 | |
142 | #endif /* __AT91_SOC_H */ |
143 | |