| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2016 Broadcom Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #include <asm/asm.h> |
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| 7 | #include <asm/regdef.h> |
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| 8 | #include <asm/mipsregs.h> |
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| 9 | #include <asm/stackframe.h> |
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| 10 | |
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| 11 | #include "pm.h" |
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| 12 | |
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| 13 | .text |
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| 14 | .set noreorder |
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| 15 | .align 5 |
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| 16 | |
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| 17 | /* |
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| 18 | * a0: u32 params array |
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| 19 | */ |
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| 20 | LEAF(brcm_pm_do_s2) |
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| 21 | |
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| 22 | subu sp, 64 |
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| 23 | sw ra, 0(sp) |
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| 24 | sw s0, 4(sp) |
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| 25 | sw s1, 8(sp) |
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| 26 | sw s2, 12(sp) |
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| 27 | sw s3, 16(sp) |
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| 28 | sw s4, 20(sp) |
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| 29 | sw s5, 24(sp) |
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| 30 | sw s6, 28(sp) |
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| 31 | sw s7, 32(sp) |
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| 32 | |
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| 33 | /* |
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| 34 | * Dereference the params array |
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| 35 | * s0: AON_CTRL base register |
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| 36 | * s1: DDR_PHY base register |
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| 37 | * s2: TIMERS base register |
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| 38 | * s3: I-Cache line size |
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| 39 | * s4: Restart vector address |
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| 40 | * s5: Restart vector size |
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| 41 | */ |
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| 42 | move t0, a0 |
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| 43 | |
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| 44 | lw s0, 0(t0) |
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| 45 | lw s1, 4(t0) |
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| 46 | lw s2, 8(t0) |
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| 47 | lw s3, 12(t0) |
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| 48 | lw s4, 16(t0) |
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| 49 | lw s5, 20(t0) |
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| 50 | |
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| 51 | /* Lock this asm section into the I-cache */ |
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| 52 | addiu t1, s3, -1 |
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| 53 | not t1 |
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| 54 | |
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| 55 | la t0, brcm_pm_do_s2 |
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| 56 | and t0, t1 |
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| 57 | |
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| 58 | la t2, asm_end |
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| 59 | and t2, t1 |
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| 60 | |
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| 61 | 1: cache 0x1c, 0(t0) |
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| 62 | bne t0, t2, 1b |
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| 63 | addu t0, s3 |
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| 64 | |
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| 65 | /* Lock the interrupt vector into the I-cache */ |
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| 66 | move t0, zero |
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| 67 | |
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| 68 | 2: move t1, s4 |
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| 69 | cache 0x1c, 0(t1) |
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| 70 | addu t1, s3 |
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| 71 | addu t0, s3 |
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| 72 | ble t0, s5, 2b |
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| 73 | nop |
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| 74 | |
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| 75 | sync |
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| 76 | |
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| 77 | /* Power down request */ |
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| 78 | li t0, PM_S2_COMMAND |
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| 79 | sw zero, AON_CTRL_PM_CTRL(s0) |
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| 80 | lw zero, AON_CTRL_PM_CTRL(s0) |
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| 81 | sw t0, AON_CTRL_PM_CTRL(s0) |
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| 82 | lw t0, AON_CTRL_PM_CTRL(s0) |
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| 83 | |
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| 84 | /* Enable CP0 interrupt 2 and wait for interrupt */ |
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| 85 | mfc0 t0, CP0_STATUS |
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| 86 | /* Save cp0 sr for restoring later */ |
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| 87 | move s6, t0 |
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| 88 | |
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| 89 | li t1, ~(ST0_IM | ST0_IE) |
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| 90 | and t0, t1 |
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| 91 | ori t0, STATUSF_IP2 |
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| 92 | mtc0 t0, CP0_STATUS |
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| 93 | nop |
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| 94 | nop |
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| 95 | nop |
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| 96 | ori t0, ST0_IE |
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| 97 | mtc0 t0, CP0_STATUS |
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| 98 | |
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| 99 | /* Wait for interrupt */ |
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| 100 | wait |
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| 101 | nop |
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| 102 | |
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| 103 | /* Wait for memc0 */ |
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| 104 | 1: lw t0, DDR40_PHY_CONTROL_REGS_0_PLL_STATUS(s1) |
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| 105 | andi t0, 1 |
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| 106 | beqz t0, 1b |
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| 107 | nop |
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| 108 | |
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| 109 | /* 1ms delay needed for stable recovery */ |
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| 110 | /* Use TIMER1 to count 1 ms */ |
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| 111 | li t0, RESET_TIMER |
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| 112 | sw t0, TIMER_TIMER1_CTRL(s2) |
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| 113 | lw t0, TIMER_TIMER1_CTRL(s2) |
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| 114 | |
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| 115 | li t0, START_TIMER |
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| 116 | sw t0, TIMER_TIMER1_CTRL(s2) |
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| 117 | lw t0, TIMER_TIMER1_CTRL(s2) |
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| 118 | |
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| 119 | /* Prepare delay */ |
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| 120 | li t0, TIMER_MASK |
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| 121 | lw t1, TIMER_TIMER1_STAT(s2) |
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| 122 | and t1, t0 |
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| 123 | /* 1ms delay */ |
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| 124 | addi t1, 27000 |
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| 125 | |
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| 126 | /* Wait for the timer value to exceed t1 */ |
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| 127 | 1: lw t0, TIMER_TIMER1_STAT(s2) |
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| 128 | sgtu t2, t1, t0 |
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| 129 | bnez t2, 1b |
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| 130 | nop |
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| 131 | |
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| 132 | /* Power back up */ |
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| 133 | li t1, 1 |
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| 134 | sw t1, AON_CTRL_HOST_MISC_CMDS(s0) |
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| 135 | lw t1, AON_CTRL_HOST_MISC_CMDS(s0) |
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| 136 | |
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| 137 | sw zero, AON_CTRL_PM_CTRL(s0) |
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| 138 | lw zero, AON_CTRL_PM_CTRL(s0) |
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| 139 | |
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| 140 | /* Unlock I-cache */ |
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| 141 | addiu t1, s3, -1 |
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| 142 | not t1 |
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| 143 | |
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| 144 | la t0, brcm_pm_do_s2 |
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| 145 | and t0, t1 |
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| 146 | |
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| 147 | la t2, asm_end |
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| 148 | and t2, t1 |
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| 149 | |
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| 150 | 1: cache 0x00, 0(t0) |
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| 151 | bne t0, t2, 1b |
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| 152 | addu t0, s3 |
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| 153 | |
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| 154 | /* Unlock interrupt vector */ |
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| 155 | move t0, zero |
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| 156 | |
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| 157 | 2: move t1, s4 |
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| 158 | cache 0x00, 0(t1) |
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| 159 | addu t1, s3 |
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| 160 | addu t0, s3 |
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| 161 | ble t0, s5, 2b |
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| 162 | nop |
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| 163 | |
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| 164 | /* Restore cp0 sr */ |
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| 165 | sync |
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| 166 | nop |
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| 167 | mtc0 s6, CP0_STATUS |
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| 168 | nop |
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| 169 | |
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| 170 | /* Set return value to success */ |
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| 171 | li v0, 0 |
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| 172 | |
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| 173 | /* Return to caller */ |
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| 174 | lw s7, 32(sp) |
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| 175 | lw s6, 28(sp) |
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| 176 | lw s5, 24(sp) |
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| 177 | lw s4, 20(sp) |
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| 178 | lw s3, 16(sp) |
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| 179 | lw s2, 12(sp) |
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| 180 | lw s1, 8(sp) |
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| 181 | lw s0, 4(sp) |
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| 182 | lw ra, 0(sp) |
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| 183 | addiu sp, 64 |
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| 184 | |
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| 185 | jr ra |
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| 186 | nop |
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| 187 | END(brcm_pm_do_s2) |
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| 188 | |
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| 189 | .globl asm_end |
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| 190 | asm_end: |
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| 191 | nop |
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| 192 | |
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| 193 | |
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