1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * FB driver for the ILI9163 LCD Controller |
4 | * |
5 | * Copyright (C) 2015 Kozhevnikov Anatoly |
6 | * |
7 | * Based on ili9325.c by Noralf Tronnes and |
8 | * .S.U.M.O.T.O.Y. by Max MC Costa (https://github.com/sumotoy/TFT_ILI9163C). |
9 | */ |
10 | |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> |
13 | #include <linux/init.h> |
14 | #include <linux/delay.h> |
15 | #include <video/mipi_display.h> |
16 | |
17 | #include "fbtft.h" |
18 | |
19 | #define DRVNAME "fb_ili9163" |
20 | #define WIDTH 128 |
21 | #define HEIGHT 128 |
22 | #define BPP 16 |
23 | #define FPS 30 |
24 | |
25 | #ifdef GAMMA_ADJ |
26 | #define GAMMA_LEN 15 |
27 | #define GAMMA_NUM 1 |
28 | #define DEFAULT_GAMMA "36 29 12 22 1C 15 42 B7 2F 13 12 0A 11 0B 06\n" |
29 | #endif |
30 | |
31 | /* ILI9163C commands */ |
32 | #define CMD_FRMCTR1 0xB1 /* Frame Rate Control */ |
33 | /* (In normal mode/Full colors) */ |
34 | #define CMD_FRMCTR2 0xB2 /* Frame Rate Control (In Idle mode/8-colors) */ |
35 | #define CMD_FRMCTR3 0xB3 /* Frame Rate Control */ |
36 | /* (In Partial mode/full colors) */ |
37 | #define CMD_DINVCTR 0xB4 /* Display Inversion Control */ |
38 | #define CMD_RGBBLK 0xB5 /* RGB Interface Blanking Porch setting */ |
39 | #define CMD_DFUNCTR 0xB6 /* Display Function set 5 */ |
40 | #define CMD_SDRVDIR 0xB7 /* Source Driver Direction Control */ |
41 | #define CMD_GDRVDIR 0xB8 /* Gate Driver Direction Control */ |
42 | |
43 | #define CMD_PWCTR1 0xC0 /* Power_Control1 */ |
44 | #define CMD_PWCTR2 0xC1 /* Power_Control2 */ |
45 | #define CMD_PWCTR3 0xC2 /* Power_Control3 */ |
46 | #define CMD_PWCTR4 0xC3 /* Power_Control4 */ |
47 | #define CMD_PWCTR5 0xC4 /* Power_Control5 */ |
48 | #define CMD_VCOMCTR1 0xC5 /* VCOM_Control 1 */ |
49 | #define CMD_VCOMCTR2 0xC6 /* VCOM_Control 2 */ |
50 | #define CMD_VCOMOFFS 0xC7 /* VCOM Offset Control */ |
51 | #define CMD_PGAMMAC 0xE0 /* Positive Gamma Correction Setting */ |
52 | #define CMD_NGAMMAC 0xE1 /* Negative Gamma Correction Setting */ |
53 | #define CMD_GAMRSEL 0xF2 /* GAM_R_SEL */ |
54 | |
55 | /* |
56 | * This display: |
57 | * http://www.ebay.com/itm/Replace-Nokia-5110-LCD-1-44-Red-Serial-128X128-SPI- |
58 | * Color-TFT-LCD-Display-Module-/271422122271 |
59 | * This particular display has a design error! The controller has 3 pins to |
60 | * configure to constrain the memory and resolution to a fixed dimension (in |
61 | * that case 128x128) but they leaved those pins configured for 128x160 so |
62 | * there was several pixel memory addressing problems. |
63 | * I solved by setup several parameters that dinamically fix the resolution as |
64 | * needit so below the parameters for this display. If you have a strain or a |
65 | * correct display (can happen with chinese) you can copy those parameters and |
66 | * create setup for different displays. |
67 | */ |
68 | |
69 | #ifdef RED |
70 | #define __OFFSET 32 /*see note 2 - this is the red version */ |
71 | #else |
72 | #define __OFFSET 0 /*see note 2 - this is the black version */ |
73 | #endif |
74 | |
75 | static int init_display(struct fbtft_par *par) |
76 | { |
77 | par->fbtftops.reset(par); |
78 | |
79 | write_reg(par, MIPI_DCS_SOFT_RESET); /* software reset */ |
80 | mdelay(500); |
81 | write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); /* exit sleep */ |
82 | mdelay(5); |
83 | write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); |
84 | /* default gamma curve 3 */ |
85 | write_reg(par, MIPI_DCS_SET_GAMMA_CURVE, 0x02); |
86 | #ifdef GAMMA_ADJ |
87 | write_reg(par, CMD_GAMRSEL, 0x01); /* Enable Gamma adj */ |
88 | #endif |
89 | write_reg(par, MIPI_DCS_ENTER_NORMAL_MODE); |
90 | write_reg(par, CMD_DFUNCTR, 0xff, 0x06); |
91 | /* Frame Rate Control (In normal mode/Full colors) */ |
92 | write_reg(par, CMD_FRMCTR1, 0x08, 0x02); |
93 | write_reg(par, CMD_DINVCTR, 0x07); /* display inversion */ |
94 | /* Set VRH1[4:0] & VC[2:0] for VCI1 & GVDD */ |
95 | write_reg(par, CMD_PWCTR1, 0x0A, 0x02); |
96 | /* Set BT[2:0] for AVDD & VCL & VGH & VGL */ |
97 | write_reg(par, CMD_PWCTR2, 0x02); |
98 | /* Set VMH[6:0] & VML[6:0] for VOMH & VCOML */ |
99 | write_reg(par, CMD_VCOMCTR1, 0x50, 0x63); |
100 | write_reg(par, CMD_VCOMOFFS, 0); |
101 | |
102 | write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0, 0, WIDTH); |
103 | write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0, 0, HEIGHT); |
104 | |
105 | write_reg(par, MIPI_DCS_SET_DISPLAY_ON); /* display ON */ |
106 | write_reg(par, MIPI_DCS_WRITE_MEMORY_START); /* Memory Write */ |
107 | |
108 | return 0; |
109 | } |
110 | |
111 | static void set_addr_win(struct fbtft_par *par, int xs, int ys, |
112 | int xe, int ye) |
113 | { |
114 | switch (par->info->var.rotate) { |
115 | case 0: |
116 | write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, |
117 | xs >> 8, xs & 0xff, xe >> 8, xe & 0xff); |
118 | write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, |
119 | (ys + __OFFSET) >> 8, (ys + __OFFSET) & 0xff, |
120 | (ye + __OFFSET) >> 8, (ye + __OFFSET) & 0xff); |
121 | break; |
122 | case 90: |
123 | write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, |
124 | (xs + __OFFSET) >> 8, (xs + __OFFSET) & 0xff, |
125 | (xe + __OFFSET) >> 8, (xe + __OFFSET) & 0xff); |
126 | write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, |
127 | ys >> 8, ys & 0xff, ye >> 8, ye & 0xff); |
128 | break; |
129 | case 180: |
130 | case 270: |
131 | write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, |
132 | xs >> 8, xs & 0xff, xe >> 8, xe & 0xff); |
133 | write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, |
134 | ys >> 8, ys & 0xff, ye >> 8, ye & 0xff); |
135 | break; |
136 | default: |
137 | /* Fix incorrect setting */ |
138 | par->info->var.rotate = 0; |
139 | } |
140 | write_reg(par, MIPI_DCS_WRITE_MEMORY_START); |
141 | } |
142 | |
143 | /* |
144 | * 7) MY: 1(bottom to top), 0(top to bottom) Row Address Order |
145 | * 6) MX: 1(R to L), 0(L to R) Column Address Order |
146 | * 5) MV: 1(Exchanged), 0(normal) Row/Column exchange |
147 | * 4) ML: 1(bottom to top), 0(top to bottom) Vertical Refresh Order |
148 | * 3) RGB: 1(BGR), 0(RGB) Color Space |
149 | * 2) MH: 1(R to L), 0(L to R) Horizontal Refresh Order |
150 | * 1) |
151 | * 0) |
152 | * |
153 | * MY, MX, MV, ML,RGB, MH, D1, D0 |
154 | * 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 //normal |
155 | * 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 //Y-Mirror |
156 | * 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 //X-Mirror |
157 | * 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 //X-Y-Mirror |
158 | * 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 //X-Y Exchange |
159 | * 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 //X-Y Exchange, Y-Mirror |
160 | * 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 //XY exchange |
161 | * 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
162 | */ |
163 | static int set_var(struct fbtft_par *par) |
164 | { |
165 | u8 mactrl_data = 0; /* Avoid compiler warning */ |
166 | |
167 | switch (par->info->var.rotate) { |
168 | case 0: |
169 | mactrl_data = 0x08; |
170 | break; |
171 | case 180: |
172 | mactrl_data = 0xC8; |
173 | break; |
174 | case 270: |
175 | mactrl_data = 0xA8; |
176 | break; |
177 | case 90: |
178 | mactrl_data = 0x68; |
179 | break; |
180 | } |
181 | |
182 | /* Colorspcae */ |
183 | if (par->bgr) |
184 | mactrl_data |= BIT(2); |
185 | write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, mactrl_data); |
186 | write_reg(par, MIPI_DCS_WRITE_MEMORY_START); |
187 | return 0; |
188 | } |
189 | |
190 | #ifdef GAMMA_ADJ |
191 | #define CURVE(num, idx) curves[(num) * par->gamma.num_values + (idx)] |
192 | static int gamma_adj(struct fbtft_par *par, u32 *curves) |
193 | { |
194 | static const unsigned long mask[] = { |
195 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, |
196 | 0x1f, 0x3f, 0x0f, 0x0f, 0x7f, 0x1f, |
197 | 0x3F, 0x3F, 0x3F, 0x3F, 0x3F}; |
198 | int i, j; |
199 | |
200 | for (i = 0; i < GAMMA_NUM; i++) |
201 | for (j = 0; j < GAMMA_LEN; j++) |
202 | CURVE(i, j) &= mask[i * par->gamma.num_values + j]; |
203 | |
204 | write_reg(par, CMD_PGAMMAC, |
205 | CURVE(0, 0), |
206 | CURVE(0, 1), |
207 | CURVE(0, 2), |
208 | CURVE(0, 3), |
209 | CURVE(0, 4), |
210 | CURVE(0, 5), |
211 | CURVE(0, 6), |
212 | (CURVE(0, 7) << 4) | CURVE(0, 8), |
213 | CURVE(0, 9), |
214 | CURVE(0, 10), |
215 | CURVE(0, 11), |
216 | CURVE(0, 12), |
217 | CURVE(0, 13), |
218 | CURVE(0, 14), |
219 | CURVE(0, 15)); |
220 | |
221 | /* Write Data to GRAM mode */ |
222 | write_reg(par, MIPI_DCS_WRITE_MEMORY_START); |
223 | |
224 | return 0; |
225 | } |
226 | |
227 | #undef CURVE |
228 | #endif |
229 | |
230 | static struct fbtft_display display = { |
231 | .regwidth = 8, |
232 | .width = WIDTH, |
233 | .height = HEIGHT, |
234 | .bpp = BPP, |
235 | .fps = FPS, |
236 | #ifdef GAMMA_ADJ |
237 | .gamma_num = GAMMA_NUM, |
238 | .gamma_len = GAMMA_LEN, |
239 | .gamma = DEFAULT_GAMMA, |
240 | #endif |
241 | .fbtftops = { |
242 | .init_display = init_display, |
243 | .set_addr_win = set_addr_win, |
244 | .set_var = set_var, |
245 | #ifdef GAMMA_ADJ |
246 | .set_gamma = gamma_adj, |
247 | #endif |
248 | }, |
249 | }; |
250 | |
251 | FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9163" , &display); |
252 | |
253 | MODULE_ALIAS("spi:" DRVNAME); |
254 | MODULE_ALIAS("platform:" DRVNAME); |
255 | MODULE_ALIAS("spi:ili9163" ); |
256 | MODULE_ALIAS("platform:ili9163" ); |
257 | |
258 | MODULE_DESCRIPTION("FB driver for the ILI9163 LCD Controller" ); |
259 | MODULE_AUTHOR("Kozhevnikov Anatoly" ); |
260 | MODULE_LICENSE("GPL" ); |
261 | |