1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * FB driver for the NHD-1.69-160128UGC3 (Newhaven Display International, Inc.) |
4 | * using the SEPS525 (Syncoam) LCD Controller |
5 | * |
6 | * Copyright (C) 2016 Analog Devices Inc. |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by |
10 | * the Free Software Foundation; either version 2 of the License, or |
11 | * (at your option) any later version. |
12 | * |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 | * GNU General Public License for more details. |
17 | */ |
18 | |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> |
21 | #include <linux/init.h> |
22 | #include <linux/gpio.h> |
23 | #include <linux/delay.h> |
24 | |
25 | #include "fbtft.h" |
26 | |
27 | #define DRVNAME "fb_seps525" |
28 | #define WIDTH 160 |
29 | #define HEIGHT 128 |
30 | |
31 | #define SEPS525_INDEX 0x00 |
32 | #define SEPS525_STATUS_RD 0x01 |
33 | #define SEPS525_OSC_CTL 0x02 |
34 | #define SEPS525_IREF 0x80 |
35 | #define SEPS525_CLOCK_DIV 0x03 |
36 | #define SEPS525_REDUCE_CURRENT 0x04 |
37 | #define SEPS525_SOFT_RST 0x05 |
38 | #define SEPS525_DISP_ONOFF 0x06 |
39 | #define SEPS525_PRECHARGE_TIME_R 0x08 |
40 | #define SEPS525_PRECHARGE_TIME_G 0x09 |
41 | #define SEPS525_PRECHARGE_TIME_B 0x0A |
42 | #define SEPS525_PRECHARGE_CURRENT_R 0x0B |
43 | #define SEPS525_PRECHARGE_CURRENT_G 0x0C |
44 | #define SEPS525_PRECHARGE_CURRENT_B 0x0D |
45 | #define SEPS525_DRIVING_CURRENT_R 0x10 |
46 | #define SEPS525_DRIVING_CURRENT_G 0x11 |
47 | #define SEPS525_DRIVING_CURRENT_B 0x12 |
48 | #define SEPS525_DISPLAYMODE_SET 0x13 |
49 | #define SEPS525_RGBIF 0x14 |
50 | #define SEPS525_RGB_POL 0x15 |
51 | #define SEPS525_MEMORY_WRITEMODE 0x16 |
52 | #define SEPS525_MX1_ADDR 0x17 |
53 | #define SEPS525_MX2_ADDR 0x18 |
54 | #define SEPS525_MY1_ADDR 0x19 |
55 | #define SEPS525_MY2_ADDR 0x1A |
56 | #define SEPS525_MEMORY_ACCESS_POINTER_X 0x20 |
57 | #define SEPS525_MEMORY_ACCESS_POINTER_Y 0x21 |
58 | #define SEPS525_DDRAM_DATA_ACCESS_PORT 0x22 |
59 | #define SEPS525_GRAY_SCALE_TABLE_INDEX 0x50 |
60 | #define SEPS525_GRAY_SCALE_TABLE_DATA 0x51 |
61 | #define SEPS525_DUTY 0x28 |
62 | #define SEPS525_DSL 0x29 |
63 | #define SEPS525_D1_DDRAM_FAC 0x2E |
64 | #define SEPS525_D1_DDRAM_FAR 0x2F |
65 | #define SEPS525_D2_DDRAM_SAC 0x31 |
66 | #define SEPS525_D2_DDRAM_SAR 0x32 |
67 | #define SEPS525_SCR1_FX1 0x33 |
68 | #define SEPS525_SCR1_FX2 0x34 |
69 | #define SEPS525_SCR1_FY1 0x35 |
70 | #define SEPS525_SCR1_FY2 0x36 |
71 | #define SEPS525_SCR2_SX1 0x37 |
72 | #define SEPS525_SCR2_SX2 0x38 |
73 | #define SEPS525_SCR2_SY1 0x39 |
74 | #define SEPS525_SCR2_SY2 0x3A |
75 | #define SEPS525_SCREEN_SAVER_CONTEROL 0x3B |
76 | #define SEPS525_SS_SLEEP_TIMER 0x3C |
77 | #define SEPS525_SCREEN_SAVER_MODE 0x3D |
78 | #define SEPS525_SS_SCR1_FU 0x3E |
79 | #define SEPS525_SS_SCR1_MXY 0x3F |
80 | #define SEPS525_SS_SCR2_FU 0x40 |
81 | #define SEPS525_SS_SCR2_MXY 0x41 |
82 | #define SEPS525_MOVING_DIRECTION 0x42 |
83 | #define SEPS525_SS_SCR2_SX1 0x47 |
84 | #define SEPS525_SS_SCR2_SX2 0x48 |
85 | #define SEPS525_SS_SCR2_SY1 0x49 |
86 | #define SEPS525_SS_SCR2_SY2 0x4A |
87 | |
88 | /* SEPS525_DISPLAYMODE_SET */ |
89 | #define MODE_SWAP_BGR BIT(7) |
90 | #define MODE_SM BIT(6) |
91 | #define MODE_RD BIT(5) |
92 | #define MODE_CD BIT(4) |
93 | |
94 | #define seps525_use_window 0 /* FBTFT doesn't really use it today */ |
95 | |
96 | /* Init sequence taken from: Arduino Library for the Adafruit 2.2" display */ |
97 | static int init_display(struct fbtft_par *par) |
98 | { |
99 | par->fbtftops.reset(par); |
100 | |
101 | usleep_range(min: 1000, max: 5000); |
102 | |
103 | /* Disable Oscillator Power Down */ |
104 | write_reg(par, SEPS525_REDUCE_CURRENT, 0x03); |
105 | usleep_range(min: 1000, max: 5000); |
106 | /* Set Normal Driving Current */ |
107 | write_reg(par, SEPS525_REDUCE_CURRENT, 0x00); |
108 | usleep_range(min: 1000, max: 5000); |
109 | |
110 | write_reg(par, SEPS525_SCREEN_SAVER_CONTEROL, 0x00); |
111 | /* Set EXPORT1 Pin at Internal Clock */ |
112 | write_reg(par, SEPS525_OSC_CTL, 0x01); |
113 | /* Set Clock as 120 Frames/Sec */ |
114 | write_reg(par, SEPS525_CLOCK_DIV, 0x90); |
115 | /* Set Reference Voltage Controlled by External Resister */ |
116 | write_reg(par, SEPS525_IREF, 0x01); |
117 | |
118 | /* precharge time R G B */ |
119 | write_reg(par, SEPS525_PRECHARGE_TIME_R, 0x04); |
120 | write_reg(par, SEPS525_PRECHARGE_TIME_G, 0x05); |
121 | write_reg(par, SEPS525_PRECHARGE_TIME_B, 0x05); |
122 | |
123 | /* precharge current R G B (uA) */ |
124 | write_reg(par, SEPS525_PRECHARGE_CURRENT_R, 0x9D); |
125 | write_reg(par, SEPS525_PRECHARGE_CURRENT_G, 0x8C); |
126 | write_reg(par, SEPS525_PRECHARGE_CURRENT_B, 0x57); |
127 | |
128 | /* driving current R G B (uA) */ |
129 | write_reg(par, SEPS525_DRIVING_CURRENT_R, 0x56); |
130 | write_reg(par, SEPS525_DRIVING_CURRENT_G, 0x4D); |
131 | write_reg(par, SEPS525_DRIVING_CURRENT_B, 0x46); |
132 | /* Set Color Sequence */ |
133 | write_reg(par, SEPS525_DISPLAYMODE_SET, 0xA0); |
134 | write_reg(par, SEPS525_RGBIF, 0x01); /* Set MCU Interface Mode */ |
135 | /* Set Memory Write Mode */ |
136 | write_reg(par, SEPS525_MEMORY_WRITEMODE, 0x66); |
137 | write_reg(par, SEPS525_DUTY, 0x7F); /* 1/128 Duty (0x0F~0x7F) */ |
138 | /* Set Mapping RAM Display Start Line (0x00~0x7F) */ |
139 | write_reg(par, SEPS525_DSL, 0x00); |
140 | write_reg(par, SEPS525_DISP_ONOFF, 0x01); /* Display On (0x00/0x01) */ |
141 | /* Set All Internal Register Value as Normal Mode */ |
142 | write_reg(par, SEPS525_SOFT_RST, 0x00); |
143 | /* Set RGB Interface Polarity as Active Low */ |
144 | write_reg(par, SEPS525_RGB_POL, 0x00); |
145 | |
146 | write_reg(par, SEPS525_DDRAM_DATA_ACCESS_PORT); |
147 | |
148 | return 0; |
149 | } |
150 | |
151 | static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) |
152 | { |
153 | if (seps525_use_window) { |
154 | /* Set Window Xs,Ys Xe,Ye*/ |
155 | write_reg(par, SEPS525_MX1_ADDR, xs); |
156 | write_reg(par, SEPS525_MX2_ADDR, xe); |
157 | write_reg(par, SEPS525_MY1_ADDR, ys); |
158 | write_reg(par, SEPS525_MY2_ADDR, ye); |
159 | } |
160 | /* start position X,Y */ |
161 | write_reg(par, SEPS525_MEMORY_ACCESS_POINTER_X, xs); |
162 | write_reg(par, SEPS525_MEMORY_ACCESS_POINTER_Y, ys); |
163 | |
164 | write_reg(par, SEPS525_DDRAM_DATA_ACCESS_PORT); |
165 | } |
166 | |
167 | static int set_var(struct fbtft_par *par) |
168 | { |
169 | u8 val; |
170 | |
171 | switch (par->info->var.rotate) { |
172 | case 0: |
173 | val = 0; |
174 | break; |
175 | case 180: |
176 | val = MODE_RD | MODE_CD; |
177 | break; |
178 | case 90: |
179 | case 270: |
180 | |
181 | default: |
182 | return -EINVAL; |
183 | } |
184 | /* Memory Access Control */ |
185 | write_reg(par, SEPS525_DISPLAYMODE_SET, val | |
186 | (par->bgr ? MODE_SWAP_BGR : 0)); |
187 | |
188 | write_reg(par, SEPS525_DDRAM_DATA_ACCESS_PORT); |
189 | |
190 | return 0; |
191 | } |
192 | |
193 | static struct fbtft_display display = { |
194 | .regwidth = 8, |
195 | .width = WIDTH, |
196 | .height = HEIGHT, |
197 | .fbtftops = { |
198 | .init_display = init_display, |
199 | .set_addr_win = set_addr_win, |
200 | .set_var = set_var, |
201 | }, |
202 | }; |
203 | |
204 | FBTFT_REGISTER_DRIVER(DRVNAME, "syncoam,seps525" , &display); |
205 | |
206 | MODULE_ALIAS("spi:" DRVNAME); |
207 | MODULE_ALIAS("platform:" DRVNAME); |
208 | MODULE_ALIAS("spi:seps525" ); |
209 | MODULE_ALIAS("platform:seps525" ); |
210 | |
211 | MODULE_DESCRIPTION("FB driver for the SEPS525 LCD Controller" ); |
212 | MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>" ); |
213 | MODULE_LICENSE("GPL" ); |
214 | |