1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (C) 2018 Intel Corporation */ |
3 | |
4 | #ifndef __IPU3_ABI_H |
5 | #define __IPU3_ABI_H |
6 | |
7 | #include "include/uapi/intel-ipu3.h" |
8 | |
9 | /******************* IMGU Hardware information *******************/ |
10 | |
11 | typedef u32 imgu_addr_t; |
12 | |
13 | #define IMGU_ISP_VMEM_ALIGN 128 |
14 | #define IMGU_DVS_BLOCK_W 64 |
15 | #define IMGU_DVS_BLOCK_H 32 |
16 | #define IMGU_GDC_BUF_X (2 * IMGU_DVS_BLOCK_W) |
17 | #define IMGU_GDC_BUF_Y IMGU_DVS_BLOCK_H |
18 | /* n = 0..1 */ |
19 | #define IMGU_SP_PMEM_BASE(n) (0x20000 + (n) * 0x4000) |
20 | #define IMGU_MAX_BQ_GRID_WIDTH 80 |
21 | #define IMGU_MAX_BQ_GRID_HEIGHT 60 |
22 | #define IMGU_OBGRID_TILE_SIZE 16 |
23 | #define IMGU_PIXELS_PER_WORD 50 |
24 | #define IMGU_BYTES_PER_WORD 64 |
25 | #define IMGU_STRIPE_FIXED_HALF_OVERLAP 2 |
26 | #define IMGU_SHD_SETS 3 |
27 | #define IMGU_BDS_MIN_CLIP_VAL 0 |
28 | #define IMGU_BDS_MAX_CLIP_VAL 2 |
29 | |
30 | #define IMGU_ABI_AWB_MAX_CELLS_PER_SET 160 |
31 | #define IMGU_ABI_AF_MAX_CELLS_PER_SET 32 |
32 | #define IMGU_ABI_AWB_FR_MAX_CELLS_PER_SET 32 |
33 | |
34 | #define IMGU_ABI_ACC_OP_IDLE 0 |
35 | #define IMGU_ABI_ACC_OP_END_OF_ACK 1 |
36 | #define IMGU_ABI_ACC_OP_END_OF_OPS 2 |
37 | #define IMGU_ABI_ACC_OP_NO_OPS 3 |
38 | |
39 | #define IMGU_ABI_ACC_OPTYPE_PROCESS_LINES 0 |
40 | #define IMGU_ABI_ACC_OPTYPE_TRANSFER_DATA 1 |
41 | |
42 | /* Register definitions */ |
43 | |
44 | /* PM_CTRL_0_5_0_IMGHMMADR */ |
45 | #define IMGU_REG_PM_CTRL 0x0 |
46 | #define IMGU_PM_CTRL_START BIT(0) |
47 | #define IMGU_PM_CTRL_CFG_DONE BIT(1) |
48 | #define IMGU_PM_CTRL_RACE_TO_HALT BIT(2) |
49 | #define IMGU_PM_CTRL_NACK_ALL BIT(3) |
50 | #define IMGU_PM_CTRL_CSS_PWRDN BIT(4) |
51 | #define IMGU_PM_CTRL_RST_AT_EOF BIT(5) |
52 | #define IMGU_PM_CTRL_FORCE_HALT BIT(6) |
53 | #define IMGU_PM_CTRL_FORCE_UNHALT BIT(7) |
54 | #define IMGU_PM_CTRL_FORCE_PWRDN BIT(8) |
55 | #define IMGU_PM_CTRL_FORCE_RESET BIT(9) |
56 | |
57 | /* SYSTEM_REQ_0_5_0_IMGHMMADR */ |
58 | #define IMGU_REG_SYSTEM_REQ 0x18 |
59 | #define IMGU_SYSTEM_REQ_FREQ_MASK 0x3f |
60 | #define IMGU_SYSTEM_REQ_FREQ_DIVIDER 25 |
61 | #define IMGU_REG_INT_STATUS 0x30 |
62 | #define IMGU_REG_INT_ENABLE 0x34 |
63 | #define IMGU_REG_INT_CSS_IRQ BIT(31) |
64 | /* STATE_0_5_0_IMGHMMADR */ |
65 | #define IMGU_REG_STATE 0x130 |
66 | #define IMGU_STATE_HALT_STS BIT(0) |
67 | #define IMGU_STATE_IDLE_STS BIT(1) |
68 | #define IMGU_STATE_POWER_UP BIT(2) |
69 | #define IMGU_STATE_POWER_DOWN BIT(3) |
70 | #define IMGU_STATE_CSS_BUSY_MASK 0xc0 |
71 | #define IMGU_STATE_PM_FSM_MASK 0x180 |
72 | #define IMGU_STATE_PWRDNM_FSM_MASK 0x1E00000 |
73 | /* PM_STS_0_5_0_IMGHMMADR */ |
74 | #define IMGU_REG_PM_STS 0x140 |
75 | |
76 | #define IMGU_REG_BASE 0x4000 |
77 | |
78 | #define IMGU_REG_ISP_CTRL (IMGU_REG_BASE + 0x00) |
79 | #define IMGU_CTRL_RST BIT(0) |
80 | #define IMGU_CTRL_START BIT(1) |
81 | #define IMGU_CTRL_BREAK BIT(2) |
82 | #define IMGU_CTRL_RUN BIT(3) |
83 | #define IMGU_CTRL_BROKEN BIT(4) |
84 | #define IMGU_CTRL_IDLE BIT(5) |
85 | #define IMGU_CTRL_SLEEPING BIT(6) |
86 | #define IMGU_CTRL_STALLING BIT(7) |
87 | #define IMGU_CTRL_IRQ_CLEAR BIT(8) |
88 | #define IMGU_CTRL_IRQ_READY BIT(10) |
89 | #define IMGU_CTRL_IRQ_SLEEPING BIT(11) |
90 | #define IMGU_CTRL_ICACHE_INV BIT(12) |
91 | #define IMGU_CTRL_IPREFETCH_EN BIT(13) |
92 | #define IMGU_REG_ISP_START_ADDR (IMGU_REG_BASE + 0x04) |
93 | #define IMGU_REG_ISP_ICACHE_ADDR (IMGU_REG_BASE + 0x10) |
94 | #define IMGU_REG_ISP_PC (IMGU_REG_BASE + 0x1c) |
95 | |
96 | /* SP Registers, sp = 0:SP0; 1:SP1 */ |
97 | #define IMGU_REG_SP_CTRL(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x100) |
98 | /* For bits in IMGU_REG_SP_CTRL, see IMGU_CTRL_* */ |
99 | #define IMGU_REG_SP_START_ADDR(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x104) |
100 | #define IMGU_REG_SP_ICACHE_ADDR(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x11c) |
101 | #define IMGU_REG_SP_CTRL_SINK(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x130) |
102 | #define IMGU_REG_SP_PC(sp) (IMGU_REG_BASE + (sp) * 0x100 + 0x134) |
103 | |
104 | #define IMGU_REG_TLB_INVALIDATE (IMGU_REG_BASE + 0x300) |
105 | #define IMGU_TLB_INVALIDATE 1 |
106 | #define IMGU_REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */ |
107 | |
108 | #define IMGU_REG_CIO_GATE_BURST_STATE (IMGU_REG_BASE + 0x404) |
109 | #define IMGU_CIO_GATE_BURST_MASK 0x80 |
110 | |
111 | #define IMGU_REG_GP_BUSY (IMGU_REG_BASE + 0x500) |
112 | #define IMGU_REG_GP_STARVING (IMGU_REG_BASE + 0x504) |
113 | #define IMGU_REG_GP_WORKLOAD (IMGU_REG_BASE + 0x508) |
114 | #define IMGU_REG_GP_IRQ(n) (IMGU_REG_BASE + (n) * 4 + 0x50c) /* n = 0..4 */ |
115 | #define IMGU_REG_GP_SP1_STRMON_STAT (IMGU_REG_BASE + 0x520) |
116 | #define IMGU_REG_GP_SP2_STRMON_STAT (IMGU_REG_BASE + 0x524) |
117 | #define IMGU_REG_GP_ISP_STRMON_STAT (IMGU_REG_BASE + 0x528) |
118 | #define IMGU_REG_GP_MOD_STRMON_STAT (IMGU_REG_BASE + 0x52c) |
119 | |
120 | /* Port definitions for the streaming monitors. */ |
121 | /* For each definition there is signal pair : valid [bit 0]- accept [bit 1] */ |
122 | #define IMGU_GP_STRMON_STAT_SP1_PORT_SP12DMA BIT(0) |
123 | #define IMGU_GP_STRMON_STAT_SP1_PORT_DMA2SP1 BIT(2) |
124 | #define IMGU_GP_STRMON_STAT_SP1_PORT_SP12SP2 BIT(4) |
125 | #define IMGU_GP_STRMON_STAT_SP1_PORT_SP22SP1 BIT(6) |
126 | #define IMGU_GP_STRMON_STAT_SP1_PORT_SP12ISP BIT(8) |
127 | #define IMGU_GP_STRMON_STAT_SP1_PORT_ISP2SP1 BIT(10) |
128 | |
129 | #define IMGU_GP_STRMON_STAT_SP2_PORT_SP22DMA BIT(0) |
130 | #define IMGU_GP_STRMON_STAT_SP2_PORT_DMA2SP2 BIT(2) |
131 | #define IMGU_GP_STRMON_STAT_SP2_PORT_SP22SP1 BIT(4) |
132 | #define IMGU_GP_STRMON_STAT_SP2_PORT_SP12SP2 BIT(6) |
133 | |
134 | #define IMGU_GP_STRMON_STAT_ISP_PORT_ISP2DMA BIT(0) |
135 | #define IMGU_GP_STRMON_STAT_ISP_PORT_DMA2ISP BIT(2) |
136 | #define IMGU_GP_STRMON_STAT_ISP_PORT_ISP2SP1 BIT(4) |
137 | #define IMGU_GP_STRMON_STAT_ISP_PORT_SP12ISP BIT(6) |
138 | |
139 | /* Between the devices and the fifo */ |
140 | #define IMGU_GP_STRMON_STAT_MOD_PORT_SP12DMA BIT(0) |
141 | #define IMGU_GP_STRMON_STAT_MOD_PORT_DMA2SP1 BIT(2) |
142 | #define IMGU_GP_STRMON_STAT_MOD_PORT_SP22DMA BIT(4) |
143 | #define IMGU_GP_STRMON_STAT_MOD_PORT_DMA2SP2 BIT(6) |
144 | #define IMGU_GP_STRMON_STAT_MOD_PORT_ISP2DMA BIT(8) |
145 | #define IMGU_GP_STRMON_STAT_MOD_PORT_DMA2ISP BIT(10) |
146 | #define IMGU_GP_STRMON_STAT_MOD_PORT_CELLS2GDC BIT(12) |
147 | #define IMGU_GP_STRMON_STAT_MOD_PORT_GDC2CELLS BIT(14) |
148 | #define IMGU_GP_STRMON_STAT_MOD_PORT_CELLS2DECOMP BIT(16) |
149 | #define IMGU_GP_STRMON_STAT_MOD_PORT_DECOMP2CELLS BIT(18) |
150 | /* n = 1..6 */ |
151 | #define IMGU_GP_STRMON_STAT_MOD_PORT_S2V(n) (1 << (((n) - 1) * 2 + 20)) |
152 | |
153 | /* n = 1..15 */ |
154 | #define IMGU_GP_STRMON_STAT_ACCS_PORT_ACC(n) (1 << (((n) - 1) * 2)) |
155 | |
156 | /* After FIFO and demux before SP1, n = 1..15 */ |
157 | #define IMGU_GP_STRMON_STAT_ACCS2SP1_MON_PORT_ACC(n) (1 << (((n) - 1) * 2)) |
158 | |
159 | /* After FIFO and demux before SP2, n = 1..15 */ |
160 | #define IMGU_GP_STRMON_STAT_ACCS2SP2_MON_PORT_ACC(n) (1 << (((n) - 1) * 2)) |
161 | |
162 | #define IMGU_REG_GP_HALT (IMGU_REG_BASE + 0x5dc) |
163 | |
164 | /* n = 0..2 (main ctrl, SP0, SP1) */ |
165 | #define IMGU_REG_IRQCTRL_BASE(n) (IMGU_REG_BASE + (n) * 0x100 + 0x700) |
166 | #define IMGU_IRQCTRL_MAIN 0 |
167 | #define IMGU_IRQCTRL_SP0 1 |
168 | #define IMGU_IRQCTRL_SP1 2 |
169 | #define IMGU_IRQCTRL_NUM 3 |
170 | #define IMGU_IRQCTRL_IRQ_SP1 BIT(0) |
171 | #define IMGU_IRQCTRL_IRQ_SP2 BIT(1) |
172 | #define IMGU_IRQCTRL_IRQ_ISP BIT(2) |
173 | #define IMGU_IRQCTRL_IRQ_SP1_STREAM_MON BIT(3) |
174 | #define IMGU_IRQCTRL_IRQ_SP2_STREAM_MON BIT(4) |
175 | #define IMGU_IRQCTRL_IRQ_ISP_STREAM_MON BIT(5) |
176 | #define IMGU_IRQCTRL_IRQ_MOD_STREAM_MON BIT(6) |
177 | #define IMGU_IRQCTRL_IRQ_MOD_ISP_STREAM_MON BIT(7) |
178 | #define IMGU_IRQCTRL_IRQ_ACCS_STREAM_MON BIT(8) |
179 | #define IMGU_IRQCTRL_IRQ_ACCS_SP1_STREAM_MON BIT(9) |
180 | #define IMGU_IRQCTRL_IRQ_ACCS_SP2_STREAM_MON BIT(10) |
181 | #define IMGU_IRQCTRL_IRQ_ISP_PMEM_ERROR BIT(11) |
182 | #define IMGU_IRQCTRL_IRQ_ISP_BAMEM_ERROR BIT(12) |
183 | #define IMGU_IRQCTRL_IRQ_ISP_VMEM_ERROR BIT(13) |
184 | #define IMGU_IRQCTRL_IRQ_ISP_DMEM_ERROR BIT(14) |
185 | #define IMGU_IRQCTRL_IRQ_SP1_ICACHE_MEM_ERROR BIT(15) |
186 | #define IMGU_IRQCTRL_IRQ_SP1_DMEM_ERROR BIT(16) |
187 | #define IMGU_IRQCTRL_IRQ_SP2_ICACHE_MEM_ERROR BIT(17) |
188 | #define IMGU_IRQCTRL_IRQ_SP2_DMEM_ERROR BIT(18) |
189 | #define IMGU_IRQCTRL_IRQ_ACCS_SCRATCH_MEM_ERROR BIT(19) |
190 | #define IMGU_IRQCTRL_IRQ_GP_TIMER(n) BIT(20 + (n)) /* n=0..1 */ |
191 | #define IMGU_IRQCTRL_IRQ_DMA BIT(22) |
192 | #define IMGU_IRQCTRL_IRQ_SW_PIN(n) BIT(23 + (n)) /* n=0..4 */ |
193 | #define IMGU_IRQCTRL_IRQ_ACC_SYS BIT(28) |
194 | #define IMGU_IRQCTRL_IRQ_OUT_FORM_IRQ_CTRL BIT(29) |
195 | #define IMGU_IRQCTRL_IRQ_SP1_IRQ_CTRL BIT(30) |
196 | #define IMGU_IRQCTRL_IRQ_SP2_IRQ_CTRL BIT(31) |
197 | #define IMGU_REG_IRQCTRL_EDGE(n) (IMGU_REG_IRQCTRL_BASE(n) + 0x00) |
198 | #define IMGU_REG_IRQCTRL_MASK(n) (IMGU_REG_IRQCTRL_BASE(n) + 0x04) |
199 | #define IMGU_REG_IRQCTRL_STATUS(n) (IMGU_REG_IRQCTRL_BASE(n) + 0x08) |
200 | #define IMGU_REG_IRQCTRL_CLEAR(n) (IMGU_REG_IRQCTRL_BASE(n) + 0x0c) |
201 | #define IMGU_REG_IRQCTRL_ENABLE(n) (IMGU_REG_IRQCTRL_BASE(n) + 0x10) |
202 | #define IMGU_REG_IRQCTRL_EDGE_NOT_PULSE(n) (IMGU_REG_IRQCTRL_BASE(n) + 0x14) |
203 | #define IMGU_REG_IRQCTRL_STR_OUT_ENABLE(n) (IMGU_REG_IRQCTRL_BASE(n) + 0x18) |
204 | |
205 | #define IMGU_REG_GP_TIMER (IMGU_REG_BASE + 0xa34) |
206 | |
207 | #define IMGU_REG_SP_DMEM_BASE(n) (IMGU_REG_BASE + (n) * 0x4000 + 0x4000) |
208 | #define IMGU_REG_ISP_DMEM_BASE (IMGU_REG_BASE + 0xc000) |
209 | |
210 | #define IMGU_REG_GDC_BASE (IMGU_REG_BASE + 0x18000) |
211 | #define IMGU_REG_GDC_LUT_BASE (IMGU_REG_GDC_BASE + 0x140) |
212 | #define IMGU_GDC_LUT_MASK ((1 << 12) - 1) /* Range -1024..+1024 */ |
213 | |
214 | #define IMGU_SCALER_PHASES 32 |
215 | #define IMGU_SCALER_COEFF_BITS 24 |
216 | #define IMGU_SCALER_PHASE_COUNTER_PREC_REF 6 |
217 | #define IMGU_SCALER_MAX_EXPONENT_SHIFT 3 |
218 | #define IMGU_SCALER_FILTER_TAPS 4 |
219 | #define IMGU_SCALER_TAPS_Y IMGU_SCALER_FILTER_TAPS |
220 | #define IMGU_SCALER_TAPS_UV (IMGU_SCALER_FILTER_TAPS / 2) |
221 | #define IMGU_SCALER_FIR_PHASES \ |
222 | (IMGU_SCALER_PHASES << IMGU_SCALER_PHASE_COUNTER_PREC_REF) |
223 | |
224 | /******************* imgu_abi_acc_param *******************/ |
225 | |
226 | #define IMGU_ABI_SHD_MAX_PROCESS_LINES 31 |
227 | #define IMGU_ABI_SHD_MAX_TRANSFERS 31 |
228 | #define IMGU_ABI_SHD_MAX_OPERATIONS \ |
229 | (IMGU_ABI_SHD_MAX_PROCESS_LINES + IMGU_ABI_SHD_MAX_TRANSFERS) |
230 | #define IMGU_ABI_SHD_MAX_CELLS_PER_SET 146 |
231 | /* largest grid is 73x56 */ |
232 | #define IMGU_ABI_SHD_MAX_CFG_SETS (2 * 28) |
233 | |
234 | #define IMGU_ABI_DVS_STAT_MAX_OPERATIONS 100 |
235 | #define IMGU_ABI_DVS_STAT_MAX_PROCESS_LINES 52 |
236 | #define IMGU_ABI_DVS_STAT_MAX_TRANSFERS 52 |
237 | |
238 | #define IMGU_ABI_BDS_SAMPLE_PATTERN_ARRAY_SIZE 8 |
239 | #define IMGU_ABI_BDS_PHASE_COEFFS_ARRAY_SIZE 32 |
240 | |
241 | #define IMGU_ABI_AWB_FR_MAX_TRANSFERS 30 |
242 | #define IMGU_ABI_AWB_FR_MAX_PROCESS_LINES 30 |
243 | #define IMGU_ABI_AWB_FR_MAX_OPERATIONS \ |
244 | (IMGU_ABI_AWB_FR_MAX_TRANSFERS + IMGU_ABI_AWB_FR_MAX_PROCESS_LINES) |
245 | |
246 | #define IMGU_ABI_AF_MAX_TRANSFERS 30 |
247 | #define IMGU_ABI_AF_MAX_PROCESS_LINES 30 |
248 | #define IMGU_ABI_AF_MAX_OPERATIONS \ |
249 | (IMGU_ABI_AF_MAX_TRANSFERS + IMGU_ABI_AF_MAX_PROCESS_LINES) |
250 | |
251 | #define IMGU_ABI_AWB_MAX_PROCESS_LINES 68 |
252 | #define IMGU_ABI_AWB_MAX_TRANSFERS 68 |
253 | #define IMGU_ABI_AWB_MAX_OPERATIONS \ |
254 | (IMGU_ABI_AWB_MAX_PROCESS_LINES + IMGU_ABI_AWB_MAX_TRANSFERS) |
255 | |
256 | #define IMGU_ABI_OSYS_PIN_VF 0 |
257 | #define IMGU_ABI_OSYS_PIN_OUT 1 |
258 | #define IMGU_ABI_OSYS_PINS 2 |
259 | |
260 | #define IMGU_ABI_DVS_STAT_LEVELS 3 |
261 | #define IMGU_ABI_YUVP2_YTM_LUT_ENTRIES 256 |
262 | #define IMGU_ABI_GDC_FRAC_BITS 8 |
263 | #define IMGU_ABI_BINARY_MAX_OUTPUT_PORTS 2 |
264 | #define IMGU_ABI_MAX_BINARY_NAME 64 |
265 | #define IMGU_ABI_ISP_DDR_WORD_BITS 256 |
266 | #define IMGU_ABI_ISP_DDR_WORD_BYTES (IMGU_ABI_ISP_DDR_WORD_BITS / 8) |
267 | #define IMGU_ABI_MAX_STAGES 3 |
268 | #define IMGU_ABI_MAX_IF_CONFIGS 3 |
269 | #define IMGU_ABI_PIPE_CONFIG_ACQUIRE_ISP BIT(31) |
270 | #define IMGU_ABI_PORT_CONFIG_TYPE_INPUT_HOST BIT(0) |
271 | #define IMGU_ABI_PORT_CONFIG_TYPE_OUTPUT_HOST BIT(4) |
272 | #define IMGU_ABI_MAX_SP_THREADS 4 |
273 | #define IMGU_ABI_FRAMES_REF 3 |
274 | #define IMGU_ABI_FRAMES_TNR 4 |
275 | #define IMGU_ABI_BUF_SETS_TNR 1 |
276 | |
277 | #define IMGU_ABI_EVENT_BUFFER_ENQUEUED(thread, queue) \ |
278 | (0 << 24 | (thread) << 16 | (queue) << 8) |
279 | #define IMGU_ABI_EVENT_BUFFER_DEQUEUED(queue) (1 << 24 | (queue) << 8) |
280 | #define IMGU_ABI_EVENT_EVENT_DEQUEUED (2 << 24) |
281 | #define IMGU_ABI_EVENT_START_STREAM (3 << 24) |
282 | #define IMGU_ABI_EVENT_STOP_STREAM (4 << 24) |
283 | #define IMGU_ABI_EVENT_MIPI_BUFFERS_READY (5 << 24) |
284 | #define IMGU_ABI_EVENT_UNLOCK_RAW_BUFFER (6 << 24) |
285 | #define IMGU_ABI_EVENT_STAGE_ENABLE_DISABLE (7 << 24) |
286 | |
287 | #define IMGU_ABI_HOST2SP_BUFQ_SIZE 3 |
288 | #define IMGU_ABI_SP2HOST_BUFQ_SIZE (2 * IMGU_ABI_MAX_SP_THREADS) |
289 | #define IMGU_ABI_HOST2SP_EVTQ_SIZE (IMGU_ABI_QUEUE_NUM * \ |
290 | IMGU_ABI_MAX_SP_THREADS * 2 + IMGU_ABI_MAX_SP_THREADS * 4) |
291 | #define IMGU_ABI_SP2HOST_EVTQ_SIZE (6 * IMGU_ABI_MAX_SP_THREADS) |
292 | |
293 | #define IMGU_ABI_EVTTYPE_EVENT_SHIFT 0 |
294 | #define IMGU_ABI_EVTTYPE_EVENT_MASK (0xff << IMGU_ABI_EVTTYPE_EVENT_SHIFT) |
295 | #define IMGU_ABI_EVTTYPE_PIPE_SHIFT 8 |
296 | #define IMGU_ABI_EVTTYPE_PIPE_MASK (0xff << IMGU_ABI_EVTTYPE_PIPE_SHIFT) |
297 | #define IMGU_ABI_EVTTYPE_PIPEID_SHIFT 16 |
298 | #define IMGU_ABI_EVTTYPE_PIPEID_MASK (0xff << IMGU_ABI_EVTTYPE_PIPEID_SHIFT) |
299 | #define IMGU_ABI_EVTTYPE_MODULEID_SHIFT 8 |
300 | #define IMGU_ABI_EVTTYPE_MODULEID_MASK (0xff << IMGU_ABI_EVTTYPE_MODULEID_SHIFT) |
301 | #define IMGU_ABI_EVTTYPE_LINENO_SHIFT 16 |
302 | #define IMGU_ABI_EVTTYPE_LINENO_MASK (0xffff << IMGU_ABI_EVTTYPE_LINENO_SHIFT) |
303 | |
304 | /* Output frame ready */ |
305 | #define IMGU_ABI_EVTTYPE_OUT_FRAME_DONE 0 |
306 | /* Second output frame ready */ |
307 | #define IMGU_ABI_EVTTYPE_2ND_OUT_FRAME_DONE 1 |
308 | /* Viewfinder Output frame ready */ |
309 | #define IMGU_ABI_EVTTYPE_VF_OUT_FRAME_DONE 2 |
310 | /* Second viewfinder Output frame ready */ |
311 | #define IMGU_ABI_EVTTYPE_2ND_VF_OUT_FRAME_DONE 3 |
312 | /* Indication that 3A statistics are available */ |
313 | #define IMGU_ABI_EVTTYPE_3A_STATS_DONE 4 |
314 | /* Indication that DIS statistics are available */ |
315 | #define IMGU_ABI_EVTTYPE_DIS_STATS_DONE 5 |
316 | /* Pipeline Done event, sent after last pipeline stage */ |
317 | #define IMGU_ABI_EVTTYPE_PIPELINE_DONE 6 |
318 | /* Frame tagged */ |
319 | #define IMGU_ABI_EVTTYPE_FRAME_TAGGED 7 |
320 | /* Input frame ready */ |
321 | #define IMGU_ABI_EVTTYPE_INPUT_FRAME_DONE 8 |
322 | /* Metadata ready */ |
323 | #define IMGU_ABI_EVTTYPE_METADATA_DONE 9 |
324 | /* Indication that LACE statistics are available */ |
325 | #define IMGU_ABI_EVTTYPE_LACE_STATS_DONE 10 |
326 | /* Extension stage executed */ |
327 | #define IMGU_ABI_EVTTYPE_ACC_STAGE_COMPLETE 11 |
328 | /* Timing measurement data */ |
329 | #define IMGU_ABI_EVTTYPE_TIMER 12 |
330 | /* End Of Frame event, sent when in buffered sensor mode */ |
331 | #define IMGU_ABI_EVTTYPE_PORT_EOF 13 |
332 | /* Performance warning encountered by FW */ |
333 | #define IMGU_ABI_EVTTYPE_FW_WARNING 14 |
334 | /* Assertion hit by FW */ |
335 | #define IMGU_ABI_EVTTYPE_FW_ASSERT 15 |
336 | |
337 | #define IMGU_ABI_NUM_CONTINUOUS_FRAMES 10 |
338 | #define IMGU_ABI_SP_COMM_COMMAND 0x00 |
339 | |
340 | /* |
341 | * The host2sp_cmd_ready command is the only command written by the SP |
342 | * It acknowledges that is previous command has been received. |
343 | * (this does not mean that the command has been executed) |
344 | * It also indicates that a new command can be send (it is a queue |
345 | * with depth 1). |
346 | */ |
347 | #define IMGU_ABI_SP_COMM_COMMAND_READY 1 |
348 | /* Command written by the Host */ |
349 | #define IMGU_ABI_SP_COMM_COMMAND_DUMMY 2 /* No action */ |
350 | #define IMGU_ABI_SP_COMM_COMMAND_START_FLASH 3 /* Start the flash */ |
351 | #define IMGU_ABI_SP_COMM_COMMAND_TERMINATE 4 /* Terminate */ |
352 | |
353 | /* n = 0..IPU3_CSS_PIPE_ID_NUM-1 */ |
354 | #define IMGU_ABI_SP_COMM_EVENT_IRQ_MASK(n) ((n) * 4 + 0x60) |
355 | #define IMGU_ABI_SP_COMM_EVENT_IRQ_MASK_OR_SHIFT 0 |
356 | #define IMGU_ABI_SP_COMM_EVENT_IRQ_MASK_AND_SHIFT 16 |
357 | |
358 | #define IMGU_ABI_BL_DMACMD_TYPE_SP_PMEM 1 /* sp_pmem */ |
359 | |
360 | /***** For parameter computation *****/ |
361 | |
362 | #define IMGU_HIVE_OF_SYS_SCALER_TO_FA_OFFSET 0xC |
363 | #define IMGU_HIVE_OF_SYS_OF_TO_FA_OFFSET 0x8 |
364 | #define IMGU_HIVE_OF_SYS_OF_SYSTEM_NWAYS 32 |
365 | |
366 | #define IMGU_SCALER_ELEMS_PER_VEC 0x10 |
367 | #define IMGU_SCALER_FILTER_TAPS_Y 0x4 |
368 | #define IMGU_SCALER_OUT_BPP 0x8 |
369 | |
370 | #define IMGU_SCALER_MS_TO_OUTFORMACC_SL_ADDR 0x400 |
371 | #define IMGU_SCALER_TO_OF_ACK_FA_ADDR \ |
372 | (0xC00 + IMGU_HIVE_OF_SYS_SCALER_TO_FA_OFFSET) |
373 | #define IMGU_OF_TO_ACK_FA_ADDR (0xC00 + IMGU_HIVE_OF_SYS_OF_TO_FA_OFFSET) |
374 | #define IMGU_OUTFORMACC_MS_TO_SCALER_SL_ADDR 0 |
375 | #define IMGU_SCALER_INTR_BPP 10 |
376 | |
377 | #define IMGU_PS_SNR_PRESERVE_BITS 3 |
378 | #define IMGU_CNTX_BPP 11 |
379 | #define IMGU_SCALER_FILTER_TAPS_UV (IMGU_SCALER_FILTER_TAPS_Y / 2) |
380 | |
381 | #define IMGU_VMEM2_ELEMS_PER_VEC (IMGU_SCALER_ELEMS_PER_VEC) |
382 | #define IMGU_STRIDE_Y (IMGU_SCALER_FILTER_TAPS_Y + 1) |
383 | #define IMGU_MAX_FRAME_WIDTH 3840 |
384 | #define IMGU_VMEM3_ELEMS_PER_VEC (IMGU_SCALER_ELEMS_PER_VEC) |
385 | |
386 | #define IMGU_VER_CNTX_WORDS DIV_ROUND_UP((IMGU_SCALER_OUT_BPP + \ |
387 | IMGU_PS_SNR_PRESERVE_BITS), IMGU_CNTX_BPP) /* 1 */ |
388 | #define IMGU_MAX_INPUT_BLOCK_HEIGHT 64 |
389 | #define IMGU_HOR_CNTX_WORDS DIV_ROUND_UP((IMGU_SCALER_INTR_BPP + \ |
390 | IMGU_PS_SNR_PRESERVE_BITS), IMGU_CNTX_BPP) /* 2 */ |
391 | #define IMGU_MAX_OUTPUT_BLOCK_WIDTH 128 |
392 | #define IMGU_CNTX_STRIDE_UV (IMGU_SCALER_FILTER_TAPS_UV + 1) |
393 | |
394 | #define IMGU_OSYS_DMA_CROP_W_LIMIT 64 |
395 | #define IMGU_OSYS_DMA_CROP_H_LIMIT 4 |
396 | #define IMGU_OSYS_BLOCK_WIDTH (2 * IPU3_UAPI_ISP_VEC_ELEMS) |
397 | #define IMGU_OSYS_BLOCK_HEIGHT 32 |
398 | #define IMGU_OSYS_PHASES 0x20 |
399 | #define IMGU_OSYS_FILTER_TAPS 0x4 |
400 | #define IMGU_OSYS_PHASE_COUNTER_PREC_REF 6 |
401 | #define IMGU_OSYS_NUM_INPUT_BUFFERS 2 |
402 | #define IMGU_OSYS_FIR_PHASES \ |
403 | (IMGU_OSYS_PHASES << IMGU_OSYS_PHASE_COUNTER_PREC_REF) |
404 | #define IMGU_OSYS_TAPS_UV (IMGU_OSYS_FILTER_TAPS / 2) |
405 | #define IMGU_OSYS_TAPS_Y (IMGU_OSYS_FILTER_TAPS) |
406 | #define IMGU_OSYS_NUM_INTERM_BUFFERS 2 |
407 | |
408 | #define IMGU_VMEM1_Y_SIZE \ |
409 | (IMGU_OSYS_BLOCK_HEIGHT * IMGU_VMEM1_Y_STRIDE) |
410 | #define IMGU_VMEM1_UV_SIZE (IMGU_VMEM1_Y_SIZE / 4) |
411 | #define IMGU_VMEM1_OUT_BUF_ADDR (IMGU_VMEM1_INP_BUF_ADDR + \ |
412 | (IMGU_OSYS_NUM_INPUT_BUFFERS * IMGU_VMEM1_BUF_SIZE)) |
413 | #define IMGU_OSYS_NUM_OUTPUT_BUFFERS 2 |
414 | |
415 | /* transpose of input height */ |
416 | #define IMGU_VMEM2_VECS_PER_LINE \ |
417 | (DIV_ROUND_UP(IMGU_OSYS_BLOCK_HEIGHT, IMGU_VMEM2_ELEMS_PER_VEC)) |
418 | /* size in words (vectors) */ |
419 | #define IMGU_VMEM2_BUF_SIZE \ |
420 | (IMGU_VMEM2_VECS_PER_LINE * IMGU_VMEM2_LINES_PER_BLOCK) |
421 | #define IMGU_VMEM3_VER_Y_SIZE \ |
422 | ((IMGU_STRIDE_Y * IMGU_MAX_FRAME_WIDTH \ |
423 | / IMGU_VMEM3_ELEMS_PER_VEC) * IMGU_VER_CNTX_WORDS) |
424 | #define IMGU_VMEM3_HOR_Y_SIZE \ |
425 | ((IMGU_STRIDE_Y * IMGU_MAX_INPUT_BLOCK_HEIGHT \ |
426 | / IMGU_VMEM3_ELEMS_PER_VEC) * IMGU_HOR_CNTX_WORDS) |
427 | #define \ |
428 | ((IMGU_STRIDE_Y * IMGU_MAX_OUTPUT_BLOCK_WIDTH \ |
429 | / IMGU_VMEM3_ELEMS_PER_VEC) * IMGU_VER_CNTX_WORDS) |
430 | #define IMGU_VMEM3_VER_U_SIZE \ |
431 | (((IMGU_CNTX_STRIDE_UV * IMGU_MAX_FRAME_WIDTH \ |
432 | / IMGU_VMEM3_ELEMS_PER_VEC) * IMGU_VER_CNTX_WORDS) / 2) |
433 | #define IMGU_VMEM3_HOR_U_SIZE \ |
434 | (((IMGU_STRIDE_Y * IMGU_MAX_INPUT_BLOCK_HEIGHT \ |
435 | / IMGU_VMEM3_ELEMS_PER_VEC) * IMGU_HOR_CNTX_WORDS) / 2) |
436 | #define \ |
437 | (((IMGU_CNTX_STRIDE_UV * IMGU_MAX_OUTPUT_BLOCK_WIDTH \ |
438 | / IMGU_VMEM3_ELEMS_PER_VEC) * IMGU_VER_CNTX_WORDS) / 2) |
439 | #define IMGU_VMEM3_VER_V_SIZE \ |
440 | (((IMGU_CNTX_STRIDE_UV * IMGU_MAX_FRAME_WIDTH \ |
441 | / IMGU_VMEM3_ELEMS_PER_VEC) * IMGU_VER_CNTX_WORDS) / 2) |
442 | |
443 | #define IMGU_ISP_VEC_NELEMS 64 |
444 | #define IMGU_LUMA_TO_CHROMA_RATIO 2 |
445 | #define IMGU_INPUT_BLOCK_WIDTH (128) |
446 | #define IMGU_FIFO_ADDR_SCALER_TO_FMT \ |
447 | (IMGU_SCALER_MS_TO_OUTFORMACC_SL_ADDR >> 2) |
448 | #define IMGU_FIFO_ADDR_SCALER_TO_SP (IMGU_SCALER_TO_OF_ACK_FA_ADDR >> 2) |
449 | #define IMGU_VMEM1_INP_BUF_ADDR 0 |
450 | #define IMGU_VMEM1_Y_STRIDE \ |
451 | (IMGU_OSYS_BLOCK_WIDTH / IMGU_VMEM1_ELEMS_PER_VEC) |
452 | #define IMGU_VMEM1_BUF_SIZE (IMGU_VMEM1_V_OFFSET + IMGU_VMEM1_UV_SIZE) |
453 | |
454 | #define IMGU_VMEM1_U_OFFSET (IMGU_VMEM1_Y_SIZE) |
455 | #define IMGU_VMEM1_V_OFFSET (IMGU_VMEM1_U_OFFSET + IMGU_VMEM1_UV_SIZE) |
456 | #define IMGU_VMEM1_UV_STRIDE (IMGU_VMEM1_Y_STRIDE / 2) |
457 | #define IMGU_VMEM1_INT_BUF_ADDR (IMGU_VMEM1_OUT_BUF_ADDR + \ |
458 | (IMGU_OSYS_NUM_OUTPUT_BUFFERS * IMGU_VMEM1_BUF_SIZE)) |
459 | |
460 | #define IMGU_VMEM1_ELEMS_PER_VEC (IMGU_HIVE_OF_SYS_OF_SYSTEM_NWAYS) |
461 | #define IMGU_VMEM2_BUF_Y_ADDR 0 |
462 | #define IMGU_VMEM2_BUF_Y_STRIDE (IMGU_VMEM2_VECS_PER_LINE) |
463 | #define IMGU_VMEM2_BUF_U_ADDR \ |
464 | (IMGU_VMEM2_BUF_Y_ADDR + IMGU_VMEM2_BUF_SIZE) |
465 | #define IMGU_VMEM2_BUF_V_ADDR \ |
466 | (IMGU_VMEM2_BUF_U_ADDR + IMGU_VMEM2_BUF_SIZE / 4) |
467 | #define IMGU_VMEM2_BUF_UV_STRIDE (IMGU_VMEM2_VECS_PER_LINE / 2) |
468 | /* 1.5 x depth of intermediate buffer */ |
469 | #define IMGU_VMEM2_LINES_PER_BLOCK 192 |
470 | #define IMGU_VMEM3_HOR_Y_ADDR \ |
471 | (IMGU_VMEM3_VER_Y_ADDR + IMGU_VMEM3_VER_Y_SIZE) |
472 | #define IMGU_VMEM3_HOR_U_ADDR \ |
473 | (IMGU_VMEM3_VER_U_ADDR + IMGU_VMEM3_VER_U_SIZE) |
474 | #define IMGU_VMEM3_HOR_V_ADDR \ |
475 | (IMGU_VMEM3_VER_V_ADDR + IMGU_VMEM3_VER_V_SIZE) |
476 | #define IMGU_VMEM3_VER_Y_ADDR 0 |
477 | #define IMGU_VMEM3_VER_U_ADDR \ |
478 | (IMGU_VMEM3_VER_Y_ADDR + IMGU_VMEM3_VER_Y_SIZE + \ |
479 | max(IMGU_VMEM3_HOR_Y_SIZE, IMGU_VMEM3_VER_Y_EXTRA)) |
480 | #define IMGU_VMEM3_VER_V_ADDR \ |
481 | (IMGU_VMEM3_VER_U_ADDR + IMGU_VMEM3_VER_U_SIZE + \ |
482 | max(IMGU_VMEM3_HOR_U_SIZE, IMGU_VMEM3_VER_U_EXTRA)) |
483 | #define IMGU_FIFO_ADDR_FMT_TO_SP (IMGU_OF_TO_ACK_FA_ADDR >> 2) |
484 | #define IMGU_FIFO_ADDR_FMT_TO_SCALER (IMGU_OUTFORMACC_MS_TO_SCALER_SL_ADDR >> 2) |
485 | #define IMGU_VMEM1_HST_BUF_ADDR (IMGU_VMEM1_INT_BUF_ADDR + \ |
486 | (IMGU_OSYS_NUM_INTERM_BUFFERS * IMGU_VMEM1_BUF_SIZE)) |
487 | #define IMGU_VMEM1_HST_BUF_STRIDE 120 |
488 | #define IMGU_VMEM1_HST_BUF_NLINES 3 |
489 | |
490 | enum imgu_abi_frame_format { |
491 | IMGU_ABI_FRAME_FORMAT_NV11, /* 12 bit YUV 411, Y, UV plane */ |
492 | IMGU_ABI_FRAME_FORMAT_NV12, /* 12 bit YUV 420, Y, UV plane */ |
493 | IMGU_ABI_FRAME_FORMAT_NV12_16, /* 16 bit YUV 420, Y, UV plane */ |
494 | IMGU_ABI_FRAME_FORMAT_NV12_TILEY,/* 12 bit YUV 420,Intel tiled format */ |
495 | IMGU_ABI_FRAME_FORMAT_NV16, /* 16 bit YUV 422, Y, UV plane */ |
496 | IMGU_ABI_FRAME_FORMAT_NV21, /* 12 bit YUV 420, Y, VU plane */ |
497 | IMGU_ABI_FRAME_FORMAT_NV61, /* 16 bit YUV 422, Y, VU plane */ |
498 | IMGU_ABI_FRAME_FORMAT_YV12, /* 12 bit YUV 420, Y, V, U plane */ |
499 | IMGU_ABI_FRAME_FORMAT_YV16, /* 16 bit YUV 422, Y, V, U plane */ |
500 | IMGU_ABI_FRAME_FORMAT_YUV420, /* 12 bit YUV 420, Y, U, V plane */ |
501 | IMGU_ABI_FRAME_FORMAT_YUV420_16,/* yuv420, 16 bits per subpixel */ |
502 | IMGU_ABI_FRAME_FORMAT_YUV422, /* 16 bit YUV 422, Y, U, V plane */ |
503 | IMGU_ABI_FRAME_FORMAT_YUV422_16,/* yuv422, 16 bits per subpixel */ |
504 | IMGU_ABI_FRAME_FORMAT_UYVY, /* 16 bit YUV 422, UYVY interleaved */ |
505 | IMGU_ABI_FRAME_FORMAT_YUYV, /* 16 bit YUV 422, YUYV interleaved */ |
506 | IMGU_ABI_FRAME_FORMAT_YUV444, /* 24 bit YUV 444, Y, U, V plane */ |
507 | IMGU_ABI_FRAME_FORMAT_YUV_LINE, /* Internal format, 2 y lines */ |
508 | /* followed by a uv-interleaved line */ |
509 | IMGU_ABI_FRAME_FORMAT_RAW, /* RAW, 1 plane */ |
510 | IMGU_ABI_FRAME_FORMAT_RGB565, /* 16 bit RGB, 1 plane. Each 3 sub |
511 | * pixels are packed into one 16 bit |
512 | * value, 5 bits for R, 6 bits for G |
513 | * and 5 bits for B. |
514 | */ |
515 | IMGU_ABI_FRAME_FORMAT_PLANAR_RGB888, /* 24 bit RGB, 3 planes */ |
516 | IMGU_ABI_FRAME_FORMAT_RGBA888, /* 32 bit RGBA, 1 plane, A=Alpha |
517 | * (alpha is unused) |
518 | */ |
519 | IMGU_ABI_FRAME_FORMAT_QPLANE6, /* Internal, for advanced ISP */ |
520 | IMGU_ABI_FRAME_FORMAT_BINARY_8, /* byte stream, used for jpeg. For |
521 | * frames of this type, we set the |
522 | * height to 1 and the width to the |
523 | * number of allocated bytes. |
524 | */ |
525 | IMGU_ABI_FRAME_FORMAT_MIPI, /* MIPI frame, 1 plane */ |
526 | IMGU_ABI_FRAME_FORMAT_RAW_PACKED, /* RAW, 1 plane, packed */ |
527 | IMGU_ABI_FRAME_FORMAT_CSI_MIPI_YUV420_8, /* 8 bit per Y/U/V. Y odd line |
528 | * UYVY interleaved even line |
529 | */ |
530 | IMGU_ABI_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8, /* Legacy YUV420. |
531 | * UY odd line; |
532 | * VY even line |
533 | */ |
534 | IMGU_ABI_FRAME_FORMAT_CSI_MIPI_YUV420_10,/* 10 bit per Y/U/V. Y odd |
535 | * line; UYVY interleaved |
536 | * even line |
537 | */ |
538 | IMGU_ABI_FRAME_FORMAT_YCGCO444_16, /* Internal format for ISP2.7, |
539 | * 16 bits per plane YUV 444, |
540 | * Y, U, V plane |
541 | */ |
542 | IMGU_ABI_FRAME_FORMAT_NUM |
543 | }; |
544 | |
545 | enum imgu_abi_bayer_order { |
546 | IMGU_ABI_BAYER_ORDER_GRBG, |
547 | IMGU_ABI_BAYER_ORDER_RGGB, |
548 | IMGU_ABI_BAYER_ORDER_BGGR, |
549 | IMGU_ABI_BAYER_ORDER_GBRG |
550 | }; |
551 | |
552 | enum imgu_abi_osys_format { |
553 | IMGU_ABI_OSYS_FORMAT_YUV420, |
554 | IMGU_ABI_OSYS_FORMAT_YV12, |
555 | IMGU_ABI_OSYS_FORMAT_NV12, |
556 | IMGU_ABI_OSYS_FORMAT_NV21, |
557 | IMGU_ABI_OSYS_FORMAT_YUV_LINE, |
558 | IMGU_ABI_OSYS_FORMAT_YUY2, /* = IMGU_ABI_OSYS_FORMAT_YUYV */ |
559 | IMGU_ABI_OSYS_FORMAT_NV16, |
560 | IMGU_ABI_OSYS_FORMAT_RGBA, |
561 | IMGU_ABI_OSYS_FORMAT_BGRA |
562 | }; |
563 | |
564 | enum imgu_abi_osys_tiling { |
565 | IMGU_ABI_OSYS_TILING_NONE, |
566 | IMGU_ABI_OSYS_TILING_Y, |
567 | IMGU_ABI_OSYS_TILING_YF, |
568 | }; |
569 | |
570 | enum imgu_abi_osys_procmode { |
571 | IMGU_ABI_OSYS_PROCMODE_BYPASS, |
572 | IMGU_ABI_OSYS_PROCMODE_UPSCALE, |
573 | IMGU_ABI_OSYS_PROCMODE_DOWNSCALE, |
574 | }; |
575 | |
576 | enum imgu_abi_queue_id { |
577 | IMGU_ABI_QUEUE_EVENT_ID = -1, |
578 | IMGU_ABI_QUEUE_A_ID = 0, |
579 | IMGU_ABI_QUEUE_B_ID, |
580 | IMGU_ABI_QUEUE_C_ID, |
581 | IMGU_ABI_QUEUE_D_ID, |
582 | IMGU_ABI_QUEUE_E_ID, |
583 | IMGU_ABI_QUEUE_F_ID, |
584 | IMGU_ABI_QUEUE_G_ID, |
585 | IMGU_ABI_QUEUE_H_ID, /* input frame queue for skycam */ |
586 | IMGU_ABI_QUEUE_NUM |
587 | }; |
588 | |
589 | enum imgu_abi_buffer_type { |
590 | IMGU_ABI_BUFFER_TYPE_INVALID = -1, |
591 | IMGU_ABI_BUFFER_TYPE_3A_STATISTICS = 0, |
592 | IMGU_ABI_BUFFER_TYPE_DIS_STATISTICS, |
593 | IMGU_ABI_BUFFER_TYPE_LACE_STATISTICS, |
594 | IMGU_ABI_BUFFER_TYPE_INPUT_FRAME, |
595 | IMGU_ABI_BUFFER_TYPE_OUTPUT_FRAME, |
596 | IMGU_ABI_BUFFER_TYPE_SEC_OUTPUT_FRAME, |
597 | IMGU_ABI_BUFFER_TYPE_VF_OUTPUT_FRAME, |
598 | IMGU_ABI_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME, |
599 | IMGU_ABI_BUFFER_TYPE_RAW_OUTPUT_FRAME, |
600 | IMGU_ABI_BUFFER_TYPE_CUSTOM_INPUT, |
601 | IMGU_ABI_BUFFER_TYPE_CUSTOM_OUTPUT, |
602 | IMGU_ABI_BUFFER_TYPE_METADATA, |
603 | IMGU_ABI_BUFFER_TYPE_PARAMETER_SET, |
604 | IMGU_ABI_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, |
605 | IMGU_ABI_NUM_DYNAMIC_BUFFER_TYPE, |
606 | IMGU_ABI_NUM_BUFFER_TYPE |
607 | }; |
608 | |
609 | enum imgu_abi_raw_type { |
610 | IMGU_ABI_RAW_TYPE_BAYER, |
611 | IMGU_ABI_RAW_TYPE_IR_ON_GR, |
612 | IMGU_ABI_RAW_TYPE_IR_ON_GB |
613 | }; |
614 | |
615 | enum imgu_abi_memories { |
616 | IMGU_ABI_MEM_ISP_PMEM0 = 0, |
617 | IMGU_ABI_MEM_ISP_DMEM0, |
618 | IMGU_ABI_MEM_ISP_VMEM0, |
619 | IMGU_ABI_MEM_ISP_VAMEM0, |
620 | IMGU_ABI_MEM_ISP_VAMEM1, |
621 | IMGU_ABI_MEM_ISP_VAMEM2, |
622 | IMGU_ABI_MEM_ISP_HMEM0, |
623 | IMGU_ABI_MEM_SP0_DMEM0, |
624 | IMGU_ABI_MEM_SP1_DMEM0, |
625 | IMGU_ABI_MEM_DDR, |
626 | IMGU_ABI_NUM_MEMORIES |
627 | }; |
628 | |
629 | enum imgu_abi_param_class { |
630 | IMGU_ABI_PARAM_CLASS_PARAM, /* Late binding parameters, like 3A */ |
631 | IMGU_ABI_PARAM_CLASS_CONFIG, /* Pipe config time parameters */ |
632 | IMGU_ABI_PARAM_CLASS_STATE, /* State parameters, eg. buffer index */ |
633 | IMGU_ABI_PARAM_CLASS_NUM |
634 | }; |
635 | |
636 | enum imgu_abi_bin_input_src { |
637 | IMGU_ABI_BINARY_INPUT_SOURCE_SENSOR, |
638 | IMGU_ABI_BINARY_INPUT_SOURCE_MEMORY, |
639 | IMGU_ABI_BINARY_INPUT_SOURCE_VARIABLE, |
640 | }; |
641 | |
642 | enum imgu_abi_sp_swstate { |
643 | IMGU_ABI_SP_SWSTATE_TERMINATED, |
644 | IMGU_ABI_SP_SWSTATE_INITIALIZED, |
645 | IMGU_ABI_SP_SWSTATE_CONNECTED, |
646 | IMGU_ABI_SP_SWSTATE_RUNNING, |
647 | }; |
648 | |
649 | enum imgu_abi_bl_swstate { |
650 | IMGU_ABI_BL_SWSTATE_OK = 0x100, |
651 | IMGU_ABI_BL_SWSTATE_BUSY, |
652 | IMGU_ABI_BL_SWSTATE_ERR, |
653 | }; |
654 | |
655 | /* The type of pipe stage */ |
656 | enum imgu_abi_stage_type { |
657 | IMGU_ABI_STAGE_TYPE_SP, |
658 | IMGU_ABI_STAGE_TYPE_ISP, |
659 | }; |
660 | |
661 | struct imgu_abi_acc_operation { |
662 | /* |
663 | * zero means on init, |
664 | * others mean upon receiving an ack signal from the BC acc. |
665 | */ |
666 | u8 op_indicator; |
667 | u8 op_type; |
668 | } __packed; |
669 | |
670 | struct imgu_abi_acc_process_lines_cmd_data { |
671 | u16 lines; |
672 | u8 cfg_set; |
673 | u8 reserved; /* Align to 4 bytes */ |
674 | } __packed; |
675 | |
676 | /* Bayer shading definitions */ |
677 | |
678 | struct imgu_abi_shd_transfer_luts_set_data { |
679 | u8 set_number; |
680 | u8 padding[3]; |
681 | imgu_addr_t rg_lut_ddr_addr; |
682 | imgu_addr_t bg_lut_ddr_addr; |
683 | u32 align_dummy; |
684 | } __packed; |
685 | |
686 | struct imgu_abi_shd_grid_config { |
687 | /* reg 0 */ |
688 | u32 grid_width:8; |
689 | u32 grid_height:8; |
690 | u32 block_width:3; |
691 | u32 reserved0:1; |
692 | u32 block_height:3; |
693 | u32 reserved1:1; |
694 | u32 grid_height_per_slice:8; |
695 | /* reg 1 */ |
696 | s32 x_start:13; |
697 | s32 reserved2:3; |
698 | s32 y_start:13; |
699 | s32 reserved3:3; |
700 | } __packed; |
701 | |
702 | struct imgu_abi_shd_general_config { |
703 | u32 init_set_vrt_offst_ul:8; |
704 | u32 shd_enable:1; |
705 | /* aka 'gf' */ |
706 | u32 gain_factor:2; |
707 | u32 reserved:21; |
708 | } __packed; |
709 | |
710 | struct imgu_abi_shd_black_level_config { |
711 | /* reg 0 */ |
712 | s32 bl_r:12; |
713 | s32 reserved0:4; |
714 | s32 bl_gr:12; |
715 | u32 reserved1:1; |
716 | /* aka 'nf' */ |
717 | u32 normalization_shift:3; |
718 | /* reg 1 */ |
719 | s32 bl_gb:12; |
720 | s32 reserved2:4; |
721 | s32 bl_b:12; |
722 | s32 reserved3:4; |
723 | } __packed; |
724 | |
725 | struct imgu_abi_shd_intra_frame_operations_data { |
726 | struct imgu_abi_acc_operation |
727 | operation_list[IMGU_ABI_SHD_MAX_OPERATIONS] __aligned(32); |
728 | struct imgu_abi_acc_process_lines_cmd_data |
729 | process_lines_data[IMGU_ABI_SHD_MAX_PROCESS_LINES] __aligned(32); |
730 | struct imgu_abi_shd_transfer_luts_set_data |
731 | transfer_data[IMGU_ABI_SHD_MAX_TRANSFERS] __aligned(32); |
732 | } __packed; |
733 | |
734 | struct imgu_abi_shd_config { |
735 | struct ipu3_uapi_shd_config_static shd __aligned(32); |
736 | struct imgu_abi_shd_intra_frame_operations_data shd_ops __aligned(32); |
737 | struct ipu3_uapi_shd_lut shd_lut __aligned(32); |
738 | } __packed; |
739 | |
740 | struct imgu_abi_stripe_input_frame_resolution { |
741 | u16 width; |
742 | u16 height; |
743 | u32 bayer_order; /* enum ipu3_uapi_bayer_order */ |
744 | u32 raw_bit_depth; |
745 | } __packed; |
746 | |
747 | /* Stripe-based processing */ |
748 | |
749 | struct imgu_abi_stripes { |
750 | /* offset from start of frame - measured in pixels */ |
751 | u16 offset; |
752 | /* stripe width - measured in pixels */ |
753 | u16 width; |
754 | /* stripe width - measured in pixels */ |
755 | u16 height; |
756 | } __packed; |
757 | |
758 | struct imgu_abi_stripe_data { |
759 | /* |
760 | * number of stripes for current processing source |
761 | * - VLIW binary parameter we currently support 1 or 2 stripes |
762 | */ |
763 | u16 num_of_stripes; |
764 | |
765 | u8 padding[2]; |
766 | |
767 | /* |
768 | * the following data is derived from resolution-related |
769 | * pipe config and from num_of_stripes |
770 | */ |
771 | |
772 | /* |
773 | *'input-stripes' - before input cropping |
774 | * used by input feeder |
775 | */ |
776 | struct imgu_abi_stripe_input_frame_resolution input_frame; |
777 | |
778 | /*'effective-stripes' - after input cropping used dpc, bds */ |
779 | struct imgu_abi_stripes effective_stripes[IPU3_UAPI_MAX_STRIPES]; |
780 | |
781 | /* 'down-scaled-stripes' - after down-scaling ONLY. used by BDS */ |
782 | struct imgu_abi_stripes down_scaled_stripes[IPU3_UAPI_MAX_STRIPES]; |
783 | |
784 | /* |
785 | *'bds-out-stripes' - after bayer down-scaling and padding. |
786 | * used by all algos starting with norm up to the ref-frame for GDC |
787 | * (currently up to the output kernel) |
788 | */ |
789 | struct imgu_abi_stripes bds_out_stripes[IPU3_UAPI_MAX_STRIPES]; |
790 | |
791 | /* 'bds-out-stripes (no overlap)' - used for ref kernel */ |
792 | struct imgu_abi_stripes |
793 | bds_out_stripes_no_overlap[IPU3_UAPI_MAX_STRIPES]; |
794 | |
795 | /* |
796 | * input resolution for output system (equal to bds_out - envelope) |
797 | * output-system input frame width as configured by user |
798 | */ |
799 | u16 output_system_in_frame_width; |
800 | /* output-system input frame height as configured by user */ |
801 | u16 output_system_in_frame_height; |
802 | |
803 | /* |
804 | * 'output-stripes' - accounts for stiching on the output (no overlap) |
805 | * used by the output kernel |
806 | */ |
807 | struct imgu_abi_stripes output_stripes[IPU3_UAPI_MAX_STRIPES]; |
808 | |
809 | /* |
810 | * 'block-stripes' - accounts for stiching by the output system |
811 | * (1 or more blocks overlap) |
812 | * used by DVS, TNR and the output system kernel |
813 | */ |
814 | struct imgu_abi_stripes block_stripes[IPU3_UAPI_MAX_STRIPES]; |
815 | |
816 | u16 effective_frame_width; /* Needed for vertical cropping */ |
817 | u16 bds_frame_width; |
818 | u16 out_frame_width; /* Output frame width as configured by user */ |
819 | u16 out_frame_height; /* Output frame height as configured by user */ |
820 | |
821 | /* GDC in buffer (A.K.A delay frame,ref buffer) info */ |
822 | u16 gdc_in_buffer_width; /* GDC in buffer width */ |
823 | u16 gdc_in_buffer_height; /* GDC in buffer height */ |
824 | /* GDC in buffer first valid pixel x offset */ |
825 | u16 gdc_in_buffer_offset_x; |
826 | /* GDC in buffer first valid pixel y offset */ |
827 | u16 gdc_in_buffer_offset_y; |
828 | |
829 | /* Display frame width as configured by user */ |
830 | u16 display_frame_width; |
831 | /* Display frame height as configured by user */ |
832 | u16 display_frame_height; |
833 | u16 bds_aligned_frame_width; |
834 | /* Number of vectors to left-crop when writing stripes (not stripe 0) */ |
835 | u16 half_overlap_vectors; |
836 | /* Decimate ISP and fixed func resolutions after BDS (ir_extraction) */ |
837 | u16 ir_ext_decimation; |
838 | u8 padding1[2]; |
839 | } __packed; |
840 | |
841 | /* Input feeder related structs */ |
842 | |
843 | struct imgu_abi_input_feeder_data { |
844 | u32 row_stride; /* row stride */ |
845 | u32 start_row_address; /* start row address */ |
846 | u32 start_pixel; /* start pixel */ |
847 | } __packed; |
848 | |
849 | struct imgu_abi_input_feeder_data_aligned { |
850 | struct imgu_abi_input_feeder_data data __aligned(32); |
851 | } __packed; |
852 | |
853 | struct imgu_abi_input_feeder_data_per_stripe { |
854 | struct imgu_abi_input_feeder_data_aligned |
855 | input_feeder_data[IPU3_UAPI_MAX_STRIPES]; |
856 | } __packed; |
857 | |
858 | struct imgu_abi_input_feeder_config { |
859 | struct imgu_abi_input_feeder_data data; |
860 | struct imgu_abi_input_feeder_data_per_stripe data_per_stripe |
861 | __aligned(32); |
862 | } __packed; |
863 | |
864 | /* DVS related definitions */ |
865 | |
866 | struct imgu_abi_dvs_stat_grd_config { |
867 | u8 grid_width; |
868 | u8 grid_height; |
869 | u8 block_width; |
870 | u8 block_height; |
871 | u16 x_start; |
872 | u16 y_start; |
873 | u16 enable; |
874 | u16 x_end; |
875 | u16 y_end; |
876 | } __packed; |
877 | |
878 | struct imgu_abi_dvs_stat_cfg { |
879 | u8 reserved0[4]; |
880 | struct imgu_abi_dvs_stat_grd_config |
881 | grd_config[IMGU_ABI_DVS_STAT_LEVELS]; |
882 | u8 reserved1[18]; |
883 | } __packed; |
884 | |
885 | struct imgu_abi_dvs_stat_transfer_op_data { |
886 | u8 set_number; |
887 | } __packed; |
888 | |
889 | struct imgu_abi_dvs_stat_intra_frame_operations_data { |
890 | struct imgu_abi_acc_operation |
891 | ops[IMGU_ABI_DVS_STAT_MAX_OPERATIONS] __aligned(32); |
892 | struct imgu_abi_acc_process_lines_cmd_data |
893 | process_lines_data[IMGU_ABI_DVS_STAT_MAX_PROCESS_LINES] |
894 | __aligned(32); |
895 | struct imgu_abi_dvs_stat_transfer_op_data |
896 | transfer_data[IMGU_ABI_DVS_STAT_MAX_TRANSFERS] __aligned(32); |
897 | } __packed; |
898 | |
899 | struct imgu_abi_dvs_stat_config { |
900 | struct imgu_abi_dvs_stat_cfg cfg __aligned(32); |
901 | u8 reserved0[128]; |
902 | struct imgu_abi_dvs_stat_intra_frame_operations_data operations_data; |
903 | u8 reserved1[64]; |
904 | } __packed; |
905 | |
906 | /* Y-tone Mapping */ |
907 | |
908 | struct imgu_abi_yuvp2_y_tm_lut_static_config { |
909 | u16 entries[IMGU_ABI_YUVP2_YTM_LUT_ENTRIES]; |
910 | u32 enable; |
911 | } __packed; |
912 | |
913 | /* Output formatter related structs */ |
914 | |
915 | struct imgu_abi_osys_formatter_params { |
916 | u32 format; |
917 | u32 flip; |
918 | u32 mirror; |
919 | u32 tiling; |
920 | u32 reduce_range; |
921 | u32 alpha_blending; |
922 | u32 release_inp_addr; |
923 | u32 release_inp_en; |
924 | u32 process_out_buf_addr; |
925 | u32 image_width_vecs; |
926 | u32 image_height_lines; |
927 | u32 inp_buff_y_st_addr; |
928 | u32 inp_buff_y_line_stride; |
929 | u32 inp_buff_y_buffer_stride; |
930 | u32 int_buff_u_st_addr; |
931 | u32 int_buff_v_st_addr; |
932 | u32 inp_buff_uv_line_stride; |
933 | u32 inp_buff_uv_buffer_stride; |
934 | u32 out_buff_level; |
935 | u32 out_buff_nr_y_lines; |
936 | u32 out_buff_u_st_offset; |
937 | u32 out_buff_v_st_offset; |
938 | u32 out_buff_y_line_stride; |
939 | u32 out_buff_uv_line_stride; |
940 | u32 hist_buff_st_addr; |
941 | u32 hist_buff_line_stride; |
942 | u32 hist_buff_nr_lines; |
943 | } __packed; |
944 | |
945 | struct imgu_abi_osys_formatter { |
946 | struct imgu_abi_osys_formatter_params param __aligned(32); |
947 | } __packed; |
948 | |
949 | struct imgu_abi_osys_scaler_params { |
950 | u32 inp_buf_y_st_addr; |
951 | u32 inp_buf_y_line_stride; |
952 | u32 inp_buf_y_buffer_stride; |
953 | u32 inp_buf_u_st_addr; |
954 | u32 inp_buf_v_st_addr; |
955 | u32 inp_buf_uv_line_stride; |
956 | u32 inp_buf_uv_buffer_stride; |
957 | u32 inp_buf_chunk_width; |
958 | u32 inp_buf_nr_buffers; |
959 | /* Output buffers */ |
960 | u32 out_buf_y_st_addr; |
961 | u32 out_buf_y_line_stride; |
962 | u32 out_buf_y_buffer_stride; |
963 | u32 out_buf_u_st_addr; |
964 | u32 out_buf_v_st_addr; |
965 | u32 out_buf_uv_line_stride; |
966 | u32 out_buf_uv_buffer_stride; |
967 | u32 out_buf_nr_buffers; |
968 | /* Intermediate buffers */ |
969 | u32 int_buf_y_st_addr; |
970 | u32 int_buf_y_line_stride; |
971 | u32 int_buf_u_st_addr; |
972 | u32 int_buf_v_st_addr; |
973 | u32 int_buf_uv_line_stride; |
974 | u32 int_buf_height; |
975 | u32 int_buf_chunk_width; |
976 | u32 int_buf_chunk_height; |
977 | /* Context buffers */ |
978 | u32 ctx_buf_hor_y_st_addr; |
979 | u32 ctx_buf_hor_u_st_addr; |
980 | u32 ctx_buf_hor_v_st_addr; |
981 | u32 ctx_buf_ver_y_st_addr; |
982 | u32 ctx_buf_ver_u_st_addr; |
983 | u32 ctx_buf_ver_v_st_addr; |
984 | /* Addresses for release-input and process-output tokens */ |
985 | u32 release_inp_buf_addr; |
986 | u32 release_inp_buf_en; |
987 | u32 release_out_buf_en; |
988 | u32 process_out_buf_addr; |
989 | /* Settings dimensions, padding, cropping */ |
990 | u32 input_image_y_width; |
991 | u32 input_image_y_height; |
992 | u32 input_image_y_start_column; |
993 | u32 input_image_uv_start_column; |
994 | u32 input_image_y_left_pad; |
995 | u32 input_image_uv_left_pad; |
996 | u32 input_image_y_right_pad; |
997 | u32 input_image_uv_right_pad; |
998 | u32 input_image_y_top_pad; |
999 | u32 input_image_uv_top_pad; |
1000 | u32 input_image_y_bottom_pad; |
1001 | u32 input_image_uv_bottom_pad; |
1002 | u32 processing_mode; /* enum imgu_abi_osys_procmode */ |
1003 | u32 scaling_ratio; |
1004 | u32 y_left_phase_init; |
1005 | u32 uv_left_phase_init; |
1006 | u32 y_top_phase_init; |
1007 | u32 uv_top_phase_init; |
1008 | u32 coeffs_exp_shift; |
1009 | u32 out_y_left_crop; |
1010 | u32 out_uv_left_crop; |
1011 | u32 out_y_top_crop; |
1012 | u32 out_uv_top_crop; |
1013 | } __packed; |
1014 | |
1015 | struct imgu_abi_osys_scaler { |
1016 | struct imgu_abi_osys_scaler_params param __aligned(32); |
1017 | } __packed; |
1018 | |
1019 | struct imgu_abi_osys_frame_params { |
1020 | /* Output pins */ |
1021 | u32 enable; |
1022 | u32 format; /* enum imgu_abi_osys_format */ |
1023 | u32 flip; |
1024 | u32 mirror; |
1025 | u32 tiling; /* enum imgu_abi_osys_tiling */ |
1026 | u32 width; |
1027 | u32 height; |
1028 | u32 stride; |
1029 | u32 scaled; |
1030 | } __packed; |
1031 | |
1032 | struct imgu_abi_osys_frame { |
1033 | struct imgu_abi_osys_frame_params param __aligned(32); |
1034 | } __packed; |
1035 | |
1036 | struct imgu_abi_osys_stripe { |
1037 | /* Input resolution */ |
1038 | u32 input_width; |
1039 | u32 input_height; |
1040 | /* Output Stripe */ |
1041 | u32 output_width[IMGU_ABI_OSYS_PINS]; |
1042 | u32 output_height[IMGU_ABI_OSYS_PINS]; |
1043 | u32 output_offset[IMGU_ABI_OSYS_PINS]; |
1044 | u32 buf_stride[IMGU_ABI_OSYS_PINS]; |
1045 | /* Scaler params */ |
1046 | u32 block_width; |
1047 | u32 block_height; |
1048 | /* Output Crop factor */ |
1049 | u32 crop_top[IMGU_ABI_OSYS_PINS]; |
1050 | u32 crop_left[IMGU_ABI_OSYS_PINS]; |
1051 | } __packed; |
1052 | |
1053 | struct imgu_abi_osys_config { |
1054 | struct imgu_abi_osys_formatter |
1055 | formatter[IPU3_UAPI_MAX_STRIPES][IMGU_ABI_OSYS_PINS]; |
1056 | struct imgu_abi_osys_scaler scaler[IPU3_UAPI_MAX_STRIPES]; |
1057 | struct imgu_abi_osys_frame frame[IMGU_ABI_OSYS_PINS]; |
1058 | struct imgu_abi_osys_stripe stripe[IPU3_UAPI_MAX_STRIPES]; |
1059 | /* 32 packed coefficients for luma and chroma */ |
1060 | s8 scaler_coeffs_chroma[128]; |
1061 | s8 scaler_coeffs_luma[128]; |
1062 | } __packed; |
1063 | |
1064 | /* BDS */ |
1065 | |
1066 | struct imgu_abi_bds_hor_ctrl0 { |
1067 | u32 sample_patrn_length:9; |
1068 | u32 reserved0:3; |
1069 | u32 hor_ds_en:1; |
1070 | u32 min_clip_val:1; |
1071 | u32 max_clip_val:2; |
1072 | u32 out_frame_width:13; |
1073 | u32 reserved1:3; |
1074 | } __packed; |
1075 | |
1076 | struct imgu_abi_bds_ptrn_arr { |
1077 | u32 elems[IMGU_ABI_BDS_SAMPLE_PATTERN_ARRAY_SIZE]; |
1078 | } __packed; |
1079 | |
1080 | struct imgu_abi_bds_phase_entry { |
1081 | s8 coeff_min2; |
1082 | s8 coeff_min1; |
1083 | s8 coeff_0; |
1084 | s8 nf; |
1085 | s8 coeff_pls1; |
1086 | s8 coeff_pls2; |
1087 | s8 coeff_pls3; |
1088 | u8 reserved; |
1089 | } __packed; |
1090 | |
1091 | struct imgu_abi_bds_phase_arr { |
1092 | struct imgu_abi_bds_phase_entry |
1093 | even[IMGU_ABI_BDS_PHASE_COEFFS_ARRAY_SIZE]; |
1094 | struct imgu_abi_bds_phase_entry |
1095 | odd[IMGU_ABI_BDS_PHASE_COEFFS_ARRAY_SIZE]; |
1096 | } __packed; |
1097 | |
1098 | struct imgu_abi_bds_hor_ctrl1 { |
1099 | u32 hor_crop_start:13; |
1100 | u32 reserved0:3; |
1101 | u32 hor_crop_end:13; |
1102 | u32 reserved1:1; |
1103 | u32 hor_crop_en:1; |
1104 | u32 reserved2:1; |
1105 | } __packed; |
1106 | |
1107 | struct imgu_abi_bds_hor_ctrl2 { |
1108 | u32 input_frame_height:13; |
1109 | u32 reserved0:19; |
1110 | } __packed; |
1111 | |
1112 | struct imgu_abi_bds_hor { |
1113 | struct imgu_abi_bds_hor_ctrl0 hor_ctrl0; |
1114 | struct imgu_abi_bds_ptrn_arr hor_ptrn_arr; |
1115 | struct imgu_abi_bds_phase_arr hor_phase_arr; |
1116 | struct imgu_abi_bds_hor_ctrl1 hor_ctrl1; |
1117 | struct imgu_abi_bds_hor_ctrl2 hor_ctrl2; |
1118 | } __packed; |
1119 | |
1120 | struct imgu_abi_bds_ver_ctrl0 { |
1121 | u32 sample_patrn_length:9; |
1122 | u32 reserved0:3; |
1123 | u32 ver_ds_en:1; |
1124 | u32 min_clip_val:1; |
1125 | u32 max_clip_val:2; |
1126 | u32 reserved1:16; |
1127 | } __packed; |
1128 | |
1129 | struct imgu_abi_bds_ver_ctrl1 { |
1130 | u32 out_frame_width:13; |
1131 | u32 reserved0:3; |
1132 | u32 out_frame_height:13; |
1133 | u32 reserved1:3; |
1134 | } __packed; |
1135 | |
1136 | struct imgu_abi_bds_ver { |
1137 | struct imgu_abi_bds_ver_ctrl0 ver_ctrl0; |
1138 | struct imgu_abi_bds_ptrn_arr ver_ptrn_arr; |
1139 | struct imgu_abi_bds_phase_arr ver_phase_arr; |
1140 | struct imgu_abi_bds_ver_ctrl1 ver_ctrl1; |
1141 | } __packed; |
1142 | |
1143 | struct imgu_abi_bds_per_stripe_data { |
1144 | struct imgu_abi_bds_hor_ctrl0 hor_ctrl0; |
1145 | struct imgu_abi_bds_ver_ctrl1 ver_ctrl1; |
1146 | struct imgu_abi_bds_hor_ctrl1 crop; |
1147 | } __packed; |
1148 | |
1149 | struct imgu_abi_bds_per_stripe_data_aligned { |
1150 | struct imgu_abi_bds_per_stripe_data data __aligned(32); |
1151 | } __packed; |
1152 | |
1153 | struct imgu_abi_bds_per_stripe { |
1154 | struct imgu_abi_bds_per_stripe_data_aligned |
1155 | aligned_data[IPU3_UAPI_MAX_STRIPES]; |
1156 | } __packed; |
1157 | |
1158 | struct imgu_abi_bds_config { |
1159 | struct imgu_abi_bds_hor hor __aligned(32); |
1160 | struct imgu_abi_bds_ver ver __aligned(32); |
1161 | struct imgu_abi_bds_per_stripe per_stripe __aligned(32); |
1162 | u32 enabled; |
1163 | } __packed; |
1164 | |
1165 | /* ANR */ |
1166 | |
1167 | struct imgu_abi_anr_search_config { |
1168 | u32 enable; |
1169 | u16 frame_width; |
1170 | u16 frame_height; |
1171 | } __packed; |
1172 | |
1173 | struct imgu_abi_anr_stitch_config { |
1174 | u32 anr_stitch_en; |
1175 | u16 frame_width; |
1176 | u16 frame_height; |
1177 | u8 reserved[40]; |
1178 | struct ipu3_uapi_anr_stitch_pyramid pyramid[IPU3_UAPI_ANR_PYRAMID_SIZE]; |
1179 | } __packed; |
1180 | |
1181 | struct imgu_abi_anr_tile2strm_config { |
1182 | u32 enable; |
1183 | u16 frame_width; |
1184 | u16 frame_height; |
1185 | } __packed; |
1186 | |
1187 | struct imgu_abi_anr_config { |
1188 | struct imgu_abi_anr_search_config search __aligned(32); |
1189 | struct ipu3_uapi_anr_transform_config transform __aligned(32); |
1190 | struct imgu_abi_anr_stitch_config stitch __aligned(32); |
1191 | struct imgu_abi_anr_tile2strm_config tile2strm __aligned(32); |
1192 | } __packed; |
1193 | |
1194 | /* AF */ |
1195 | |
1196 | struct imgu_abi_af_frame_size { |
1197 | u16 width; |
1198 | u16 height; |
1199 | } __packed; |
1200 | |
1201 | struct imgu_abi_af_config_s { |
1202 | struct ipu3_uapi_af_filter_config filter_config __aligned(32); |
1203 | struct imgu_abi_af_frame_size frame_size; |
1204 | struct ipu3_uapi_grid_config grid_cfg __aligned(32); |
1205 | } __packed; |
1206 | |
1207 | struct imgu_abi_af_intra_frame_operations_data { |
1208 | struct imgu_abi_acc_operation ops[IMGU_ABI_AF_MAX_OPERATIONS] |
1209 | __aligned(32); |
1210 | struct imgu_abi_acc_process_lines_cmd_data |
1211 | process_lines_data[IMGU_ABI_AF_MAX_PROCESS_LINES] __aligned(32); |
1212 | } __packed; |
1213 | |
1214 | struct imgu_abi_af_stripe_config { |
1215 | struct imgu_abi_af_frame_size frame_size __aligned(32); |
1216 | struct ipu3_uapi_grid_config grid_cfg __aligned(32); |
1217 | } __packed; |
1218 | |
1219 | struct imgu_abi_af_config { |
1220 | struct imgu_abi_af_config_s config; |
1221 | struct imgu_abi_af_intra_frame_operations_data operations_data; |
1222 | struct imgu_abi_af_stripe_config stripes[IPU3_UAPI_MAX_STRIPES]; |
1223 | } __packed; |
1224 | |
1225 | /* AE */ |
1226 | |
1227 | struct imgu_abi_ae_config { |
1228 | struct ipu3_uapi_ae_grid_config grid_cfg __aligned(32); |
1229 | struct ipu3_uapi_ae_weight_elem weights[IPU3_UAPI_AE_WEIGHTS] |
1230 | __aligned(32); |
1231 | struct ipu3_uapi_ae_ccm ae_ccm __aligned(32); |
1232 | struct { |
1233 | struct ipu3_uapi_ae_grid_config grid __aligned(32); |
1234 | } stripes[IPU3_UAPI_MAX_STRIPES]; |
1235 | } __packed; |
1236 | |
1237 | /* AWB_FR */ |
1238 | |
1239 | struct imgu_abi_awb_fr_intra_frame_operations_data { |
1240 | struct imgu_abi_acc_operation ops[IMGU_ABI_AWB_FR_MAX_OPERATIONS] |
1241 | __aligned(32); |
1242 | struct imgu_abi_acc_process_lines_cmd_data |
1243 | process_lines_data[IMGU_ABI_AWB_FR_MAX_PROCESS_LINES] __aligned(32); |
1244 | } __packed; |
1245 | |
1246 | struct imgu_abi_awb_fr_config { |
1247 | struct ipu3_uapi_awb_fr_config_s config; |
1248 | struct imgu_abi_awb_fr_intra_frame_operations_data operations_data; |
1249 | struct ipu3_uapi_awb_fr_config_s stripes[IPU3_UAPI_MAX_STRIPES]; |
1250 | } __packed; |
1251 | |
1252 | struct imgu_abi_acc_transfer_op_data { |
1253 | u8 set_number; |
1254 | } __packed; |
1255 | |
1256 | struct imgu_abi_awb_intra_frame_operations_data { |
1257 | struct imgu_abi_acc_operation ops[IMGU_ABI_AWB_MAX_OPERATIONS] |
1258 | __aligned(32); |
1259 | struct imgu_abi_acc_process_lines_cmd_data |
1260 | process_lines_data[IMGU_ABI_AWB_MAX_PROCESS_LINES] __aligned(32); |
1261 | struct imgu_abi_acc_transfer_op_data |
1262 | transfer_data[IMGU_ABI_AWB_MAX_TRANSFERS] __aligned(32); |
1263 | } __aligned(32) __packed; |
1264 | |
1265 | struct imgu_abi_awb_config { |
1266 | struct ipu3_uapi_awb_config_s config __aligned(32); |
1267 | struct imgu_abi_awb_intra_frame_operations_data operations_data; |
1268 | struct ipu3_uapi_awb_config_s stripes[IPU3_UAPI_MAX_STRIPES]; |
1269 | } __packed; |
1270 | |
1271 | struct imgu_abi_acc_param { |
1272 | struct imgu_abi_stripe_data stripe; |
1273 | u8 padding[8]; |
1274 | struct imgu_abi_input_feeder_config input_feeder; |
1275 | struct ipu3_uapi_bnr_static_config bnr; |
1276 | struct ipu3_uapi_bnr_static_config_green_disparity green_disparity |
1277 | __aligned(32); |
1278 | struct ipu3_uapi_dm_config dm __aligned(32); |
1279 | struct ipu3_uapi_ccm_mat_config ccm __aligned(32); |
1280 | struct ipu3_uapi_gamma_config gamma __aligned(32); |
1281 | struct ipu3_uapi_csc_mat_config csc __aligned(32); |
1282 | struct ipu3_uapi_cds_params cds __aligned(32); |
1283 | struct imgu_abi_shd_config shd __aligned(32); |
1284 | struct imgu_abi_dvs_stat_config dvs_stat; |
1285 | u8 padding1[224]; /* reserved for lace_stat */ |
1286 | struct ipu3_uapi_yuvp1_iefd_config iefd __aligned(32); |
1287 | struct ipu3_uapi_yuvp1_yds_config yds_c0 __aligned(32); |
1288 | struct ipu3_uapi_yuvp1_chnr_config chnr_c0 __aligned(32); |
1289 | struct ipu3_uapi_yuvp1_y_ee_nr_config y_ee_nr __aligned(32); |
1290 | struct ipu3_uapi_yuvp1_yds_config yds __aligned(32); |
1291 | struct ipu3_uapi_yuvp1_chnr_config chnr __aligned(32); |
1292 | struct imgu_abi_yuvp2_y_tm_lut_static_config ytm __aligned(32); |
1293 | struct ipu3_uapi_yuvp1_yds_config yds2 __aligned(32); |
1294 | struct ipu3_uapi_yuvp2_tcc_static_config tcc __aligned(32); |
1295 | /* reserved for defect pixel correction */ |
1296 | u8 dpc[240832] __aligned(32); |
1297 | struct imgu_abi_bds_config bds; |
1298 | struct imgu_abi_anr_config anr; |
1299 | struct imgu_abi_awb_fr_config awb_fr; |
1300 | struct imgu_abi_ae_config ae; |
1301 | struct imgu_abi_af_config af; |
1302 | struct imgu_abi_awb_config awb; |
1303 | struct imgu_abi_osys_config osys; |
1304 | } __packed; |
1305 | |
1306 | /***** Morphing table entry *****/ |
1307 | |
1308 | struct imgu_abi_gdc_warp_param { |
1309 | u32 origin_x; |
1310 | u32 origin_y; |
1311 | u32 in_addr_offset; |
1312 | u32 in_block_width; |
1313 | u32 in_block_height; |
1314 | u32 p0_x; |
1315 | u32 p0_y; |
1316 | u32 p1_x; |
1317 | u32 p1_y; |
1318 | u32 p2_x; |
1319 | u32 p2_y; |
1320 | u32 p3_x; |
1321 | u32 p3_y; |
1322 | u32 in_block_width_a; |
1323 | u32 in_block_width_b; |
1324 | u32 padding; /* struct size multiple of DDR word */ |
1325 | } __packed; |
1326 | |
1327 | /******************* Firmware ABI definitions *******************/ |
1328 | |
1329 | /***** struct imgu_abi_sp_stage *****/ |
1330 | |
1331 | struct imgu_abi_crop_pos { |
1332 | u16 x; |
1333 | u16 y; |
1334 | } __packed; |
1335 | |
1336 | struct imgu_abi_sp_resolution { |
1337 | u16 width; /* Width of valid data in pixels */ |
1338 | u16 height; /* Height of valid data in lines */ |
1339 | } __packed; |
1340 | |
1341 | /* |
1342 | * Frame info struct. This describes the contents of an image frame buffer. |
1343 | */ |
1344 | struct imgu_abi_frame_sp_info { |
1345 | struct imgu_abi_sp_resolution res; |
1346 | u16 padded_width; /* stride of line in memory |
1347 | * (in pixels) |
1348 | */ |
1349 | u8 format; /* format of the frame data */ |
1350 | u8 raw_bit_depth; /* number of valid bits per pixel, |
1351 | * only valid for RAW bayer frames |
1352 | */ |
1353 | u8 raw_bayer_order; /* bayer order, only valid |
1354 | * for RAW bayer frames |
1355 | */ |
1356 | u8 raw_type; /* To choose the proper raw frame type. for |
1357 | * Legacy SKC pipes/Default is set to |
1358 | * IMGU_ABI_RAW_TYPE_BAYER. For RGB IR sensor - |
1359 | * driver should set it to: |
1360 | * IronGr case - IMGU_ABI_RAW_TYPE_IR_ON_GR |
1361 | * IronGb case - IMGU_ABI_RAW_TYPE_IR_ON_GB |
1362 | */ |
1363 | u8 padding[2]; /* Extend to 32 bit multiple */ |
1364 | } __packed; |
1365 | |
1366 | struct imgu_abi_buffer_sp { |
1367 | union { |
1368 | imgu_addr_t xmem_addr; |
1369 | s32 queue_id; /* enum imgu_abi_queue_id */ |
1370 | } buf_src; |
1371 | s32 buf_type; /* enum imgu_abi_buffer_type */ |
1372 | } __packed; |
1373 | |
1374 | struct imgu_abi_frame_sp_plane { |
1375 | u32 offset; /* offset in bytes to start of frame data */ |
1376 | /* offset is wrt data in imgu_abi_sp_sp_frame */ |
1377 | } __packed; |
1378 | |
1379 | struct imgu_abi_frame_sp_rgb_planes { |
1380 | struct imgu_abi_frame_sp_plane r; |
1381 | struct imgu_abi_frame_sp_plane g; |
1382 | struct imgu_abi_frame_sp_plane b; |
1383 | } __packed; |
1384 | |
1385 | struct imgu_abi_frame_sp_yuv_planes { |
1386 | struct imgu_abi_frame_sp_plane y; |
1387 | struct imgu_abi_frame_sp_plane u; |
1388 | struct imgu_abi_frame_sp_plane v; |
1389 | } __packed; |
1390 | |
1391 | struct imgu_abi_frame_sp_nv_planes { |
1392 | struct imgu_abi_frame_sp_plane y; |
1393 | struct imgu_abi_frame_sp_plane uv; |
1394 | } __packed; |
1395 | |
1396 | struct imgu_abi_frame_sp_plane6 { |
1397 | struct imgu_abi_frame_sp_plane r; |
1398 | struct imgu_abi_frame_sp_plane r_at_b; |
1399 | struct imgu_abi_frame_sp_plane gr; |
1400 | struct imgu_abi_frame_sp_plane gb; |
1401 | struct imgu_abi_frame_sp_plane b; |
1402 | struct imgu_abi_frame_sp_plane b_at_r; |
1403 | } __packed; |
1404 | |
1405 | struct imgu_abi_frame_sp_binary_plane { |
1406 | u32 size; |
1407 | struct imgu_abi_frame_sp_plane data; |
1408 | } __packed; |
1409 | |
1410 | struct imgu_abi_frame_sp { |
1411 | struct imgu_abi_frame_sp_info info; |
1412 | struct imgu_abi_buffer_sp buf_attr; |
1413 | union { |
1414 | struct imgu_abi_frame_sp_plane raw; |
1415 | struct imgu_abi_frame_sp_plane rgb; |
1416 | struct imgu_abi_frame_sp_rgb_planes planar_rgb; |
1417 | struct imgu_abi_frame_sp_plane yuyv; |
1418 | struct imgu_abi_frame_sp_yuv_planes yuv; |
1419 | struct imgu_abi_frame_sp_nv_planes nv; |
1420 | struct imgu_abi_frame_sp_plane6 plane6; |
1421 | struct imgu_abi_frame_sp_binary_plane binary; |
1422 | } planes; |
1423 | } __packed; |
1424 | |
1425 | struct imgu_abi_resolution { |
1426 | u32 width; |
1427 | u32 height; |
1428 | } __packed; |
1429 | |
1430 | struct imgu_abi_frames_sp { |
1431 | struct imgu_abi_frame_sp in; |
1432 | struct imgu_abi_frame_sp out[IMGU_ABI_BINARY_MAX_OUTPUT_PORTS]; |
1433 | struct imgu_abi_resolution effective_in_res; |
1434 | struct imgu_abi_frame_sp out_vf; |
1435 | struct imgu_abi_frame_sp_info internal_frame_info; |
1436 | struct imgu_abi_buffer_sp s3a_buf; |
1437 | struct imgu_abi_buffer_sp dvs_buf; |
1438 | struct imgu_abi_buffer_sp lace_buf; |
1439 | } __packed; |
1440 | |
1441 | struct imgu_abi_uds_info { |
1442 | u16 curr_dx; |
1443 | u16 curr_dy; |
1444 | u16 xc; |
1445 | u16 yc; |
1446 | } __packed; |
1447 | |
1448 | /* Information for a single pipeline stage */ |
1449 | struct imgu_abi_sp_stage { |
1450 | /* Multiple boolean flags can be stored in an integer */ |
1451 | u8 num; /* Stage number */ |
1452 | u8 isp_online; |
1453 | u8 isp_copy_vf; |
1454 | u8 isp_copy_output; |
1455 | u8 sp_enable_xnr; |
1456 | u8 isp_deci_log_factor; |
1457 | u8 isp_vf_downscale_bits; |
1458 | u8 deinterleaved; |
1459 | /* |
1460 | * NOTE: Programming the input circuit can only be done at the |
1461 | * start of a session. It is illegal to program it during execution |
1462 | * The input circuit defines the connectivity |
1463 | */ |
1464 | u8 program_input_circuit; |
1465 | u8 func; |
1466 | u8 stage_type; /* enum imgu_abi_stage_type */ |
1467 | u8 num_stripes; |
1468 | u8 isp_pipe_version; |
1469 | struct { |
1470 | u8 vf_output; |
1471 | u8 s3a; |
1472 | u8 sdis; |
1473 | u8 dvs_stats; |
1474 | u8 lace_stats; |
1475 | } enable; |
1476 | |
1477 | struct imgu_abi_crop_pos sp_out_crop_pos; |
1478 | u8 padding[2]; |
1479 | struct imgu_abi_frames_sp frames; |
1480 | struct imgu_abi_resolution dvs_envelope; |
1481 | struct imgu_abi_uds_info uds; |
1482 | imgu_addr_t isp_stage_addr; |
1483 | imgu_addr_t xmem_bin_addr; |
1484 | imgu_addr_t xmem_map_addr; |
1485 | |
1486 | u16 top_cropping; |
1487 | u16 row_stripes_height; |
1488 | u16 row_stripes_overlap_lines; |
1489 | u8 if_config_index; /* Which should be applied by this stage. */ |
1490 | u8 padding2; |
1491 | } __packed; |
1492 | |
1493 | /***** struct imgu_abi_isp_stage *****/ |
1494 | |
1495 | struct imgu_abi_isp_param_memory_offsets { |
1496 | u32 offsets[IMGU_ABI_PARAM_CLASS_NUM]; /* offset wrt hdr in bytes */ |
1497 | } __packed; |
1498 | |
1499 | /* |
1500 | * Blob descriptor. |
1501 | * This structure describes an SP or ISP blob. |
1502 | * It describes the test, data and bss sections as well as position in a |
1503 | * firmware file. |
1504 | * For convenience, it contains dynamic data after loading. |
1505 | */ |
1506 | struct imgu_abi_blob_info { |
1507 | /* Static blob data */ |
1508 | u32 offset; /* Blob offset in fw file */ |
1509 | struct imgu_abi_isp_param_memory_offsets memory_offsets; |
1510 | /* offset wrt hdr in bytes */ |
1511 | u32 prog_name_offset; /* offset wrt hdr in bytes */ |
1512 | u32 size; /* Size of blob */ |
1513 | u32 padding_size; /* total cumulative of bytes added |
1514 | * due to section alignment |
1515 | */ |
1516 | u32 icache_source; /* Position of icache in blob */ |
1517 | u32 icache_size; /* Size of icache section */ |
1518 | u32 icache_padding; /* added due to icache section alignment */ |
1519 | u32 text_source; /* Position of text in blob */ |
1520 | u32 text_size; /* Size of text section */ |
1521 | u32 text_padding; /* bytes added due to text section alignment */ |
1522 | u32 data_source; /* Position of data in blob */ |
1523 | u32 data_target; /* Start of data in SP dmem */ |
1524 | u32 data_size; /* Size of text section */ |
1525 | u32 data_padding; /* bytes added due to data section alignment */ |
1526 | u32 bss_target; /* Start position of bss in SP dmem */ |
1527 | u32 bss_size; /* Size of bss section |
1528 | * Dynamic data filled by loader |
1529 | */ |
1530 | u64 code __aligned(8); /* Code section absolute pointer */ |
1531 | /* within fw, code = icache + text */ |
1532 | u64 data __aligned(8); /* Data section absolute pointer */ |
1533 | /* within fw, data = data + bss */ |
1534 | } __packed; |
1535 | |
1536 | struct imgu_abi_binary_pipeline_info { |
1537 | u32 mode; |
1538 | u32 isp_pipe_version; |
1539 | u32 pipelining; |
1540 | u32 c_subsampling; |
1541 | u32 top_cropping; |
1542 | u32 left_cropping; |
1543 | u32 variable_resolution; |
1544 | } __packed; |
1545 | |
1546 | struct imgu_abi_binary_input_info { |
1547 | u32 min_width; |
1548 | u32 min_height; |
1549 | u32 max_width; |
1550 | u32 max_height; |
1551 | u32 source; /* enum imgu_abi_bin_input_src */ |
1552 | } __packed; |
1553 | |
1554 | struct imgu_abi_binary_output_info { |
1555 | u32 min_width; |
1556 | u32 min_height; |
1557 | u32 max_width; |
1558 | u32 max_height; |
1559 | u32 num_chunks; |
1560 | u32 variable_format; |
1561 | } __packed; |
1562 | |
1563 | struct imgu_abi_binary_internal_info { |
1564 | u32 max_width; |
1565 | u32 max_height; |
1566 | } __packed; |
1567 | |
1568 | struct imgu_abi_binary_bds_info { |
1569 | u32 supported_bds_factors; |
1570 | } __packed; |
1571 | |
1572 | struct imgu_abi_binary_dvs_info { |
1573 | u32 max_envelope_width; |
1574 | u32 max_envelope_height; |
1575 | } __packed; |
1576 | |
1577 | struct imgu_abi_binary_vf_dec_info { |
1578 | u32 is_variable; |
1579 | u32 max_log_downscale; |
1580 | } __packed; |
1581 | |
1582 | struct imgu_abi_binary_s3a_info { |
1583 | u32 s3atbl_use_dmem; |
1584 | u32 fixed_s3a_deci_log; |
1585 | } __packed; |
1586 | |
1587 | struct imgu_abi_binary_dpc_info { |
1588 | u32 bnr_lite; /* bnr lite enable flag */ |
1589 | } __packed; |
1590 | |
1591 | struct imgu_abi_binary_iterator_info { |
1592 | u32 num_stripes; |
1593 | u32 row_stripes_height; |
1594 | u32 row_stripes_overlap_lines; |
1595 | } __packed; |
1596 | |
1597 | struct imgu_abi_binary_address_info { |
1598 | u32 isp_addresses; /* Address in ISP dmem */ |
1599 | u32 main_entry; /* Address of entry fct */ |
1600 | u32 in_frame; /* Address in ISP dmem */ |
1601 | u32 out_frame; /* Address in ISP dmem */ |
1602 | u32 in_data; /* Address in ISP dmem */ |
1603 | u32 out_data; /* Address in ISP dmem */ |
1604 | u32 sh_dma_cmd_ptr; /* In ISP dmem */ |
1605 | } __packed; |
1606 | |
1607 | struct imgu_abi_binary_uds_info { |
1608 | u16 bpp; |
1609 | u16 use_bci; |
1610 | u16 use_str; |
1611 | u16 woix; |
1612 | u16 woiy; |
1613 | u16 ; |
1614 | u16 vectors_per_line_in; |
1615 | u16 vectors_per_line_out; |
1616 | u16 vectors_c_per_line_in; |
1617 | u16 vectors_c_per_line_out; |
1618 | u16 vmem_gdc_in_block_height_y; |
1619 | u16 vmem_gdc_in_block_height_c; |
1620 | } __packed; |
1621 | |
1622 | struct imgu_abi_binary_block_info { |
1623 | u32 block_width; |
1624 | u32 block_height; |
1625 | u32 output_block_height; |
1626 | } __packed; |
1627 | |
1628 | struct imgu_abi_isp_data { |
1629 | imgu_addr_t address; /* ISP address */ |
1630 | u32 size; /* Disabled if 0 */ |
1631 | } __packed; |
1632 | |
1633 | struct imgu_abi_isp_param_segments { |
1634 | struct imgu_abi_isp_data |
1635 | params[IMGU_ABI_PARAM_CLASS_NUM][IMGU_ABI_NUM_MEMORIES]; |
1636 | } __packed; |
1637 | |
1638 | struct imgu_abi_binary_info { |
1639 | u32 id __aligned(8); /* IMGU_ABI_BINARY_ID_* */ |
1640 | struct imgu_abi_binary_pipeline_info pipeline; |
1641 | struct imgu_abi_binary_input_info input; |
1642 | struct imgu_abi_binary_output_info output; |
1643 | struct imgu_abi_binary_internal_info internal; |
1644 | struct imgu_abi_binary_bds_info bds; |
1645 | struct imgu_abi_binary_dvs_info dvs; |
1646 | struct imgu_abi_binary_vf_dec_info vf_dec; |
1647 | struct imgu_abi_binary_s3a_info s3a; |
1648 | struct imgu_abi_binary_dpc_info dpc_bnr; /* DPC related binary info */ |
1649 | struct imgu_abi_binary_iterator_info iterator; |
1650 | struct imgu_abi_binary_address_info addresses; |
1651 | struct imgu_abi_binary_uds_info uds; |
1652 | struct imgu_abi_binary_block_info block; |
1653 | struct imgu_abi_isp_param_segments mem_initializers; |
1654 | struct { |
1655 | u8 input_feeder; |
1656 | u8 output_system; |
1657 | u8 obgrid; |
1658 | u8 lin; |
1659 | u8 dpc_acc; |
1660 | u8 bds_acc; |
1661 | u8 shd_acc; |
1662 | u8 shd_ff; |
1663 | u8 stats_3a_raw_buffer; |
1664 | u8 acc_bayer_denoise; |
1665 | u8 bnr_ff; |
1666 | u8 awb_acc; |
1667 | u8 awb_fr_acc; |
1668 | u8 anr_acc; |
1669 | u8 rgbpp_acc; |
1670 | u8 rgbpp_ff; |
1671 | u8 demosaic_acc; |
1672 | u8 demosaic_ff; |
1673 | u8 dvs_stats; |
1674 | u8 lace_stats; |
1675 | u8 yuvp1_b0_acc; |
1676 | u8 yuvp1_c0_acc; |
1677 | u8 yuvp2_acc; |
1678 | u8 ae; |
1679 | u8 af; |
1680 | u8 dergb; |
1681 | u8 rgb2yuv; |
1682 | u8 high_quality; |
1683 | u8 kerneltest; |
1684 | u8 routing_shd_to_bnr; /* connect SHD with BNR ACCs */ |
1685 | u8 routing_bnr_to_anr; /* connect BNR with ANR ACCs */ |
1686 | u8 routing_anr_to_de; /* connect ANR with DE ACCs */ |
1687 | u8 routing_rgb_to_yuvp1; /* connect RGB with YUVP1 */ |
1688 | u8 routing_yuvp1_to_yuvp2; /* connect YUVP1 with YUVP2 */ |
1689 | u8 luma_only; |
1690 | u8 input_yuv; |
1691 | u8 input_raw; |
1692 | u8 reduced_pipe; |
1693 | u8 vf_veceven; |
1694 | u8 dis; |
1695 | u8 dvs_envelope; |
1696 | u8 uds; |
1697 | u8 dvs_6axis; |
1698 | u8 block_output; |
1699 | u8 streaming_dma; |
1700 | u8 ds; |
1701 | u8 bayer_fir_6db; |
1702 | u8 raw_binning; |
1703 | u8 continuous; |
1704 | u8 s3a; |
1705 | u8 fpnr; |
1706 | u8 sc; |
1707 | u8 macc; |
1708 | u8 output; |
1709 | u8 ref_frame; |
1710 | u8 tnr; |
1711 | u8 xnr; |
1712 | u8 params; |
1713 | u8 ca_gdc; |
1714 | u8 isp_addresses; |
1715 | u8 in_frame; |
1716 | u8 out_frame; |
1717 | u8 high_speed; |
1718 | u8 dpc; |
1719 | u8 padding[2]; |
1720 | u8 rgbir; |
1721 | } enable; |
1722 | struct { |
1723 | u8 ref_y_channel; |
1724 | u8 ref_c_channel; |
1725 | u8 tnr_channel; |
1726 | u8 tnr_out_channel; |
1727 | u8 dvs_coords_channel; |
1728 | u8 output_channel; |
1729 | u8 c_channel; |
1730 | u8 vfout_channel; |
1731 | u8 vfout_c_channel; |
1732 | u8 vfdec_bits_per_pixel; |
1733 | u8 claimed_by_isp; |
1734 | u8 padding[2]; |
1735 | } dma; |
1736 | } __packed; |
1737 | |
1738 | struct imgu_abi_isp_stage { |
1739 | struct imgu_abi_blob_info blob_info; |
1740 | struct imgu_abi_binary_info binary_info; |
1741 | char binary_name[IMGU_ABI_MAX_BINARY_NAME]; |
1742 | struct imgu_abi_isp_param_segments mem_initializers; |
1743 | } __packed; |
1744 | |
1745 | /***** struct imgu_abi_ddr_address_map and parameter set *****/ |
1746 | |
1747 | /* xmem address map allocation */ |
1748 | struct imgu_abi_ddr_address_map { |
1749 | imgu_addr_t isp_mem_param[IMGU_ABI_MAX_STAGES][IMGU_ABI_NUM_MEMORIES]; |
1750 | imgu_addr_t obgrid_tbl[IPU3_UAPI_MAX_STRIPES]; |
1751 | imgu_addr_t acc_cluster_params_for_sp; |
1752 | imgu_addr_t dvs_6axis_params_y; |
1753 | } __packed; |
1754 | |
1755 | struct imgu_abi_parameter_set_info { |
1756 | /* Pointers to Parameters in ISP format IMPT */ |
1757 | struct imgu_abi_ddr_address_map mem_map; |
1758 | /* Unique ID to track per-frame configurations */ |
1759 | u32 isp_parameters_id; |
1760 | /* Output frame to which this config has to be applied (optional) */ |
1761 | imgu_addr_t output_frame_ptr; |
1762 | } __packed; |
1763 | |
1764 | /***** struct imgu_abi_sp_group *****/ |
1765 | |
1766 | /* SP configuration information */ |
1767 | struct imgu_abi_sp_config { |
1768 | u8 no_isp_sync; /* Signal host immediately after start */ |
1769 | u8 enable_raw_pool_locking; /* Enable Raw Buffer Locking for HALv3 */ |
1770 | u8 lock_all; |
1771 | u8 disable_cont_vf; |
1772 | u8 disable_preview_on_capture; |
1773 | u8 padding[3]; |
1774 | } __packed; |
1775 | |
1776 | /* Information for a pipeline */ |
1777 | struct imgu_abi_sp_pipeline { |
1778 | u32 pipe_id; /* the pipe ID */ |
1779 | u32 pipe_num; /* the dynamic pipe number */ |
1780 | u32 thread_id; /* the sp thread ID */ |
1781 | u32 pipe_config; /* the pipe config */ |
1782 | u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw |
1783 | * state, 0xffffffff indicates non |
1784 | * QOS pipe. |
1785 | */ |
1786 | u32 inout_port_config; |
1787 | u32 required_bds_factor; |
1788 | u32 dvs_frame_delay; |
1789 | u32 num_stages; /* the pipe config */ |
1790 | u32 running; /* needed for pipe termination */ |
1791 | imgu_addr_t sp_stage_addr[IMGU_ABI_MAX_STAGES]; |
1792 | imgu_addr_t scaler_pp_lut; /* Early bound LUT */ |
1793 | u32 stage; /* stage ptr is only used on sp */ |
1794 | s32 num_execs; /* number of times to run if this is |
1795 | * an acceleration pipe. |
1796 | */ |
1797 | union { |
1798 | struct { |
1799 | u32 bytes_available; |
1800 | } bin; |
1801 | struct { |
1802 | u32 height; |
1803 | u32 width; |
1804 | u32 padded_width; |
1805 | u32 max_input_width; |
1806 | u32 raw_bit_depth; |
1807 | } raw; |
1808 | } copy; |
1809 | |
1810 | /* Parameters passed to Shading Correction kernel. */ |
1811 | struct { |
1812 | /* Origin X (bqs) of internal frame on shading table */ |
1813 | u32 internal_frame_origin_x_bqs_on_sctbl; |
1814 | /* Origin Y (bqs) of internal frame on shading table */ |
1815 | u32 internal_frame_origin_y_bqs_on_sctbl; |
1816 | } shading; |
1817 | } __packed; |
1818 | |
1819 | struct imgu_abi_sp_debug_command { |
1820 | /* |
1821 | * The DMA software-mask, |
1822 | * Bit 31...24: unused. |
1823 | * Bit 23...16: unused. |
1824 | * Bit 15...08: reading-request enabling bits for DMA channel 7..0 |
1825 | * Bit 07...00: writing-request enabling bits for DMA channel 7..0 |
1826 | * |
1827 | * For example, "0...0 0...0 11111011 11111101" indicates that the |
1828 | * writing request through DMA Channel 1 and the reading request |
1829 | * through DMA channel 2 are both disabled. The others are enabled. |
1830 | */ |
1831 | u32 dma_sw_reg; |
1832 | } __packed; |
1833 | |
1834 | /* |
1835 | * Group all host initialized SP variables into this struct. |
1836 | * This is initialized every stage through dma. |
1837 | * The stage part itself is transferred through imgu_abi_sp_stage. |
1838 | */ |
1839 | struct imgu_abi_sp_group { |
1840 | struct imgu_abi_sp_config config; |
1841 | struct imgu_abi_sp_pipeline pipe[IMGU_ABI_MAX_SP_THREADS]; |
1842 | struct imgu_abi_sp_debug_command debug; |
1843 | } __packed; |
1844 | |
1845 | /***** parameter and state class binary configurations *****/ |
1846 | |
1847 | struct imgu_abi_isp_iterator_config { |
1848 | struct imgu_abi_frame_sp_info input_info; |
1849 | struct imgu_abi_frame_sp_info internal_info; |
1850 | struct imgu_abi_frame_sp_info output_info; |
1851 | struct imgu_abi_frame_sp_info vf_info; |
1852 | struct imgu_abi_sp_resolution dvs_envelope; |
1853 | } __packed; |
1854 | |
1855 | struct imgu_abi_dma_port_config { |
1856 | u8 crop, elems; |
1857 | u16 width; |
1858 | u32 stride; |
1859 | } __packed; |
1860 | |
1861 | struct imgu_abi_isp_ref_config { |
1862 | u32 width_a_over_b; |
1863 | struct imgu_abi_dma_port_config port_b; |
1864 | u32 ref_frame_addr_y[IMGU_ABI_FRAMES_REF]; |
1865 | u32 ref_frame_addr_c[IMGU_ABI_FRAMES_REF]; |
1866 | u32 dvs_frame_delay; |
1867 | } __packed; |
1868 | |
1869 | struct imgu_abi_isp_ref_dmem_state { |
1870 | u32 ref_in_buf_idx; |
1871 | u32 ref_out_buf_idx; |
1872 | } __packed; |
1873 | |
1874 | struct imgu_abi_isp_dvs_config { |
1875 | u32 num_horizontal_blocks; |
1876 | u32 num_vertical_blocks; |
1877 | } __packed; |
1878 | |
1879 | struct imgu_abi_isp_tnr3_config { |
1880 | u32 width_a_over_b; |
1881 | u32 frame_height; |
1882 | struct imgu_abi_dma_port_config port_b; |
1883 | u32 delay_frame; |
1884 | u32 frame_addr[IMGU_ABI_FRAMES_TNR]; |
1885 | } __packed; |
1886 | |
1887 | struct imgu_abi_isp_tnr3_dmem_state { |
1888 | u32 in_bufidx; |
1889 | u32 out_bufidx; |
1890 | u32 total_frame_counter; |
1891 | u32 buffer_frame_counter[IMGU_ABI_BUF_SETS_TNR]; |
1892 | u32 bypass_filter; |
1893 | } __packed; |
1894 | |
1895 | /***** Queues *****/ |
1896 | |
1897 | struct imgu_abi_queue_info { |
1898 | u8 size; /* the maximum number of elements*/ |
1899 | u8 step; /* number of bytes per element */ |
1900 | u8 start; /* index of the oldest element */ |
1901 | u8 end; /* index at which to write the new element */ |
1902 | } __packed; |
1903 | |
1904 | struct imgu_abi_queues { |
1905 | /* |
1906 | * Queues for the dynamic frame information, |
1907 | * i.e. the "in_frame" buffer, the "out_frame" |
1908 | * buffer and the "vf_out_frame" buffer. |
1909 | */ |
1910 | struct imgu_abi_queue_info host2sp_bufq_info |
1911 | [IMGU_ABI_MAX_SP_THREADS][IMGU_ABI_QUEUE_NUM]; |
1912 | u32 host2sp_bufq[IMGU_ABI_MAX_SP_THREADS][IMGU_ABI_QUEUE_NUM] |
1913 | [IMGU_ABI_HOST2SP_BUFQ_SIZE]; |
1914 | struct imgu_abi_queue_info sp2host_bufq_info[IMGU_ABI_QUEUE_NUM]; |
1915 | u32 sp2host_bufq[IMGU_ABI_QUEUE_NUM][IMGU_ABI_SP2HOST_BUFQ_SIZE]; |
1916 | |
1917 | /* |
1918 | * The queues for the events. |
1919 | */ |
1920 | struct imgu_abi_queue_info host2sp_evtq_info; |
1921 | u32 host2sp_evtq[IMGU_ABI_HOST2SP_EVTQ_SIZE]; |
1922 | struct imgu_abi_queue_info sp2host_evtq_info; |
1923 | u32 sp2host_evtq[IMGU_ABI_SP2HOST_EVTQ_SIZE]; |
1924 | } __packed; |
1925 | |
1926 | /***** Buffer descriptor *****/ |
1927 | |
1928 | struct imgu_abi_metadata_info { |
1929 | struct imgu_abi_resolution resolution; /* Resolution */ |
1930 | u32 stride; /* Stride in bytes */ |
1931 | u32 size; /* Total size in bytes */ |
1932 | } __packed; |
1933 | |
1934 | struct imgu_abi_isp_3a_statistics { |
1935 | union { |
1936 | struct { |
1937 | imgu_addr_t s3a_tbl; |
1938 | } dmem; |
1939 | struct { |
1940 | imgu_addr_t s3a_tbl_hi; |
1941 | imgu_addr_t s3a_tbl_lo; |
1942 | } vmem; |
1943 | } data; |
1944 | struct { |
1945 | imgu_addr_t rgby_tbl; |
1946 | } data_hmem; |
1947 | u32 exp_id; /* exposure id, to match statistics to a frame, */ |
1948 | u32 isp_config_id; /* Tracks per-frame configs */ |
1949 | imgu_addr_t data_ptr; /* pointer to base of all data */ |
1950 | u32 size; /* total size of all data */ |
1951 | u32 dmem_size; |
1952 | u32 vmem_size; /* both lo and hi have this size */ |
1953 | u32 hmem_size; |
1954 | } __packed; |
1955 | |
1956 | struct imgu_abi_metadata { |
1957 | struct imgu_abi_metadata_info info; /* Layout info */ |
1958 | imgu_addr_t address; /* CSS virtual address */ |
1959 | u32 exp_id; /* Exposure ID */ |
1960 | } __packed; |
1961 | |
1962 | struct imgu_abi_time_meas { |
1963 | u32 start_timer_value; /* measured time in ticks */ |
1964 | u32 end_timer_value; /* measured time in ticks */ |
1965 | } __packed; |
1966 | |
1967 | struct imgu_abi_buffer { |
1968 | union { |
1969 | struct imgu_abi_isp_3a_statistics s3a; |
1970 | u8 reserved[28]; |
1971 | imgu_addr_t skc_dvs_statistics; |
1972 | imgu_addr_t lace_stat; |
1973 | struct imgu_abi_metadata metadata; |
1974 | struct { |
1975 | imgu_addr_t frame_data; |
1976 | u32 flashed; |
1977 | u32 exp_id; |
1978 | u32 isp_parameters_id; /* Tracks per-frame configs */ |
1979 | u32 padded_width; |
1980 | } frame; |
1981 | imgu_addr_t ddr_ptrs; |
1982 | } payload; |
1983 | /* |
1984 | * kernel_ptr is present for host administration purposes only. |
1985 | * type is uint64_t in order to be 64-bit host compatible. |
1986 | * uint64_t does not exist on SP/ISP. |
1987 | * Size of the struct is checked by sp.hive.c. |
1988 | */ |
1989 | u64 cookie_ptr __aligned(8); |
1990 | u64 kernel_ptr; |
1991 | struct imgu_abi_time_meas timing_data; |
1992 | u32 isys_eof_clock_tick; |
1993 | } __packed; |
1994 | |
1995 | struct imgu_abi_bl_dma_cmd_entry { |
1996 | u32 src_addr; /* virtual DDR address */ |
1997 | u32 size; /* number of bytes to transferred */ |
1998 | u32 dst_type; |
1999 | u32 dst_addr; /* hmm address of xMEM or MMIO */ |
2000 | } __packed; |
2001 | |
2002 | struct imgu_abi_sp_init_dmem_cfg { |
2003 | u32 ddr_data_addr; /* data segment address in ddr */ |
2004 | u32 dmem_data_addr; /* data segment address in dmem */ |
2005 | u32 dmem_bss_addr; /* bss segment address in dmem */ |
2006 | u32 data_size; /* data segment size */ |
2007 | u32 bss_size; /* bss segment size */ |
2008 | u32 sp_id; /* sp id */ |
2009 | } __packed; |
2010 | |
2011 | #endif |
2012 | |