1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (C) 2018 Intel Corporation */ |
3 | |
4 | #ifndef __IPU3_UTIL_H |
5 | #define __IPU3_UTIL_H |
6 | |
7 | struct device; |
8 | struct imgu_device; |
9 | |
10 | #define IPU3_CSS_POOL_SIZE 4 |
11 | |
12 | /** |
13 | * struct imgu_css_map - store DMA mapping info for buffer |
14 | * |
15 | * @size: size of the buffer in bytes. |
16 | * @vaddr: kernel virtual address. |
17 | * @daddr: iova dma address to access IPU3. |
18 | * @pages: pages mapped to this buffer |
19 | */ |
20 | struct imgu_css_map { |
21 | size_t size; |
22 | void *vaddr; |
23 | dma_addr_t daddr; |
24 | struct page **pages; |
25 | }; |
26 | |
27 | /** |
28 | * struct imgu_css_pool - circular buffer pool definition |
29 | * |
30 | * @entry: array with IPU3_CSS_POOL_SIZE elements. |
31 | * @entry.param: a &struct imgu_css_map for storing the mem mapping. |
32 | * @entry.valid: used to mark if the entry has valid data. |
33 | * @last: write pointer, initialized to IPU3_CSS_POOL_SIZE. |
34 | */ |
35 | struct imgu_css_pool { |
36 | struct { |
37 | struct imgu_css_map param; |
38 | bool valid; |
39 | } entry[IPU3_CSS_POOL_SIZE]; |
40 | u32 last; |
41 | }; |
42 | |
43 | int imgu_css_dma_buffer_resize(struct imgu_device *imgu, |
44 | struct imgu_css_map *map, size_t size); |
45 | void imgu_css_pool_cleanup(struct imgu_device *imgu, |
46 | struct imgu_css_pool *pool); |
47 | int imgu_css_pool_init(struct imgu_device *imgu, struct imgu_css_pool *pool, |
48 | size_t size); |
49 | void imgu_css_pool_get(struct imgu_css_pool *pool); |
50 | void imgu_css_pool_put(struct imgu_css_pool *pool); |
51 | const struct imgu_css_map *imgu_css_pool_last(struct imgu_css_pool *pool, |
52 | u32 last); |
53 | |
54 | #endif |
55 | |