| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * register description for HopeRf rf69 radio module |
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| 4 | * |
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| 5 | * Copyright (C) 2016 Wolf-Entwicklungen |
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| 6 | * Marcus Wolf <linux@wolf-entwicklungen.de> |
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| 7 | */ |
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| 8 | |
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| 9 | /*******************************************/ |
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| 10 | /* RF69 register addresses */ |
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| 11 | /*******************************************/ |
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| 12 | #define REG_FIFO 0x00 |
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| 13 | #define REG_OPMODE 0x01 |
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| 14 | #define REG_DATAMODUL 0x02 |
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| 15 | #define REG_BITRATE_MSB 0x03 |
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| 16 | #define REG_BITRATE_LSB 0x04 |
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| 17 | #define REG_FDEV_MSB 0x05 |
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| 18 | #define REG_FDEV_LSB 0x06 |
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| 19 | #define REG_FRF_MSB 0x07 |
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| 20 | #define REG_FRF_MID 0x08 |
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| 21 | #define REG_FRF_LSB 0x09 |
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| 22 | #define REG_OSC1 0x0A |
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| 23 | #define REG_AFCCTRL 0x0B |
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| 24 | #define REG_LOWBAT 0x0C |
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| 25 | #define REG_LISTEN1 0x0D |
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| 26 | #define REG_LISTEN2 0x0E |
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| 27 | #define REG_LISTEN3 0x0F |
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| 28 | #define REG_VERSION 0x10 |
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| 29 | #define REG_PALEVEL 0x11 |
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| 30 | #define REG_PARAMP 0x12 |
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| 31 | #define REG_OCP 0x13 |
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| 32 | #define REG_AGCREF 0x14 /* not available on RF69 */ |
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| 33 | #define REG_AGCTHRESH1 0x15 /* not available on RF69 */ |
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| 34 | #define REG_AGCTHRESH2 0x16 /* not available on RF69 */ |
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| 35 | #define REG_AGCTHRESH3 0x17 /* not available on RF69 */ |
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| 36 | #define REG_LNA 0x18 |
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| 37 | #define REG_RXBW 0x19 |
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| 38 | #define REG_AFCBW 0x1A |
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| 39 | #define REG_OOKPEAK 0x1B |
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| 40 | #define REG_OOKAVG 0x1C |
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| 41 | #define REG_OOKFIX 0x1D |
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| 42 | #define REG_AFCFEI 0x1E |
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| 43 | #define REG_AFCMSB 0x1F |
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| 44 | #define REG_AFCLSB 0x20 |
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| 45 | #define REG_FEIMSB 0x21 |
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| 46 | #define REG_FEILSB 0x22 |
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| 47 | #define 0x23 |
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| 48 | #define 0x24 |
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| 49 | #define REG_DIOMAPPING1 0x25 |
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| 50 | #define REG_DIOMAPPING2 0x26 |
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| 51 | #define REG_IRQFLAGS1 0x27 |
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| 52 | #define REG_IRQFLAGS2 0x28 |
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| 53 | #define 0x29 |
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| 54 | #define REG_RXTIMEOUT1 0x2A |
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| 55 | #define REG_RXTIMEOUT2 0x2B |
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| 56 | #define REG_PREAMBLE_MSB 0x2C |
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| 57 | #define REG_PREAMBLE_LSB 0x2D |
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| 58 | #define REG_SYNC_CONFIG 0x2E |
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| 59 | #define REG_SYNCVALUE1 0x2F |
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| 60 | #define REG_SYNCVALUE2 0x30 |
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| 61 | #define REG_SYNCVALUE3 0x31 |
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| 62 | #define REG_SYNCVALUE4 0x32 |
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| 63 | #define REG_SYNCVALUE5 0x33 |
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| 64 | #define REG_SYNCVALUE6 0x34 |
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| 65 | #define REG_SYNCVALUE7 0x35 |
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| 66 | #define REG_SYNCVALUE8 0x36 |
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| 67 | #define REG_PACKETCONFIG1 0x37 |
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| 68 | #define REG_PAYLOAD_LENGTH 0x38 |
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| 69 | #define REG_NODEADRS 0x39 |
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| 70 | #define REG_BROADCASTADRS 0x3A |
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| 71 | #define REG_AUTOMODES 0x3B |
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| 72 | #define REG_FIFO_THRESH 0x3C |
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| 73 | #define REG_PACKETCONFIG2 0x3D |
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| 74 | #define REG_AESKEY1 0x3E |
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| 75 | #define REG_AESKEY2 0x3F |
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| 76 | #define REG_AESKEY3 0x40 |
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| 77 | #define REG_AESKEY4 0x41 |
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| 78 | #define REG_AESKEY5 0x42 |
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| 79 | #define REG_AESKEY6 0x43 |
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| 80 | #define REG_AESKEY7 0x44 |
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| 81 | #define REG_AESKEY8 0x45 |
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| 82 | #define REG_AESKEY9 0x46 |
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| 83 | #define REG_AESKEY10 0x47 |
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| 84 | #define REG_AESKEY11 0x48 |
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| 85 | #define REG_AESKEY12 0x49 |
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| 86 | #define REG_AESKEY13 0x4A |
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| 87 | #define REG_AESKEY14 0x4B |
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| 88 | #define REG_AESKEY15 0x4C |
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| 89 | #define REG_AESKEY16 0x4D |
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| 90 | #define REG_TEMP1 0x4E |
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| 91 | #define REG_TEMP2 0x4F |
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| 92 | #define REG_TESTLNA 0x58 |
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| 93 | #define REG_TESTPA1 0x5A /* only present on RFM69HW */ |
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| 94 | #define REG_TESTPA2 0x5C /* only present on RFM69HW */ |
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| 95 | #define REG_TESTDAGC 0x6F |
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| 96 | #define REG_TESTAFC 0x71 |
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| 97 | |
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| 98 | /******************************************************/ |
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| 99 | /* RF69/SX1231 bit definition */ |
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| 100 | /******************************************************/ |
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| 101 | /* write bit */ |
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| 102 | #define WRITE_BIT 0x80 |
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| 103 | |
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| 104 | /* RegOpMode */ |
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| 105 | #define MASK_OPMODE_SEQUENCER_OFF 0x80 |
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| 106 | #define MASK_OPMODE_LISTEN_ON 0x40 |
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| 107 | #define MASK_OPMODE_LISTEN_ABORT 0x20 |
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| 108 | #define MASK_OPMODE_MODE 0x1C |
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| 109 | |
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| 110 | #define OPMODE_MODE_SLEEP 0x00 |
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| 111 | #define OPMODE_MODE_STANDBY 0x04 /* default */ |
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| 112 | #define OPMODE_MODE_SYNTHESIZER 0x08 |
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| 113 | #define OPMODE_MODE_TRANSMIT 0x0C |
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| 114 | #define OPMODE_MODE_RECEIVE 0x10 |
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| 115 | |
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| 116 | /* RegDataModul */ |
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| 117 | #define MASK_DATAMODUL_MODE 0x06 |
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| 118 | #define MASK_DATAMODUL_MODULATION_TYPE 0x18 |
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| 119 | #define MASK_DATAMODUL_MODULATION_SHAPE 0x03 |
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| 120 | |
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| 121 | #define DATAMODUL_MODE_PACKET 0x00 /* default */ |
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| 122 | #define DATAMODUL_MODE_CONTINUOUS 0x40 |
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| 123 | #define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60 |
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| 124 | |
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| 125 | #define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */ |
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| 126 | #define DATAMODUL_MODULATION_TYPE_OOK 0x08 |
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| 127 | |
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| 128 | #define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */ |
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| 129 | #define DATAMODUL_MODULATION_SHAPE_1_0 0x01 |
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| 130 | #define DATAMODUL_MODULATION_SHAPE_0_5 0x02 |
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| 131 | #define DATAMODUL_MODULATION_SHAPE_0_3 0x03 |
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| 132 | #define DATAMODUL_MODULATION_SHAPE_BR 0x01 |
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| 133 | #define DATAMODUL_MODULATION_SHAPE_2BR 0x02 |
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| 134 | |
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| 135 | /* RegFDevMsb (0x05)*/ |
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| 136 | #define FDEVMASB_MASK 0x3f |
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| 137 | |
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| 138 | /* |
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| 139 | * // RegOsc1 |
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| 140 | * #define OSC1_RCCAL_START 0x80 |
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| 141 | * #define OSC1_RCCAL_DONE 0x40 |
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| 142 | * |
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| 143 | * // RegLowBat |
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| 144 | * #define LOWBAT_MONITOR 0x10 |
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| 145 | * #define LOWBAT_ON 0x08 |
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| 146 | * #define LOWBAT_OFF 0x00 // Default |
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| 147 | * |
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| 148 | * #define LOWBAT_TRIM_1695 0x00 |
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| 149 | * #define LOWBAT_TRIM_1764 0x01 |
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| 150 | * #define LOWBAT_TRIM_1835 0x02 // Default |
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| 151 | * #define LOWBAT_TRIM_1905 0x03 |
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| 152 | * #define LOWBAT_TRIM_1976 0x04 |
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| 153 | * #define LOWBAT_TRIM_2045 0x05 |
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| 154 | * #define LOWBAT_TRIM_2116 0x06 |
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| 155 | * #define LOWBAT_TRIM_2185 0x07 |
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| 156 | * |
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| 157 | * |
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| 158 | * // RegListen1 |
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| 159 | * #define LISTEN1_RESOL_64 0x50 |
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| 160 | * #define LISTEN1_RESOL_4100 0xA0 // Default |
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| 161 | * #define LISTEN1_RESOL_262000 0xF0 |
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| 162 | * |
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| 163 | * #define LISTEN1_CRITERIA_RSSI 0x00 // Default |
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| 164 | * #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08 |
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| 165 | * |
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| 166 | * #define LISTEN1_END_00 0x00 |
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| 167 | * #define LISTEN1_END_01 0x02 // Default |
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| 168 | * #define LISTEN1_END_10 0x04 |
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| 169 | * |
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| 170 | * |
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| 171 | * // RegListen2 |
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| 172 | * #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default |
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| 173 | * |
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| 174 | * // RegListen3 |
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| 175 | * #define LISTEN3_COEFRX_VALUE 0x20 // Default |
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| 176 | */ |
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| 177 | |
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| 178 | // RegPaLevel |
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| 179 | #define MASK_PALEVEL_PA0 0x80 |
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| 180 | #define MASK_PALEVEL_PA1 0x40 |
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| 181 | #define MASK_PALEVEL_PA2 0x20 |
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| 182 | #define MASK_PALEVEL_OUTPUT_POWER 0x1F |
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| 183 | |
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| 184 | // RegPaRamp |
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| 185 | #define PARAMP_3400 0x00 |
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| 186 | #define PARAMP_2000 0x01 |
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| 187 | #define PARAMP_1000 0x02 |
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| 188 | #define PARAMP_500 0x03 |
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| 189 | #define PARAMP_250 0x04 |
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| 190 | #define PARAMP_125 0x05 |
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| 191 | #define PARAMP_100 0x06 |
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| 192 | #define PARAMP_62 0x07 |
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| 193 | #define PARAMP_50 0x08 |
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| 194 | #define PARAMP_40 0x09 /* default */ |
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| 195 | #define PARAMP_31 0x0A |
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| 196 | #define PARAMP_25 0x0B |
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| 197 | #define PARAMP_20 0x0C |
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| 198 | #define PARAMP_15 0x0D |
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| 199 | #define PARAMP_12 0x0E |
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| 200 | #define PARAMP_10 0x0F |
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| 201 | |
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| 202 | #define MASK_PARAMP 0x0F |
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| 203 | |
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| 204 | /* |
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| 205 | * // RegOcp |
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| 206 | * #define OCP_OFF 0x0F |
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| 207 | * #define OCP_ON 0x1A // Default |
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| 208 | * |
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| 209 | * #define OCP_TRIM_45 0x00 |
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| 210 | * #define OCP_TRIM_50 0x01 |
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| 211 | * #define OCP_TRIM_55 0x02 |
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| 212 | * #define OCP_TRIM_60 0x03 |
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| 213 | * #define OCP_TRIM_65 0x04 |
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| 214 | * #define OCP_TRIM_70 0x05 |
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| 215 | * #define OCP_TRIM_75 0x06 |
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| 216 | * #define OCP_TRIM_80 0x07 |
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| 217 | * #define OCP_TRIM_85 0x08 |
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| 218 | * #define OCP_TRIM_90 0x09 |
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| 219 | * #define OCP_TRIM_95 0x0A |
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| 220 | * #define OCP_TRIM_100 0x0B // Default |
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| 221 | * #define OCP_TRIM_105 0x0C |
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| 222 | * #define OCP_TRIM_110 0x0D |
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| 223 | * #define OCP_TRIM_115 0x0E |
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| 224 | * #define OCP_TRIM_120 0x0F |
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| 225 | */ |
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| 226 | |
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| 227 | /* RegLna (0x18) */ |
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| 228 | #define MASK_LNA_ZIN 0x80 |
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| 229 | #define MASK_LNA_CURRENT_GAIN 0x38 |
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| 230 | #define MASK_LNA_GAIN 0x07 |
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| 231 | |
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| 232 | #define LNA_GAIN_AUTO 0x00 /* default */ |
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| 233 | #define LNA_GAIN_MAX 0x01 |
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| 234 | #define LNA_GAIN_MAX_MINUS_6 0x02 |
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| 235 | #define LNA_GAIN_MAX_MINUS_12 0x03 |
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| 236 | #define LNA_GAIN_MAX_MINUS_24 0x04 |
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| 237 | #define LNA_GAIN_MAX_MINUS_36 0x05 |
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| 238 | #define LNA_GAIN_MAX_MINUS_48 0x06 |
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| 239 | |
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| 240 | /* RegRxBw (0x19) and RegAfcBw (0x1A) */ |
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| 241 | #define MASK_BW_DCC_FREQ 0xE0 |
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| 242 | #define MASK_BW_MANTISSE 0x18 |
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| 243 | #define MASK_BW_EXPONENT 0x07 |
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| 244 | |
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| 245 | #define BW_DCC_16_PERCENT 0x00 |
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| 246 | #define BW_DCC_8_PERCENT 0x20 |
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| 247 | #define BW_DCC_4_PERCENT 0x40 /* default */ |
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| 248 | #define BW_DCC_2_PERCENT 0x60 |
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| 249 | #define BW_DCC_1_PERCENT 0x80 |
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| 250 | #define BW_DCC_0_5_PERCENT 0xA0 |
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| 251 | #define BW_DCC_0_25_PERCENT 0xC0 |
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| 252 | #define BW_DCC_0_125_PERCENT 0xE0 |
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| 253 | |
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| 254 | #define BW_MANT_16 0x00 |
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| 255 | #define BW_MANT_20 0x08 |
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| 256 | #define BW_MANT_24 0x10 /* default */ |
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| 257 | |
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| 258 | /* RegOokPeak (0x1B) */ |
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| 259 | #define MASK_OOKPEAK_THRESTYPE 0xc0 |
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| 260 | #define MASK_OOKPEAK_THRESSTEP 0x38 |
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| 261 | #define MASK_OOKPEAK_THRESDEC 0x07 |
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| 262 | |
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| 263 | #define OOKPEAK_THRESHTYPE_FIXED 0x00 |
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| 264 | #define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */ |
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| 265 | #define OOKPEAK_THRESHTYPE_AVERAGE 0x80 |
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| 266 | |
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| 267 | #define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */ |
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| 268 | #define OOKPEAK_THRESHSTEP_1_0_DB 0x08 |
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| 269 | #define OOKPEAK_THRESHSTEP_1_5_DB 0x10 |
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| 270 | #define OOKPEAK_THRESHSTEP_2_0_DB 0x18 |
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| 271 | #define OOKPEAK_THRESHSTEP_3_0_DB 0x20 |
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| 272 | #define OOKPEAK_THRESHSTEP_4_0_DB 0x28 |
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| 273 | #define OOKPEAK_THRESHSTEP_5_0_DB 0x30 |
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| 274 | #define OOKPEAK_THRESHSTEP_6_0_DB 0x38 |
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| 275 | |
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| 276 | #define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */ |
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| 277 | #define OOKPEAK_THRESHDEC_EVERY_2ND 0x01 |
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| 278 | #define OOKPEAK_THRESHDEC_EVERY_4TH 0x02 |
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| 279 | #define OOKPEAK_THRESHDEC_EVERY_8TH 0x03 |
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| 280 | #define OOKPEAK_THRESHDEC_TWICE 0x04 |
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| 281 | #define OOKPEAK_THRESHDEC_4_TIMES 0x05 |
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| 282 | #define OOKPEAK_THRESHDEC_8_TIMES 0x06 |
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| 283 | #define OOKPEAK_THRESHDEC_16_TIMES 0x07 |
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| 284 | |
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| 285 | /* |
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| 286 | * // RegOokAvg |
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| 287 | * #define OOKAVG_AVERAGETHRESHFILT_00 0x00 |
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| 288 | * #define OOKAVG_AVERAGETHRESHFILT_01 0x40 |
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| 289 | * #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default |
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| 290 | * #define OOKAVG_AVERAGETHRESHFILT_11 0xC0 |
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| 291 | * |
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| 292 | * |
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| 293 | * // RegAfcFei |
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| 294 | * #define AFCFEI_FEI_DONE 0x40 |
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| 295 | * #define AFCFEI_FEI_START 0x20 |
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| 296 | * #define AFCFEI_AFC_DONE 0x10 |
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| 297 | * #define AFCFEI_AFCAUTOCLEAR_ON 0x08 |
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| 298 | * #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default |
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| 299 | * |
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| 300 | * #define AFCFEI_AFCAUTO_ON 0x04 |
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| 301 | * #define AFCFEI_AFCAUTO_OFF 0x00 // Default |
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| 302 | * |
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| 303 | * #define AFCFEI_AFC_CLEAR 0x02 |
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| 304 | * #define AFCFEI_AFC_START 0x01 |
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| 305 | * |
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| 306 | * // RegRssiConfig |
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| 307 | * #define RSSI_FASTRX_ON 0x08 |
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| 308 | * #define RSSI_FASTRX_OFF 0x00 // Default |
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| 309 | * #define RSSI_DONE 0x02 |
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| 310 | * #define RSSI_START 0x01 |
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| 311 | */ |
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| 312 | |
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| 313 | /* RegDioMapping1 */ |
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| 314 | #define MASK_DIO0 0xC0 |
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| 315 | #define MASK_DIO1 0x30 |
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| 316 | #define MASK_DIO2 0x0C |
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| 317 | #define MASK_DIO3 0x03 |
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| 318 | #define SHIFT_DIO0 6 |
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| 319 | #define SHIFT_DIO1 4 |
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| 320 | #define SHIFT_DIO2 2 |
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| 321 | #define SHIFT_DIO3 0 |
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| 322 | |
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| 323 | /* RegDioMapping2 */ |
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| 324 | #define MASK_DIO4 0xC0 |
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| 325 | #define MASK_DIO5 0x30 |
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| 326 | #define SHIFT_DIO4 6 |
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| 327 | #define SHIFT_DIO5 4 |
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| 328 | |
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| 329 | /* DIO numbers */ |
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| 330 | #define DIO0 0 |
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| 331 | #define DIO1 1 |
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| 332 | #define DIO2 2 |
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| 333 | #define DIO3 3 |
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| 334 | #define DIO4 4 |
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| 335 | #define DIO5 5 |
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| 336 | |
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| 337 | /* DIO Mapping values (packet mode) */ |
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| 338 | #define DIO_MODE_READY_DIO4 0x00 |
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| 339 | #define DIO_MODE_READY_DIO5 0x03 |
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| 340 | #define DIO_CLK_OUT 0x00 |
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| 341 | #define DIO_DATA 0x01 |
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| 342 | #define DIO_TIMEOUT_DIO1 0x03 |
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| 343 | #define DIO_TIMEOUT_DIO4 0x00 |
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| 344 | #define 0x03 |
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| 345 | #define 0x01 |
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| 346 | #define DIO_RX_READY 0x02 |
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| 347 | #define DIO_PLL_LOCK 0x03 |
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| 348 | #define DIO_TX_READY 0x01 |
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| 349 | #define DIO_FIFO_FULL_DIO1 0x01 |
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| 350 | #define DIO_FIFO_FULL_DIO3 0x00 |
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| 351 | #define DIO_SYNC_ADDRESS 0x02 |
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| 352 | #define DIO_FIFO_NOT_EMPTY_DIO1 0x02 |
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| 353 | #define DIO_FIFO_NOT_EMPTY_FIO2 0x00 |
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| 354 | #define DIO_AUTOMODE 0x04 |
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| 355 | #define DIO_FIFO_LEVEL 0x00 |
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| 356 | #define DIO_CRC_OK 0x00 |
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| 357 | #define DIO_PAYLOAD_READY 0x01 |
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| 358 | #define DIO_PACKET_SENT 0x00 |
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| 359 | #define DIO_DCLK 0x00 |
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| 360 | |
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| 361 | /* RegDioMapping2 CLK_OUT part */ |
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| 362 | #define MASK_DIOMAPPING2_CLK_OUT 0x07 |
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| 363 | |
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| 364 | #define DIOMAPPING2_CLK_OUT_NO_DIV 0x00 |
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| 365 | #define DIOMAPPING2_CLK_OUT_DIV_2 0x01 |
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| 366 | #define DIOMAPPING2_CLK_OUT_DIV_4 0x02 |
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| 367 | #define DIOMAPPING2_CLK_OUT_DIV_8 0x03 |
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| 368 | #define DIOMAPPING2_CLK_OUT_DIV_16 0x04 |
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| 369 | #define DIOMAPPING2_CLK_OUT_DIV_32 0x05 |
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| 370 | #define DIOMAPPING2_CLK_OUT_RC 0x06 |
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| 371 | #define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */ |
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| 372 | |
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| 373 | /* RegIrqFlags1 */ |
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| 374 | #define MASK_IRQFLAGS1_MODE_READY 0x80 |
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| 375 | #define MASK_IRQFLAGS1_RX_READY 0x40 |
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| 376 | #define MASK_IRQFLAGS1_TX_READY 0x20 |
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| 377 | #define MASK_IRQFLAGS1_PLL_LOCK 0x10 |
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| 378 | #define 0x08 |
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| 379 | #define MASK_IRQFLAGS1_TIMEOUT 0x04 |
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| 380 | #define MASK_IRQFLAGS1_AUTOMODE 0x02 |
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| 381 | #define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01 |
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| 382 | |
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| 383 | /* RegIrqFlags2 */ |
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| 384 | #define MASK_IRQFLAGS2_FIFO_FULL 0x80 |
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| 385 | #define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40 |
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| 386 | #define MASK_IRQFLAGS2_FIFO_LEVEL 0x20 |
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| 387 | #define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10 |
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| 388 | #define MASK_IRQFLAGS2_PACKET_SENT 0x08 |
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| 389 | #define MASK_IRQFLAGS2_PAYLOAD_READY 0x04 |
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| 390 | #define MASK_IRQFLAGS2_CRC_OK 0x02 |
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| 391 | #define MASK_IRQFLAGS2_LOW_BAT 0x01 |
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| 392 | |
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| 393 | /* RegSyncConfig */ |
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| 394 | #define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */ |
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| 395 | #define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40 |
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| 396 | #define MASK_SYNC_CONFIG_SYNC_SIZE 0x38 |
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| 397 | #define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07 |
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| 398 | |
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| 399 | /* RegPacketConfig1 */ |
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| 400 | #define MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE 0x80 |
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| 401 | #define MASK_PACKETCONFIG1_DCFREE 0x60 |
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| 402 | #define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */ |
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| 403 | #define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 |
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| 404 | #define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06 |
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| 405 | |
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| 406 | #define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */ |
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| 407 | #define PACKETCONFIG1_DCFREE_MANCHESTER 0x20 |
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| 408 | #define PACKETCONFIG1_DCFREE_WHITENING 0x40 |
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| 409 | #define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */ |
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| 410 | #define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02 |
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| 411 | #define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04 |
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| 412 | |
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| 413 | /* |
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| 414 | * // RegAutoModes |
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| 415 | * #define AUTOMODES_ENTER_OFF 0x00 // Default |
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| 416 | * #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20 |
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| 417 | * #define AUTOMODES_ENTER_FIFOLEVEL 0x40 |
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| 418 | * #define AUTOMODES_ENTER_CRCOK 0x60 |
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| 419 | * #define AUTOMODES_ENTER_PAYLOADREADY 0x80 |
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| 420 | * #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0 |
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| 421 | * #define AUTOMODES_ENTER_PACKETSENT 0xC0 |
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| 422 | * #define AUTOMODES_ENTER_FIFOEMPTY 0xE0 |
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| 423 | * |
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| 424 | * #define AUTOMODES_EXIT_OFF 0x00 // Default |
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| 425 | * #define AUTOMODES_EXIT_FIFOEMPTY 0x04 |
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| 426 | * #define AUTOMODES_EXIT_FIFOLEVEL 0x08 |
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| 427 | * #define AUTOMODES_EXIT_CRCOK 0x0C |
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| 428 | * #define AUTOMODES_EXIT_PAYLOADREADY 0x10 |
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| 429 | * #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14 |
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| 430 | * #define AUTOMODES_EXIT_PACKETSENT 0x18 |
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| 431 | * #define AUTOMODES_EXIT_RXTIMEOUT 0x1C |
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| 432 | * |
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| 433 | * #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default |
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| 434 | * #define AUTOMODES_INTERMEDIATE_STANDBY 0x01 |
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| 435 | * #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02 |
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| 436 | * #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03 |
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| 437 | * |
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| 438 | */ |
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| 439 | /* RegFifoThresh (0x3c) */ |
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| 440 | #define MASK_FIFO_THRESH_TXSTART 0x80 |
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| 441 | #define MASK_FIFO_THRESH_VALUE 0x7F |
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| 442 | |
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| 443 | /* |
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| 444 | * |
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| 445 | * // RegPacketConfig2 |
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| 446 | * #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default |
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| 447 | * #define PACKET2_RXRESTARTDELAY_2BITS 0x10 |
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| 448 | * #define PACKET2_RXRESTARTDELAY_4BITS 0x20 |
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| 449 | * #define PACKET2_RXRESTARTDELAY_8BITS 0x30 |
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| 450 | * #define PACKET2_RXRESTARTDELAY_16BITS 0x40 |
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| 451 | * #define PACKET2_RXRESTARTDELAY_32BITS 0x50 |
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| 452 | * #define PACKET2_RXRESTARTDELAY_64BITS 0x60 |
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| 453 | * #define PACKET2_RXRESTARTDELAY_128BITS 0x70 |
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| 454 | * #define PACKET2_RXRESTARTDELAY_256BITS 0x80 |
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| 455 | * #define PACKET2_RXRESTARTDELAY_512BITS 0x90 |
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| 456 | * #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0 |
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| 457 | * #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0 |
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| 458 | * #define PACKET2_RXRESTARTDELAY_NONE 0xC0 |
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| 459 | * #define PACKET2_RXRESTART 0x04 |
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| 460 | * |
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| 461 | * #define PACKET2_AUTORXRESTART_ON 0x02 // Default |
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| 462 | * #define PACKET2_AUTORXRESTART_OFF 0x00 |
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| 463 | * |
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| 464 | * #define PACKET2_AES_ON 0x01 |
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| 465 | * #define PACKET2_AES_OFF 0x00 // Default |
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| 466 | * |
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| 467 | * |
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| 468 | * // RegTemp1 |
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| 469 | * #define TEMP1_MEAS_START 0x08 |
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| 470 | * #define TEMP1_MEAS_RUNNING 0x04 |
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| 471 | * #define TEMP1_ADCLOWPOWER_ON 0x01 // Default |
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| 472 | * #define TEMP1_ADCLOWPOWER_OFF 0x00 |
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| 473 | */ |
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| 474 | |
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| 475 | // RegTestDagc (0x6F) |
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| 476 | #define DAGC_NORMAL 0x00 /* Reset value */ |
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| 477 | #define DAGC_IMPROVED_LOWBETA1 0x20 |
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| 478 | #define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */ |
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| 479 | |
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