1/* SPDX-License-Identifier: GPL-2.0 */
2/******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7/*****************************************************************************
8 *
9 * Module: __INC_HAL8192CPHYREG_H
10 *
11 *
12 * Note: 1. Define PMAC/BB register map
13 * 2. Define RF register map
14 * 3. PMAC/BB register bit mask.
15 * 4. RF reg bit mask.
16 * 5. Other BB/RF relative definition.
17 *
18 *
19 * Export: Constants, macro, functions(API), global variables(None).
20 *
21 * Abbrev:
22 *
23 * History:
24 * Data Who Remark
25 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
26 * 2. Reorganize code architecture.
27 *09/25/2008 MH 1. Add RL6052 register definition
28 *
29 *****************************************************************************/
30#ifndef __INC_HAL8192CPHYREG_H
31#define __INC_HAL8192CPHYREG_H
32
33
34/*--------------------------Define Parameters-------------------------------*/
35
36/* */
37/* 8192S Register offset definition */
38/* */
39
40/* */
41/* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
42/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
43/* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44/* 3. RF register 0x00-2E */
45/* 4. Bit Mask for BB/RF register */
46/* 5. Other definition for BB/RF R/W */
47/* */
48
49
50/* */
51/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
52/* 1. Page1(0x100) */
53/* */
54#define rPMAC_Reset 0x100
55#define rPMAC_TxStart 0x104
56#define rPMAC_TxLegacySIG 0x108
57#define rPMAC_TxHTSIG1 0x10c
58#define rPMAC_TxHTSIG2 0x110
59#define rPMAC_PHYDebug 0x114
60#define rPMAC_TxPacketNum 0x118
61#define rPMAC_TxIdle 0x11c
62#define rPMAC_TxMACHeader0 0x120
63#define rPMAC_TxMACHeader1 0x124
64#define rPMAC_TxMACHeader2 0x128
65#define rPMAC_TxMACHeader3 0x12c
66#define rPMAC_TxMACHeader4 0x130
67#define rPMAC_TxMACHeader5 0x134
68#define rPMAC_TxDataType 0x138
69#define rPMAC_TxRandomSeed 0x13c
70#define rPMAC_CCKPLCPPreamble 0x140
71#define rPMAC_CCKPLCPHeader 0x144
72#define rPMAC_CCKCRC16 0x148
73#define rPMAC_OFDMRxCRC32OK 0x170
74#define rPMAC_OFDMRxCRC32Er 0x174
75#define rPMAC_OFDMRxParityEr 0x178
76#define rPMAC_OFDMRxCRC8Er 0x17c
77#define rPMAC_CCKCRxRC16Er 0x180
78#define rPMAC_CCKCRxRC32Er 0x184
79#define rPMAC_CCKCRxRC32OK 0x188
80#define rPMAC_TxStatus 0x18c
81
82/* */
83/* 2. Page2(0x200) */
84/* */
85/* The following two definition are only used for USB interface. */
86#define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */
87#define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */
88
89/* */
90/* 3. Page8(0x800) */
91/* */
92#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */
93
94#define rFPGA0_TxInfo 0x804 /* Status report?? */
95#define rFPGA0_PSDFunction 0x808
96
97#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
98
99#define rFPGA0_RFTiming1 0x810 /* Useless now */
100#define rFPGA0_RFTiming2 0x814
101
102#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
103#define rFPGA0_XA_HSSIParameter2 0x824
104#define rFPGA0_XB_HSSIParameter1 0x828
105#define rFPGA0_XB_HSSIParameter2 0x82c
106#define rTxAGC_B_Rate18_06 0x830
107#define rTxAGC_B_Rate54_24 0x834
108#define rTxAGC_B_CCK1_55_Mcs32 0x838
109#define rTxAGC_B_Mcs03_Mcs00 0x83c
110
111#define rTxAGC_B_Mcs07_Mcs04 0x848
112
113#define rFPGA0_XA_LSSIParameter 0x840
114#define rFPGA0_XB_LSSIParameter 0x844
115
116#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
117#define rFPGA0_RFSleepUpParameter 0x854
118
119#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
120#define rFPGA0_XCD_SwitchControl 0x85c
121
122#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
123#define rFPGA0_XB_RFInterfaceOE 0x864
124
125#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
126
127#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
128#define rFPGA0_XCD_RFInterfaceSW 0x874
129
130#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
131#define rFPGA0_XCD_RFParameter 0x87c
132
133#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
134#define rFPGA0_AnalogParameter2 0x884
135#define rFPGA0_AnalogParameter3 0x888 /* Useless now */
136#define rFPGA0_AnalogParameter4 0x88c
137
138#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Transceiver LSSI Readback */
139#define rFPGA0_XB_LSSIReadBack 0x8a4
140#define rFPGA0_XC_LSSIReadBack 0x8a8
141#define rFPGA0_XD_LSSIReadBack 0x8ac
142
143#define rFPGA0_PSDReport 0x8b4 /* Useless now */
144#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
145#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
146#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */
147#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
148
149/* */
150/* 4. Page9(0x900) */
151/* */
152#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */
153
154#define rFPGA1_TxBlock 0x904 /* Useless now */
155#define rFPGA1_DebugSelect 0x908 /* Useless now */
156#define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */
157#define rS0S1_PathSwitch 0x948
158
159/* */
160/* 5. PageA(0xA00) */
161/* */
162/* Set Control channel to upper or lower. These settings are required only for 40MHz */
163#define rCCK0_System 0xa00
164
165#define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */
166#define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */
167
168#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
169#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
170
171#define rCCK0_RxHP 0xa14
172
173#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */
174#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
175
176#define rCCK0_TxFilter1 0xa20
177#define rCCK0_TxFilter2 0xa24
178#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
179#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
180#define rCCK0_TRSSIReport 0xa50
181#define rCCK0_RxReport 0xa54 /* 0xa57 */
182#define rCCK0_FACounterLower 0xa5c /* 0xa5b */
183#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
184/* */
185/* PageB(0xB00) */
186/* */
187#define rPdp_AntA 0xb00
188#define rPdp_AntA_4 0xb04
189#define rConfig_Pmpd_AntA 0xb28
190#define rConfig_AntA 0xb68
191#define rConfig_AntB 0xb6c
192#define rPdp_AntB 0xb70
193#define rPdp_AntB_4 0xb74
194#define rConfig_Pmpd_AntB 0xb98
195#define rAPK 0xbd8
196
197/* */
198/* 6. PageC(0xC00) */
199/* */
200#define rOFDM0_LSTF 0xc00
201
202#define rOFDM0_TRxPathEnable 0xc04
203#define rOFDM0_TRMuxPar 0xc08
204#define rOFDM0_TRSWIsolation 0xc0c
205
206#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
207#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */
208#define rOFDM0_XBRxAFE 0xc18
209#define rOFDM0_XBRxIQImbalance 0xc1c
210#define rOFDM0_XCRxAFE 0xc20
211#define rOFDM0_XCRxIQImbalance 0xc24
212#define rOFDM0_XDRxAFE 0xc28
213#define rOFDM0_XDRxIQImbalance 0xc2c
214
215#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD DM tune init gain */
216#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
217#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
218#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
219
220#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
221#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
222#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
223#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
224
225#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
226#define rOFDM0_XAAGCCore2 0xc54
227#define rOFDM0_XBAGCCore1 0xc58
228#define rOFDM0_XBAGCCore2 0xc5c
229#define rOFDM0_XCAGCCore1 0xc60
230#define rOFDM0_XCAGCCore2 0xc64
231#define rOFDM0_XDAGCCore1 0xc68
232#define rOFDM0_XDAGCCore2 0xc6c
233
234#define rOFDM0_AGCParameter1 0xc70
235#define rOFDM0_AGCParameter2 0xc74
236#define rOFDM0_AGCRSSITable 0xc78
237#define rOFDM0_HTSTFAGC 0xc7c
238
239#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
240#define rOFDM0_XATxAFE 0xc84
241#define rOFDM0_XBTxIQImbalance 0xc88
242#define rOFDM0_XBTxAFE 0xc8c
243#define rOFDM0_XCTxIQImbalance 0xc90
244#define rOFDM0_XCTxAFE 0xc94
245#define rOFDM0_XDTxIQImbalance 0xc98
246#define rOFDM0_XDTxAFE 0xc9c
247
248#define rOFDM0_RxIQExtAnta 0xca0
249#define rOFDM0_TxCoeff1 0xca4
250#define rOFDM0_TxCoeff2 0xca8
251#define rOFDM0_TxCoeff3 0xcac
252#define rOFDM0_TxCoeff4 0xcb0
253#define rOFDM0_TxCoeff5 0xcb4
254#define rOFDM0_TxCoeff6 0xcb8
255#define rOFDM0_RxHPParameter 0xce0
256#define rOFDM0_TxPseudoNoiseWgt 0xce4
257#define rOFDM0_FrameSync 0xcf0
258#define rOFDM0_DFSReport 0xcf4
259
260/* */
261/* 7. PageD(0xD00) */
262/* */
263#define rOFDM1_LSTF 0xd00
264#define rOFDM1_TRxPathEnable 0xd04
265
266#define rOFDM1_CFO 0xd08 /* No setting now */
267#define rOFDM1_CSI1 0xd10
268#define rOFDM1_SBD 0xd14
269#define rOFDM1_CSI2 0xd18
270#define rOFDM1_CFOTracking 0xd2c
271#define rOFDM1_TRxMesaure1 0xd34
272#define rOFDM1_IntfDet 0xd3c
273#define rOFDM1_PseudoNoiseStateAB 0xd50
274#define rOFDM1_PseudoNoiseStateCD 0xd54
275#define rOFDM1_RxPseudoNoiseWgt 0xd58
276
277#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
278#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
279#define rOFDM_PHYCounter3 0xda8 /* MCS not support */
280
281#define rOFDM_ShortCFOAB 0xdac /* No setting now */
282#define rOFDM_ShortCFOCD 0xdb0
283#define rOFDM_LongCFOAB 0xdb4
284#define rOFDM_LongCFOCD 0xdb8
285#define rOFDM_TailCFOAB 0xdbc
286#define rOFDM_TailCFOCD 0xdc0
287#define rOFDM_PWMeasure1 0xdc4
288#define rOFDM_PWMeasure2 0xdc8
289#define rOFDM_BWReport 0xdcc
290#define rOFDM_AGCReport 0xdd0
291#define rOFDM_RxSNR 0xdd4
292#define rOFDM_RxEVMCSI 0xdd8
293#define rOFDM_SIGReport 0xddc
294
295
296/* */
297/* 8. PageE(0xE00) */
298/* */
299#define rTxAGC_A_Rate18_06 0xe00
300#define rTxAGC_A_Rate54_24 0xe04
301#define rTxAGC_A_CCK1_Mcs32 0xe08
302#define rTxAGC_A_Mcs03_Mcs00 0xe10
303#define rTxAGC_A_Mcs07_Mcs04 0xe14
304
305#define rFPGA0_IQK 0xe28
306#define rTx_IQK_Tone_A 0xe30
307#define rRx_IQK_Tone_A 0xe34
308#define rTx_IQK_PI_A 0xe38
309#define rRx_IQK_PI_A 0xe3c
310
311#define rTx_IQK 0xe40
312#define rRx_IQK 0xe44
313#define rIQK_AGC_Pts 0xe48
314#define rIQK_AGC_Rsp 0xe4c
315#define rTx_IQK_Tone_B 0xe50
316#define rRx_IQK_Tone_B 0xe54
317#define rTx_IQK_PI_B 0xe58
318#define rRx_IQK_PI_B 0xe5c
319#define rIQK_AGC_Cont 0xe60
320
321#define rBlue_Tooth 0xe6c
322#define rRx_Wait_CCA 0xe70
323#define rTx_CCK_RFON 0xe74
324#define rTx_CCK_BBON 0xe78
325#define rTx_OFDM_RFON 0xe7c
326#define rTx_OFDM_BBON 0xe80
327#define rTx_To_Rx 0xe84
328#define rTx_To_Tx 0xe88
329#define rRx_CCK 0xe8c
330
331#define rTx_Power_Before_IQK_A 0xe94
332#define rTx_Power_After_IQK_A 0xe9c
333
334#define rRx_Power_Before_IQK_A 0xea0
335#define rRx_Power_Before_IQK_A_2 0xea4
336#define rRx_Power_After_IQK_A 0xea8
337#define rRx_Power_After_IQK_A_2 0xeac
338
339#define rTx_Power_Before_IQK_B 0xeb4
340#define rTx_Power_After_IQK_B 0xebc
341
342#define rRx_Power_Before_IQK_B 0xec0
343#define rRx_Power_Before_IQK_B_2 0xec4
344#define rRx_Power_After_IQK_B 0xec8
345#define rRx_Power_After_IQK_B_2 0xecc
346
347#define rRx_OFDM 0xed0
348#define rRx_Wait_RIFS 0xed4
349#define rRx_TO_Rx 0xed8
350#define rStandby 0xedc
351#define rSleep 0xee0
352#define rPMPD_ANAEN 0xeec
353
354/* */
355/* 7. RF Register 0x00-0x2E (RF 8256) */
356/* RF-0222D 0x00-3F */
357/* */
358/* Zebra1 */
359#define rZebra1_HSSIEnable 0x0 /* Useless now */
360#define rZebra1_TRxEnable1 0x1
361#define rZebra1_TRxEnable2 0x2
362#define rZebra1_AGC 0x4
363#define rZebra1_ChargePump 0x5
364#define rZebra1_Channel 0x7 /* RF channel switch */
365
366/* endif */
367#define rZebra1_TxGain 0x8 /* Useless now */
368#define rZebra1_TxLPF 0x9
369#define rZebra1_RxLPF 0xb
370#define rZebra1_RxHPFCorner 0xc
371
372/* Zebra4 */
373#define rGlobalCtrl 0 /* Useless now */
374#define rRTL8256_TxLPF 19
375#define rRTL8256_RxLPF 11
376
377/* RTL8258 */
378#define rRTL8258_TxLPF 0x11 /* Useless now */
379#define rRTL8258_RxLPF 0x13
380#define rRTL8258_RSSILPF 0xa
381
382/* */
383/* RL6052 Register definition */
384/* */
385#define RF_AC 0x00 /* */
386
387#define RF_IQADJ_G1 0x01 /* */
388#define RF_IQADJ_G2 0x02 /* */
389#define RF_BS_PA_APSET_G1_G4 0x03
390#define RF_BS_PA_APSET_G5_G8 0x04
391#define RF_POW_TRSW 0x05 /* */
392
393#define RF_GAIN_RX 0x06 /* */
394#define RF_GAIN_TX 0x07 /* */
395
396#define RF_TXM_IDAC 0x08 /* */
397#define RF_IPA_G 0x09 /* */
398#define RF_TXBIAS_G 0x0A
399#define RF_TXPA_AG 0x0B
400#define RF_IPA_A 0x0C /* */
401#define RF_TXBIAS_A 0x0D
402#define RF_BS_PA_APSET_G9_G11 0x0E
403#define RF_BS_IQGEN 0x0F /* */
404
405#define RF_MODE1 0x10 /* */
406#define RF_MODE2 0x11 /* */
407
408#define RF_RX_AGC_HP 0x12 /* */
409#define RF_TX_AGC 0x13 /* */
410#define RF_BIAS 0x14 /* */
411#define RF_IPA 0x15 /* */
412#define RF_TXBIAS 0x16 /* */
413#define RF_POW_ABILITY 0x17 /* */
414#define RF_MODE_AG 0x18 /* */
415#define rRfChannel 0x18 /* RF channel and BW switch */
416#define RF_CHNLBW 0x18 /* RF channel and BW switch */
417#define RF_TOP 0x19 /* */
418
419#define RF_RX_G1 0x1A /* */
420#define RF_RX_G2 0x1B /* */
421
422#define RF_RX_BB2 0x1C /* */
423#define RF_RX_BB1 0x1D /* */
424
425#define RF_RCK1 0x1E /* */
426#define RF_RCK2 0x1F /* */
427
428#define RF_TX_G1 0x20 /* */
429#define RF_TX_G2 0x21 /* */
430#define RF_TX_G3 0x22 /* */
431
432#define RF_TX_BB1 0x23 /* */
433
434#define RF_T_METER 0x24 /* */
435
436#define RF_SYN_G1 0x25 /* RF TX Power control */
437#define RF_SYN_G2 0x26 /* RF TX Power control */
438#define RF_SYN_G3 0x27 /* RF TX Power control */
439#define RF_SYN_G4 0x28 /* RF TX Power control */
440#define RF_SYN_G5 0x29 /* RF TX Power control */
441#define RF_SYN_G6 0x2A /* RF TX Power control */
442#define RF_SYN_G7 0x2B /* RF TX Power control */
443#define RF_SYN_G8 0x2C /* RF TX Power control */
444
445#define RF_RCK_OS 0x30 /* RF TX PA control */
446
447#define RF_TXPA_G1 0x31 /* RF TX PA control */
448#define RF_TXPA_G2 0x32 /* RF TX PA control */
449#define RF_TXPA_G3 0x33 /* RF TX PA control */
450#define RF_TX_BIAS_A 0x35
451#define RF_TX_BIAS_D 0x36
452#define RF_LOBF_9 0x38
453#define RF_RXRF_A3 0x3C /* */
454#define RF_TRSW 0x3F
455
456#define RF_TXRF_A2 0x41
457#define RF_TXPA_G4 0x46
458#define RF_TXPA_A4 0x4B
459#define RF_0x52 0x52
460#define RF_WE_LUT 0xEF
461#define RF_S0S1 0xB0
462
463/* */
464/* Bit Mask */
465/* */
466/* 1. Page1(0x100) */
467#define bBBResetB 0x100 /* Useless now? */
468#define bGlobalResetB 0x200
469#define bOFDMTxStart 0x4
470#define bCCKTxStart 0x8
471#define bCRC32Debug 0x100
472#define bPMACLoopback 0x10
473#define bTxLSIG 0xffffff
474#define bOFDMTxRate 0xf
475#define bOFDMTxReserved 0x10
476#define bOFDMTxLength 0x1ffe0
477#define bOFDMTxParity 0x20000
478#define bTxHTSIG1 0xffffff
479#define bTxHTMCSRate 0x7f
480#define bTxHTBW 0x80
481#define bTxHTLength 0xffff00
482#define bTxHTSIG2 0xffffff
483#define bTxHTSmoothing 0x1
484#define bTxHTSounding 0x2
485#define bTxHTReserved 0x4
486#define bTxHTAggreation 0x8
487#define bTxHTSTBC 0x30
488#define bTxHTAdvanceCoding 0x40
489#define bTxHTShortGI 0x80
490#define bTxHTNumberHT_LTF 0x300
491#define bTxHTCRC8 0x3fc00
492#define bCounterReset 0x10000
493#define bNumOfOFDMTx 0xffff
494#define bNumOfCCKTx 0xffff0000
495#define bTxIdleInterval 0xffff
496#define bOFDMService 0xffff0000
497#define bTxMACHeader 0xffffffff
498#define bTxDataInit 0xff
499#define bTxHTMode 0x100
500#define bTxDataType 0x30000
501#define bTxRandomSeed 0xffffffff
502#define bCCKTxPreamble 0x1
503#define bCCKTxSFD 0xffff0000
504#define bCCKTxSIG 0xff
505#define bCCKTxService 0xff00
506#define bCCKLengthExt 0x8000
507#define bCCKTxLength 0xffff0000
508#define bCCKTxCRC16 0xffff
509#define bCCKTxStatus 0x1
510#define bOFDMTxStatus 0x2
511
512#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
513
514/* 2. Page8(0x800) */
515#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
516#define bJapanMode 0x2
517#define bCCKTxSC 0x30
518#define bCCKEn 0x1000000
519#define bOFDMEn 0x2000000
520
521#define bOFDMRxADCPhase 0x10000 /* Useless now */
522#define bOFDMTxDACPhase 0x40000
523#define bXATxAGC 0x3f
524
525#define bAntennaSelect 0x0300
526
527#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
528#define bXCTxAGC 0xf000
529#define bXDTxAGC 0xf0000
530
531#define bPAStart 0xf0000000 /* Useless now */
532#define bTRStart 0x00f00000
533#define bRFStart 0x0000f000
534#define bBBStart 0x000000f0
535#define bBBCCKStart 0x0000000f
536#define bPAEnd 0xf /* Reg0x814 */
537#define bTREnd 0x0f000000
538#define bRFEnd 0x000f0000
539#define bCCAMask 0x000000f0 /* T2R */
540#define bR2RCCAMask 0x00000f00
541#define bHSSI_R2TDelay 0xf8000000
542#define bHSSI_T2RDelay 0xf80000
543#define bContTxHSSI 0x400 /* chane gain at continue Tx */
544#define bIGFromCCK 0x200
545#define bAGCAddress 0x3f
546#define bRxHPTx 0x7000
547#define bRxHPT2R 0x38000
548#define bRxHPCCKIni 0xc0000
549#define bAGCTxCode 0xc00000
550#define bAGCRxCode 0x300000
551
552#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
553#define b3WireAddressLength 0x400
554
555#define b3WireRFPowerDown 0x1 /* Useless now */
556/* define bHWSISelect 0x8 */
557#define b2GPAPEPolarity 0x80000000
558#define bRFSW_TxDefaultAnt 0x3
559#define bRFSW_TxOptionAnt 0x30
560#define bRFSW_RxDefaultAnt 0x300
561#define bRFSW_RxOptionAnt 0x3000
562#define bRFSI_3WireData 0x1
563#define bRFSI_3WireClock 0x2
564#define bRFSI_3WireLoad 0x4
565#define bRFSI_3WireRW 0x8
566#define bRFSI_3Wire 0xf
567
568#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
569
570#define bRFSI_TRSW 0x20 /* Useless now */
571#define bRFSI_TRSWB 0x40
572#define bRFSI_ANTSW 0x100
573#define bRFSI_ANTSWB 0x200
574#define bRFSI_PAPE 0x400
575#define bBandSelect 0x1
576#define bHTSIG2_GI 0x80
577#define bHTSIG2_Smoothing 0x01
578#define bHTSIG2_Sounding 0x02
579#define bHTSIG2_Aggreaton 0x08
580#define bHTSIG2_STBC 0x30
581#define bHTSIG2_AdvCoding 0x40
582#define bHTSIG2_NumOfHTLTF 0x300
583#define bHTSIG2_CRC8 0x3fc
584#define bHTSIG1_MCS 0x7f
585#define bHTSIG1_BandWidth 0x80
586#define bHTSIG1_HTLength 0xffff
587#define bLSIG_Rate 0xf
588#define bLSIG_Reserved 0x10
589#define bLSIG_Length 0x1fffe
590#define bLSIG_Parity 0x20
591#define bCCKRxPhase 0x4
592
593#define bLSSIReadAddress 0x7f800000 /* T65 RF */
594
595#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
596
597#define bLSSIReadBackData 0xfffff /* T65 RF */
598
599#define bLSSIReadOKFlag 0x1000 /* Useless now */
600#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
601#define bRegulator0Standby 0x1
602#define bRegulatorPLLStandby 0x2
603#define bRegulator1Standby 0x4
604#define bPLLPowerUp 0x8
605#define bDPLLPowerUp 0x10
606#define bDA10PowerUp 0x20
607#define bAD7PowerUp 0x200
608#define bDA6PowerUp 0x2000
609#define bXtalPowerUp 0x4000
610#define b40MDClkPowerUP 0x8000
611#define bDA6DebugMode 0x20000
612#define bDA6Swing 0x380000
613
614#define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
615
616#define b80MClkDelay 0x18000000 /* Useless */
617#define bAFEWatchDogEnable 0x20000000
618
619#define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
620#define bXtalCap23 0x3
621#define bXtalCap92x 0x0f000000
622#define bXtalCap 0x0f000000
623
624#define bIntDifClkEnable 0x400 /* Useless */
625#define bExtSigClkEnable 0x800
626#define bBandgapMbiasPowerUp 0x10000
627#define bAD11SHGain 0xc0000
628#define bAD11InputRange 0x700000
629#define bAD11OPCurrent 0x3800000
630#define bIPathLoopback 0x4000000
631#define bQPathLoopback 0x8000000
632#define bAFELoopback 0x10000000
633#define bDA10Swing 0x7e0
634#define bDA10Reverse 0x800
635#define bDAClkSource 0x1000
636#define bAD7InputRange 0x6000
637#define bAD7Gain 0x38000
638#define bAD7OutputCMMode 0x40000
639#define bAD7InputCMMode 0x380000
640#define bAD7Current 0xc00000
641#define bRegulatorAdjust 0x7000000
642#define bAD11PowerUpAtTx 0x1
643#define bDA10PSAtTx 0x10
644#define bAD11PowerUpAtRx 0x100
645#define bDA10PSAtRx 0x1000
646#define bCCKRxAGCFormat 0x200
647#define bPSDFFTSamplepPoint 0xc000
648#define bPSDAverageNum 0x3000
649#define bIQPathControl 0xc00
650#define bPSDFreq 0x3ff
651#define bPSDAntennaPath 0x30
652#define bPSDIQSwitch 0x40
653#define bPSDRxTrigger 0x400000
654#define bPSDTxTrigger 0x80000000
655#define bPSDSineToneScale 0x7f000000
656#define bPSDReport 0xffff
657
658/* 3. Page9(0x900) */
659#define bOFDMTxSC 0x30000000 /* Useless */
660#define bCCKTxOn 0x1
661#define bOFDMTxOn 0x2
662#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */
663#define bDebugItem 0xff /* reset debug page and LWord */
664#define bAntL 0x10
665#define bAntNonHT 0x100
666#define bAntHT1 0x1000
667#define bAntHT2 0x10000
668#define bAntHT1S1 0x100000
669#define bAntNonHTS1 0x1000000
670
671/* 4. PageA(0xA00) */
672#define bCCKBBMode 0x3 /* Useless */
673#define bCCKTxPowerSaving 0x80
674#define bCCKRxPowerSaving 0x40
675
676#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
677
678#define bCCKScramble 0x8 /* Useless */
679#define bCCKAntDiversity 0x8000
680#define bCCKCarrierRecovery 0x4000
681#define bCCKTxRate 0x3000
682#define bCCKDCCancel 0x0800
683#define bCCKISICancel 0x0400
684#define bCCKMatchFilter 0x0200
685#define bCCKEqualizer 0x0100
686#define bCCKPreambleDetect 0x800000
687#define bCCKFastFalseCCA 0x400000
688#define bCCKChEstStart 0x300000
689#define bCCKCCACount 0x080000
690#define bCCKcs_lim 0x070000
691#define bCCKBistMode 0x80000000
692#define bCCKCCAMask 0x40000000
693#define bCCKTxDACPhase 0x4
694#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
695#define bCCKr_cp_mode0 0x0100
696#define bCCKTxDCOffset 0xf0
697#define bCCKRxDCOffset 0xf
698#define bCCKCCAMode 0xc000
699#define bCCKFalseCS_lim 0x3f00
700#define bCCKCS_ratio 0xc00000
701#define bCCKCorgBit_sel 0x300000
702#define bCCKPD_lim 0x0f0000
703#define bCCKNewCCA 0x80000000
704#define bCCKRxHPofIG 0x8000
705#define bCCKRxIG 0x7f00
706#define bCCKLNAPolarity 0x800000
707#define bCCKRx1stGain 0x7f0000
708#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
709#define bCCKRxAGCSatLevel 0x1f000000
710#define bCCKRxAGCSatCount 0xe0
711#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
712#define bCCKFixedRxAGC 0x8000
713#define bCCKAntennaPolarity 0x2000
714#define bCCKTxFilterType 0x0c00
715#define bCCKRxAGCReportType 0x0300
716#define bCCKRxDAGCEn 0x80000000
717#define bCCKRxDAGCPeriod 0x20000000
718#define bCCKRxDAGCSatLevel 0x1f000000
719#define bCCKTimingRecovery 0x800000
720#define bCCKTxC0 0x3f0000
721#define bCCKTxC1 0x3f000000
722#define bCCKTxC2 0x3f
723#define bCCKTxC3 0x3f00
724#define bCCKTxC4 0x3f0000
725#define bCCKTxC5 0x3f000000
726#define bCCKTxC6 0x3f
727#define bCCKTxC7 0x3f00
728#define bCCKDebugPort 0xff0000
729#define bCCKDACDebug 0x0f000000
730#define bCCKFalseAlarmEnable 0x8000
731#define bCCKFalseAlarmRead 0x4000
732#define bCCKTRSSI 0x7f
733#define bCCKRxAGCReport 0xfe
734#define bCCKRxReport_AntSel 0x80000000
735#define bCCKRxReport_MFOff 0x40000000
736#define bCCKRxRxReport_SQLoss 0x20000000
737#define bCCKRxReport_Pktloss 0x10000000
738#define bCCKRxReport_Lockedbit 0x08000000
739#define bCCKRxReport_RateError 0x04000000
740#define bCCKRxReport_RxRate 0x03000000
741#define bCCKRxFACounterLower 0xff
742#define bCCKRxFACounterUpper 0xff000000
743#define bCCKRxHPAGCStart 0xe000
744#define bCCKRxHPAGCFinal 0x1c00
745#define bCCKRxFalseAlarmEnable 0x8000
746#define bCCKFACounterFreeze 0x4000
747#define bCCKTxPathSel 0x10000000
748#define bCCKDefaultRxPath 0xc000000
749#define bCCKOptionRxPath 0x3000000
750
751/* 5. PageC(0xC00) */
752#define bNumOfSTF 0x3 /* Useless */
753#define bShift_L 0xc0
754#define bGI_TH 0xc
755#define bRxPathA 0x1
756#define bRxPathB 0x2
757#define bRxPathC 0x4
758#define bRxPathD 0x8
759#define bTxPathA 0x1
760#define bTxPathB 0x2
761#define bTxPathC 0x4
762#define bTxPathD 0x8
763#define bTRSSIFreq 0x200
764#define bADCBackoff 0x3000
765#define bDFIRBackoff 0xc000
766#define bTRSSILatchPhase 0x10000
767#define bRxIDCOffset 0xff
768#define bRxQDCOffset 0xff00
769#define bRxDFIRMode 0x1800000
770#define bRxDCNFType 0xe000000
771#define bRXIQImb_A 0x3ff
772#define bRXIQImb_B 0xfc00
773#define bRXIQImb_C 0x3f0000
774#define bRXIQImb_D 0xffc00000
775#define bDC_dc_Notch 0x60000
776#define bRxNBINotch 0x1f000000
777#define bPD_TH 0xf
778#define bPD_TH_Opt2 0xc000
779#define bPWED_TH 0x700
780#define bIfMF_Win_L 0x800
781#define bPD_Option 0x1000
782#define bMF_Win_L 0xe000
783#define bBW_Search_L 0x30000
784#define bwin_enh_L 0xc0000
785#define bBW_TH 0x700000
786#define bED_TH2 0x3800000
787#define bBW_option 0x4000000
788#define bRatio_TH 0x18000000
789#define bWindow_L 0xe0000000
790#define bSBD_Option 0x1
791#define bFrame_TH 0x1c
792#define bFS_Option 0x60
793#define bDC_Slope_check 0x80
794#define bFGuard_Counter_DC_L 0xe00
795#define bFrame_Weight_Short 0x7000
796#define bSub_Tune 0xe00000
797#define bFrame_DC_Length 0xe000000
798#define bSBD_start_offset 0x30000000
799#define bFrame_TH_2 0x7
800#define bFrame_GI2_TH 0x38
801#define bGI2_Sync_en 0x40
802#define bSarch_Short_Early 0x300
803#define bSarch_Short_Late 0xc00
804#define bSarch_GI2_Late 0x70000
805#define bCFOAntSum 0x1
806#define bCFOAcc 0x2
807#define bCFOStartOffset 0xc
808#define bCFOLookBack 0x70
809#define bCFOSumWeight 0x80
810#define bDAGCEnable 0x10000
811#define bTXIQImb_A 0x3ff
812#define bTXIQImb_B 0xfc00
813#define bTXIQImb_C 0x3f0000
814#define bTXIQImb_D 0xffc00000
815#define bTxIDCOffset 0xff
816#define bTxQDCOffset 0xff00
817#define bTxDFIRMode 0x10000
818#define bTxPesudoNoiseOn 0x4000000
819#define bTxPesudoNoise_A 0xff
820#define bTxPesudoNoise_B 0xff00
821#define bTxPesudoNoise_C 0xff0000
822#define bTxPesudoNoise_D 0xff000000
823#define bCCADropOption 0x20000
824#define bCCADropThres 0xfff00000
825#define bEDCCA_H 0xf
826#define bEDCCA_L 0xf0
827#define bLambda_ED 0x300
828#define bRxInitialGain 0x7f
829#define bRxAntDivEn 0x80
830#define bRxAGCAddressForLNA 0x7f00
831#define bRxHighPowerFlow 0x8000
832#define bRxAGCFreezeThres 0xc0000
833#define bRxFreezeStep_AGC1 0x300000
834#define bRxFreezeStep_AGC2 0xc00000
835#define bRxFreezeStep_AGC3 0x3000000
836#define bRxFreezeStep_AGC0 0xc000000
837#define bRxRssi_Cmp_En 0x10000000
838#define bRxQuickAGCEn 0x20000000
839#define bRxAGCFreezeThresMode 0x40000000
840#define bRxOverFlowCheckType 0x80000000
841#define bRxAGCShift 0x7f
842#define bTRSW_Tri_Only 0x80
843#define bPowerThres 0x300
844#define bRxAGCEn 0x1
845#define bRxAGCTogetherEn 0x2
846#define bRxAGCMin 0x4
847#define bRxHP_Ini 0x7
848#define bRxHP_TRLNA 0x70
849#define bRxHP_RSSI 0x700
850#define bRxHP_BBP1 0x7000
851#define bRxHP_BBP2 0x70000
852#define bRxHP_BBP3 0x700000
853#define bRSSI_H 0x7f0000 /* the threshold for high power */
854#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */
855#define bRxSettle_TRSW 0x7
856#define bRxSettle_LNA 0x38
857#define bRxSettle_RSSI 0x1c0
858#define bRxSettle_BBP 0xe00
859#define bRxSettle_RxHP 0x7000
860#define bRxSettle_AntSW_RSSI 0x38000
861#define bRxSettle_AntSW 0xc0000
862#define bRxProcessTime_DAGC 0x300000
863#define bRxSettle_HSSI 0x400000
864#define bRxProcessTime_BBPPW 0x800000
865#define bRxAntennaPowerShift 0x3000000
866#define bRSSITableSelect 0xc000000
867#define bRxHP_Final 0x7000000
868#define bRxHTSettle_BBP 0x7
869#define bRxHTSettle_HSSI 0x8
870#define bRxHTSettle_RxHP 0x70
871#define bRxHTSettle_BBPPW 0x80
872#define bRxHTSettle_Idle 0x300
873#define bRxHTSettle_Reserved 0x1c00
874#define bRxHTRxHPEn 0x8000
875#define bRxHTAGCFreezeThres 0x30000
876#define bRxHTAGCTogetherEn 0x40000
877#define bRxHTAGCMin 0x80000
878#define bRxHTAGCEn 0x100000
879#define bRxHTDAGCEn 0x200000
880#define bRxHTRxHP_BBP 0x1c00000
881#define bRxHTRxHP_Final 0xe0000000
882#define bRxPWRatioTH 0x3
883#define bRxPWRatioEn 0x4
884#define bRxMFHold 0x3800
885#define bRxPD_Delay_TH1 0x38
886#define bRxPD_Delay_TH2 0x1c0
887#define bRxPD_DC_COUNT_MAX 0x600
888/* define bRxMF_Hold 0x3800 */
889#define bRxPD_Delay_TH 0x8000
890#define bRxProcess_Delay 0xf0000
891#define bRxSearchrange_GI2_Early 0x700000
892#define bRxFrame_Guard_Counter_L 0x3800000
893#define bRxSGI_Guard_L 0xc000000
894#define bRxSGI_Search_L 0x30000000
895#define bRxSGI_TH 0xc0000000
896#define bDFSCnt0 0xff
897#define bDFSCnt1 0xff00
898#define bDFSFlag 0xf0000
899#define bMFWeightSum 0x300000
900#define bMinIdxTH 0x7f000000
901#define bDAFormat 0x40000
902#define bTxChEmuEnable 0x01000000
903#define bTRSWIsolation_A 0x7f
904#define bTRSWIsolation_B 0x7f00
905#define bTRSWIsolation_C 0x7f0000
906#define bTRSWIsolation_D 0x7f000000
907#define bExtLNAGain 0x7c00
908
909/* 6. PageE(0xE00) */
910#define bSTBCEn 0x4 /* Useless */
911#define bAntennaMapping 0x10
912#define bNss 0x20
913#define bCFOAntSumD 0x200
914#define bPHYCounterReset 0x8000000
915#define bCFOReportGet 0x4000000
916#define bOFDMContinueTx 0x10000000
917#define bOFDMSingleCarrier 0x20000000
918#define bOFDMSingleTone 0x40000000
919/* define bRxPath1 0x01 */
920/* define bRxPath2 0x02 */
921/* define bRxPath3 0x04 */
922/* define bRxPath4 0x08 */
923/* define bTxPath1 0x10 */
924/* define bTxPath2 0x20 */
925#define bHTDetect 0x100
926#define bCFOEn 0x10000
927#define bCFOValue 0xfff00000
928#define bSigTone_Re 0x3f
929#define bSigTone_Im 0x7f00
930#define bCounter_CCA 0xffff
931#define bCounter_ParityFail 0xffff0000
932#define bCounter_RateIllegal 0xffff
933#define bCounter_CRC8Fail 0xffff0000
934#define bCounter_MCSNoSupport 0xffff
935#define bCounter_FastSync 0xffff
936#define bShortCFO 0xfff
937#define bShortCFOTLength 12 /* total */
938#define bShortCFOFLength 11 /* fraction */
939#define bLongCFO 0x7ff
940#define bLongCFOTLength 11
941#define bLongCFOFLength 11
942#define bTailCFO 0x1fff
943#define bTailCFOTLength 13
944#define bTailCFOFLength 12
945#define bmax_en_pwdB 0xffff
946#define bCC_power_dB 0xffff0000
947#define bnoise_pwdB 0xffff
948#define bPowerMeasTLength 10
949#define bPowerMeasFLength 3
950#define bRx_HT_BW 0x1
951#define bRxSC 0x6
952#define bRx_HT 0x8
953#define bNB_intf_det_on 0x1
954#define bIntf_win_len_cfg 0x30
955#define bNB_Intf_TH_cfg 0x1c0
956#define bRFGain 0x3f
957#define bTableSel 0x40
958#define bTRSW 0x80
959#define bRxSNR_A 0xff
960#define bRxSNR_B 0xff00
961#define bRxSNR_C 0xff0000
962#define bRxSNR_D 0xff000000
963#define bSNREVMTLength 8
964#define bSNREVMFLength 1
965#define bCSI1st 0xff
966#define bCSI2nd 0xff00
967#define bRxEVM1st 0xff0000
968#define bRxEVM2nd 0xff000000
969#define bSIGEVM 0xff
970#define bPWDB 0xff00
971#define bSGIEN 0x10000
972
973#define bSFactorQAM1 0xf /* Useless */
974#define bSFactorQAM2 0xf0
975#define bSFactorQAM3 0xf00
976#define bSFactorQAM4 0xf000
977#define bSFactorQAM5 0xf0000
978#define bSFactorQAM6 0xf0000
979#define bSFactorQAM7 0xf00000
980#define bSFactorQAM8 0xf000000
981#define bSFactorQAM9 0xf0000000
982#define bCSIScheme 0x100000
983
984#define bNoiseLvlTopSet 0x3 /* Useless */
985#define bChSmooth 0x4
986#define bChSmoothCfg1 0x38
987#define bChSmoothCfg2 0x1c0
988#define bChSmoothCfg3 0xe00
989#define bChSmoothCfg4 0x7000
990#define bMRCMode 0x800000
991#define bTHEVMCfg 0x7000000
992
993#define bLoopFitType 0x1 /* Useless */
994#define bUpdCFO 0x40
995#define bUpdCFOOffData 0x80
996#define bAdvUpdCFO 0x100
997#define bAdvTimeCtrl 0x800
998#define bUpdClko 0x1000
999#define bFC 0x6000
1000#define bTrackingMode 0x8000
1001#define bPhCmpEnable 0x10000
1002#define bUpdClkoLTF 0x20000
1003#define bComChCFO 0x40000
1004#define bCSIEstiMode 0x80000
1005#define bAdvUpdEqz 0x100000
1006#define bUChCfg 0x7000000
1007#define bUpdEqz 0x8000000
1008
1009/* Rx Pseduo noise */
1010#define bRxPesudoNoiseOn 0x20000000 /* Useless */
1011#define bRxPesudoNoise_A 0xff
1012#define bRxPesudoNoise_B 0xff00
1013#define bRxPesudoNoise_C 0xff0000
1014#define bRxPesudoNoise_D 0xff000000
1015#define bPesudoNoiseState_A 0xffff
1016#define bPesudoNoiseState_B 0xffff0000
1017#define bPesudoNoiseState_C 0xffff
1018#define bPesudoNoiseState_D 0xffff0000
1019
1020/* 7. RF Register */
1021/* Zebra1 */
1022#define bZebra1_HSSIEnable 0x8 /* Useless */
1023#define bZebra1_TRxControl 0xc00
1024#define bZebra1_TRxGainSetting 0x07f
1025#define bZebra1_RxCorner 0xc00
1026#define bZebra1_TxChargePump 0x38
1027#define bZebra1_RxChargePump 0x7
1028#define bZebra1_ChannelNum 0xf80
1029#define bZebra1_TxLPFBW 0x400
1030#define bZebra1_RxLPFBW 0x600
1031
1032/* Zebra4 */
1033#define bRTL8256RegModeCtrl1 0x100 /* Useless */
1034#define bRTL8256RegModeCtrl0 0x40
1035#define bRTL8256_TxLPFBW 0x18
1036#define bRTL8256_RxLPFBW 0x600
1037
1038/* RTL8258 */
1039#define bRTL8258_TxLPFBW 0xc /* Useless */
1040#define bRTL8258_RxLPFBW 0xc00
1041#define bRTL8258_RSSILPFBW 0xc0
1042
1043
1044/* */
1045/* Other Definition */
1046/* */
1047
1048/* byte endable for sb_write */
1049#define bByte0 0x1 /* Useless */
1050#define bByte1 0x2
1051#define bByte2 0x4
1052#define bByte3 0x8
1053#define bWord0 0x3
1054#define bWord1 0xc
1055#define bDWord 0xf
1056
1057/* for PutRegsetting & GetRegSetting BitMask */
1058#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
1059#define bMaskByte1 0xff00
1060#define bMaskByte2 0xff0000
1061#define bMaskByte3 0xff000000
1062#define bMaskHWord 0xffff0000
1063#define bMaskLWord 0x0000ffff
1064#define bMaskDWord 0xffffffff
1065#define bMaskH3Bytes 0xffffff00
1066#define bMask12Bits 0xfff
1067#define bMaskH4Bits 0xf0000000
1068#define bMaskOFDM_D 0xffc00000
1069#define bMaskCCK 0x3f3f3f3f
1070
1071
1072#define bEnable 0x1 /* Useless */
1073#define bDisable 0x0
1074
1075#define LeftAntenna 0x0 /* Useless */
1076#define RightAntenna 0x1
1077
1078#define tCheckTxStatus 500 /* 500ms Useless */
1079#define tUpdateRxCounter 100 /* 100ms */
1080
1081#define rateCCK 0 /* Useless */
1082#define rateOFDM 1
1083#define rateHT 2
1084
1085/* define Register-End */
1086#define bPMAC_End 0x1ff /* Useless */
1087#define bFPGAPHY0_End 0x8ff
1088#define bFPGAPHY1_End 0x9ff
1089#define bCCKPHY0_End 0xaff
1090#define bOFDMPHY0_End 0xcff
1091#define bOFDMPHY1_End 0xdff
1092
1093/* define max debug item in each debug page */
1094/* define bMaxItem_FPGA_PHY0 0x9 */
1095/* define bMaxItem_FPGA_PHY1 0x3 */
1096/* define bMaxItem_PHY_11B 0x16 */
1097/* define bMaxItem_OFDM_PHY0 0x29 */
1098/* define bMaxItem_OFDM_PHY1 0x0 */
1099
1100#define bPMACControl 0x0 /* Useless */
1101#define bWMACControl 0x1
1102#define bWNICControl 0x2
1103
1104#define PathA 0x0 /* Useless */
1105#define PathB 0x1
1106#define PathC 0x2
1107#define PathD 0x3
1108
1109/*--------------------------Define Parameters-------------------------------*/
1110
1111
1112#endif /* __INC_HAL8192SPHYREG_H */
1113

source code of linux/drivers/staging/rtl8723bs/include/Hal8192CPhyReg.h