1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /****************************************************************************** |
3 | * |
4 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. |
5 | * |
6 | ******************************************************************************/ |
7 | #ifndef __HALPWRSEQCMD_H__ |
8 | #define __HALPWRSEQCMD_H__ |
9 | |
10 | #include <drv_types.h> |
11 | |
12 | /*---------------------------------------------*/ |
13 | /* 3 The value of cmd: 4 bits */ |
14 | /*---------------------------------------------*/ |
15 | #define PWR_CMD_READ 0x00 |
16 | /* offset: the read register offset */ |
17 | /* msk: the mask of the read value */ |
18 | /* value: N/A, left by 0 */ |
19 | /* note: dirver shall implement this function by read & msk */ |
20 | |
21 | #define PWR_CMD_WRITE 0x01 |
22 | /* offset: the read register offset */ |
23 | /* msk: the mask of the write bits */ |
24 | /* value: write value */ |
25 | /* note: driver shall implement this cmd by read & msk after write */ |
26 | |
27 | #define PWR_CMD_POLLING 0x02 |
28 | /* offset: the read register offset */ |
29 | /* msk: the mask of the polled value */ |
30 | /* value: the value to be polled, masked by the msd field. */ |
31 | /* note: driver shall implement this cmd by */ |
32 | /* do{ */ |
33 | /* if ((Read(offset) & msk) == (value & msk)) */ |
34 | /* break; */ |
35 | /* } while (not timeout); */ |
36 | |
37 | #define PWR_CMD_DELAY 0x03 |
38 | /* offset: the value to delay */ |
39 | /* msk: N/A */ |
40 | /* value: the unit of delay, 0: us, 1: ms */ |
41 | |
42 | #define PWR_CMD_END 0x04 |
43 | /* offset: N/A */ |
44 | /* msk: N/A */ |
45 | /* value: N/A */ |
46 | |
47 | /*---------------------------------------------*/ |
48 | /* 3 The value of base: 4 bits */ |
49 | /*---------------------------------------------*/ |
50 | /* define the base address of each block */ |
51 | #define PWR_BASEADDR_MAC 0x00 |
52 | #define PWR_BASEADDR_USB 0x01 |
53 | #define PWR_BASEADDR_PCIE 0x02 |
54 | #define PWR_BASEADDR_SDIO 0x03 |
55 | |
56 | /*---------------------------------------------*/ |
57 | /* 3 The value of interface_msk: 4 bits */ |
58 | /*---------------------------------------------*/ |
59 | #define PWR_INTF_SDIO_MSK BIT(0) |
60 | #define PWR_INTF_USB_MSK BIT(1) |
61 | #define PWR_INTF_PCI_MSK BIT(2) |
62 | #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) |
63 | |
64 | /*---------------------------------------------*/ |
65 | /* 3 The value of fab_msk: 4 bits */ |
66 | /*---------------------------------------------*/ |
67 | #define PWR_FAB_TSMC_MSK BIT(0) |
68 | #define PWR_FAB_UMC_MSK BIT(1) |
69 | #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) |
70 | |
71 | /*---------------------------------------------*/ |
72 | /* 3 The value of cut_msk: 8 bits */ |
73 | /*---------------------------------------------*/ |
74 | #define PWR_CUT_TESTCHIP_MSK BIT(0) |
75 | #define PWR_CUT_A_MSK BIT(1) |
76 | #define PWR_CUT_B_MSK BIT(2) |
77 | #define PWR_CUT_C_MSK BIT(3) |
78 | #define PWR_CUT_D_MSK BIT(4) |
79 | #define PWR_CUT_E_MSK BIT(5) |
80 | #define PWR_CUT_F_MSK BIT(6) |
81 | #define PWR_CUT_G_MSK BIT(7) |
82 | #define PWR_CUT_ALL_MSK 0xFF |
83 | |
84 | |
85 | enum { |
86 | PWRSEQ_DELAY_US, |
87 | PWRSEQ_DELAY_MS, |
88 | }; |
89 | |
90 | struct wlan_pwr_cfg { |
91 | u16 offset; |
92 | u8 cut_msk; |
93 | u8 fab_msk:4; |
94 | u8 interface_msk:4; |
95 | u8 base:4; |
96 | u8 cmd:4; |
97 | u8 msk; |
98 | u8 value; |
99 | }; |
100 | |
101 | |
102 | #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset |
103 | #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk |
104 | #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk |
105 | #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk |
106 | #define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base |
107 | #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd |
108 | #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk |
109 | #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value |
110 | |
111 | |
112 | /* */ |
113 | /* Prototype of protected function. */ |
114 | /* */ |
115 | u8 HalPwrSeqCmdParsing( |
116 | struct adapter *padapter, |
117 | u8 CutVersion, |
118 | u8 FabVersion, |
119 | u8 InterfaceType, |
120 | struct wlan_pwr_cfg PwrCfgCmd[]); |
121 | |
122 | #endif |
123 | |