1/* SPDX-License-Identifier: GPL-2.0 */
2/******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7#ifndef __HAL_DATA_H__
8#define __HAL_DATA_H__
9
10#include "odm_precomp.h"
11#include <hal_btcoex.h>
12
13#include <hal_sdio.h>
14
15/* */
16/* <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */
17/* */
18enum rt_multi_func {
19 RT_MULTI_FUNC_NONE = 0x00,
20 RT_MULTI_FUNC_WIFI = 0x01,
21 RT_MULTI_FUNC_BT = 0x02,
22 RT_MULTI_FUNC_GPS = 0x04,
23};
24/* */
25/* <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */
26/* */
27enum rt_polarity_ctl {
28 RT_POLARITY_LOW_ACT = 0,
29 RT_POLARITY_HIGH_ACT = 1,
30};
31
32/* For RTL8723 regulator mode. by tynli. 2011.01.14. */
33enum rt_regulator_mode {
34 RT_SWITCHING_REGULATOR = 0,
35 RT_LDO_REGULATOR = 1,
36};
37
38enum rt_ampdu_burst {
39 RT_AMPDU_BURST_NONE = 0,
40 RT_AMPDU_BURST_92D = 1,
41 RT_AMPDU_BURST_88E = 2,
42 RT_AMPDU_BURST_8812_4 = 3,
43 RT_AMPDU_BURST_8812_8 = 4,
44 RT_AMPDU_BURST_8812_12 = 5,
45 RT_AMPDU_BURST_8812_15 = 6,
46 RT_AMPDU_BURST_8723B = 7,
47};
48
49#define CHANNEL_MAX_NUMBER (14) /* 14 is the max channel number */
50#define CHANNEL_MAX_NUMBER_2G 14
51#define MAX_PG_GROUP 13
52
53/* Tx Power Limit Table Size */
54#define MAX_REGULATION_NUM 4
55#define MAX_2_4G_BANDWIDTH_NUM 2
56#define MAX_RATE_SECTION_NUM 3 /* CCK:1, OFDM:1, HT:1 */
57
58/* duplicate code, will move to ODM ######### */
59/* define IQK_MAC_REG_NUM 4 */
60/* define IQK_ADDA_REG_NUM 16 */
61
62/* define IQK_BB_REG_NUM 10 */
63
64/* define HP_THERMAL_NUM 8 */
65/* duplicate code, will move to ODM ######### */
66
67enum {
68 SINGLEMAC_SINGLEPHY, /* SMSP */
69 DUALMAC_DUALPHY, /* DMDP */
70 DUALMAC_SINGLEPHY, /* DMSP */
71};
72
73#define PAGE_SIZE_128 128
74#define PAGE_SIZE_256 256
75#define PAGE_SIZE_512 512
76
77struct dm_priv {
78 u8 DM_Type;
79
80#define DYNAMIC_FUNC_BT BIT0
81
82 u8 DMFlag;
83 u8 InitDMFlag;
84 /* u8 RSVD_1; */
85
86 u32 InitODMFlag;
87 /* Upper and Lower Signal threshold for Rate Adaptive */
88 int UndecoratedSmoothedPWDB;
89 int UndecoratedSmoothedCCK;
90 int EntryMinUndecoratedSmoothedPWDB;
91 int EntryMaxUndecoratedSmoothedPWDB;
92 int MinUndecoratedPWDBForDM;
93 int LastMinUndecoratedPWDBForDM;
94
95 s32 UndecoratedSmoothedBeacon;
96
97/* duplicate code, will move to ODM ######### */
98 /* for High Power */
99 u8 bDynamicTxPowerEnable;
100 u8 LastDTPLvl;
101 u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 */
102
103 /* for tx power tracking */
104 u8 bTXPowerTracking;
105 u8 TXPowercount;
106 u8 bTXPowerTrackingInit;
107 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
108 u8 TM_Trigger;
109
110 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
111 u8 ThermalValue;
112 u8 ThermalValue_LCK;
113 u8 ThermalValue_IQK;
114 u8 ThermalValue_DPK;
115 u8 bRfPiEnable;
116 /* u8 RSVD_2; */
117
118 /* for APK */
119 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
120 u8 bAPKdone;
121 u8 bAPKThermalMeterIgnore;
122 u8 bDPdone;
123 u8 bDPPathAOK;
124 u8 bDPPathBOK;
125 /* u8 RSVD_3; */
126 /* u8 RSVD_4; */
127 /* u8 RSVD_5; */
128
129 /* for IQK */
130 u32 ADDA_backup[IQK_ADDA_REG_NUM];
131 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
132 u32 IQK_BB_backup_recover[9];
133 u32 IQK_BB_backup[IQK_BB_REG_NUM];
134
135 u8 PowerIndex_backup[6];
136 u8 OFDM_index[2];
137
138 u8 bCCKinCH14;
139 u8 CCK_index;
140 u8 bDoneTxpower;
141 u8 CCK_index_HP;
142
143 u8 OFDM_index_HP[2];
144 u8 ThermalValue_HP[HP_THERMAL_NUM];
145 u8 ThermalValue_HP_index;
146 /* u8 RSVD_6; */
147
148 /* for TxPwrTracking2 */
149 s32 RegE94;
150 s32 RegE9C;
151 s32 RegEB4;
152 s32 RegEBC;
153
154 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
155
156 u32 prv_traffic_idx; /* edca turbo */
157/* duplicate code, will move to ODM ######### */
158
159 /* Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas */
160 u8 INIDATA_RATE[32];
161};
162
163
164struct hal_com_data {
165 struct hal_version VersionID;
166 enum rt_multi_func MultiFunc; /* For multi-function consideration. */
167 enum rt_polarity_ctl PolarityCtl; /* For Wifi PDn Polarity control. */
168 enum rt_regulator_mode RegulatorMode; /* switching regulator or LDO */
169
170 u16 FirmwareVersion;
171 u16 FirmwareVersionRev;
172 u16 FirmwareSubVersion;
173 u16 FirmwareSignature;
174
175 /* current WIFI_PHY values */
176 enum wireless_mode CurrentWirelessMode;
177 enum channel_width CurrentChannelBW;
178 u8 CurrentChannel;
179 u8 CurrentCenterFrequencyIndex1;
180 u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */
181 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */
182
183 u16 CustomerID;
184 u16 BasicRateSet;
185 u16 ForcedDataRate;/* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
186 u32 ReceiveConfig;
187
188 /* rf_ctrl */
189 u8 rf_chip;
190 u8 PackageType;
191 u8 NumTotalRFPath;
192
193 u8 InterfaceSel;
194 u8 framesync;
195 u32 framesyncC34;
196 u8 framesyncMonitor;
197 u8 DefaultInitialGain[4];
198 /* EEPROM setting. */
199 u16 EEPROMVID;
200 u16 EEPROMSVID;
201
202 u8 EEPROMCustomerID;
203 u8 EEPROMSubCustomerID;
204 u8 EEPROMVersion;
205 u8 EEPROMRegulatory;
206 u8 EEPROMThermalMeter;
207 u8 EEPROMBluetoothCoexist;
208 u8 EEPROMBluetoothType;
209 u8 EEPROMBluetoothAntNum;
210 u8 EEPROMBluetoothAntIsolation;
211 u8 EEPROMBluetoothRadioShared;
212 u8 bTXPowerDataReadFromEEPORM;
213 u8 bAPKThermalMeterIgnore;
214 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */
215
216 bool EepromOrEfuse;
217 u8 EfuseUsedPercentage;
218 u16 EfuseUsedBytes;
219 struct efuse_hal EfuseHal;
220
221 /* 3 [2.4G] */
222 u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
223 u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
224 /* If only one tx, only BW20 and OFDM are used. */
225 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
226 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
227 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
228 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
229
230 u8 Regulation2_4G;
231
232 u8 TxPwrInPercentage;
233
234 u8 TxPwrCalibrateRate;
235 /* TX power by rate table */
236 /* RF: at most 2 = AB = 0/1 */
237 /* CCK = 0 OFDM = 1 HT-MCS 0-7 = 2 */
238 u8 TxPwrByRateTable;
239 u8 TxPwrByRateBand;
240 s8 TxPwrByRateOffset[MAX_RF_PATH_NUM][TX_PWR_BY_RATE_NUM_RATE];
241 /* */
242
243 /* 2 Power Limit Table */
244 u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
245 u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
246 u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
247 s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */
248 u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */
249
250 /* Power Limit Table for 2.4G */
251 s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
252 [MAX_2_4G_BANDWIDTH_NUM]
253 [MAX_RATE_SECTION_NUM]
254 [CHANNEL_MAX_NUMBER_2G]
255 [MAX_RF_PATH_NUM];
256
257 /* Store the original power by rate value of the base of each rate section of rf path A & B */
258 u8 TxPwrByRateBase2_4G[MAX_RF_PATH_NUM][MAX_RATE_SECTION_NUM];
259
260 /* For power group */
261 u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
262 u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
263
264
265
266
267 u8 PGMaxGroup;
268 u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */
269 /* The current Tx Power Level */
270 u8 CurrentCckTxPwrIdx;
271 u8 CurrentOfdm24GTxPwrIdx;
272 u8 CurrentBW2024GTxPwrIdx;
273 u8 CurrentBW4024GTxPwrIdx;
274
275 /* Read/write are allow for following hardware information variables */
276 u8 pwrGroupCnt;
277 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
278 u32 CCKTxPowerLevelOriginalOffset;
279
280 u8 CrystalCap;
281 u32 AntennaTxPath; /* Antenna path Tx */
282 u32 AntennaRxPath; /* Antenna path Rx */
283
284 u8 PAType_2G;
285 u8 LNAType_2G;
286 u8 ExternalPA_2G;
287 u8 ExternalLNA_2G;
288 u8 TypeGLNA;
289 u8 TypeGPA;
290 u8 TypeALNA;
291 u8 TypeAPA;
292 u8 RFEType;
293 u8 BoardType;
294 u8 ExternalPA;
295 u8 bIQKInitialized;
296 bool bLCKInProgress;
297
298 bool bSwChnl;
299 bool bSetChnlBW;
300 bool bChnlBWInitialized;
301 bool bNeedIQK;
302
303 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
304 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
305 u8 b1x1RecvCombine; /* for 1T1R receive combining */
306
307 u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
308
309 struct bb_register_def PHYRegDef[4]; /* Radio A/B/C/D */
310
311 u32 RfRegChnlVal[2];
312
313 /* RDG enable */
314 bool bRDGEnable;
315
316 /* for host message to fw */
317 u8 LastHMEBoxNum;
318
319 u8 fw_ractrl;
320 u8 RegTxPause;
321 /* Beacon function related global variable. */
322 u8 RegBcnCtrlVal;
323 u8 RegFwHwTxQCtrl;
324 u8 RegReg542;
325 u8 RegCR_1;
326 u8 Reg837;
327 u8 RegRFPathS1;
328 u16 RegRRSR;
329
330 u8 CurAntenna;
331 u8 AntDivCfg;
332 u8 AntDetection;
333 u8 TRxAntDivType;
334 u8 ant_path; /* for 8723B s0/s1 selection */
335
336 u8 u1ForcedIgiLb; /* forced IGI lower bound */
337
338 u8 bDumpRxPkt;/* for debug */
339 u8 bDumpTxPkt;/* for debug */
340 u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */
341
342 /* 2010/08/09 MH Add CU power down mode. */
343 bool pwrdown;
344
345 /* Add for dual MAC 0--Mac0 1--Mac1 */
346 u32 interfaceIndex;
347
348 u8 OutEpQueueSel;
349 u8 OutEpNumber;
350
351 /* 2010/12/10 MH Add for USB aggregation mode dynamic scheme. */
352 bool UsbRxHighSpeedMode;
353
354 /* 2010/11/22 MH Add for slim combo debug mode selective. */
355 /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */
356 bool SlimComboDbg;
357
358 /* u8 AMPDUDensity; */
359
360 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
361 u8 bMacPwrCtrlOn;
362
363 u8 RegIQKFWOffload;
364 struct submit_ctx iqk_sctx;
365
366 enum rt_ampdu_burst AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */
367
368 u32 sdio_himr;
369 u32 sdio_hisr;
370
371 /* SDIO Tx FIFO related. */
372 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
373 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
374 spinlock_t SdioTxFIFOFreePageLock;
375 u8 SdioTxOQTMaxFreeSpace;
376 u8 SdioTxOQTFreeSpace;
377
378
379 /* SDIO Rx FIFO related. */
380 u8 SdioRxFIFOCnt;
381 u16 SdioRxFIFOSize;
382
383 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
384
385 struct dm_priv dmpriv;
386 struct dm_odm_t odmpriv;
387
388 /* For bluetooth co-existance */
389 struct bt_coexist bt_coexist;
390
391 /* Interrupt related register information. */
392 u32 SysIntrStatus;
393 u32 SysIntrMask;
394};
395
396#define GET_HAL_DATA(__padapter) ((struct hal_com_data *)((__padapter)->HalData))
397#define GET_HAL_RFPATH_NUM(__padapter) (((struct hal_com_data *)((__padapter)->HalData))->NumTotalRFPath)
398#define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel)
399
400#endif /* __HAL_DATA_H__ */
401

source code of linux/drivers/staging/rtl8723bs/include/hal_data.h