1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /****************************************************************************** |
3 | * |
4 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. |
5 | * |
6 | *******************************************************************************/ |
7 | #ifndef __RTL8723B_SPEC_H__ |
8 | #define __RTL8723B_SPEC_H__ |
9 | |
10 | #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */ |
11 | |
12 | /* */ |
13 | /* */ |
14 | /* 0x0000h ~ 0x00FFh System Configuration */ |
15 | /* */ |
16 | /* */ |
17 | #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ |
18 | #define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038 |
19 | #define REG_HSISR_8723B 0x005c |
20 | #define REG_PAD_CTRL1_8723B 0x0064 |
21 | #define REG_AFE_CTRL_4_8723B 0x0078 |
22 | #define REG_HMEBOX_DBG_0_8723B 0x0088 |
23 | #define REG_HMEBOX_DBG_1_8723B 0x008A |
24 | #define REG_HMEBOX_DBG_2_8723B 0x008C |
25 | #define REG_HMEBOX_DBG_3_8723B 0x008E |
26 | #define REG_HIMR0_8723B 0x00B0 |
27 | #define REG_HISR0_8723B 0x00B4 |
28 | #define REG_HIMR1_8723B 0x00B8 |
29 | #define REG_HISR1_8723B 0x00BC |
30 | #define REG_PMC_DBG_CTRL2_8723B 0x00CC |
31 | |
32 | /* */ |
33 | /* */ |
34 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ |
35 | /* */ |
36 | /* */ |
37 | #define REG_C2HEVT_CMD_ID_8723B 0x01A0 |
38 | #define REG_C2HEVT_CMD_LEN_8723B 0x01AE |
39 | #define REG_WOWLAN_WAKE_REASON 0x01C7 |
40 | #define REG_WOWLAN_GTK_DBG1 0x630 |
41 | #define REG_WOWLAN_GTK_DBG2 0x634 |
42 | |
43 | #define REG_HMEBOX_EXT0_8723B 0x01F0 |
44 | #define REG_HMEBOX_EXT1_8723B 0x01F4 |
45 | #define REG_HMEBOX_EXT2_8723B 0x01F8 |
46 | #define REG_HMEBOX_EXT3_8723B 0x01FC |
47 | |
48 | /* */ |
49 | /* */ |
50 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ |
51 | /* */ |
52 | /* */ |
53 | |
54 | /* */ |
55 | /* */ |
56 | /* 0x0280h ~ 0x02FFh RXDMA Configuration */ |
57 | /* */ |
58 | /* */ |
59 | #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ |
60 | #define REG_RXDMA_MODE_CTRL_8723B 0x0290 |
61 | |
62 | /* */ |
63 | /* */ |
64 | /* 0x0300h ~ 0x03FFh PCIe */ |
65 | /* */ |
66 | /* */ |
67 | #define REG_PCIE_CTRL_REG_8723B 0x0300 |
68 | #define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ |
69 | #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */ |
70 | #define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ |
71 | #define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */ |
72 | #define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */ |
73 | #define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ |
74 | #define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */ |
75 | #define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */ |
76 | #define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ |
77 | #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ |
78 | #define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ |
79 | #define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ |
80 | #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ |
81 | #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ |
82 | #define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ |
83 | #define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ |
84 | #define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ |
85 | #define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ |
86 | #define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ |
87 | #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ |
88 | |
89 | /* */ |
90 | /* */ |
91 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ |
92 | /* */ |
93 | /* */ |
94 | #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 |
95 | #define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 |
96 | #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D |
97 | #define REG_AMPDU_BURST_MODE_8723B 0x04BC |
98 | |
99 | /* */ |
100 | /* */ |
101 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ |
102 | /* */ |
103 | /* */ |
104 | #define REG_SECONDARY_CCA_CTRL_8723B 0x0577 |
105 | |
106 | /* */ |
107 | /* */ |
108 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ |
109 | /* */ |
110 | /* */ |
111 | |
112 | /* */ |
113 | /* SDIO Bus Specification */ |
114 | /* */ |
115 | |
116 | /* */ |
117 | /* SDIO CMD Address Mapping */ |
118 | /* */ |
119 | |
120 | /* */ |
121 | /* I/O bus domain (Host) */ |
122 | /* */ |
123 | |
124 | /* */ |
125 | /* SDIO register */ |
126 | /* */ |
127 | #define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */ |
128 | |
129 | /* */ |
130 | /* 8723 Register Bit and Content definition */ |
131 | /* */ |
132 | |
133 | /* 2 HSISR */ |
134 | /* interrupt mask which needs to clear */ |
135 | #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ |
136 | HSISR_SPS_OCP_INT |\ |
137 | HSISR_RON_INT |\ |
138 | HSISR_PDNINT |\ |
139 | HSISR_GPIO9_INT) |
140 | |
141 | /* */ |
142 | /* */ |
143 | /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ |
144 | /* */ |
145 | /* */ |
146 | |
147 | /* */ |
148 | /* */ |
149 | /* 0x0200h ~ 0x027Fh TXDMA Configuration */ |
150 | /* */ |
151 | /* */ |
152 | |
153 | /* */ |
154 | /* */ |
155 | /* 0x0280h ~ 0x02FFh RXDMA Configuration */ |
156 | /* */ |
157 | /* */ |
158 | #define BIT_USB_RXDMA_AGG_EN BIT(31) |
159 | #define RXDMA_AGG_MODE_EN BIT(1) |
160 | |
161 | /* */ |
162 | /* */ |
163 | /* 0x0400h ~ 0x047Fh Protocol Configuration */ |
164 | /* */ |
165 | /* */ |
166 | |
167 | /* */ |
168 | /* 8723B REG_CCK_CHECK (offset 0x454) */ |
169 | /* */ |
170 | #define BIT_BCN_PORT_SEL BIT5 |
171 | |
172 | /* */ |
173 | /* */ |
174 | /* 0x0500h ~ 0x05FFh EDCA Configuration */ |
175 | /* */ |
176 | /* */ |
177 | |
178 | /* */ |
179 | /* */ |
180 | /* 0x0600h ~ 0x07FFh WMAC Configuration */ |
181 | /* */ |
182 | /* */ |
183 | #define EEPROM_RF_GAIN_OFFSET 0xC1 |
184 | #define EEPROM_RF_GAIN_VAL 0x1F6 |
185 | |
186 | /* */ |
187 | /* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ |
188 | /* */ |
189 | #define IMR_DISABLED_8723B 0 |
190 | /* IMR DW0(0x00B0-00B3) Bit 0-31 */ |
191 | #define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ |
192 | #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ |
193 | #define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ |
194 | #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ |
195 | #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ |
196 | #define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ |
197 | #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ |
198 | #define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ |
199 | #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ |
200 | #define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ |
201 | #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ |
202 | #define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ |
203 | #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ |
204 | #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ |
205 | #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ |
206 | #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ |
207 | #define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ |
208 | #define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ |
209 | #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ |
210 | #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ |
211 | #define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ |
212 | #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ |
213 | #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ |
214 | #define IMR_ROK_8723B BIT0 /* Receive DMA OK */ |
215 | |
216 | /* IMR DW1(0x00B4-00B7) Bit 0-31 */ |
217 | #define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */ |
218 | #define IMR_BCNDMAINT6_8723B BIT26 /* Beacon DMA Interrupt 6 */ |
219 | #define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */ |
220 | #define IMR_BCNDMAINT4_8723B BIT24 /* Beacon DMA Interrupt 4 */ |
221 | #define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ |
222 | #define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ |
223 | #define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ |
224 | #define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrupt 7 */ |
225 | #define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrupt 6 */ |
226 | #define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */ |
227 | #define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrupt 4 */ |
228 | #define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrupt 3 */ |
229 | #define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */ |
230 | #define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrupt 1 */ |
231 | #define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ |
232 | #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ |
233 | #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ |
234 | #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ |
235 | #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */ |
236 | |
237 | #endif |
238 | |