1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /****************************************************************************** |
3 | * |
4 | * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. |
5 | * |
6 | ******************************************************************************/ |
7 | #ifndef __RTL8723B_XMIT_H__ |
8 | #define __RTL8723B_XMIT_H__ |
9 | |
10 | /* */ |
11 | /* Queue Select Value in TxDesc */ |
12 | /* */ |
13 | #define QSLT_BK 0x2/* 0x01 */ |
14 | #define QSLT_BE 0x0 |
15 | #define QSLT_VI 0x5/* 0x4 */ |
16 | #define QSLT_VO 0x7/* 0x6 */ |
17 | #define QSLT_BEACON 0x10 |
18 | #define QSLT_HIGH 0x11 |
19 | #define QSLT_MGNT 0x12 |
20 | #define QSLT_CMD 0x13 |
21 | |
22 | #define MAX_TID (15) |
23 | |
24 | /* OFFSET 0 */ |
25 | #define OFFSET_SZ 0 |
26 | #define OFFSET_SHT 16 |
27 | #define BMC BIT(24) |
28 | #define LSG BIT(26) |
29 | #define FSG BIT(27) |
30 | #define OWN BIT(31) |
31 | |
32 | |
33 | /* OFFSET 4 */ |
34 | #define PKT_OFFSET_SZ 0 |
35 | #define BK BIT(6) |
36 | #define QSEL_SHT 8 |
37 | #define Rate_ID_SHT 16 |
38 | #define NAVUSEHDR BIT(20) |
39 | #define PKT_OFFSET_SHT 26 |
40 | #define HWPC BIT(31) |
41 | |
42 | /* OFFSET 8 */ |
43 | #define AGG_EN BIT(29) |
44 | |
45 | /* OFFSET 12 */ |
46 | #define SEQ_SHT 16 |
47 | |
48 | /* OFFSET 16 */ |
49 | #define QoS BIT(6) |
50 | #define HW_SEQ_EN BIT(7) |
51 | #define USERATE BIT(8) |
52 | #define DISDATAFB BIT(10) |
53 | #define DATA_SHORT BIT(24) |
54 | #define DATA_BW BIT(25) |
55 | |
56 | /* OFFSET 20 */ |
57 | #define SGI BIT(6) |
58 | |
59 | /* */ |
60 | /* defined for TX DESC Operation */ |
61 | /* */ |
62 | struct txdesc_8723b { |
63 | /* Offset 0 */ |
64 | u32 pktlen:16; |
65 | u32 offset:8; |
66 | u32 bmc:1; |
67 | u32 htc:1; |
68 | u32 rsvd0026:1; |
69 | u32 rsvd0027:1; |
70 | u32 linip:1; |
71 | u32 noacm:1; |
72 | u32 gf:1; |
73 | u32 rsvd0031:1; |
74 | |
75 | /* Offset 4 */ |
76 | u32 macid:7; |
77 | u32 rsvd0407:1; |
78 | u32 qsel:5; |
79 | u32 rdg_nav_ext:1; |
80 | u32 lsig_txop_en:1; |
81 | u32 pifs:1; |
82 | u32 rate_id:5; |
83 | u32 en_desc_id:1; |
84 | u32 sectype:2; |
85 | u32 pkt_offset:5; /* unit: 8 bytes */ |
86 | u32 moredata:1; |
87 | u32 txop_ps_cap:1; |
88 | u32 txop_ps_mode:1; |
89 | |
90 | /* Offset 8 */ |
91 | u32 p_aid:9; |
92 | u32 rsvd0809:1; |
93 | u32 cca_rts:2; |
94 | u32 agg_en:1; |
95 | u32 rdg_en:1; |
96 | u32 null_0:1; |
97 | u32 null_1:1; |
98 | u32 bk:1; |
99 | u32 morefrag:1; |
100 | u32 raw:1; |
101 | u32 spe_rpt:1; |
102 | u32 ampdu_density:3; |
103 | u32 bt_null:1; |
104 | u32 g_id:6; |
105 | u32 rsvd0830:2; |
106 | |
107 | /* Offset 12 */ |
108 | u32 :4; |
109 | u32 chk_en:1; |
110 | u32 early_rate:1; |
111 | u32 hw_ssn_sel:2; |
112 | u32 userate:1; |
113 | u32 disrtsfb:1; |
114 | u32 disdatafb:1; |
115 | u32 cts2self:1; |
116 | u32 rtsen:1; |
117 | u32 hw_rts_en:1; |
118 | u32 port_id:1; |
119 | u32 navusehdr:1; |
120 | u32 use_max_len:1; |
121 | u32 max_agg_num:5; |
122 | u32 ndpa:2; |
123 | u32 ampdu_max_time:8; |
124 | |
125 | /* Offset 16 */ |
126 | u32 datarate:7; |
127 | u32 try_rate:1; |
128 | u32 data_ratefb_lmt:5; |
129 | u32 rts_ratefb_lmt:4; |
130 | u32 rty_lmt_en:1; |
131 | u32 data_rt_lmt:6; |
132 | u32 rtsrate:5; |
133 | u32 pcts_en:1; |
134 | u32 pcts_mask_idx:2; |
135 | |
136 | /* Offset 20 */ |
137 | u32 data_sc:4; |
138 | u32 data_short:1; |
139 | u32 data_bw:2; |
140 | u32 data_ldpc:1; |
141 | u32 data_stbc:2; |
142 | u32 vcs_stbc:2; |
143 | u32 rts_short:1; |
144 | u32 rts_sc:4; |
145 | u32 rsvd2016:7; |
146 | u32 tx_ant:4; |
147 | u32 txpwr_offset:3; |
148 | u32 rsvd2031:1; |
149 | |
150 | /* Offset 24 */ |
151 | u32 sw_define:12; |
152 | u32 mbssid:4; |
153 | u32 antsel_A:3; |
154 | u32 antsel_B:3; |
155 | u32 antsel_C:3; |
156 | u32 antsel_D:3; |
157 | u32 rsvd2428:4; |
158 | |
159 | /* Offset 28 */ |
160 | u32 checksum:16; |
161 | u32 rsvd2816:8; |
162 | u32 usb_txagg_num:8; |
163 | |
164 | /* Offset 32 */ |
165 | u32 rts_rc:6; |
166 | u32 bar_rty_th:2; |
167 | u32 data_rc:6; |
168 | u32 rsvd3214:1; |
169 | u32 en_hwseq:1; |
170 | u32 nextneadpage:8; |
171 | u32 tailpage:8; |
172 | |
173 | /* Offset 36 */ |
174 | u32 padding_len:11; |
175 | u32 txbf_path:1; |
176 | u32 seq:12; |
177 | u32 final_data_rate:8; |
178 | }; |
179 | |
180 | #ifndef __INC_HAL8723BDESC_H |
181 | #define __INC_HAL8723BDESC_H |
182 | |
183 | #define RX_STATUS_DESC_SIZE_8723B 24 |
184 | #define RX_DRV_INFO_SIZE_UNIT_8723B 8 |
185 | |
186 | |
187 | /* DWORD 0 */ |
188 | #define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) |
189 | #define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) |
190 | #define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) |
191 | |
192 | #define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) |
193 | #define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) |
194 | #define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) |
195 | #define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) |
196 | #define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) |
197 | #define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) |
198 | #define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) |
199 | #define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) |
200 | #define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) |
201 | #define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1) |
202 | #define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1) |
203 | #define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) |
204 | #define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) |
205 | |
206 | /* DWORD 1 */ |
207 | #define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) |
208 | #define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) |
209 | #define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) |
210 | #define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) |
211 | #define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) |
212 | #define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) |
213 | #define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) |
214 | #define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) |
215 | #define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) |
216 | #define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) |
217 | #define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) |
218 | #define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) |
219 | #define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) |
220 | #define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) |
221 | #define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) |
222 | #define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) |
223 | #define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) |
224 | |
225 | /* DWORD 2 */ |
226 | #define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) |
227 | #define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) |
228 | #define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) |
229 | #define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) |
230 | #define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) |
231 | |
232 | /* DWORD 3 */ |
233 | #define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) |
234 | #define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) |
235 | #define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) |
236 | #define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) |
237 | #define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) |
238 | #define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) |
239 | #define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) |
240 | |
241 | /* DWORD 6 */ |
242 | #define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1) |
243 | #define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1) |
244 | #define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1) |
245 | #define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2) |
246 | |
247 | /* DWORD 5 */ |
248 | #define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) |
249 | |
250 | #define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) |
251 | #define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) |
252 | |
253 | #define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) |
254 | |
255 | |
256 | /* Dword 0 */ |
257 | #define GET_TX_DESC_OWN_8723B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) |
258 | |
259 | #define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) |
260 | #define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) |
261 | #define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) |
262 | #define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) |
263 | #define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) |
264 | #define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) |
265 | #define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) |
266 | #define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) |
267 | #define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) |
268 | #define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) |
269 | |
270 | /* Dword 1 */ |
271 | #define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) |
272 | #define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) |
273 | #define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) |
274 | #define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) |
275 | #define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) |
276 | #define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) |
277 | #define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) |
278 | #define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) |
279 | #define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) |
280 | |
281 | |
282 | /* Dword 2 */ |
283 | #define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) |
284 | #define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) |
285 | #define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) |
286 | #define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) |
287 | #define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) |
288 | #define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) |
289 | #define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) |
290 | #define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) |
291 | #define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) |
292 | #define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) |
293 | #define SET_TX_DESC_GID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) |
294 | |
295 | |
296 | /* Dword 3 */ |
297 | #define (__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) |
298 | #define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) |
299 | #define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) |
300 | #define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) |
301 | #define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) |
302 | #define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) |
303 | #define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) |
304 | #define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) |
305 | #define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) |
306 | #define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) |
307 | #define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) |
308 | #define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) |
309 | #define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) |
310 | #define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) |
311 | #define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) |
312 | |
313 | /* Dword 4 */ |
314 | #define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) |
315 | #define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) |
316 | #define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) |
317 | #define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) |
318 | #define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) |
319 | #define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) |
320 | |
321 | |
322 | /* Dword 5 */ |
323 | #define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) |
324 | #define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) |
325 | #define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) |
326 | #define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) |
327 | #define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) |
328 | #define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) |
329 | #define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) |
330 | #define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) |
331 | |
332 | |
333 | /* Dword 6 */ |
334 | #define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) |
335 | #define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) |
336 | #define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) |
337 | #define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) |
338 | #define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) |
339 | |
340 | /* Dword 7 */ |
341 | #define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) |
342 | #define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) |
343 | #define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) |
344 | |
345 | /* Dword 8 */ |
346 | #define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) |
347 | |
348 | /* Dword 9 */ |
349 | #define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) |
350 | |
351 | /* Dword 10 */ |
352 | #define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) |
353 | #define GET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32) |
354 | |
355 | /* Dword 11 */ |
356 | #define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) |
357 | |
358 | |
359 | #define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) |
360 | #define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) |
361 | #define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) |
362 | #define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) |
363 | #define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) |
364 | #define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) |
365 | |
366 | #endif |
367 | /* */ |
368 | /* */ |
369 | /* Rate */ |
370 | /* */ |
371 | /* */ |
372 | /* CCK Rates, TxHT = 0 */ |
373 | #define DESC8723B_RATE1M 0x00 |
374 | #define DESC8723B_RATE2M 0x01 |
375 | #define DESC8723B_RATE5_5M 0x02 |
376 | #define DESC8723B_RATE11M 0x03 |
377 | |
378 | /* OFDM Rates, TxHT = 0 */ |
379 | #define DESC8723B_RATE6M 0x04 |
380 | #define DESC8723B_RATE9M 0x05 |
381 | #define DESC8723B_RATE12M 0x06 |
382 | #define DESC8723B_RATE18M 0x07 |
383 | #define DESC8723B_RATE24M 0x08 |
384 | #define DESC8723B_RATE36M 0x09 |
385 | #define DESC8723B_RATE48M 0x0a |
386 | #define DESC8723B_RATE54M 0x0b |
387 | |
388 | /* MCS Rates, TxHT = 1 */ |
389 | #define DESC8723B_RATEMCS0 0x0c |
390 | #define DESC8723B_RATEMCS1 0x0d |
391 | #define DESC8723B_RATEMCS2 0x0e |
392 | #define DESC8723B_RATEMCS3 0x0f |
393 | #define DESC8723B_RATEMCS4 0x10 |
394 | #define DESC8723B_RATEMCS5 0x11 |
395 | #define DESC8723B_RATEMCS6 0x12 |
396 | #define DESC8723B_RATEMCS7 0x13 |
397 | |
398 | #define RX_HAL_IS_CCK_RATE_8723B(pDesc)\ |
399 | (GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE1M ||\ |
400 | GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE2M ||\ |
401 | GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE5_5M ||\ |
402 | GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE11M) |
403 | |
404 | |
405 | void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); |
406 | void rtl8723b_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); |
407 | |
408 | s32 rtl8723bs_init_xmit_priv(struct adapter *padapter); |
409 | void rtl8723bs_free_xmit_priv(struct adapter *padapter); |
410 | s32 rtl8723bs_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe); |
411 | s32 rtl8723bs_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe); |
412 | s32 rtl8723bs_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe); |
413 | s32 rtl8723bs_xmit_buf_handler(struct adapter *padapter); |
414 | int rtl8723bs_xmit_thread(void *context); |
415 | #define hal_xmit_handler rtl8723bs_xmit_buf_handler |
416 | |
417 | u8 BWMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib); |
418 | u8 SCMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib); |
419 | |
420 | #endif |
421 | |