1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * tsi148.h
4 *
5 * Support for the Tundra TSI148 VME Bridge chip
6 *
7 * Author: Tom Armistead
8 * Updated and maintained by Ajit Prem
9 * Copyright 2004 Motorola Inc.
10 */
11
12#ifndef TSI148_H
13#define TSI148_H
14
15#ifndef PCI_VENDOR_ID_TUNDRA
16#define PCI_VENDOR_ID_TUNDRA 0x10e3
17#endif
18
19#ifndef PCI_DEVICE_ID_TUNDRA_TSI148
20#define PCI_DEVICE_ID_TUNDRA_TSI148 0x148
21#endif
22
23/*
24 * Define the number of each that the Tsi148 supports.
25 */
26#define TSI148_MAX_MASTER 8 /* Max Master Windows */
27#define TSI148_MAX_SLAVE 8 /* Max Slave Windows */
28#define TSI148_MAX_DMA 2 /* Max DMA Controllers */
29#define TSI148_MAX_MAILBOX 4 /* Max Mail Box registers */
30#define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */
31
32/* Structure used to hold driver specific information */
33struct tsi148_driver {
34 void __iomem *base; /* Base Address of device registers */
35 wait_queue_head_t dma_queue[2];
36 wait_queue_head_t iack_queue;
37 void (*lm_callback[4])(void *); /* Called in interrupt handler */
38 void *lm_data[4];
39 void *crcsr_kernel;
40 dma_addr_t crcsr_bus;
41 struct vme_master_resource *flush_image;
42 struct mutex vme_rmw; /* Only one RMW cycle at a time */
43 struct mutex vme_int; /*
44 * Only one VME interrupt can be
45 * generated at a time, provide locking
46 */
47};
48
49/*
50 * Layout of a DMAC Linked-List Descriptor
51 *
52 * Note: This structure is accessed via the chip and therefore must be
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
54 */
55struct tsi148_dma_descriptor {
56 __be32 dsau; /* Source Address */
57 __be32 dsal;
58 __be32 ddau; /* Destination Address */
59 __be32 ddal;
60 __be32 dsat; /* Source attributes */
61 __be32 ddat; /* Destination attributes */
62 __be32 dnlau; /* Next link address */
63 __be32 dnlal;
64 __be32 dcnt; /* Byte count */
65 __be32 ddbs; /* 2eSST Broadcast select */
66};
67
68struct tsi148_dma_entry {
69 /*
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
71 * the chance of this by putting it first in the structure.
72 */
73 struct tsi148_dma_descriptor descriptor;
74 struct list_head list;
75 dma_addr_t dma_handle;
76};
77
78/*
79 * TSI148 ASIC register structure overlays and bit field definitions.
80 *
81 * Note: Tsi148 Register Group (CRG) consists of the following
82 * combination of registers:
83 * PCFS - PCI Configuration Space Registers
84 * LCSR - Local Control and Status Registers
85 * GCSR - Global Control and Status Registers
86 * CR/CSR - Subset of Configuration ROM /
87 * Control and Status Registers
88 */
89
90/*
91 * Command/Status Registers (CRG + $004)
92 */
93#define TSI148_PCFS_ID 0x0
94#define TSI148_PCFS_CSR 0x4
95#define TSI148_PCFS_CLASS 0x8
96#define TSI148_PCFS_MISC0 0xC
97#define TSI148_PCFS_MBARL 0x10
98#define TSI148_PCFS_MBARU 0x14
99#define TSI148_PCFS_SUBID 0x28
100#define TSI148_PCFS_CAPP 0x34
101#define TSI148_PCFS_MISC1 0x3C
102#define TSI148_PCFS_XCAPP 0x40
103#define TSI148_PCFS_XSTAT 0x44
104
105/*
106 * LCSR definitions
107 */
108
109/*
110 * Outbound Translations
111 */
112#define TSI148_LCSR_OT0_OTSAU 0x100
113#define TSI148_LCSR_OT0_OTSAL 0x104
114#define TSI148_LCSR_OT0_OTEAU 0x108
115#define TSI148_LCSR_OT0_OTEAL 0x10C
116#define TSI148_LCSR_OT0_OTOFU 0x110
117#define TSI148_LCSR_OT0_OTOFL 0x114
118#define TSI148_LCSR_OT0_OTBS 0x118
119#define TSI148_LCSR_OT0_OTAT 0x11C
120
121#define TSI148_LCSR_OT1_OTSAU 0x120
122#define TSI148_LCSR_OT1_OTSAL 0x124
123#define TSI148_LCSR_OT1_OTEAU 0x128
124#define TSI148_LCSR_OT1_OTEAL 0x12C
125#define TSI148_LCSR_OT1_OTOFU 0x130
126#define TSI148_LCSR_OT1_OTOFL 0x134
127#define TSI148_LCSR_OT1_OTBS 0x138
128#define TSI148_LCSR_OT1_OTAT 0x13C
129
130#define TSI148_LCSR_OT2_OTSAU 0x140
131#define TSI148_LCSR_OT2_OTSAL 0x144
132#define TSI148_LCSR_OT2_OTEAU 0x148
133#define TSI148_LCSR_OT2_OTEAL 0x14C
134#define TSI148_LCSR_OT2_OTOFU 0x150
135#define TSI148_LCSR_OT2_OTOFL 0x154
136#define TSI148_LCSR_OT2_OTBS 0x158
137#define TSI148_LCSR_OT2_OTAT 0x15C
138
139#define TSI148_LCSR_OT3_OTSAU 0x160
140#define TSI148_LCSR_OT3_OTSAL 0x164
141#define TSI148_LCSR_OT3_OTEAU 0x168
142#define TSI148_LCSR_OT3_OTEAL 0x16C
143#define TSI148_LCSR_OT3_OTOFU 0x170
144#define TSI148_LCSR_OT3_OTOFL 0x174
145#define TSI148_LCSR_OT3_OTBS 0x178
146#define TSI148_LCSR_OT3_OTAT 0x17C
147
148#define TSI148_LCSR_OT4_OTSAU 0x180
149#define TSI148_LCSR_OT4_OTSAL 0x184
150#define TSI148_LCSR_OT4_OTEAU 0x188
151#define TSI148_LCSR_OT4_OTEAL 0x18C
152#define TSI148_LCSR_OT4_OTOFU 0x190
153#define TSI148_LCSR_OT4_OTOFL 0x194
154#define TSI148_LCSR_OT4_OTBS 0x198
155#define TSI148_LCSR_OT4_OTAT 0x19C
156
157#define TSI148_LCSR_OT5_OTSAU 0x1A0
158#define TSI148_LCSR_OT5_OTSAL 0x1A4
159#define TSI148_LCSR_OT5_OTEAU 0x1A8
160#define TSI148_LCSR_OT5_OTEAL 0x1AC
161#define TSI148_LCSR_OT5_OTOFU 0x1B0
162#define TSI148_LCSR_OT5_OTOFL 0x1B4
163#define TSI148_LCSR_OT5_OTBS 0x1B8
164#define TSI148_LCSR_OT5_OTAT 0x1BC
165
166#define TSI148_LCSR_OT6_OTSAU 0x1C0
167#define TSI148_LCSR_OT6_OTSAL 0x1C4
168#define TSI148_LCSR_OT6_OTEAU 0x1C8
169#define TSI148_LCSR_OT6_OTEAL 0x1CC
170#define TSI148_LCSR_OT6_OTOFU 0x1D0
171#define TSI148_LCSR_OT6_OTOFL 0x1D4
172#define TSI148_LCSR_OT6_OTBS 0x1D8
173#define TSI148_LCSR_OT6_OTAT 0x1DC
174
175#define TSI148_LCSR_OT7_OTSAU 0x1E0
176#define TSI148_LCSR_OT7_OTSAL 0x1E4
177#define TSI148_LCSR_OT7_OTEAU 0x1E8
178#define TSI148_LCSR_OT7_OTEAL 0x1EC
179#define TSI148_LCSR_OT7_OTOFU 0x1F0
180#define TSI148_LCSR_OT7_OTOFL 0x1F4
181#define TSI148_LCSR_OT7_OTBS 0x1F8
182#define TSI148_LCSR_OT7_OTAT 0x1FC
183
184#define TSI148_LCSR_OT0 0x100
185#define TSI148_LCSR_OT1 0x120
186#define TSI148_LCSR_OT2 0x140
187#define TSI148_LCSR_OT3 0x160
188#define TSI148_LCSR_OT4 0x180
189#define TSI148_LCSR_OT5 0x1A0
190#define TSI148_LCSR_OT6 0x1C0
191#define TSI148_LCSR_OT7 0x1E0
192
193static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
194 TSI148_LCSR_OT2, TSI148_LCSR_OT3,
195 TSI148_LCSR_OT4, TSI148_LCSR_OT5,
196 TSI148_LCSR_OT6, TSI148_LCSR_OT7 };
197
198#define TSI148_LCSR_OFFSET_OTSAU 0x0
199#define TSI148_LCSR_OFFSET_OTSAL 0x4
200#define TSI148_LCSR_OFFSET_OTEAU 0x8
201#define TSI148_LCSR_OFFSET_OTEAL 0xC
202#define TSI148_LCSR_OFFSET_OTOFU 0x10
203#define TSI148_LCSR_OFFSET_OTOFL 0x14
204#define TSI148_LCSR_OFFSET_OTBS 0x18
205#define TSI148_LCSR_OFFSET_OTAT 0x1C
206
207/*
208 * VMEbus interrupt ack
209 * offset 0x200
210 */
211#define TSI148_LCSR_VIACK1 0x204
212#define TSI148_LCSR_VIACK2 0x208
213#define TSI148_LCSR_VIACK3 0x20C
214#define TSI148_LCSR_VIACK4 0x210
215#define TSI148_LCSR_VIACK5 0x214
216#define TSI148_LCSR_VIACK6 0x218
217#define TSI148_LCSR_VIACK7 0x21C
218
219static const int TSI148_LCSR_VIACK[8] = { 0, TSI148_LCSR_VIACK1,
220 TSI148_LCSR_VIACK2, TSI148_LCSR_VIACK3,
221 TSI148_LCSR_VIACK4, TSI148_LCSR_VIACK5,
222 TSI148_LCSR_VIACK6, TSI148_LCSR_VIACK7 };
223
224/*
225 * RMW
226 * offset 0x220
227 */
228#define TSI148_LCSR_RMWAU 0x220
229#define TSI148_LCSR_RMWAL 0x224
230#define TSI148_LCSR_RMWEN 0x228
231#define TSI148_LCSR_RMWC 0x22C
232#define TSI148_LCSR_RMWS 0x230
233
234/*
235 * VMEbus control
236 * offset 0x234
237 */
238#define TSI148_LCSR_VMCTRL 0x234
239#define TSI148_LCSR_VCTRL 0x238
240#define TSI148_LCSR_VSTAT 0x23C
241
242/*
243 * PCI status
244 * offset 0x240
245 */
246#define TSI148_LCSR_PSTAT 0x240
247
248/*
249 * VME filter.
250 * offset 0x250
251 */
252#define TSI148_LCSR_VMEFL 0x250
253
254/*
255 * VME exception.
256 * offset 0x260
257 */
258#define TSI148_LCSR_VEAU 0x260
259#define TSI148_LCSR_VEAL 0x264
260#define TSI148_LCSR_VEAT 0x268
261
262/*
263 * PCI error
264 * offset 0x270
265 */
266#define TSI148_LCSR_EDPAU 0x270
267#define TSI148_LCSR_EDPAL 0x274
268#define TSI148_LCSR_EDPXA 0x278
269#define TSI148_LCSR_EDPXS 0x27C
270#define TSI148_LCSR_EDPAT 0x280
271
272/*
273 * Inbound Translations
274 * offset 0x300
275 */
276#define TSI148_LCSR_IT0_ITSAU 0x300
277#define TSI148_LCSR_IT0_ITSAL 0x304
278#define TSI148_LCSR_IT0_ITEAU 0x308
279#define TSI148_LCSR_IT0_ITEAL 0x30C
280#define TSI148_LCSR_IT0_ITOFU 0x310
281#define TSI148_LCSR_IT0_ITOFL 0x314
282#define TSI148_LCSR_IT0_ITAT 0x318
283
284#define TSI148_LCSR_IT1_ITSAU 0x320
285#define TSI148_LCSR_IT1_ITSAL 0x324
286#define TSI148_LCSR_IT1_ITEAU 0x328
287#define TSI148_LCSR_IT1_ITEAL 0x32C
288#define TSI148_LCSR_IT1_ITOFU 0x330
289#define TSI148_LCSR_IT1_ITOFL 0x334
290#define TSI148_LCSR_IT1_ITAT 0x338
291
292#define TSI148_LCSR_IT2_ITSAU 0x340
293#define TSI148_LCSR_IT2_ITSAL 0x344
294#define TSI148_LCSR_IT2_ITEAU 0x348
295#define TSI148_LCSR_IT2_ITEAL 0x34C
296#define TSI148_LCSR_IT2_ITOFU 0x350
297#define TSI148_LCSR_IT2_ITOFL 0x354
298#define TSI148_LCSR_IT2_ITAT 0x358
299
300#define TSI148_LCSR_IT3_ITSAU 0x360
301#define TSI148_LCSR_IT3_ITSAL 0x364
302#define TSI148_LCSR_IT3_ITEAU 0x368
303#define TSI148_LCSR_IT3_ITEAL 0x36C
304#define TSI148_LCSR_IT3_ITOFU 0x370
305#define TSI148_LCSR_IT3_ITOFL 0x374
306#define TSI148_LCSR_IT3_ITAT 0x378
307
308#define TSI148_LCSR_IT4_ITSAU 0x380
309#define TSI148_LCSR_IT4_ITSAL 0x384
310#define TSI148_LCSR_IT4_ITEAU 0x388
311#define TSI148_LCSR_IT4_ITEAL 0x38C
312#define TSI148_LCSR_IT4_ITOFU 0x390
313#define TSI148_LCSR_IT4_ITOFL 0x394
314#define TSI148_LCSR_IT4_ITAT 0x398
315
316#define TSI148_LCSR_IT5_ITSAU 0x3A0
317#define TSI148_LCSR_IT5_ITSAL 0x3A4
318#define TSI148_LCSR_IT5_ITEAU 0x3A8
319#define TSI148_LCSR_IT5_ITEAL 0x3AC
320#define TSI148_LCSR_IT5_ITOFU 0x3B0
321#define TSI148_LCSR_IT5_ITOFL 0x3B4
322#define TSI148_LCSR_IT5_ITAT 0x3B8
323
324#define TSI148_LCSR_IT6_ITSAU 0x3C0
325#define TSI148_LCSR_IT6_ITSAL 0x3C4
326#define TSI148_LCSR_IT6_ITEAU 0x3C8
327#define TSI148_LCSR_IT6_ITEAL 0x3CC
328#define TSI148_LCSR_IT6_ITOFU 0x3D0
329#define TSI148_LCSR_IT6_ITOFL 0x3D4
330#define TSI148_LCSR_IT6_ITAT 0x3D8
331
332#define TSI148_LCSR_IT7_ITSAU 0x3E0
333#define TSI148_LCSR_IT7_ITSAL 0x3E4
334#define TSI148_LCSR_IT7_ITEAU 0x3E8
335#define TSI148_LCSR_IT7_ITEAL 0x3EC
336#define TSI148_LCSR_IT7_ITOFU 0x3F0
337#define TSI148_LCSR_IT7_ITOFL 0x3F4
338#define TSI148_LCSR_IT7_ITAT 0x3F8
339
340#define TSI148_LCSR_IT0 0x300
341#define TSI148_LCSR_IT1 0x320
342#define TSI148_LCSR_IT2 0x340
343#define TSI148_LCSR_IT3 0x360
344#define TSI148_LCSR_IT4 0x380
345#define TSI148_LCSR_IT5 0x3A0
346#define TSI148_LCSR_IT6 0x3C0
347#define TSI148_LCSR_IT7 0x3E0
348
349static const int TSI148_LCSR_IT[8] = { TSI148_LCSR_IT0, TSI148_LCSR_IT1,
350 TSI148_LCSR_IT2, TSI148_LCSR_IT3,
351 TSI148_LCSR_IT4, TSI148_LCSR_IT5,
352 TSI148_LCSR_IT6, TSI148_LCSR_IT7 };
353
354#define TSI148_LCSR_OFFSET_ITSAU 0x0
355#define TSI148_LCSR_OFFSET_ITSAL 0x4
356#define TSI148_LCSR_OFFSET_ITEAU 0x8
357#define TSI148_LCSR_OFFSET_ITEAL 0xC
358#define TSI148_LCSR_OFFSET_ITOFU 0x10
359#define TSI148_LCSR_OFFSET_ITOFL 0x14
360#define TSI148_LCSR_OFFSET_ITAT 0x18
361
362/*
363 * Inbound Translation GCSR
364 * offset 0x400
365 */
366#define TSI148_LCSR_GBAU 0x400
367#define TSI148_LCSR_GBAL 0x404
368#define TSI148_LCSR_GCSRAT 0x408
369
370/*
371 * Inbound Translation CRG
372 * offset 0x40C
373 */
374#define TSI148_LCSR_CBAU 0x40C
375#define TSI148_LCSR_CBAL 0x410
376#define TSI148_LCSR_CSRAT 0x414
377
378/*
379 * Inbound Translation CR/CSR
380 * CRG
381 * offset 0x418
382 */
383#define TSI148_LCSR_CROU 0x418
384#define TSI148_LCSR_CROL 0x41C
385#define TSI148_LCSR_CRAT 0x420
386
387/*
388 * Inbound Translation Location Monitor
389 * offset 0x424
390 */
391#define TSI148_LCSR_LMBAU 0x424
392#define TSI148_LCSR_LMBAL 0x428
393#define TSI148_LCSR_LMAT 0x42C
394
395/*
396 * VMEbus Interrupt Control.
397 * offset 0x430
398 */
399#define TSI148_LCSR_BCU 0x430
400#define TSI148_LCSR_BCL 0x434
401#define TSI148_LCSR_BPGTR 0x438
402#define TSI148_LCSR_BPCTR 0x43C
403#define TSI148_LCSR_VICR 0x440
404
405/*
406 * Local Bus Interrupt Control.
407 * offset 0x448
408 */
409#define TSI148_LCSR_INTEN 0x448
410#define TSI148_LCSR_INTEO 0x44C
411#define TSI148_LCSR_INTS 0x450
412#define TSI148_LCSR_INTC 0x454
413#define TSI148_LCSR_INTM1 0x458
414#define TSI148_LCSR_INTM2 0x45C
415
416/*
417 * DMA Controllers
418 * offset 0x500
419 */
420#define TSI148_LCSR_DCTL0 0x500
421#define TSI148_LCSR_DSTA0 0x504
422#define TSI148_LCSR_DCSAU0 0x508
423#define TSI148_LCSR_DCSAL0 0x50C
424#define TSI148_LCSR_DCDAU0 0x510
425#define TSI148_LCSR_DCDAL0 0x514
426#define TSI148_LCSR_DCLAU0 0x518
427#define TSI148_LCSR_DCLAL0 0x51C
428#define TSI148_LCSR_DSAU0 0x520
429#define TSI148_LCSR_DSAL0 0x524
430#define TSI148_LCSR_DDAU0 0x528
431#define TSI148_LCSR_DDAL0 0x52C
432#define TSI148_LCSR_DSAT0 0x530
433#define TSI148_LCSR_DDAT0 0x534
434#define TSI148_LCSR_DNLAU0 0x538
435#define TSI148_LCSR_DNLAL0 0x53C
436#define TSI148_LCSR_DCNT0 0x540
437#define TSI148_LCSR_DDBS0 0x544
438
439#define TSI148_LCSR_DCTL1 0x580
440#define TSI148_LCSR_DSTA1 0x584
441#define TSI148_LCSR_DCSAU1 0x588
442#define TSI148_LCSR_DCSAL1 0x58C
443#define TSI148_LCSR_DCDAU1 0x590
444#define TSI148_LCSR_DCDAL1 0x594
445#define TSI148_LCSR_DCLAU1 0x598
446#define TSI148_LCSR_DCLAL1 0x59C
447#define TSI148_LCSR_DSAU1 0x5A0
448#define TSI148_LCSR_DSAL1 0x5A4
449#define TSI148_LCSR_DDAU1 0x5A8
450#define TSI148_LCSR_DDAL1 0x5AC
451#define TSI148_LCSR_DSAT1 0x5B0
452#define TSI148_LCSR_DDAT1 0x5B4
453#define TSI148_LCSR_DNLAU1 0x5B8
454#define TSI148_LCSR_DNLAL1 0x5BC
455#define TSI148_LCSR_DCNT1 0x5C0
456#define TSI148_LCSR_DDBS1 0x5C4
457
458#define TSI148_LCSR_DMA0 0x500
459#define TSI148_LCSR_DMA1 0x580
460
461static const int TSI148_LCSR_DMA[TSI148_MAX_DMA] = { TSI148_LCSR_DMA0,
462 TSI148_LCSR_DMA1 };
463
464#define TSI148_LCSR_OFFSET_DCTL 0x0
465#define TSI148_LCSR_OFFSET_DSTA 0x4
466#define TSI148_LCSR_OFFSET_DCSAU 0x8
467#define TSI148_LCSR_OFFSET_DCSAL 0xC
468#define TSI148_LCSR_OFFSET_DCDAU 0x10
469#define TSI148_LCSR_OFFSET_DCDAL 0x14
470#define TSI148_LCSR_OFFSET_DCLAU 0x18
471#define TSI148_LCSR_OFFSET_DCLAL 0x1C
472#define TSI148_LCSR_OFFSET_DSAU 0x20
473#define TSI148_LCSR_OFFSET_DSAL 0x24
474#define TSI148_LCSR_OFFSET_DDAU 0x28
475#define TSI148_LCSR_OFFSET_DDAL 0x2C
476#define TSI148_LCSR_OFFSET_DSAT 0x30
477#define TSI148_LCSR_OFFSET_DDAT 0x34
478#define TSI148_LCSR_OFFSET_DNLAU 0x38
479#define TSI148_LCSR_OFFSET_DNLAL 0x3C
480#define TSI148_LCSR_OFFSET_DCNT 0x40
481#define TSI148_LCSR_OFFSET_DDBS 0x44
482
483/*
484 * GCSR Register Group
485 */
486
487/*
488 * GCSR CRG
489 * offset 0x00 0x600 - DEVI/VENI
490 * offset 0x04 0x604 - CTRL/GA/REVID
491 * offset 0x08 0x608 - Semaphore3/2/1/0
492 * offset 0x0C 0x60C - Seamphore7/6/5/4
493 */
494#define TSI148_GCSR_ID 0x600
495#define TSI148_GCSR_CSR 0x604
496#define TSI148_GCSR_SEMA0 0x608
497#define TSI148_GCSR_SEMA1 0x60C
498
499/*
500 * Mail Box
501 * GCSR CRG
502 * offset 0x10 0x610 - Mailbox0
503 */
504#define TSI148_GCSR_MBOX0 0x610
505#define TSI148_GCSR_MBOX1 0x614
506#define TSI148_GCSR_MBOX2 0x618
507#define TSI148_GCSR_MBOX3 0x61C
508
509static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
510 TSI148_GCSR_MBOX1,
511 TSI148_GCSR_MBOX2,
512 TSI148_GCSR_MBOX3 };
513
514/*
515 * CR/CSR
516 */
517
518/*
519 * CR/CSR CRG
520 * offset 0x7FFF4 0xFF4 - CSRBCR
521 * offset 0x7FFF8 0xFF8 - CSRBSR
522 * offset 0x7FFFC 0xFFC - CBAR
523 */
524#define TSI148_CSRBCR 0xFF4
525#define TSI148_CSRBSR 0xFF8
526#define TSI148_CBAR 0xFFC
527
528/*
529 * TSI148 Register Bit Definitions
530 */
531
532/*
533 * PFCS Register Set
534 */
535#define TSI148_PCFS_CMMD_SERR BIT(8) /* SERR_L out pin ssys err */
536#define TSI148_PCFS_CMMD_PERR BIT(6) /* PERR_L out pin parity */
537#define TSI148_PCFS_CMMD_MSTR BIT(2) /* PCI bus master */
538#define TSI148_PCFS_CMMD_MEMSP BIT(1) /* PCI mem space access */
539#define TSI148_PCFS_CMMD_IOSP BIT(0) /* PCI I/O space enable */
540
541#define TSI148_PCFS_STAT_RCPVE BIT(15) /* Detected Parity Error */
542#define TSI148_PCFS_STAT_SIGSE BIT(14) /* Signalled System Error */
543#define TSI148_PCFS_STAT_RCVMA BIT(13) /* Received Master Abort */
544#define TSI148_PCFS_STAT_RCVTA BIT(12) /* Received Target Abort */
545#define TSI148_PCFS_STAT_SIGTA BIT(11) /* Signalled Target Abort */
546#define TSI148_PCFS_STAT_SELTIM (3 << 9) /* DELSEL Timing */
547#define TSI148_PCFS_STAT_DPAR BIT(8) /* Data Parity Err Reported */
548#define TSI148_PCFS_STAT_FAST BIT(7) /* Fast back-to-back Cap */
549#define TSI148_PCFS_STAT_P66M BIT(5) /* 66 MHz Capable */
550#define TSI148_PCFS_STAT_CAPL BIT(4) /* Capab List - address $34 */
551
552/*
553 * Revision ID/Class Code Registers (CRG +$008)
554 */
555#define TSI148_PCFS_CLAS_M (0xFF << 24) /* Class ID */
556#define TSI148_PCFS_SUBCLAS_M (0xFF << 16) /* Sub-Class ID */
557#define TSI148_PCFS_PROGIF_M (0xFF << 8) /* Sub-Class ID */
558#define TSI148_PCFS_REVID_M (0xFF << 0) /* Rev ID */
559
560/*
561 * Cache Line Size/ Master Latency Timer/ Header Type Registers (CRG + $00C)
562 */
563#define TSI148_PCFS_HEAD_M (0xFF << 16) /* Master Lat Timer */
564#define TSI148_PCFS_MLAT_M (0xFF << 8) /* Master Lat Timer */
565#define TSI148_PCFS_CLSZ_M (0xFF << 0) /* Cache Line Size */
566
567/*
568 * Memory Base Address Lower Reg (CRG + $010)
569 */
570#define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF << 12) /* Base Addr Lower Mask */
571#define TSI148_PCFS_MBARL_PRE BIT(3) /* Prefetch */
572#define TSI148_PCFS_MBARL_MTYPE_M (3 << 1) /* Memory Type Mask */
573#define TSI148_PCFS_MBARL_IOMEM BIT(0) /* I/O Space Indicator */
574
575/*
576 * Message Signaled Interrupt Capabilities Register (CRG + $040)
577 */
578#define TSI148_PCFS_MSICAP_64BAC BIT(7) /* 64-bit Address Capable */
579#define TSI148_PCFS_MSICAP_MME_M (7 << 4) /* Multiple Msg Enable Mask */
580#define TSI148_PCFS_MSICAP_MMC_M (7 << 1) /* Multiple Msg Capable Mask */
581#define TSI148_PCFS_MSICAP_MSIEN BIT(0) /* Msg signaled INT Enable */
582
583/*
584 * Message Address Lower Register (CRG +$044)
585 */
586#define TSI148_PCFS_MSIAL_M (0x3FFFFFFF << 2) /* Mask */
587
588/*
589 * Message Data Register (CRG + 4C)
590 */
591#define TSI148_PCFS_MSIMD_M (0xFFFF << 0) /* Mask */
592
593/*
594 * PCI-X Capabilities Register (CRG + $050)
595 */
596#define TSI148_PCFS_PCIXCAP_MOST_M (7 << 4) /* Max outstanding Split Tran */
597#define TSI148_PCFS_PCIXCAP_MMRBC_M (3 << 2) /* Max Mem Read byte cnt */
598#define TSI148_PCFS_PCIXCAP_ERO BIT(1) /* Enable Relaxed Ordering */
599#define TSI148_PCFS_PCIXCAP_DPERE BIT(0) /* Data Parity Recover Enable */
600
601/*
602 * PCI-X Status Register (CRG +$054)
603 */
604#define TSI148_PCFS_PCIXSTAT_RSCEM BIT(29) /* Received Split Comp Error */
605#define TSI148_PCFS_PCIXSTAT_DMCRS_M (7 << 26) /* max Cumulative Read Size */
606#define TSI148_PCFS_PCIXSTAT_DMOST_M (7 << 23) /* max outstanding Split Trans */
607#define TSI148_PCFS_PCIXSTAT_DMMRC_M (3 << 21) /* max mem read byte count */
608#define TSI148_PCFS_PCIXSTAT_DC BIT(20) /* Device Complexity */
609#define TSI148_PCFS_PCIXSTAT_USC BIT(19) /* Unexpected Split comp */
610#define TSI148_PCFS_PCIXSTAT_SCD BIT(18) /* Split completion discard */
611#define TSI148_PCFS_PCIXSTAT_133C BIT(17) /* 133MHz capable */
612#define TSI148_PCFS_PCIXSTAT_64D BIT(16) /* 64 bit device */
613#define TSI148_PCFS_PCIXSTAT_BN_M (0xFF << 8) /* Bus number */
614#define TSI148_PCFS_PCIXSTAT_DN_M (0x1F << 3) /* Device number */
615#define TSI148_PCFS_PCIXSTAT_FN_M (7 << 0) /* Function Number */
616
617/*
618 * LCSR Registers
619 */
620
621/*
622 * Outbound Translation Starting Address Lower
623 */
624#define TSI148_LCSR_OTSAL_M (0xFFFF << 16) /* Mask */
625
626/*
627 * Outbound Translation Ending Address Lower
628 */
629#define TSI148_LCSR_OTEAL_M (0xFFFF << 16) /* Mask */
630
631/*
632 * Outbound Translation Offset Lower
633 */
634#define TSI148_LCSR_OTOFFL_M (0xFFFF << 16) /* Mask */
635
636/*
637 * Outbound Translation 2eSST Broadcast Select
638 */
639#define TSI148_LCSR_OTBS_M (0xFFFFF << 0) /* Mask */
640
641/*
642 * Outbound Translation Attribute
643 */
644#define TSI148_LCSR_OTAT_EN BIT(31) /* Window Enable */
645#define TSI148_LCSR_OTAT_MRPFD BIT(18) /* Prefetch Disable */
646
647#define TSI148_LCSR_OTAT_PFS_M (3 << 16) /* Prefetch Size Mask */
648#define TSI148_LCSR_OTAT_PFS_2 (0 << 16) /* 2 Cache Lines P Size */
649#define TSI148_LCSR_OTAT_PFS_4 BIT(16) /* 4 Cache Lines P Size */
650#define TSI148_LCSR_OTAT_PFS_8 (2 << 16) /* 8 Cache Lines P Size */
651#define TSI148_LCSR_OTAT_PFS_16 (3 << 16) /* 16 Cache Lines P Size */
652
653#define TSI148_LCSR_OTAT_2eSSTM_M (7 << 11) /* 2eSST Xfer Rate Mask */
654#define TSI148_LCSR_OTAT_2eSSTM_160 (0 << 11) /* 160MB/s 2eSST Xfer Rate */
655#define TSI148_LCSR_OTAT_2eSSTM_267 BIT(11) /* 267MB/s 2eSST Xfer Rate */
656#define TSI148_LCSR_OTAT_2eSSTM_320 (2 << 11) /* 320MB/s 2eSST Xfer Rate */
657
658#define TSI148_LCSR_OTAT_TM_M (7 << 8) /* Xfer Protocol Mask */
659#define TSI148_LCSR_OTAT_TM_SCT (0 << 8) /* SCT Xfer Protocol */
660#define TSI148_LCSR_OTAT_TM_BLT BIT(8) /* BLT Xfer Protocol */
661#define TSI148_LCSR_OTAT_TM_MBLT (2 << 8) /* MBLT Xfer Protocol */
662#define TSI148_LCSR_OTAT_TM_2eVME (3 << 8) /* 2eVME Xfer Protocol */
663#define TSI148_LCSR_OTAT_TM_2eSST (4 << 8) /* 2eSST Xfer Protocol */
664#define TSI148_LCSR_OTAT_TM_2eSSTB (5 << 8) /* 2eSST Bcast Xfer Protocol */
665
666#define TSI148_LCSR_OTAT_DBW_M (3 << 6) /* Max Data Width */
667#define TSI148_LCSR_OTAT_DBW_16 (0 << 6) /* 16-bit Data Width */
668#define TSI148_LCSR_OTAT_DBW_32 BIT(6) /* 32-bit Data Width */
669
670#define TSI148_LCSR_OTAT_SUP BIT(5) /* Supervisory Access */
671#define TSI148_LCSR_OTAT_PGM BIT(4) /* Program Access */
672
673#define TSI148_LCSR_OTAT_AMODE_M (0xf << 0) /* Address Mode Mask */
674#define TSI148_LCSR_OTAT_AMODE_A16 (0 << 0) /* A16 Address Space */
675#define TSI148_LCSR_OTAT_AMODE_A24 BIT(0) /* A24 Address Space */
676#define TSI148_LCSR_OTAT_AMODE_A32 (2 << 0) /* A32 Address Space */
677#define TSI148_LCSR_OTAT_AMODE_A64 (4 << 0) /* A32 Address Space */
678#define TSI148_LCSR_OTAT_AMODE_CRCSR (5 << 0) /* CR/CSR Address Space */
679#define TSI148_LCSR_OTAT_AMODE_USER1 (8 << 0) /* User1 Address Space */
680#define TSI148_LCSR_OTAT_AMODE_USER2 (9 << 0) /* User2 Address Space */
681#define TSI148_LCSR_OTAT_AMODE_USER3 (10 << 0) /* User3 Address Space */
682#define TSI148_LCSR_OTAT_AMODE_USER4 (11 << 0) /* User4 Address Space */
683
684/*
685 * VME Master Control Register CRG+$234
686 */
687#define TSI148_LCSR_VMCTRL_VSA BIT(27) /* VMEbus Stop Ack */
688#define TSI148_LCSR_VMCTRL_VS BIT(26) /* VMEbus Stop */
689#define TSI148_LCSR_VMCTRL_DHB BIT(25) /* Device Has Bus */
690#define TSI148_LCSR_VMCTRL_DWB BIT(24) /* Device Wants Bus */
691
692#define TSI148_LCSR_VMCTRL_RMWEN BIT(20) /* RMW Enable */
693
694#define TSI148_LCSR_VMCTRL_ATO_M (7 << 16) /* Master Access Time-out Mask */
695#define TSI148_LCSR_VMCTRL_ATO_32 (0 << 16) /* 32 us */
696#define TSI148_LCSR_VMCTRL_ATO_128 BIT(16) /* 128 us */
697#define TSI148_LCSR_VMCTRL_ATO_512 (2 << 16) /* 512 us */
698#define TSI148_LCSR_VMCTRL_ATO_2M (3 << 16) /* 2 ms */
699#define TSI148_LCSR_VMCTRL_ATO_8M (4 << 16) /* 8 ms */
700#define TSI148_LCSR_VMCTRL_ATO_32M (5 << 16) /* 32 ms */
701#define TSI148_LCSR_VMCTRL_ATO_128M (6 << 16) /* 128 ms */
702#define TSI148_LCSR_VMCTRL_ATO_DIS (7 << 16) /* Disabled */
703
704#define TSI148_LCSR_VMCTRL_VTOFF_M (7 << 12) /* VMEbus Master Time off */
705#define TSI148_LCSR_VMCTRL_VTOFF_0 (0 << 12) /* 0us */
706#define TSI148_LCSR_VMCTRL_VTOFF_1 BIT(12) /* 1us */
707#define TSI148_LCSR_VMCTRL_VTOFF_2 (2 << 12) /* 2us */
708#define TSI148_LCSR_VMCTRL_VTOFF_4 (3 << 12) /* 4us */
709#define TSI148_LCSR_VMCTRL_VTOFF_8 (4 << 12) /* 8us */
710#define TSI148_LCSR_VMCTRL_VTOFF_16 (5 << 12) /* 16us */
711#define TSI148_LCSR_VMCTRL_VTOFF_32 (6 << 12) /* 32us */
712#define TSI148_LCSR_VMCTRL_VTOFF_64 (7 << 12) /* 64us */
713
714#define TSI148_LCSR_VMCTRL_VTON_M (7 << 8) /* VMEbus Master Time On */
715#define TSI148_LCSR_VMCTRL_VTON_4 (0 << 8) /* 8us */
716#define TSI148_LCSR_VMCTRL_VTON_8 BIT(8) /* 8us */
717#define TSI148_LCSR_VMCTRL_VTON_16 (2 << 8) /* 16us */
718#define TSI148_LCSR_VMCTRL_VTON_32 (3 << 8) /* 32us */
719#define TSI148_LCSR_VMCTRL_VTON_64 (4 << 8) /* 64us */
720#define TSI148_LCSR_VMCTRL_VTON_128 (5 << 8) /* 128us */
721#define TSI148_LCSR_VMCTRL_VTON_256 (6 << 8) /* 256us */
722#define TSI148_LCSR_VMCTRL_VTON_512 (7 << 8) /* 512us */
723
724#define TSI148_LCSR_VMCTRL_VREL_M (3 << 3) /* VMEbus Master Rel Mode Mask
725 */
726#define TSI148_LCSR_VMCTRL_VREL_T_D (0 << 3) /* Time on or Done */
727#define TSI148_LCSR_VMCTRL_VREL_T_R_D BIT(3) /* Time on and REQ or Done */
728#define TSI148_LCSR_VMCTRL_VREL_T_B_D (2 << 3) /* Time on and BCLR or Done */
729#define TSI148_LCSR_VMCTRL_VREL_T_D_R (3 << 3) /* Time on or Done and REQ */
730
731#define TSI148_LCSR_VMCTRL_VFAIR BIT(2) /* VMEbus Master Fair Mode */
732#define TSI148_LCSR_VMCTRL_VREQL_M (3 << 0) /* VMEbus Master Req Level Mask
733 */
734
735/*
736 * VMEbus Control Register CRG+$238
737 */
738#define TSI148_LCSR_VCTRL_LRE BIT(31) /* Late Retry Enable */
739
740#define TSI148_LCSR_VCTRL_DLT_M (0xF << 24) /* Deadlock Timer */
741#define TSI148_LCSR_VCTRL_DLT_OFF (0 << 24) /* Deadlock Timer Off */
742#define TSI148_LCSR_VCTRL_DLT_16 BIT(24) /* 16 VCLKS */
743#define TSI148_LCSR_VCTRL_DLT_32 (2 << 24) /* 32 VCLKS */
744#define TSI148_LCSR_VCTRL_DLT_64 (3 << 24) /* 64 VCLKS */
745#define TSI148_LCSR_VCTRL_DLT_128 (4 << 24) /* 128 VCLKS */
746#define TSI148_LCSR_VCTRL_DLT_256 (5 << 24) /* 256 VCLKS */
747#define TSI148_LCSR_VCTRL_DLT_512 (6 << 24) /* 512 VCLKS */
748#define TSI148_LCSR_VCTRL_DLT_1024 (7 << 24) /* 1024 VCLKS */
749#define TSI148_LCSR_VCTRL_DLT_2048 (8 << 24) /* 2048 VCLKS */
750#define TSI148_LCSR_VCTRL_DLT_4096 (9 << 24) /* 4096 VCLKS */
751#define TSI148_LCSR_VCTRL_DLT_8192 (0xA << 24) /* 8192 VCLKS */
752#define TSI148_LCSR_VCTRL_DLT_16384 (0xB << 24) /* 16384 VCLKS */
753#define TSI148_LCSR_VCTRL_DLT_32768 (0xC << 24) /* 32768 VCLKS */
754
755#define TSI148_LCSR_VCTRL_NERBB BIT(20) /* No Early Release of Bus Busy */
756
757#define TSI148_LCSR_VCTRL_SRESET BIT(17) /* System Reset */
758#define TSI148_LCSR_VCTRL_LRESET BIT(16) /* Local Reset */
759
760#define TSI148_LCSR_VCTRL_SFAILAI BIT(15) /* SYSFAIL Auto Slot ID */
761#define TSI148_LCSR_VCTRL_BID_M (0x1F << 8) /* Broadcast ID Mask */
762
763#define TSI148_LCSR_VCTRL_ATOEN BIT(7) /* Arbiter Time-out Enable */
764#define TSI148_LCSR_VCTRL_ROBIN BIT(6) /* VMEbus Round Robin */
765
766#define TSI148_LCSR_VCTRL_GTO_M (7 << 0) /* VMEbus Global Time-out Mask*/
767#define TSI148_LCSR_VCTRL_GTO_8 (0 << 0) /* 8 us */
768#define TSI148_LCSR_VCTRL_GTO_16 BIT(0) /* 16 us */
769#define TSI148_LCSR_VCTRL_GTO_32 (2 << 0) /* 32 us */
770#define TSI148_LCSR_VCTRL_GTO_64 (3 << 0) /* 64 us */
771#define TSI148_LCSR_VCTRL_GTO_128 (4 << 0) /* 128 us */
772#define TSI148_LCSR_VCTRL_GTO_256 (5 << 0) /* 256 us */
773#define TSI148_LCSR_VCTRL_GTO_512 (6 << 0) /* 512 us */
774#define TSI148_LCSR_VCTRL_GTO_DIS (7 << 0) /* Disabled */
775
776/*
777 * VMEbus Status Register CRG + $23C
778 */
779#define TSI148_LCSR_VSTAT_CPURST BIT(15) /* Clear power up reset */
780#define TSI148_LCSR_VSTAT_BRDFL BIT(14) /* Board fail */
781#define TSI148_LCSR_VSTAT_PURSTS BIT(12) /* Power up reset status */
782#define TSI148_LCSR_VSTAT_BDFAILS BIT(11) /* Board Fail Status */
783#define TSI148_LCSR_VSTAT_SYSFAILS BIT(10) /* System Fail Status */
784#define TSI148_LCSR_VSTAT_ACFAILS BIT(9) /* AC fail status */
785#define TSI148_LCSR_VSTAT_SCONS BIT(8) /* System Cont Status */
786#define TSI148_LCSR_VSTAT_GAP BIT(5) /* Geographic Addr Parity */
787#define TSI148_LCSR_VSTAT_GA_M (0x1F << 0) /* Geographic Addr Mask */
788
789/*
790 * PCI Configuration Status Register CRG+$240
791 */
792#define TSI148_LCSR_PSTAT_REQ64S BIT(6) /* Request 64 status set */
793#define TSI148_LCSR_PSTAT_M66ENS BIT(5) /* M66ENS 66Mhz enable */
794#define TSI148_LCSR_PSTAT_FRAMES BIT(4) /* Frame Status */
795#define TSI148_LCSR_PSTAT_IRDYS BIT(3) /* IRDY status */
796#define TSI148_LCSR_PSTAT_DEVSELS BIT(2) /* DEVL status */
797#define TSI148_LCSR_PSTAT_STOPS BIT(1) /* STOP status */
798#define TSI148_LCSR_PSTAT_TRDYS BIT(0) /* TRDY status */
799
800/*
801 * VMEbus Exception Attributes Register CRG + $268
802 */
803#define TSI148_LCSR_VEAT_VES BIT(31) /* Status */
804#define TSI148_LCSR_VEAT_VEOF BIT(30) /* Overflow */
805#define TSI148_LCSR_VEAT_VESCL BIT(29) /* Status Clear */
806#define TSI148_LCSR_VEAT_2EOT BIT(21) /* 2e Odd Termination */
807#define TSI148_LCSR_VEAT_2EST BIT(20) /* 2e Slave terminated */
808#define TSI148_LCSR_VEAT_BERR BIT(19) /* Bus Error */
809#define TSI148_LCSR_VEAT_LWORD BIT(18) /* LWORD_ signal state */
810#define TSI148_LCSR_VEAT_WRITE BIT(17) /* WRITE_ signal state */
811#define TSI148_LCSR_VEAT_IACK BIT(16) /* IACK_ signal state */
812#define TSI148_LCSR_VEAT_DS1 BIT(15) /* DS1_ signal state */
813#define TSI148_LCSR_VEAT_DS0 BIT(14) /* DS0_ signal state */
814#define TSI148_LCSR_VEAT_AM_M (0x3F << 8) /* Address Mode Mask */
815#define TSI148_LCSR_VEAT_XAM_M (0xFF << 0) /* Master AMode Mask */
816
817/*
818 * VMEbus PCI Error Diagnostics PCI/X Attributes Register CRG + $280
819 */
820#define TSI148_LCSR_EDPAT_EDPCL BIT(29)
821
822/*
823 * Inbound Translation Starting Address Lower
824 */
825#define TSI148_LCSR_ITSAL6432_M (0xFFFF << 16) /* Mask */
826#define TSI148_LCSR_ITSAL24_M (0x00FFF << 12) /* Mask */
827#define TSI148_LCSR_ITSAL16_M (0x0000FFF << 4) /* Mask */
828
829/*
830 * Inbound Translation Ending Address Lower
831 */
832#define TSI148_LCSR_ITEAL6432_M (0xFFFF << 16) /* Mask */
833#define TSI148_LCSR_ITEAL24_M (0x00FFF << 12) /* Mask */
834#define TSI148_LCSR_ITEAL16_M (0x0000FFF << 4) /* Mask */
835
836/*
837 * Inbound Translation Offset Lower
838 */
839#define TSI148_LCSR_ITOFFL6432_M (0xFFFF << 16) /* Mask */
840#define TSI148_LCSR_ITOFFL24_M (0xFFFFF << 12) /* Mask */
841#define TSI148_LCSR_ITOFFL16_M (0xFFFFFFF << 4) /* Mask */
842
843/*
844 * Inbound Translation Attribute
845 */
846#define TSI148_LCSR_ITAT_EN BIT(31) /* Window Enable */
847#define TSI148_LCSR_ITAT_TH BIT(18) /* Prefetch Threshold */
848
849#define TSI148_LCSR_ITAT_VFS_M (3 << 16) /* Virtual FIFO Size Mask */
850#define TSI148_LCSR_ITAT_VFS_64 (0 << 16) /* 64 bytes Virtual FIFO Size */
851#define TSI148_LCSR_ITAT_VFS_128 BIT(16) /* 128 bytes Virtual FIFO Sz */
852#define TSI148_LCSR_ITAT_VFS_256 (2 << 16) /* 256 bytes Virtual FIFO Sz */
853#define TSI148_LCSR_ITAT_VFS_512 (3 << 16) /* 512 bytes Virtual FIFO Sz */
854
855#define TSI148_LCSR_ITAT_2eSSTM_M (7 << 12) /* 2eSST Xfer Rate Mask */
856#define TSI148_LCSR_ITAT_2eSSTM_160 (0 << 12) /* 160MB/s 2eSST Xfer Rate */
857#define TSI148_LCSR_ITAT_2eSSTM_267 BIT(12) /* 267MB/s 2eSST Xfer Rate */
858#define TSI148_LCSR_ITAT_2eSSTM_320 (2 << 12) /* 320MB/s 2eSST Xfer Rate */
859
860#define TSI148_LCSR_ITAT_2eSSTB BIT(11) /* 2eSST Bcast Xfer Protocol */
861#define TSI148_LCSR_ITAT_2eSST BIT(10) /* 2eSST Xfer Protocol */
862#define TSI148_LCSR_ITAT_2eVME BIT(9) /* 2eVME Xfer Protocol */
863#define TSI148_LCSR_ITAT_MBLT BIT(8) /* MBLT Xfer Protocol */
864#define TSI148_LCSR_ITAT_BLT BIT(7) /* BLT Xfer Protocol */
865
866#define TSI148_LCSR_ITAT_AS_M (7 << 4) /* Address Space Mask */
867#define TSI148_LCSR_ITAT_AS_A16 (0 << 4) /* A16 Address Space */
868#define TSI148_LCSR_ITAT_AS_A24 BIT(4) /* A24 Address Space */
869#define TSI148_LCSR_ITAT_AS_A32 (2 << 4) /* A32 Address Space */
870#define TSI148_LCSR_ITAT_AS_A64 (4 << 4) /* A64 Address Space */
871
872#define TSI148_LCSR_ITAT_SUPR BIT(3) /* Supervisor Access */
873#define TSI148_LCSR_ITAT_NPRIV BIT(2) /* Non-Priv (User) Access */
874#define TSI148_LCSR_ITAT_PGM BIT(1) /* Program Access */
875#define TSI148_LCSR_ITAT_DATA BIT(0) /* Data Access */
876
877/*
878 * GCSR Base Address Lower Address CRG +$404
879 */
880#define TSI148_LCSR_GBAL_M (0x7FFFFFF << 5) /* Mask */
881
882/*
883 * GCSR Attribute Register CRG + $408
884 */
885#define TSI148_LCSR_GCSRAT_EN BIT(7) /* Enable access to GCSR */
886
887#define TSI148_LCSR_GCSRAT_AS_M (7 << 4) /* Address Space Mask */
888#define TSI148_LCSR_GCSRAT_AS_A16 (0 << 4) /* Address Space 16 */
889#define TSI148_LCSR_GCSRAT_AS_A24 BIT(4) /* Address Space 24 */
890#define TSI148_LCSR_GCSRAT_AS_A32 (2 << 4) /* Address Space 32 */
891#define TSI148_LCSR_GCSRAT_AS_A64 (4 << 4) /* Address Space 64 */
892
893#define TSI148_LCSR_GCSRAT_SUPR BIT(3) /* Sup set -GCSR decoder */
894#define TSI148_LCSR_GCSRAT_NPRIV BIT(2) /* Non-Privliged set - CGSR */
895#define TSI148_LCSR_GCSRAT_PGM BIT(1) /* Program set - GCSR decoder */
896#define TSI148_LCSR_GCSRAT_DATA BIT(0) /* DATA set GCSR decoder */
897
898/*
899 * CRG Base Address Lower Address CRG + $410
900 */
901#define TSI148_LCSR_CBAL_M (0xFFFFF << 12)
902
903/*
904 * CRG Attribute Register CRG + $414
905 */
906#define TSI148_LCSR_CRGAT_EN BIT(7) /* Enable PRG Access */
907
908#define TSI148_LCSR_CRGAT_AS_M (7 << 4) /* Address Space */
909#define TSI148_LCSR_CRGAT_AS_A16 (0 << 4) /* Address Space 16 */
910#define TSI148_LCSR_CRGAT_AS_A24 BIT(4) /* Address Space 24 */
911#define TSI148_LCSR_CRGAT_AS_A32 (2 << 4) /* Address Space 32 */
912#define TSI148_LCSR_CRGAT_AS_A64 (4 << 4) /* Address Space 64 */
913
914#define TSI148_LCSR_CRGAT_SUPR BIT(3) /* Supervisor Access */
915#define TSI148_LCSR_CRGAT_NPRIV BIT(2) /* Non-Privliged(User) Access */
916#define TSI148_LCSR_CRGAT_PGM BIT(1) /* Program Access */
917#define TSI148_LCSR_CRGAT_DATA BIT(0) /* Data Access */
918
919/*
920 * CR/CSR Offset Lower Register CRG + $41C
921 */
922#define TSI148_LCSR_CROL_M (0x1FFF << 19) /* Mask */
923
924/*
925 * CR/CSR Attribute register CRG + $420
926 */
927#define TSI148_LCSR_CRAT_EN BIT(7) /* Enable access to CR/CSR */
928
929/*
930 * Location Monitor base address lower register CRG + $428
931 */
932#define TSI148_LCSR_LMBAL_M (0x7FFFFFF << 5) /* Mask */
933
934/*
935 * Location Monitor Attribute Register CRG + $42C
936 */
937#define TSI148_LCSR_LMAT_EN BIT(7) /* Enable Location Monitor */
938
939#define TSI148_LCSR_LMAT_AS_M (7 << 4) /* Address Space MASK */
940#define TSI148_LCSR_LMAT_AS_A16 (0 << 4) /* A16 */
941#define TSI148_LCSR_LMAT_AS_A24 BIT(4) /* A24 */
942#define TSI148_LCSR_LMAT_AS_A32 (2 << 4) /* A32 */
943#define TSI148_LCSR_LMAT_AS_A64 (4 << 4) /* A64 */
944
945#define TSI148_LCSR_LMAT_SUPR BIT(3) /* Supervisor Access */
946#define TSI148_LCSR_LMAT_NPRIV BIT(2) /* Non-Priv (User) Access */
947#define TSI148_LCSR_LMAT_PGM BIT(1) /* Program Access */
948#define TSI148_LCSR_LMAT_DATA BIT(0) /* Data Access */
949
950/*
951 * Broadcast Pulse Generator Timer Register CRG + $438
952 */
953#define TSI148_LCSR_BPGTR_BPGT_M (0xFFFF << 0) /* Mask */
954
955/*
956 * Broadcast Programmable Clock Timer Register CRG + $43C
957 */
958#define TSI148_LCSR_BPCTR_BPCT_M (0xFFFFFF << 0) /* Mask */
959
960/*
961 * VMEbus Interrupt Control Register CRG + $43C
962 */
963#define TSI148_LCSR_VICR_CNTS_M (3 << 22) /* Cntr Source MASK */
964#define TSI148_LCSR_VICR_CNTS_DIS BIT(22) /* Cntr Disable */
965#define TSI148_LCSR_VICR_CNTS_IRQ1 (2 << 22) /* IRQ1 to Cntr */
966#define TSI148_LCSR_VICR_CNTS_IRQ2 (3 << 22) /* IRQ2 to Cntr */
967
968#define TSI148_LCSR_VICR_EDGIS_M (3 << 20) /* Edge interrupt MASK */
969#define TSI148_LCSR_VICR_EDGIS_DIS BIT(20) /* Edge interrupt Disable */
970#define TSI148_LCSR_VICR_EDGIS_IRQ1 (2 << 20) /* IRQ1 to Edge */
971#define TSI148_LCSR_VICR_EDGIS_IRQ2 (3 << 20) /* IRQ2 to Edge */
972
973#define TSI148_LCSR_VICR_IRQIF_M (3 << 18) /* IRQ1* Function MASK */
974#define TSI148_LCSR_VICR_IRQIF_NORM BIT(18) /* Normal */
975#define TSI148_LCSR_VICR_IRQIF_PULSE (2 << 18) /* Pulse Generator */
976#define TSI148_LCSR_VICR_IRQIF_PROG (3 << 18) /* Programmable Clock */
977#define TSI148_LCSR_VICR_IRQIF_1U (4 << 18) /* 1us Clock */
978
979#define TSI148_LCSR_VICR_IRQ2F_M (3 << 16) /* IRQ2* Function MASK */
980#define TSI148_LCSR_VICR_IRQ2F_NORM BIT(16) /* Normal */
981#define TSI148_LCSR_VICR_IRQ2F_PULSE (2 << 16) /* Pulse Generator */
982#define TSI148_LCSR_VICR_IRQ2F_PROG (3 << 16) /* Programmable Clock */
983#define TSI148_LCSR_VICR_IRQ2F_1U (4 << 16) /* 1us Clock */
984
985#define TSI148_LCSR_VICR_BIP BIT(15) /* Broadcast Interrupt Pulse */
986
987#define TSI148_LCSR_VICR_IRQC BIT(12) /* VMEbus IRQ Clear */
988#define TSI148_LCSR_VICR_IRQS BIT(11) /* VMEbus IRQ Status */
989
990#define TSI148_LCSR_VICR_IRQL_M (7 << 8) /* VMEbus SW IRQ Level Mask */
991#define TSI148_LCSR_VICR_IRQL_1 BIT(8) /* VMEbus SW IRQ Level 1 */
992#define TSI148_LCSR_VICR_IRQL_2 (2 << 8) /* VMEbus SW IRQ Level 2 */
993#define TSI148_LCSR_VICR_IRQL_3 (3 << 8) /* VMEbus SW IRQ Level 3 */
994#define TSI148_LCSR_VICR_IRQL_4 (4 << 8) /* VMEbus SW IRQ Level 4 */
995#define TSI148_LCSR_VICR_IRQL_5 (5 << 8) /* VMEbus SW IRQ Level 5 */
996#define TSI148_LCSR_VICR_IRQL_6 (6 << 8) /* VMEbus SW IRQ Level 6 */
997#define TSI148_LCSR_VICR_IRQL_7 (7 << 8) /* VMEbus SW IRQ Level 7 */
998
999static const int TSI148_LCSR_VICR_IRQL[8] = { 0, TSI148_LCSR_VICR_IRQL_1,
1000 TSI148_LCSR_VICR_IRQL_2, TSI148_LCSR_VICR_IRQL_3,
1001 TSI148_LCSR_VICR_IRQL_4, TSI148_LCSR_VICR_IRQL_5,
1002 TSI148_LCSR_VICR_IRQL_6, TSI148_LCSR_VICR_IRQL_7 };
1003
1004#define TSI148_LCSR_VICR_STID_M (0xFF << 0) /* Status/ID Mask */
1005
1006/*
1007 * Interrupt Enable Register CRG + $440
1008 */
1009#define TSI148_LCSR_INTEN_DMA1EN BIT(25) /* DMAC 1 */
1010#define TSI148_LCSR_INTEN_DMA0EN BIT(24) /* DMAC 0 */
1011#define TSI148_LCSR_INTEN_LM3EN BIT(23) /* Location Monitor 3 */
1012#define TSI148_LCSR_INTEN_LM2EN BIT(22) /* Location Monitor 2 */
1013#define TSI148_LCSR_INTEN_LM1EN BIT(21) /* Location Monitor 1 */
1014#define TSI148_LCSR_INTEN_LM0EN BIT(20) /* Location Monitor 0 */
1015#define TSI148_LCSR_INTEN_MB3EN BIT(19) /* Mail Box 3 */
1016#define TSI148_LCSR_INTEN_MB2EN BIT(18) /* Mail Box 2 */
1017#define TSI148_LCSR_INTEN_MB1EN BIT(17) /* Mail Box 1 */
1018#define TSI148_LCSR_INTEN_MB0EN BIT(16) /* Mail Box 0 */
1019#define TSI148_LCSR_INTEN_PERREN BIT(13) /* PCI/X Error */
1020#define TSI148_LCSR_INTEN_VERREN BIT(12) /* VMEbus Error */
1021#define TSI148_LCSR_INTEN_VIEEN BIT(11) /* VMEbus IRQ Edge */
1022#define TSI148_LCSR_INTEN_IACKEN BIT(10) /* IACK */
1023#define TSI148_LCSR_INTEN_SYSFLEN BIT(9) /* System Fail */
1024#define TSI148_LCSR_INTEN_ACFLEN BIT(8) /* AC Fail */
1025#define TSI148_LCSR_INTEN_IRQ7EN BIT(7) /* IRQ7 */
1026#define TSI148_LCSR_INTEN_IRQ6EN BIT(6) /* IRQ6 */
1027#define TSI148_LCSR_INTEN_IRQ5EN BIT(5) /* IRQ5 */
1028#define TSI148_LCSR_INTEN_IRQ4EN BIT(4) /* IRQ4 */
1029#define TSI148_LCSR_INTEN_IRQ3EN BIT(3) /* IRQ3 */
1030#define TSI148_LCSR_INTEN_IRQ2EN BIT(2) /* IRQ2 */
1031#define TSI148_LCSR_INTEN_IRQ1EN BIT(1) /* IRQ1 */
1032
1033static const int TSI148_LCSR_INTEN_LMEN[4] = { TSI148_LCSR_INTEN_LM0EN,
1034 TSI148_LCSR_INTEN_LM1EN,
1035 TSI148_LCSR_INTEN_LM2EN,
1036 TSI148_LCSR_INTEN_LM3EN };
1037
1038static const int TSI148_LCSR_INTEN_IRQEN[7] = { TSI148_LCSR_INTEN_IRQ1EN,
1039 TSI148_LCSR_INTEN_IRQ2EN,
1040 TSI148_LCSR_INTEN_IRQ3EN,
1041 TSI148_LCSR_INTEN_IRQ4EN,
1042 TSI148_LCSR_INTEN_IRQ5EN,
1043 TSI148_LCSR_INTEN_IRQ6EN,
1044 TSI148_LCSR_INTEN_IRQ7EN };
1045
1046/*
1047 * Interrupt Enable Out Register CRG + $444
1048 */
1049#define TSI148_LCSR_INTEO_DMA1EO BIT(25) /* DMAC 1 */
1050#define TSI148_LCSR_INTEO_DMA0EO BIT(24) /* DMAC 0 */
1051#define TSI148_LCSR_INTEO_LM3EO BIT(23) /* Loc Monitor 3 */
1052#define TSI148_LCSR_INTEO_LM2EO BIT(22) /* Loc Monitor 2 */
1053#define TSI148_LCSR_INTEO_LM1EO BIT(21) /* Loc Monitor 1 */
1054#define TSI148_LCSR_INTEO_LM0EO BIT(20) /* Location Monitor 0 */
1055#define TSI148_LCSR_INTEO_MB3EO BIT(19) /* Mail Box 3 */
1056#define TSI148_LCSR_INTEO_MB2EO BIT(18) /* Mail Box 2 */
1057#define TSI148_LCSR_INTEO_MB1EO BIT(17) /* Mail Box 1 */
1058#define TSI148_LCSR_INTEO_MB0EO BIT(16) /* Mail Box 0 */
1059#define TSI148_LCSR_INTEO_PERREO BIT(13) /* PCI/X Error */
1060#define TSI148_LCSR_INTEO_VERREO BIT(12) /* VMEbus Error */
1061#define TSI148_LCSR_INTEO_VIEEO BIT(11) /* VMEbus IRQ Edge */
1062#define TSI148_LCSR_INTEO_IACKEO BIT(10) /* IACK */
1063#define TSI148_LCSR_INTEO_SYSFLEO BIT(9) /* System Fail */
1064#define TSI148_LCSR_INTEO_ACFLEO BIT(8) /* AC Fail */
1065#define TSI148_LCSR_INTEO_IRQ7EO BIT(7) /* IRQ7 */
1066#define TSI148_LCSR_INTEO_IRQ6EO BIT(6) /* IRQ6 */
1067#define TSI148_LCSR_INTEO_IRQ5EO BIT(5) /* IRQ5 */
1068#define TSI148_LCSR_INTEO_IRQ4EO BIT(4) /* IRQ4 */
1069#define TSI148_LCSR_INTEO_IRQ3EO BIT(3) /* IRQ3 */
1070#define TSI148_LCSR_INTEO_IRQ2EO BIT(2) /* IRQ2 */
1071#define TSI148_LCSR_INTEO_IRQ1EO BIT(1) /* IRQ1 */
1072
1073static const int TSI148_LCSR_INTEO_LMEO[4] = { TSI148_LCSR_INTEO_LM0EO,
1074 TSI148_LCSR_INTEO_LM1EO,
1075 TSI148_LCSR_INTEO_LM2EO,
1076 TSI148_LCSR_INTEO_LM3EO };
1077
1078static const int TSI148_LCSR_INTEO_IRQEO[7] = { TSI148_LCSR_INTEO_IRQ1EO,
1079 TSI148_LCSR_INTEO_IRQ2EO,
1080 TSI148_LCSR_INTEO_IRQ3EO,
1081 TSI148_LCSR_INTEO_IRQ4EO,
1082 TSI148_LCSR_INTEO_IRQ5EO,
1083 TSI148_LCSR_INTEO_IRQ6EO,
1084 TSI148_LCSR_INTEO_IRQ7EO };
1085
1086/*
1087 * Interrupt Status Register CRG + $448
1088 */
1089#define TSI148_LCSR_INTS_DMA1S BIT(25) /* DMA 1 */
1090#define TSI148_LCSR_INTS_DMA0S BIT(24) /* DMA 0 */
1091#define TSI148_LCSR_INTS_LM3S BIT(23) /* Location Monitor 3 */
1092#define TSI148_LCSR_INTS_LM2S BIT(22) /* Location Monitor 2 */
1093#define TSI148_LCSR_INTS_LM1S BIT(21) /* Location Monitor 1 */
1094#define TSI148_LCSR_INTS_LM0S BIT(20) /* Location Monitor 0 */
1095#define TSI148_LCSR_INTS_MB3S BIT(19) /* Mail Box 3 */
1096#define TSI148_LCSR_INTS_MB2S BIT(18) /* Mail Box 2 */
1097#define TSI148_LCSR_INTS_MB1S BIT(17) /* Mail Box 1 */
1098#define TSI148_LCSR_INTS_MB0S BIT(16) /* Mail Box 0 */
1099#define TSI148_LCSR_INTS_PERRS BIT(13) /* PCI/X Error */
1100#define TSI148_LCSR_INTS_VERRS BIT(12) /* VMEbus Error */
1101#define TSI148_LCSR_INTS_VIES BIT(11) /* VMEbus IRQ Edge */
1102#define TSI148_LCSR_INTS_IACKS BIT(10) /* IACK */
1103#define TSI148_LCSR_INTS_SYSFLS BIT(9) /* System Fail */
1104#define TSI148_LCSR_INTS_ACFLS BIT(8) /* AC Fail */
1105#define TSI148_LCSR_INTS_IRQ7S BIT(7) /* IRQ7 */
1106#define TSI148_LCSR_INTS_IRQ6S BIT(6) /* IRQ6 */
1107#define TSI148_LCSR_INTS_IRQ5S BIT(5) /* IRQ5 */
1108#define TSI148_LCSR_INTS_IRQ4S BIT(4) /* IRQ4 */
1109#define TSI148_LCSR_INTS_IRQ3S BIT(3) /* IRQ3 */
1110#define TSI148_LCSR_INTS_IRQ2S BIT(2) /* IRQ2 */
1111#define TSI148_LCSR_INTS_IRQ1S BIT(1) /* IRQ1 */
1112
1113static const int TSI148_LCSR_INTS_LMS[4] = { TSI148_LCSR_INTS_LM0S,
1114 TSI148_LCSR_INTS_LM1S,
1115 TSI148_LCSR_INTS_LM2S,
1116 TSI148_LCSR_INTS_LM3S };
1117
1118static const int TSI148_LCSR_INTS_MBS[4] = { TSI148_LCSR_INTS_MB0S,
1119 TSI148_LCSR_INTS_MB1S,
1120 TSI148_LCSR_INTS_MB2S,
1121 TSI148_LCSR_INTS_MB3S };
1122
1123/*
1124 * Interrupt Clear Register CRG + $44C
1125 */
1126#define TSI148_LCSR_INTC_DMA1C BIT(25) /* DMA 1 */
1127#define TSI148_LCSR_INTC_DMA0C BIT(24) /* DMA 0 */
1128#define TSI148_LCSR_INTC_LM3C BIT(23) /* Location Monitor 3 */
1129#define TSI148_LCSR_INTC_LM2C BIT(22) /* Location Monitor 2 */
1130#define TSI148_LCSR_INTC_LM1C BIT(21) /* Location Monitor 1 */
1131#define TSI148_LCSR_INTC_LM0C BIT(20) /* Location Monitor 0 */
1132#define TSI148_LCSR_INTC_MB3C BIT(19) /* Mail Box 3 */
1133#define TSI148_LCSR_INTC_MB2C BIT(18) /* Mail Box 2 */
1134#define TSI148_LCSR_INTC_MB1C BIT(17) /* Mail Box 1 */
1135#define TSI148_LCSR_INTC_MB0C BIT(16) /* Mail Box 0 */
1136#define TSI148_LCSR_INTC_PERRC BIT(13) /* VMEbus Error */
1137#define TSI148_LCSR_INTC_VERRC BIT(12) /* VMEbus Access Time-out */
1138#define TSI148_LCSR_INTC_VIEC BIT(11) /* VMEbus IRQ Edge */
1139#define TSI148_LCSR_INTC_IACKC BIT(10) /* IACK */
1140#define TSI148_LCSR_INTC_SYSFLC BIT(9) /* System Fail */
1141#define TSI148_LCSR_INTC_ACFLC BIT(8) /* AC Fail */
1142
1143static const int TSI148_LCSR_INTC_LMC[4] = { TSI148_LCSR_INTC_LM0C,
1144 TSI148_LCSR_INTC_LM1C,
1145 TSI148_LCSR_INTC_LM2C,
1146 TSI148_LCSR_INTC_LM3C };
1147
1148static const int TSI148_LCSR_INTC_MBC[4] = { TSI148_LCSR_INTC_MB0C,
1149 TSI148_LCSR_INTC_MB1C,
1150 TSI148_LCSR_INTC_MB2C,
1151 TSI148_LCSR_INTC_MB3C };
1152
1153/*
1154 * Interrupt Map Register 1 CRG + $458
1155 */
1156#define TSI148_LCSR_INTM1_DMA1M_M (3 << 18) /* DMA 1 */
1157#define TSI148_LCSR_INTM1_DMA0M_M (3 << 16) /* DMA 0 */
1158#define TSI148_LCSR_INTM1_LM3M_M (3 << 14) /* Location Monitor 3 */
1159#define TSI148_LCSR_INTM1_LM2M_M (3 << 12) /* Location Monitor 2 */
1160#define TSI148_LCSR_INTM1_LM1M_M (3 << 10) /* Location Monitor 1 */
1161#define TSI148_LCSR_INTM1_LM0M_M (3 << 8) /* Location Monitor 0 */
1162#define TSI148_LCSR_INTM1_MB3M_M (3 << 6) /* Mail Box 3 */
1163#define TSI148_LCSR_INTM1_MB2M_M (3 << 4) /* Mail Box 2 */
1164#define TSI148_LCSR_INTM1_MB1M_M (3 << 2) /* Mail Box 1 */
1165#define TSI148_LCSR_INTM1_MB0M_M (3 << 0) /* Mail Box 0 */
1166
1167/*
1168 * Interrupt Map Register 2 CRG + $45C
1169 */
1170#define TSI148_LCSR_INTM2_PERRM_M (3 << 26) /* PCI Bus Error */
1171#define TSI148_LCSR_INTM2_VERRM_M (3 << 24) /* VMEbus Error */
1172#define TSI148_LCSR_INTM2_VIEM_M (3 << 22) /* VMEbus IRQ Edge */
1173#define TSI148_LCSR_INTM2_IACKM_M (3 << 20) /* IACK */
1174#define TSI148_LCSR_INTM2_SYSFLM_M (3 << 18) /* System Fail */
1175#define TSI148_LCSR_INTM2_ACFLM_M (3 << 16) /* AC Fail */
1176#define TSI148_LCSR_INTM2_IRQ7M_M (3 << 14) /* IRQ7 */
1177#define TSI148_LCSR_INTM2_IRQ6M_M (3 << 12) /* IRQ6 */
1178#define TSI148_LCSR_INTM2_IRQ5M_M (3 << 10) /* IRQ5 */
1179#define TSI148_LCSR_INTM2_IRQ4M_M (3 << 8) /* IRQ4 */
1180#define TSI148_LCSR_INTM2_IRQ3M_M (3 << 6) /* IRQ3 */
1181#define TSI148_LCSR_INTM2_IRQ2M_M (3 << 4) /* IRQ2 */
1182#define TSI148_LCSR_INTM2_IRQ1M_M (3 << 2) /* IRQ1 */
1183
1184/*
1185 * DMA Control (0-1) Registers CRG + $500
1186 */
1187#define TSI148_LCSR_DCTL_ABT BIT(27) /* Abort */
1188#define TSI148_LCSR_DCTL_PAU BIT(26) /* Pause */
1189#define TSI148_LCSR_DCTL_DGO BIT(25) /* DMA Go */
1190
1191#define TSI148_LCSR_DCTL_MOD BIT(23) /* Mode */
1192
1193#define TSI148_LCSR_DCTL_VBKS_M (7 << 12) /* VMEbus block Size MASK */
1194#define TSI148_LCSR_DCTL_VBKS_32 (0 << 12) /* VMEbus block Size 32 */
1195#define TSI148_LCSR_DCTL_VBKS_64 BIT(12) /* VMEbus block Size 64 */
1196#define TSI148_LCSR_DCTL_VBKS_128 (2 << 12) /* VMEbus block Size 128 */
1197#define TSI148_LCSR_DCTL_VBKS_256 (3 << 12) /* VMEbus block Size 256 */
1198#define TSI148_LCSR_DCTL_VBKS_512 (4 << 12) /* VMEbus block Size 512 */
1199#define TSI148_LCSR_DCTL_VBKS_1024 (5 << 12) /* VMEbus block Size 1024 */
1200#define TSI148_LCSR_DCTL_VBKS_2048 (6 << 12) /* VMEbus block Size 2048 */
1201#define TSI148_LCSR_DCTL_VBKS_4096 (7 << 12) /* VMEbus block Size 4096 */
1202
1203#define TSI148_LCSR_DCTL_VBOT_M (7 << 8) /* VMEbus back-off MASK */
1204#define TSI148_LCSR_DCTL_VBOT_0 (0 << 8) /* VMEbus back-off 0us */
1205#define TSI148_LCSR_DCTL_VBOT_1 BIT(8) /* VMEbus back-off 1us */
1206#define TSI148_LCSR_DCTL_VBOT_2 (2 << 8) /* VMEbus back-off 2us */
1207#define TSI148_LCSR_DCTL_VBOT_4 (3 << 8) /* VMEbus back-off 4us */
1208#define TSI148_LCSR_DCTL_VBOT_8 (4 << 8) /* VMEbus back-off 8us */
1209#define TSI148_LCSR_DCTL_VBOT_16 (5 << 8) /* VMEbus back-off 16us */
1210#define TSI148_LCSR_DCTL_VBOT_32 (6 << 8) /* VMEbus back-off 32us */
1211#define TSI148_LCSR_DCTL_VBOT_64 (7 << 8) /* VMEbus back-off 64us */
1212
1213#define TSI148_LCSR_DCTL_PBKS_M (7 << 4) /* PCI block size MASK */
1214#define TSI148_LCSR_DCTL_PBKS_32 (0 << 4) /* PCI block size 32 bytes */
1215#define TSI148_LCSR_DCTL_PBKS_64 BIT(4) /* PCI block size 64 bytes */
1216#define TSI148_LCSR_DCTL_PBKS_128 (2 << 4) /* PCI block size 128 bytes */
1217#define TSI148_LCSR_DCTL_PBKS_256 (3 << 4) /* PCI block size 256 bytes */
1218#define TSI148_LCSR_DCTL_PBKS_512 (4 << 4) /* PCI block size 512 bytes */
1219#define TSI148_LCSR_DCTL_PBKS_1024 (5 << 4) /* PCI block size 1024 bytes */
1220#define TSI148_LCSR_DCTL_PBKS_2048 (6 << 4) /* PCI block size 2048 bytes */
1221#define TSI148_LCSR_DCTL_PBKS_4096 (7 << 4) /* PCI block size 4096 bytes */
1222
1223#define TSI148_LCSR_DCTL_PBOT_M (7 << 0) /* PCI back off MASK */
1224#define TSI148_LCSR_DCTL_PBOT_0 (0 << 0) /* PCI back off 0us */
1225#define TSI148_LCSR_DCTL_PBOT_1 BIT(0) /* PCI back off 1us */
1226#define TSI148_LCSR_DCTL_PBOT_2 (2 << 0) /* PCI back off 2us */
1227#define TSI148_LCSR_DCTL_PBOT_4 (3 << 0) /* PCI back off 3us */
1228#define TSI148_LCSR_DCTL_PBOT_8 (4 << 0) /* PCI back off 4us */
1229#define TSI148_LCSR_DCTL_PBOT_16 (5 << 0) /* PCI back off 8us */
1230#define TSI148_LCSR_DCTL_PBOT_32 (6 << 0) /* PCI back off 16us */
1231#define TSI148_LCSR_DCTL_PBOT_64 (7 << 0) /* PCI back off 32us */
1232
1233/*
1234 * DMA Status Registers (0-1) CRG + $504
1235 */
1236#define TSI148_LCSR_DSTA_SMA BIT(31) /* PCI Signalled Master Abt */
1237#define TSI148_LCSR_DSTA_RTA BIT(30) /* PCI Received Target Abt */
1238#define TSI148_LCSR_DSTA_MRC BIT(29) /* PCI Max Retry Count */
1239#define TSI148_LCSR_DSTA_VBE BIT(28) /* VMEbus error */
1240#define TSI148_LCSR_DSTA_ABT BIT(27) /* Abort */
1241#define TSI148_LCSR_DSTA_PAU BIT(26) /* Pause */
1242#define TSI148_LCSR_DSTA_DON BIT(25) /* Done */
1243#define TSI148_LCSR_DSTA_BSY BIT(24) /* Busy */
1244
1245/*
1246 * DMA Current Link Address Lower (0-1)
1247 */
1248#define TSI148_LCSR_DCLAL_M (0x3FFFFFF << 6) /* Mask */
1249
1250/*
1251 * DMA Source Attribute (0-1) Reg
1252 */
1253#define TSI148_LCSR_DSAT_TYP_M (3 << 28) /* Source Bus Type */
1254#define TSI148_LCSR_DSAT_TYP_PCI (0 << 28) /* PCI Bus */
1255#define TSI148_LCSR_DSAT_TYP_VME BIT(28) /* VMEbus */
1256#define TSI148_LCSR_DSAT_TYP_PAT (2 << 28) /* Data Pattern */
1257
1258#define TSI148_LCSR_DSAT_PSZ BIT(25) /* Pattern Size */
1259#define TSI148_LCSR_DSAT_NIN BIT(24) /* No Increment */
1260
1261#define TSI148_LCSR_DSAT_2eSSTM_M (3 << 11) /* 2eSST Trans Rate Mask */
1262#define TSI148_LCSR_DSAT_2eSSTM_160 (0 << 11) /* 160 MB/s */
1263#define TSI148_LCSR_DSAT_2eSSTM_267 BIT(11) /* 267 MB/s */
1264#define TSI148_LCSR_DSAT_2eSSTM_320 (2 << 11) /* 320 MB/s */
1265
1266#define TSI148_LCSR_DSAT_TM_M (7 << 8) /* Bus Transfer Protocol Mask */
1267#define TSI148_LCSR_DSAT_TM_SCT (0 << 8) /* SCT */
1268#define TSI148_LCSR_DSAT_TM_BLT BIT(8) /* BLT */
1269#define TSI148_LCSR_DSAT_TM_MBLT (2 << 8) /* MBLT */
1270#define TSI148_LCSR_DSAT_TM_2eVME (3 << 8) /* 2eVME */
1271#define TSI148_LCSR_DSAT_TM_2eSST (4 << 8) /* 2eSST */
1272#define TSI148_LCSR_DSAT_TM_2eSSTB (5 << 8) /* 2eSST Broadcast */
1273
1274#define TSI148_LCSR_DSAT_DBW_M (3 << 6) /* Max Data Width MASK */
1275#define TSI148_LCSR_DSAT_DBW_16 (0 << 6) /* 16 Bits */
1276#define TSI148_LCSR_DSAT_DBW_32 BIT(6) /* 32 Bits */
1277
1278#define TSI148_LCSR_DSAT_SUP BIT(5) /* Supervisory Mode */
1279#define TSI148_LCSR_DSAT_PGM BIT(4) /* Program Mode */
1280
1281#define TSI148_LCSR_DSAT_AMODE_M (0xf << 0) /* Address Space Mask */
1282#define TSI148_LCSR_DSAT_AMODE_A16 (0 << 0) /* A16 */
1283#define TSI148_LCSR_DSAT_AMODE_A24 BIT(0) /* A24 */
1284#define TSI148_LCSR_DSAT_AMODE_A32 (2 << 0) /* A32 */
1285#define TSI148_LCSR_DSAT_AMODE_A64 (4 << 0) /* A64 */
1286#define TSI148_LCSR_DSAT_AMODE_CRCSR (5 << 0) /* CR/CSR */
1287#define TSI148_LCSR_DSAT_AMODE_USER1 (8 << 0) /* User1 */
1288#define TSI148_LCSR_DSAT_AMODE_USER2 (9 << 0) /* User2 */
1289#define TSI148_LCSR_DSAT_AMODE_USER3 (0xa << 0) /* User3 */
1290#define TSI148_LCSR_DSAT_AMODE_USER4 (0xb << 0) /* User4 */
1291
1292/*
1293 * DMA Destination Attribute Registers (0-1)
1294 */
1295#define TSI148_LCSR_DDAT_TYP_PCI (0 << 28) /* Destination PCI Bus */
1296#define TSI148_LCSR_DDAT_TYP_VME BIT(28) /* Destination VMEbus */
1297
1298#define TSI148_LCSR_DDAT_2eSSTM_M (3 << 11) /* 2eSST Transfer Rate Mask */
1299#define TSI148_LCSR_DDAT_2eSSTM_160 (0 << 11) /* 160 MB/s */
1300#define TSI148_LCSR_DDAT_2eSSTM_267 BIT(11) /* 267 MB/s */
1301#define TSI148_LCSR_DDAT_2eSSTM_320 (2 << 11) /* 320 MB/s */
1302
1303#define TSI148_LCSR_DDAT_TM_M (7 << 8) /* Bus Transfer Protocol Mask */
1304#define TSI148_LCSR_DDAT_TM_SCT (0 << 8) /* SCT */
1305#define TSI148_LCSR_DDAT_TM_BLT BIT(8) /* BLT */
1306#define TSI148_LCSR_DDAT_TM_MBLT (2 << 8) /* MBLT */
1307#define TSI148_LCSR_DDAT_TM_2eVME (3 << 8) /* 2eVME */
1308#define TSI148_LCSR_DDAT_TM_2eSST (4 << 8) /* 2eSST */
1309#define TSI148_LCSR_DDAT_TM_2eSSTB (5 << 8) /* 2eSST Broadcast */
1310
1311#define TSI148_LCSR_DDAT_DBW_M (3 << 6) /* Max Data Width MASK */
1312#define TSI148_LCSR_DDAT_DBW_16 (0 << 6) /* 16 Bits */
1313#define TSI148_LCSR_DDAT_DBW_32 BIT(6) /* 32 Bits */
1314
1315#define TSI148_LCSR_DDAT_SUP BIT(5) /* Supervisory/User Access */
1316#define TSI148_LCSR_DDAT_PGM BIT(4) /* Program/Data Access */
1317
1318#define TSI148_LCSR_DDAT_AMODE_M (0xf << 0) /* Address Space Mask */
1319#define TSI148_LCSR_DDAT_AMODE_A16 (0 << 0) /* A16 */
1320#define TSI148_LCSR_DDAT_AMODE_A24 BIT(0) /* A24 */
1321#define TSI148_LCSR_DDAT_AMODE_A32 (2 << 0) /* A32 */
1322#define TSI148_LCSR_DDAT_AMODE_A64 (4 << 0) /* A64 */
1323#define TSI148_LCSR_DDAT_AMODE_CRCSR (5 << 0) /* CRC/SR */
1324#define TSI148_LCSR_DDAT_AMODE_USER1 (8 << 0) /* User1 */
1325#define TSI148_LCSR_DDAT_AMODE_USER2 (9 << 0) /* User2 */
1326#define TSI148_LCSR_DDAT_AMODE_USER3 (0xa << 0) /* User3 */
1327#define TSI148_LCSR_DDAT_AMODE_USER4 (0xb << 0) /* User4 */
1328
1329/*
1330 * DMA Next Link Address Lower
1331 */
1332#define TSI148_LCSR_DNLAL_DNLAL_M (0x3FFFFFF << 6) /* Address Mask */
1333#define TSI148_LCSR_DNLAL_LLA BIT(0) /* Last Link Address Indicator */
1334
1335/*
1336 * DMA 2eSST Broadcast Select
1337 */
1338#define TSI148_LCSR_DBS_M (0x1FFFFF << 0) /* Mask */
1339
1340/*
1341 * GCSR Register Group
1342 */
1343
1344/*
1345 * GCSR Control and Status Register CRG + $604
1346 */
1347#define TSI148_GCSR_GCTRL_LRST BIT(15) /* Local Reset */
1348#define TSI148_GCSR_GCTRL_SFAILEN BIT(14) /* System Fail enable */
1349#define TSI148_GCSR_GCTRL_BDFAILS BIT(13) /* Board Fail Status */
1350#define TSI148_GCSR_GCTRL_SCON BIT(12) /* System Copntroller */
1351#define TSI148_GCSR_GCTRL_MEN BIT(11) /* Module Enable (READY) */
1352
1353#define TSI148_GCSR_GCTRL_LMI3S BIT(7) /* Loc Monitor 3 Int Status */
1354#define TSI148_GCSR_GCTRL_LMI2S BIT(6) /* Loc Monitor 2 Int Status */
1355#define TSI148_GCSR_GCTRL_LMI1S BIT(5) /* Loc Monitor 1 Int Status */
1356#define TSI148_GCSR_GCTRL_LMI0S BIT(4) /* Loc Monitor 0 Int Status */
1357#define TSI148_GCSR_GCTRL_MBI3S BIT(3) /* Mail box 3 Int Status */
1358#define TSI148_GCSR_GCTRL_MBI2S BIT(2) /* Mail box 2 Int Status */
1359#define TSI148_GCSR_GCTRL_MBI1S BIT(1) /* Mail box 1 Int Status */
1360#define TSI148_GCSR_GCTRL_MBI0S BIT(0) /* Mail box 0 Int Status */
1361
1362#define TSI148_GCSR_GAP BIT(5) /* Geographic Addr Parity */
1363#define TSI148_GCSR_GA_M (0x1F << 0) /* Geographic Address Mask */
1364
1365/*
1366 * CR/CSR Register Group
1367 */
1368
1369/*
1370 * CR/CSR Bit Clear Register CRG + $FF4
1371 */
1372#define TSI148_CRCSR_CSRBCR_LRSTC BIT(7) /* Local Reset Clear */
1373#define TSI148_CRCSR_CSRBCR_SFAILC BIT(6) /* System Fail Enable Clear */
1374#define TSI148_CRCSR_CSRBCR_BDFAILS BIT(5) /* Board Fail Status */
1375#define TSI148_CRCSR_CSRBCR_MENC BIT(4) /* Module Enable Clear */
1376#define TSI148_CRCSR_CSRBCR_BERRSC BIT(3) /* Bus Error Status Clear */
1377
1378/*
1379 * CR/CSR Bit Set Register CRG+$FF8
1380 */
1381#define TSI148_CRCSR_CSRBSR_LISTS BIT(7) /* Local Reset Clear */
1382#define TSI148_CRCSR_CSRBSR_SFAILS BIT(6) /* System Fail Enable Clear */
1383#define TSI148_CRCSR_CSRBSR_BDFAILS BIT(5) /* Board Fail Status */
1384#define TSI148_CRCSR_CSRBSR_MENS BIT(4) /* Module Enable Clear */
1385#define TSI148_CRCSR_CSRBSR_BERRS BIT(3) /* Bus Error Status Clear */
1386
1387/*
1388 * CR/CSR Base Address Register CRG + FFC
1389 */
1390#define TSI148_CRCSR_CBAR_M (0x1F << 3) /* Mask */
1391
1392#endif /* TSI148_H */
1393

source code of linux/drivers/staging/vme_user/vme_tsi148.h