1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2015 MediaTek Inc. |
4 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> |
5 | * Sascha Hauer <s.hauer@pengutronix.de> |
6 | * Dawei Chien <dawei.chien@mediatek.com> |
7 | * Louis Yu <louis.yu@mediatek.com> |
8 | */ |
9 | |
10 | #include <linux/clk.h> |
11 | #include <linux/delay.h> |
12 | #include <linux/interrupt.h> |
13 | #include <linux/kernel.h> |
14 | #include <linux/module.h> |
15 | #include <linux/nvmem-consumer.h> |
16 | #include <linux/of.h> |
17 | #include <linux/of_address.h> |
18 | #include <linux/platform_device.h> |
19 | #include <linux/slab.h> |
20 | #include <linux/io.h> |
21 | #include <linux/thermal.h> |
22 | #include <linux/reset.h> |
23 | #include <linux/types.h> |
24 | |
25 | #include "../thermal_hwmon.h" |
26 | |
27 | /* AUXADC Registers */ |
28 | #define AUXADC_CON1_SET_V 0x008 |
29 | #define AUXADC_CON1_CLR_V 0x00c |
30 | #define AUXADC_CON2_V 0x010 |
31 | #define AUXADC_DATA(channel) (0x14 + (channel) * 4) |
32 | |
33 | #define APMIXED_SYS_TS_CON0 0x600 |
34 | #define APMIXED_SYS_TS_CON1 0x604 |
35 | |
36 | /* Thermal Controller Registers */ |
37 | #define TEMP_MONCTL0 0x000 |
38 | #define TEMP_MONCTL1 0x004 |
39 | #define TEMP_MONCTL2 0x008 |
40 | #define TEMP_MONIDET0 0x014 |
41 | #define TEMP_MONIDET1 0x018 |
42 | #define TEMP_MSRCTL0 0x038 |
43 | #define TEMP_MSRCTL1 0x03c |
44 | #define TEMP_AHBPOLL 0x040 |
45 | #define TEMP_AHBTO 0x044 |
46 | #define TEMP_ADCPNP0 0x048 |
47 | #define TEMP_ADCPNP1 0x04c |
48 | #define TEMP_ADCPNP2 0x050 |
49 | #define TEMP_ADCPNP3 0x0b4 |
50 | |
51 | #define TEMP_ADCMUX 0x054 |
52 | #define TEMP_ADCEN 0x060 |
53 | #define TEMP_PNPMUXADDR 0x064 |
54 | #define TEMP_ADCMUXADDR 0x068 |
55 | #define TEMP_ADCENADDR 0x074 |
56 | #define TEMP_ADCVALIDADDR 0x078 |
57 | #define TEMP_ADCVOLTADDR 0x07c |
58 | #define TEMP_RDCTRL 0x080 |
59 | #define TEMP_ADCVALIDMASK 0x084 |
60 | #define TEMP_ADCVOLTAGESHIFT 0x088 |
61 | #define TEMP_ADCWRITECTRL 0x08c |
62 | #define TEMP_MSR0 0x090 |
63 | #define TEMP_MSR1 0x094 |
64 | #define TEMP_MSR2 0x098 |
65 | #define TEMP_MSR3 0x0B8 |
66 | |
67 | #define TEMP_SPARE0 0x0f0 |
68 | |
69 | #define TEMP_ADCPNP0_1 0x148 |
70 | #define TEMP_ADCPNP1_1 0x14c |
71 | #define TEMP_ADCPNP2_1 0x150 |
72 | #define TEMP_MSR0_1 0x190 |
73 | #define TEMP_MSR1_1 0x194 |
74 | #define TEMP_MSR2_1 0x198 |
75 | #define TEMP_ADCPNP3_1 0x1b4 |
76 | #define TEMP_MSR3_1 0x1B8 |
77 | |
78 | #define PTPCORESEL 0x400 |
79 | |
80 | #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) |
81 | |
82 | #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) |
83 | #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) |
84 | |
85 | #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) |
86 | |
87 | #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) |
88 | #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) |
89 | |
90 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) |
91 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) |
92 | |
93 | /* MT8173 thermal sensors */ |
94 | #define MT8173_TS1 0 |
95 | #define MT8173_TS2 1 |
96 | #define MT8173_TS3 2 |
97 | #define MT8173_TS4 3 |
98 | #define MT8173_TSABB 4 |
99 | |
100 | /* AUXADC channel 11 is used for the temperature sensors */ |
101 | #define MT8173_TEMP_AUXADC_CHANNEL 11 |
102 | |
103 | /* The total number of temperature sensors in the MT8173 */ |
104 | #define MT8173_NUM_SENSORS 5 |
105 | |
106 | /* The number of banks in the MT8173 */ |
107 | #define MT8173_NUM_ZONES 4 |
108 | |
109 | /* The number of sensing points per bank */ |
110 | #define MT8173_NUM_SENSORS_PER_ZONE 4 |
111 | |
112 | /* The number of controller in the MT8173 */ |
113 | #define MT8173_NUM_CONTROLLER 1 |
114 | |
115 | /* The calibration coefficient of sensor */ |
116 | #define MT8173_CALIBRATION 165 |
117 | |
118 | /* Valid temperatures range */ |
119 | #define MT8173_TEMP_MIN -20000 |
120 | #define MT8173_TEMP_MAX 150000 |
121 | |
122 | /* |
123 | * Layout of the fuses providing the calibration data |
124 | * These macros could be used for MT8183, MT8173, MT2701, and MT2712. |
125 | * MT8183 has 6 sensors and needs 6 VTS calibration data. |
126 | * MT8173 has 5 sensors and needs 5 VTS calibration data. |
127 | * MT2701 has 3 sensors and needs 3 VTS calibration data. |
128 | * MT2712 has 4 sensors and needs 4 VTS calibration data. |
129 | */ |
130 | #define CALIB_BUF0_VALID_V1 BIT(0) |
131 | #define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff) |
132 | #define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff) |
133 | #define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff) |
134 | #define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff) |
135 | #define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff) |
136 | #define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff) |
137 | #define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff) |
138 | #define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f) |
139 | #define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f) |
140 | #define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1) |
141 | #define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1) |
142 | |
143 | /* |
144 | * Layout of the fuses providing the calibration data |
145 | * These macros could be used for MT7622. |
146 | */ |
147 | #define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff) |
148 | #define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff) |
149 | #define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f) |
150 | #define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f) |
151 | #define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff) |
152 | #define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff) |
153 | #define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff) |
154 | #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) |
155 | #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) |
156 | |
157 | /* |
158 | * Layout of the fuses providing the calibration data |
159 | * These macros can be used for MT7981 and MT7986. |
160 | */ |
161 | #define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) |
162 | #define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) |
163 | #define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) |
164 | #define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) |
165 | #define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) |
166 | #define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) |
167 | #define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) |
168 | #define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) |
169 | #define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) |
170 | |
171 | enum { |
172 | VTS1, |
173 | VTS2, |
174 | VTS3, |
175 | VTS4, |
176 | VTS5, |
177 | VTSABB, |
178 | MAX_NUM_VTS, |
179 | }; |
180 | |
181 | enum mtk_thermal_version { |
182 | MTK_THERMAL_V1 = 1, |
183 | MTK_THERMAL_V2, |
184 | MTK_THERMAL_V3, |
185 | }; |
186 | |
187 | /* MT2701 thermal sensors */ |
188 | #define MT2701_TS1 0 |
189 | #define MT2701_TS2 1 |
190 | #define MT2701_TSABB 2 |
191 | |
192 | /* AUXADC channel 11 is used for the temperature sensors */ |
193 | #define MT2701_TEMP_AUXADC_CHANNEL 11 |
194 | |
195 | /* The total number of temperature sensors in the MT2701 */ |
196 | #define MT2701_NUM_SENSORS 3 |
197 | |
198 | /* The number of sensing points per bank */ |
199 | #define MT2701_NUM_SENSORS_PER_ZONE 3 |
200 | |
201 | /* The number of controller in the MT2701 */ |
202 | #define MT2701_NUM_CONTROLLER 1 |
203 | |
204 | /* The calibration coefficient of sensor */ |
205 | #define MT2701_CALIBRATION 165 |
206 | |
207 | /* MT2712 thermal sensors */ |
208 | #define MT2712_TS1 0 |
209 | #define MT2712_TS2 1 |
210 | #define MT2712_TS3 2 |
211 | #define MT2712_TS4 3 |
212 | |
213 | /* AUXADC channel 11 is used for the temperature sensors */ |
214 | #define MT2712_TEMP_AUXADC_CHANNEL 11 |
215 | |
216 | /* The total number of temperature sensors in the MT2712 */ |
217 | #define MT2712_NUM_SENSORS 4 |
218 | |
219 | /* The number of sensing points per bank */ |
220 | #define MT2712_NUM_SENSORS_PER_ZONE 4 |
221 | |
222 | /* The number of controller in the MT2712 */ |
223 | #define MT2712_NUM_CONTROLLER 1 |
224 | |
225 | /* The calibration coefficient of sensor */ |
226 | #define MT2712_CALIBRATION 165 |
227 | |
228 | #define MT7622_TEMP_AUXADC_CHANNEL 11 |
229 | #define MT7622_NUM_SENSORS 1 |
230 | #define MT7622_NUM_ZONES 1 |
231 | #define MT7622_NUM_SENSORS_PER_ZONE 1 |
232 | #define MT7622_TS1 0 |
233 | #define MT7622_NUM_CONTROLLER 1 |
234 | |
235 | /* The maximum number of banks */ |
236 | #define MAX_NUM_ZONES 8 |
237 | |
238 | /* The calibration coefficient of sensor */ |
239 | #define MT7622_CALIBRATION 165 |
240 | |
241 | /* MT8183 thermal sensors */ |
242 | #define MT8183_TS1 0 |
243 | #define MT8183_TS2 1 |
244 | #define MT8183_TS3 2 |
245 | #define MT8183_TS4 3 |
246 | #define MT8183_TS5 4 |
247 | #define MT8183_TSABB 5 |
248 | |
249 | /* AUXADC channel is used for the temperature sensors */ |
250 | #define MT8183_TEMP_AUXADC_CHANNEL 11 |
251 | |
252 | /* The total number of temperature sensors in the MT8183 */ |
253 | #define MT8183_NUM_SENSORS 6 |
254 | |
255 | /* The number of banks in the MT8183 */ |
256 | #define MT8183_NUM_ZONES 1 |
257 | |
258 | /* The number of sensing points per bank */ |
259 | #define MT8183_NUM_SENSORS_PER_ZONE 6 |
260 | |
261 | /* The number of controller in the MT8183 */ |
262 | #define MT8183_NUM_CONTROLLER 2 |
263 | |
264 | /* The calibration coefficient of sensor */ |
265 | #define MT8183_CALIBRATION 153 |
266 | |
267 | /* AUXADC channel 11 is used for the temperature sensors */ |
268 | #define MT7986_TEMP_AUXADC_CHANNEL 11 |
269 | |
270 | /* The total number of temperature sensors in the MT7986 */ |
271 | #define MT7986_NUM_SENSORS 1 |
272 | |
273 | /* The number of banks in the MT7986 */ |
274 | #define MT7986_NUM_ZONES 1 |
275 | |
276 | /* The number of sensing points per bank */ |
277 | #define MT7986_NUM_SENSORS_PER_ZONE 1 |
278 | |
279 | /* MT7986 thermal sensors */ |
280 | #define MT7986_TS1 0 |
281 | |
282 | /* The number of controller in the MT7986 */ |
283 | #define MT7986_NUM_CONTROLLER 1 |
284 | |
285 | /* The calibration coefficient of sensor */ |
286 | #define MT7986_CALIBRATION 165 |
287 | |
288 | /* MT8365 */ |
289 | #define MT8365_TEMP_AUXADC_CHANNEL 11 |
290 | #define MT8365_CALIBRATION 164 |
291 | #define MT8365_NUM_CONTROLLER 1 |
292 | #define MT8365_NUM_BANKS 1 |
293 | #define MT8365_NUM_SENSORS 3 |
294 | #define MT8365_NUM_SENSORS_PER_ZONE 3 |
295 | #define MT8365_TS1 0 |
296 | #define MT8365_TS2 1 |
297 | #define MT8365_TS3 2 |
298 | |
299 | struct mtk_thermal; |
300 | |
301 | struct thermal_bank_cfg { |
302 | unsigned int num_sensors; |
303 | const int *sensors; |
304 | }; |
305 | |
306 | struct mtk_thermal_bank { |
307 | struct mtk_thermal *mt; |
308 | int id; |
309 | }; |
310 | |
311 | struct mtk_thermal_data { |
312 | s32 num_banks; |
313 | s32 num_sensors; |
314 | s32 auxadc_channel; |
315 | const int *vts_index; |
316 | const int *sensor_mux_values; |
317 | const int *msr; |
318 | const int *adcpnp; |
319 | const int cali_val; |
320 | const int num_controller; |
321 | const int *controller_offset; |
322 | bool need_switch_bank; |
323 | struct thermal_bank_cfg bank_data[MAX_NUM_ZONES]; |
324 | enum mtk_thermal_version version; |
325 | u32 apmixed_buffer_ctl_reg; |
326 | u32 apmixed_buffer_ctl_mask; |
327 | u32 apmixed_buffer_ctl_set; |
328 | }; |
329 | |
330 | struct mtk_thermal { |
331 | struct device *dev; |
332 | void __iomem *thermal_base; |
333 | |
334 | struct clk *clk_peri_therm; |
335 | struct clk *clk_auxadc; |
336 | /* lock: for getting and putting banks */ |
337 | struct mutex lock; |
338 | |
339 | /* Calibration values */ |
340 | s32 adc_ge; |
341 | s32 adc_oe; |
342 | s32 degc_cali; |
343 | s32 o_slope; |
344 | s32 o_slope_sign; |
345 | s32 vts[MAX_NUM_VTS]; |
346 | |
347 | const struct mtk_thermal_data *conf; |
348 | struct mtk_thermal_bank banks[MAX_NUM_ZONES]; |
349 | |
350 | int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); |
351 | }; |
352 | |
353 | /* MT8183 thermal sensor data */ |
354 | static const int mt8183_bank_data[MT8183_NUM_SENSORS] = { |
355 | MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB |
356 | }; |
357 | |
358 | static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = { |
359 | TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1 |
360 | }; |
361 | |
362 | static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = { |
363 | TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1, |
364 | TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1 |
365 | }; |
366 | |
367 | static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 }; |
368 | static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100}; |
369 | |
370 | static const int mt8183_vts_index[MT8183_NUM_SENSORS] = { |
371 | VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB |
372 | }; |
373 | |
374 | /* MT8173 thermal sensor data */ |
375 | static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { |
376 | { MT8173_TS2, MT8173_TS3 }, |
377 | { MT8173_TS2, MT8173_TS4 }, |
378 | { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, |
379 | { MT8173_TS2 }, |
380 | }; |
381 | |
382 | static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { |
383 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
384 | }; |
385 | |
386 | static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { |
387 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
388 | }; |
389 | |
390 | static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; |
391 | static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, }; |
392 | |
393 | static const int mt8173_vts_index[MT8173_NUM_SENSORS] = { |
394 | VTS1, VTS2, VTS3, VTS4, VTSABB |
395 | }; |
396 | |
397 | /* MT2701 thermal sensor data */ |
398 | static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { |
399 | MT2701_TS1, MT2701_TS2, MT2701_TSABB |
400 | }; |
401 | |
402 | static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { |
403 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 |
404 | }; |
405 | |
406 | static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { |
407 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 |
408 | }; |
409 | |
410 | static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; |
411 | static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, }; |
412 | |
413 | static const int mt2701_vts_index[MT2701_NUM_SENSORS] = { |
414 | VTS1, VTS2, VTS3 |
415 | }; |
416 | |
417 | /* MT2712 thermal sensor data */ |
418 | static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { |
419 | MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 |
420 | }; |
421 | |
422 | static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { |
423 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
424 | }; |
425 | |
426 | static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { |
427 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
428 | }; |
429 | |
430 | static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; |
431 | static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, }; |
432 | |
433 | static const int mt2712_vts_index[MT2712_NUM_SENSORS] = { |
434 | VTS1, VTS2, VTS3, VTS4 |
435 | }; |
436 | |
437 | /* MT7622 thermal sensor data */ |
438 | static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; |
439 | static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; |
440 | static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; |
441 | static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; |
442 | static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; |
443 | static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; |
444 | |
445 | /* MT7986 thermal sensor data */ |
446 | static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; |
447 | static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; |
448 | static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; |
449 | static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; |
450 | static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; |
451 | static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; |
452 | |
453 | /* MT8365 thermal sensor data */ |
454 | static const int mt8365_bank_data[MT8365_NUM_SENSORS] = { |
455 | MT8365_TS1, MT8365_TS2, MT8365_TS3 |
456 | }; |
457 | |
458 | static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = { |
459 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 |
460 | }; |
461 | |
462 | static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = { |
463 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 |
464 | }; |
465 | |
466 | static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 }; |
467 | static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 }; |
468 | |
469 | static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 }; |
470 | |
471 | /* |
472 | * The MT8173 thermal controller has four banks. Each bank can read up to |
473 | * four temperature sensors simultaneously. The MT8173 has a total of 5 |
474 | * temperature sensors. We use each bank to measure a certain area of the |
475 | * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple |
476 | * areas, hence is used in different banks. |
477 | * |
478 | * The thermal core only gets the maximum temperature of all banks, so |
479 | * the bank concept wouldn't be necessary here. However, the SVS (Smart |
480 | * Voltage Scaling) unit makes its decisions based on the same bank |
481 | * data, and this indeed needs the temperatures of the individual banks |
482 | * for making better decisions. |
483 | */ |
484 | static const struct mtk_thermal_data mt8173_thermal_data = { |
485 | .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, |
486 | .num_banks = MT8173_NUM_ZONES, |
487 | .num_sensors = MT8173_NUM_SENSORS, |
488 | .vts_index = mt8173_vts_index, |
489 | .cali_val = MT8173_CALIBRATION, |
490 | .num_controller = MT8173_NUM_CONTROLLER, |
491 | .controller_offset = mt8173_tc_offset, |
492 | .need_switch_bank = true, |
493 | .bank_data = { |
494 | { |
495 | .num_sensors = 2, |
496 | .sensors = mt8173_bank_data[0], |
497 | }, { |
498 | .num_sensors = 2, |
499 | .sensors = mt8173_bank_data[1], |
500 | }, { |
501 | .num_sensors = 3, |
502 | .sensors = mt8173_bank_data[2], |
503 | }, { |
504 | .num_sensors = 1, |
505 | .sensors = mt8173_bank_data[3], |
506 | }, |
507 | }, |
508 | .msr = mt8173_msr, |
509 | .adcpnp = mt8173_adcpnp, |
510 | .sensor_mux_values = mt8173_mux_values, |
511 | .version = MTK_THERMAL_V1, |
512 | }; |
513 | |
514 | /* |
515 | * The MT2701 thermal controller has one bank, which can read up to |
516 | * three temperature sensors simultaneously. The MT2701 has a total of 3 |
517 | * temperature sensors. |
518 | * |
519 | * The thermal core only gets the maximum temperature of this one bank, |
520 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart |
521 | * Voltage Scaling) unit makes its decisions based on the same bank |
522 | * data. |
523 | */ |
524 | static const struct mtk_thermal_data mt2701_thermal_data = { |
525 | .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, |
526 | .num_banks = 1, |
527 | .num_sensors = MT2701_NUM_SENSORS, |
528 | .vts_index = mt2701_vts_index, |
529 | .cali_val = MT2701_CALIBRATION, |
530 | .num_controller = MT2701_NUM_CONTROLLER, |
531 | .controller_offset = mt2701_tc_offset, |
532 | .need_switch_bank = true, |
533 | .bank_data = { |
534 | { |
535 | .num_sensors = 3, |
536 | .sensors = mt2701_bank_data, |
537 | }, |
538 | }, |
539 | .msr = mt2701_msr, |
540 | .adcpnp = mt2701_adcpnp, |
541 | .sensor_mux_values = mt2701_mux_values, |
542 | .version = MTK_THERMAL_V1, |
543 | }; |
544 | |
545 | /* |
546 | * The MT8365 thermal controller has one bank, which can read up to |
547 | * four temperature sensors simultaneously. The MT8365 has a total of 3 |
548 | * temperature sensors. |
549 | * |
550 | * The thermal core only gets the maximum temperature of this one bank, |
551 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart |
552 | * Voltage Scaling) unit makes its decisions based on the same bank |
553 | * data. |
554 | */ |
555 | static const struct mtk_thermal_data mt8365_thermal_data = { |
556 | .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL, |
557 | .num_banks = MT8365_NUM_BANKS, |
558 | .num_sensors = MT8365_NUM_SENSORS, |
559 | .vts_index = mt8365_vts_index, |
560 | .cali_val = MT8365_CALIBRATION, |
561 | .num_controller = MT8365_NUM_CONTROLLER, |
562 | .controller_offset = mt8365_tc_offset, |
563 | .need_switch_bank = false, |
564 | .bank_data = { |
565 | { |
566 | .num_sensors = MT8365_NUM_SENSORS, |
567 | .sensors = mt8365_bank_data |
568 | }, |
569 | }, |
570 | .msr = mt8365_msr, |
571 | .adcpnp = mt8365_adcpnp, |
572 | .sensor_mux_values = mt8365_mux_values, |
573 | .version = MTK_THERMAL_V1, |
574 | .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0, |
575 | .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28), |
576 | .apmixed_buffer_ctl_set = 0, |
577 | }; |
578 | |
579 | /* |
580 | * The MT2712 thermal controller has one bank, which can read up to |
581 | * four temperature sensors simultaneously. The MT2712 has a total of 4 |
582 | * temperature sensors. |
583 | * |
584 | * The thermal core only gets the maximum temperature of this one bank, |
585 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart |
586 | * Voltage Scaling) unit makes its decisions based on the same bank |
587 | * data. |
588 | */ |
589 | static const struct mtk_thermal_data mt2712_thermal_data = { |
590 | .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, |
591 | .num_banks = 1, |
592 | .num_sensors = MT2712_NUM_SENSORS, |
593 | .vts_index = mt2712_vts_index, |
594 | .cali_val = MT2712_CALIBRATION, |
595 | .num_controller = MT2712_NUM_CONTROLLER, |
596 | .controller_offset = mt2712_tc_offset, |
597 | .need_switch_bank = true, |
598 | .bank_data = { |
599 | { |
600 | .num_sensors = 4, |
601 | .sensors = mt2712_bank_data, |
602 | }, |
603 | }, |
604 | .msr = mt2712_msr, |
605 | .adcpnp = mt2712_adcpnp, |
606 | .sensor_mux_values = mt2712_mux_values, |
607 | .version = MTK_THERMAL_V1, |
608 | }; |
609 | |
610 | /* |
611 | * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data |
612 | * access. |
613 | */ |
614 | static const struct mtk_thermal_data mt7622_thermal_data = { |
615 | .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, |
616 | .num_banks = MT7622_NUM_ZONES, |
617 | .num_sensors = MT7622_NUM_SENSORS, |
618 | .vts_index = mt7622_vts_index, |
619 | .cali_val = MT7622_CALIBRATION, |
620 | .num_controller = MT7622_NUM_CONTROLLER, |
621 | .controller_offset = mt7622_tc_offset, |
622 | .need_switch_bank = true, |
623 | .bank_data = { |
624 | { |
625 | .num_sensors = 1, |
626 | .sensors = mt7622_bank_data, |
627 | }, |
628 | }, |
629 | .msr = mt7622_msr, |
630 | .adcpnp = mt7622_adcpnp, |
631 | .sensor_mux_values = mt7622_mux_values, |
632 | .version = MTK_THERMAL_V2, |
633 | .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, |
634 | .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), |
635 | .apmixed_buffer_ctl_set = BIT(0), |
636 | }; |
637 | |
638 | /* |
639 | * The MT8183 thermal controller has one bank for the current SW framework. |
640 | * The MT8183 has a total of 6 temperature sensors. |
641 | * There are two thermal controller to control the six sensor. |
642 | * The first one bind 2 sensor, and the other bind 4 sensors. |
643 | * The thermal core only gets the maximum temperature of all sensor, so |
644 | * the bank concept wouldn't be necessary here. However, the SVS (Smart |
645 | * Voltage Scaling) unit makes its decisions based on the same bank |
646 | * data, and this indeed needs the temperatures of the individual banks |
647 | * for making better decisions. |
648 | */ |
649 | static const struct mtk_thermal_data mt8183_thermal_data = { |
650 | .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL, |
651 | .num_banks = MT8183_NUM_ZONES, |
652 | .num_sensors = MT8183_NUM_SENSORS, |
653 | .vts_index = mt8183_vts_index, |
654 | .cali_val = MT8183_CALIBRATION, |
655 | .num_controller = MT8183_NUM_CONTROLLER, |
656 | .controller_offset = mt8183_tc_offset, |
657 | .need_switch_bank = false, |
658 | .bank_data = { |
659 | { |
660 | .num_sensors = 6, |
661 | .sensors = mt8183_bank_data, |
662 | }, |
663 | }, |
664 | |
665 | .msr = mt8183_msr, |
666 | .adcpnp = mt8183_adcpnp, |
667 | .sensor_mux_values = mt8183_mux_values, |
668 | .version = MTK_THERMAL_V1, |
669 | }; |
670 | |
671 | /* |
672 | * MT7986 uses AUXADC Channel 11 for raw data access. |
673 | */ |
674 | static const struct mtk_thermal_data mt7986_thermal_data = { |
675 | .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, |
676 | .num_banks = MT7986_NUM_ZONES, |
677 | .num_sensors = MT7986_NUM_SENSORS, |
678 | .vts_index = mt7986_vts_index, |
679 | .cali_val = MT7986_CALIBRATION, |
680 | .num_controller = MT7986_NUM_CONTROLLER, |
681 | .controller_offset = mt7986_tc_offset, |
682 | .need_switch_bank = true, |
683 | .bank_data = { |
684 | { |
685 | .num_sensors = 1, |
686 | .sensors = mt7986_bank_data, |
687 | }, |
688 | }, |
689 | .msr = mt7986_msr, |
690 | .adcpnp = mt7986_adcpnp, |
691 | .sensor_mux_values = mt7986_mux_values, |
692 | .version = MTK_THERMAL_V3, |
693 | .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1, |
694 | .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3), |
695 | .apmixed_buffer_ctl_set = BIT(0), |
696 | }; |
697 | |
698 | static bool mtk_thermal_temp_is_valid(int temp) |
699 | { |
700 | return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX); |
701 | } |
702 | |
703 | /** |
704 | * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius |
705 | * @mt: The thermal controller |
706 | * @sensno: sensor number |
707 | * @raw: raw ADC value |
708 | * |
709 | * This converts the raw ADC value to mcelsius using the SoC specific |
710 | * calibration constants |
711 | */ |
712 | static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw) |
713 | { |
714 | s32 tmp; |
715 | |
716 | raw &= 0xfff; |
717 | |
718 | tmp = 203450520 << 3; |
719 | tmp /= mt->conf->cali_val + mt->o_slope; |
720 | tmp /= 10000 + mt->adc_ge; |
721 | tmp *= raw - mt->vts[sensno] - 3350; |
722 | tmp >>= 3; |
723 | |
724 | return mt->degc_cali * 500 - tmp; |
725 | } |
726 | |
727 | static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw) |
728 | { |
729 | s32 format_1; |
730 | s32 format_2; |
731 | s32 g_oe; |
732 | s32 g_gain; |
733 | s32 g_x_roomt; |
734 | s32 tmp; |
735 | |
736 | if (raw == 0) |
737 | return 0; |
738 | |
739 | raw &= 0xfff; |
740 | g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12); |
741 | g_oe = mt->adc_oe - 512; |
742 | format_1 = mt->vts[VTS2] + 3105 - g_oe; |
743 | format_2 = (mt->degc_cali * 10) >> 1; |
744 | g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain; |
745 | |
746 | tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt; |
747 | tmp = tmp * 10 * 100 / 11; |
748 | |
749 | if (mt->o_slope_sign == 0) |
750 | tmp = tmp / (165 - mt->o_slope); |
751 | else |
752 | tmp = tmp / (165 + mt->o_slope); |
753 | |
754 | return (format_2 - tmp) * 100; |
755 | } |
756 | |
757 | static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) |
758 | { |
759 | s32 tmp; |
760 | |
761 | if (raw == 0) |
762 | return 0; |
763 | |
764 | raw &= 0xfff; |
765 | tmp = 100000 * 15 / 16 * 10000; |
766 | tmp /= 4096 - 512 + mt->adc_ge; |
767 | tmp /= 1490; |
768 | tmp *= raw - mt->vts[sensno] - 2900; |
769 | |
770 | return mt->degc_cali * 500 - tmp; |
771 | } |
772 | |
773 | /** |
774 | * mtk_thermal_get_bank - get bank |
775 | * @bank: The bank |
776 | * |
777 | * The bank registers are banked, we have to select a bank in the |
778 | * PTPCORESEL register to access it. |
779 | */ |
780 | static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) |
781 | { |
782 | struct mtk_thermal *mt = bank->mt; |
783 | u32 val; |
784 | |
785 | if (mt->conf->need_switch_bank) { |
786 | mutex_lock(&mt->lock); |
787 | |
788 | val = readl(addr: mt->thermal_base + PTPCORESEL); |
789 | val &= ~0xf; |
790 | val |= bank->id; |
791 | writel(val, addr: mt->thermal_base + PTPCORESEL); |
792 | } |
793 | } |
794 | |
795 | /** |
796 | * mtk_thermal_put_bank - release bank |
797 | * @bank: The bank |
798 | * |
799 | * release a bank previously taken with mtk_thermal_get_bank, |
800 | */ |
801 | static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) |
802 | { |
803 | struct mtk_thermal *mt = bank->mt; |
804 | |
805 | if (mt->conf->need_switch_bank) |
806 | mutex_unlock(lock: &mt->lock); |
807 | } |
808 | |
809 | /** |
810 | * mtk_thermal_bank_temperature - get the temperature of a bank |
811 | * @bank: The bank |
812 | * |
813 | * The temperature of a bank is considered the maximum temperature of |
814 | * the sensors associated to the bank. |
815 | */ |
816 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) |
817 | { |
818 | struct mtk_thermal *mt = bank->mt; |
819 | const struct mtk_thermal_data *conf = mt->conf; |
820 | int i, temp = INT_MIN, max = INT_MIN; |
821 | u32 raw; |
822 | |
823 | for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { |
824 | raw = readl(addr: mt->thermal_base + conf->msr[i]); |
825 | |
826 | temp = mt->raw_to_mcelsius( |
827 | mt, conf->bank_data[bank->id].sensors[i], raw); |
828 | |
829 | /* |
830 | * Depending on the filt/sen intervals and ADC polling time, |
831 | * we may need up to 60 milliseconds after initialization: this |
832 | * will result in the first reading containing an out of range |
833 | * temperature value. |
834 | * Validate the reading to both address the aforementioned issue |
835 | * and to eventually avoid bogus readings during runtime in the |
836 | * event that the AUXADC gets unstable due to high EMI, etc. |
837 | */ |
838 | if (!mtk_thermal_temp_is_valid(temp)) |
839 | temp = THERMAL_TEMP_INVALID; |
840 | |
841 | if (temp > max) |
842 | max = temp; |
843 | } |
844 | |
845 | return max; |
846 | } |
847 | |
848 | static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature) |
849 | { |
850 | struct mtk_thermal *mt = thermal_zone_device_priv(tzd: tz); |
851 | int i; |
852 | int tempmax = INT_MIN; |
853 | |
854 | for (i = 0; i < mt->conf->num_banks; i++) { |
855 | struct mtk_thermal_bank *bank = &mt->banks[i]; |
856 | |
857 | mtk_thermal_get_bank(bank); |
858 | |
859 | tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); |
860 | |
861 | mtk_thermal_put_bank(bank); |
862 | } |
863 | |
864 | *temperature = tempmax; |
865 | |
866 | return 0; |
867 | } |
868 | |
869 | static const struct thermal_zone_device_ops mtk_thermal_ops = { |
870 | .get_temp = mtk_read_temp, |
871 | }; |
872 | |
873 | static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, |
874 | u32 apmixed_phys_base, u32 auxadc_phys_base, |
875 | int ctrl_id) |
876 | { |
877 | struct mtk_thermal_bank *bank = &mt->banks[num]; |
878 | const struct mtk_thermal_data *conf = mt->conf; |
879 | int i; |
880 | |
881 | int offset = mt->conf->controller_offset[ctrl_id]; |
882 | void __iomem *controller_base = mt->thermal_base + offset; |
883 | |
884 | bank->id = num; |
885 | bank->mt = mt; |
886 | |
887 | mtk_thermal_get_bank(bank); |
888 | |
889 | /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ |
890 | writel(TEMP_MONCTL1_PERIOD_UNIT(12), addr: controller_base + TEMP_MONCTL1); |
891 | |
892 | /* |
893 | * filt interval is 1 * 46.540us = 46.54us, |
894 | * sen interval is 429 * 46.540us = 19.96ms |
895 | */ |
896 | writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | |
897 | TEMP_MONCTL2_SENSOR_INTERVAL(429), |
898 | addr: controller_base + TEMP_MONCTL2); |
899 | |
900 | /* poll is set to 10u */ |
901 | writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), |
902 | addr: controller_base + TEMP_AHBPOLL); |
903 | |
904 | /* temperature sampling control, 1 sample */ |
905 | writel(val: 0x0, addr: controller_base + TEMP_MSRCTL0); |
906 | |
907 | /* exceed this polling time, IRQ would be inserted */ |
908 | writel(val: 0xffffffff, addr: controller_base + TEMP_AHBTO); |
909 | |
910 | /* number of interrupts per event, 1 is enough */ |
911 | writel(val: 0x0, addr: controller_base + TEMP_MONIDET0); |
912 | writel(val: 0x0, addr: controller_base + TEMP_MONIDET1); |
913 | |
914 | /* |
915 | * The MT8173 thermal controller does not have its own ADC. Instead it |
916 | * uses AHB bus accesses to control the AUXADC. To do this the thermal |
917 | * controller has to be programmed with the physical addresses of the |
918 | * AUXADC registers and with the various bit positions in the AUXADC. |
919 | * Also the thermal controller controls a mux in the APMIXEDSYS register |
920 | * space. |
921 | */ |
922 | |
923 | /* |
924 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) |
925 | * automatically by hw |
926 | */ |
927 | writel(BIT(conf->auxadc_channel), addr: controller_base + TEMP_ADCMUX); |
928 | |
929 | /* AHB address for auxadc mux selection */ |
930 | writel(val: auxadc_phys_base + AUXADC_CON1_CLR_V, |
931 | addr: controller_base + TEMP_ADCMUXADDR); |
932 | |
933 | if (mt->conf->version == MTK_THERMAL_V1) { |
934 | /* AHB address for pnp sensor mux selection */ |
935 | writel(val: apmixed_phys_base + APMIXED_SYS_TS_CON1, |
936 | addr: controller_base + TEMP_PNPMUXADDR); |
937 | } |
938 | |
939 | /* AHB value for auxadc enable */ |
940 | writel(BIT(conf->auxadc_channel), addr: controller_base + TEMP_ADCEN); |
941 | |
942 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ |
943 | writel(val: auxadc_phys_base + AUXADC_CON1_SET_V, |
944 | addr: controller_base + TEMP_ADCENADDR); |
945 | |
946 | /* AHB address for auxadc valid bit */ |
947 | writel(val: auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
948 | addr: controller_base + TEMP_ADCVALIDADDR); |
949 | |
950 | /* AHB address for auxadc voltage output */ |
951 | writel(val: auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
952 | addr: controller_base + TEMP_ADCVOLTADDR); |
953 | |
954 | /* read valid & voltage are at the same register */ |
955 | writel(val: 0x0, addr: controller_base + TEMP_RDCTRL); |
956 | |
957 | /* indicate where the valid bit is */ |
958 | writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), |
959 | addr: controller_base + TEMP_ADCVALIDMASK); |
960 | |
961 | /* no shift */ |
962 | writel(val: 0x0, addr: controller_base + TEMP_ADCVOLTAGESHIFT); |
963 | |
964 | /* enable auxadc mux write transaction */ |
965 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, |
966 | addr: controller_base + TEMP_ADCWRITECTRL); |
967 | |
968 | for (i = 0; i < conf->bank_data[num].num_sensors; i++) |
969 | writel(val: conf->sensor_mux_values[conf->bank_data[num].sensors[i]], |
970 | addr: mt->thermal_base + conf->adcpnp[i]); |
971 | |
972 | writel(val: (1 << conf->bank_data[num].num_sensors) - 1, |
973 | addr: controller_base + TEMP_MONCTL0); |
974 | |
975 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
976 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, |
977 | addr: controller_base + TEMP_ADCWRITECTRL); |
978 | |
979 | mtk_thermal_put_bank(bank); |
980 | } |
981 | |
982 | static u64 of_get_phys_base(struct device_node *np) |
983 | { |
984 | struct resource res; |
985 | |
986 | if (of_address_to_resource(dev: np, index: 0, r: &res)) |
987 | return OF_BAD_ADDR; |
988 | |
989 | return res.start; |
990 | } |
991 | |
992 | static int (struct mtk_thermal *mt, u32 *buf) |
993 | { |
994 | int i; |
995 | |
996 | if (!(buf[0] & CALIB_BUF0_VALID_V1)) |
997 | return -EINVAL; |
998 | |
999 | mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]); |
1000 | |
1001 | for (i = 0; i < mt->conf->num_sensors; i++) { |
1002 | switch (mt->conf->vts_index[i]) { |
1003 | case VTS1: |
1004 | mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]); |
1005 | break; |
1006 | case VTS2: |
1007 | mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]); |
1008 | break; |
1009 | case VTS3: |
1010 | mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]); |
1011 | break; |
1012 | case VTS4: |
1013 | mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]); |
1014 | break; |
1015 | case VTS5: |
1016 | mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]); |
1017 | break; |
1018 | case VTSABB: |
1019 | mt->vts[VTSABB] = |
1020 | CALIB_BUF2_VTS_TSABB_V1(buf[2]); |
1021 | break; |
1022 | default: |
1023 | break; |
1024 | } |
1025 | } |
1026 | |
1027 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]); |
1028 | if (CALIB_BUF1_ID_V1(buf[1]) & |
1029 | CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0])) |
1030 | mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]); |
1031 | else |
1032 | mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]); |
1033 | |
1034 | return 0; |
1035 | } |
1036 | |
1037 | static int (struct mtk_thermal *mt, u32 *buf) |
1038 | { |
1039 | if (!CALIB_BUF1_VALID_V2(buf[1])) |
1040 | return -EINVAL; |
1041 | |
1042 | mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]); |
1043 | mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]); |
1044 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]); |
1045 | mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]); |
1046 | mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]); |
1047 | mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]); |
1048 | mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]); |
1049 | mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]); |
1050 | |
1051 | return 0; |
1052 | } |
1053 | |
1054 | static int (struct mtk_thermal *mt, u32 *buf) |
1055 | { |
1056 | if (!CALIB_BUF1_VALID_V3(buf[1])) |
1057 | return -EINVAL; |
1058 | |
1059 | mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); |
1060 | mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); |
1061 | mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); |
1062 | mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); |
1063 | mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); |
1064 | mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); |
1065 | mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); |
1066 | |
1067 | if (CALIB_BUF1_ID_V3(buf[1]) == 0) |
1068 | mt->o_slope = 0; |
1069 | |
1070 | return 0; |
1071 | } |
1072 | |
1073 | static int mtk_thermal_get_calibration_data(struct device *dev, |
1074 | struct mtk_thermal *mt) |
1075 | { |
1076 | struct nvmem_cell *cell; |
1077 | u32 *buf; |
1078 | size_t len; |
1079 | int i, ret = 0; |
1080 | |
1081 | /* Start with default values */ |
1082 | mt->adc_ge = 512; |
1083 | mt->adc_oe = 512; |
1084 | for (i = 0; i < mt->conf->num_sensors; i++) |
1085 | mt->vts[i] = 260; |
1086 | mt->degc_cali = 40; |
1087 | mt->o_slope = 0; |
1088 | |
1089 | cell = nvmem_cell_get(dev, id: "calibration-data" ); |
1090 | if (IS_ERR(ptr: cell)) { |
1091 | if (PTR_ERR(ptr: cell) == -EPROBE_DEFER) |
1092 | return PTR_ERR(ptr: cell); |
1093 | return 0; |
1094 | } |
1095 | |
1096 | buf = (u32 *)nvmem_cell_read(cell, len: &len); |
1097 | |
1098 | nvmem_cell_put(cell); |
1099 | |
1100 | if (IS_ERR(ptr: buf)) |
1101 | return PTR_ERR(ptr: buf); |
1102 | |
1103 | if (len < 3 * sizeof(u32)) { |
1104 | dev_warn(dev, "invalid calibration data\n" ); |
1105 | ret = -EINVAL; |
1106 | goto out; |
1107 | } |
1108 | |
1109 | switch (mt->conf->version) { |
1110 | case MTK_THERMAL_V1: |
1111 | ret = mtk_thermal_extract_efuse_v1(mt, buf); |
1112 | break; |
1113 | case MTK_THERMAL_V2: |
1114 | ret = mtk_thermal_extract_efuse_v2(mt, buf); |
1115 | break; |
1116 | case MTK_THERMAL_V3: |
1117 | ret = mtk_thermal_extract_efuse_v3(mt, buf); |
1118 | break; |
1119 | default: |
1120 | ret = -EINVAL; |
1121 | break; |
1122 | } |
1123 | |
1124 | if (ret) { |
1125 | dev_info(dev, "Device not calibrated, using default calibration values\n" ); |
1126 | ret = 0; |
1127 | } |
1128 | |
1129 | out: |
1130 | kfree(objp: buf); |
1131 | |
1132 | return ret; |
1133 | } |
1134 | |
1135 | static const struct of_device_id mtk_thermal_of_match[] = { |
1136 | { |
1137 | .compatible = "mediatek,mt8173-thermal" , |
1138 | .data = (void *)&mt8173_thermal_data, |
1139 | }, |
1140 | { |
1141 | .compatible = "mediatek,mt2701-thermal" , |
1142 | .data = (void *)&mt2701_thermal_data, |
1143 | }, |
1144 | { |
1145 | .compatible = "mediatek,mt2712-thermal" , |
1146 | .data = (void *)&mt2712_thermal_data, |
1147 | }, |
1148 | { |
1149 | .compatible = "mediatek,mt7622-thermal" , |
1150 | .data = (void *)&mt7622_thermal_data, |
1151 | }, |
1152 | { |
1153 | .compatible = "mediatek,mt7986-thermal" , |
1154 | .data = (void *)&mt7986_thermal_data, |
1155 | }, |
1156 | { |
1157 | .compatible = "mediatek,mt8183-thermal" , |
1158 | .data = (void *)&mt8183_thermal_data, |
1159 | }, |
1160 | { |
1161 | .compatible = "mediatek,mt8365-thermal" , |
1162 | .data = (void *)&mt8365_thermal_data, |
1163 | }, { |
1164 | }, |
1165 | }; |
1166 | MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); |
1167 | |
1168 | static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt, |
1169 | void __iomem *apmixed_base) |
1170 | { |
1171 | u32 tmp; |
1172 | |
1173 | if (!mt->conf->apmixed_buffer_ctl_reg) |
1174 | return; |
1175 | |
1176 | tmp = readl(addr: apmixed_base + mt->conf->apmixed_buffer_ctl_reg); |
1177 | tmp &= mt->conf->apmixed_buffer_ctl_mask; |
1178 | tmp |= mt->conf->apmixed_buffer_ctl_set; |
1179 | writel(val: tmp, addr: apmixed_base + mt->conf->apmixed_buffer_ctl_reg); |
1180 | udelay(200); |
1181 | } |
1182 | |
1183 | static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt, |
1184 | void __iomem *auxadc_base) |
1185 | { |
1186 | int tmp; |
1187 | |
1188 | writel(val: 0x800, addr: auxadc_base + AUXADC_CON1_SET_V); |
1189 | writel(val: 0x1, addr: mt->thermal_base + TEMP_MONCTL0); |
1190 | tmp = readl(addr: mt->thermal_base + TEMP_MSRCTL1); |
1191 | writel(val: (tmp & (~0x10e)), addr: mt->thermal_base + TEMP_MSRCTL1); |
1192 | } |
1193 | |
1194 | static int mtk_thermal_probe(struct platform_device *pdev) |
1195 | { |
1196 | int ret, i, ctrl_id; |
1197 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; |
1198 | struct mtk_thermal *mt; |
1199 | u64 auxadc_phys_base, apmixed_phys_base; |
1200 | struct thermal_zone_device *tzdev; |
1201 | void __iomem *apmixed_base, *auxadc_base; |
1202 | |
1203 | mt = devm_kzalloc(dev: &pdev->dev, size: sizeof(*mt), GFP_KERNEL); |
1204 | if (!mt) |
1205 | return -ENOMEM; |
1206 | |
1207 | mt->conf = of_device_get_match_data(dev: &pdev->dev); |
1208 | |
1209 | mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, index: 0, NULL); |
1210 | if (IS_ERR(ptr: mt->thermal_base)) |
1211 | return PTR_ERR(ptr: mt->thermal_base); |
1212 | |
1213 | ret = mtk_thermal_get_calibration_data(dev: &pdev->dev, mt); |
1214 | if (ret) |
1215 | return ret; |
1216 | |
1217 | mutex_init(&mt->lock); |
1218 | |
1219 | mt->dev = &pdev->dev; |
1220 | |
1221 | auxadc = of_parse_phandle(np, phandle_name: "mediatek,auxadc" , index: 0); |
1222 | if (!auxadc) { |
1223 | dev_err(&pdev->dev, "missing auxadc node\n" ); |
1224 | return -ENODEV; |
1225 | } |
1226 | |
1227 | auxadc_base = of_iomap(node: auxadc, index: 0); |
1228 | auxadc_phys_base = of_get_phys_base(np: auxadc); |
1229 | |
1230 | of_node_put(node: auxadc); |
1231 | |
1232 | if (auxadc_phys_base == OF_BAD_ADDR) { |
1233 | dev_err(&pdev->dev, "Can't get auxadc phys address\n" ); |
1234 | return -EINVAL; |
1235 | } |
1236 | |
1237 | apmixedsys = of_parse_phandle(np, phandle_name: "mediatek,apmixedsys" , index: 0); |
1238 | if (!apmixedsys) { |
1239 | dev_err(&pdev->dev, "missing apmixedsys node\n" ); |
1240 | return -ENODEV; |
1241 | } |
1242 | |
1243 | apmixed_base = of_iomap(node: apmixedsys, index: 0); |
1244 | apmixed_phys_base = of_get_phys_base(np: apmixedsys); |
1245 | |
1246 | of_node_put(node: apmixedsys); |
1247 | |
1248 | if (apmixed_phys_base == OF_BAD_ADDR) { |
1249 | dev_err(&pdev->dev, "Can't get auxadc phys address\n" ); |
1250 | return -EINVAL; |
1251 | } |
1252 | |
1253 | ret = device_reset_optional(dev: &pdev->dev); |
1254 | if (ret) |
1255 | return ret; |
1256 | |
1257 | mt->clk_auxadc = devm_clk_get_enabled(dev: &pdev->dev, id: "auxadc" ); |
1258 | if (IS_ERR(ptr: mt->clk_auxadc)) { |
1259 | ret = PTR_ERR(ptr: mt->clk_auxadc); |
1260 | dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n" , ret); |
1261 | return ret; |
1262 | } |
1263 | |
1264 | mt->clk_peri_therm = devm_clk_get_enabled(dev: &pdev->dev, id: "therm" ); |
1265 | if (IS_ERR(ptr: mt->clk_peri_therm)) { |
1266 | ret = PTR_ERR(ptr: mt->clk_peri_therm); |
1267 | dev_err(&pdev->dev, "Can't enable peri clk: %d\n" , ret); |
1268 | return ret; |
1269 | } |
1270 | |
1271 | mtk_thermal_turn_on_buffer(mt, apmixed_base); |
1272 | |
1273 | if (mt->conf->version != MTK_THERMAL_V1) |
1274 | mtk_thermal_release_periodic_ts(mt, auxadc_base); |
1275 | |
1276 | if (mt->conf->version == MTK_THERMAL_V1) |
1277 | mt->raw_to_mcelsius = raw_to_mcelsius_v1; |
1278 | else if (mt->conf->version == MTK_THERMAL_V2) |
1279 | mt->raw_to_mcelsius = raw_to_mcelsius_v2; |
1280 | else |
1281 | mt->raw_to_mcelsius = raw_to_mcelsius_v3; |
1282 | |
1283 | for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) |
1284 | for (i = 0; i < mt->conf->num_banks; i++) |
1285 | mtk_thermal_init_bank(mt, num: i, apmixed_phys_base, |
1286 | auxadc_phys_base, ctrl_id); |
1287 | |
1288 | tzdev = devm_thermal_of_zone_register(dev: &pdev->dev, id: 0, data: mt, |
1289 | ops: &mtk_thermal_ops); |
1290 | if (IS_ERR(ptr: tzdev)) |
1291 | return PTR_ERR(ptr: tzdev); |
1292 | |
1293 | ret = devm_thermal_add_hwmon_sysfs(dev: &pdev->dev, tz: tzdev); |
1294 | if (ret) |
1295 | dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs" ); |
1296 | |
1297 | return 0; |
1298 | } |
1299 | |
1300 | static struct platform_driver mtk_thermal_driver = { |
1301 | .probe = mtk_thermal_probe, |
1302 | .driver = { |
1303 | .name = "mtk-thermal" , |
1304 | .of_match_table = mtk_thermal_of_match, |
1305 | }, |
1306 | }; |
1307 | |
1308 | module_platform_driver(mtk_thermal_driver); |
1309 | |
1310 | MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>" ); |
1311 | MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>" ); |
1312 | MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>" ); |
1313 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>" ); |
1314 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>" ); |
1315 | MODULE_DESCRIPTION("Mediatek thermal driver" ); |
1316 | MODULE_LICENSE("GPL v2" ); |
1317 | |