1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #include <linux/bitops.h> |
7 | #include <linux/delay.h> |
8 | #include <linux/err.h> |
9 | #include <linux/iio/consumer.h> |
10 | #include <linux/interrupt.h> |
11 | #include <linux/module.h> |
12 | #include <linux/of.h> |
13 | #include <linux/platform_device.h> |
14 | #include <linux/regmap.h> |
15 | #include <linux/thermal.h> |
16 | |
17 | #include "../thermal_hwmon.h" |
18 | |
19 | #define QPNP_TM_REG_DIG_MAJOR 0x01 |
20 | #define QPNP_TM_REG_TYPE 0x04 |
21 | #define QPNP_TM_REG_SUBTYPE 0x05 |
22 | #define QPNP_TM_REG_STATUS 0x08 |
23 | #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 |
24 | #define QPNP_TM_REG_ALARM_CTRL 0x46 |
25 | |
26 | #define QPNP_TM_TYPE 0x09 |
27 | #define QPNP_TM_SUBTYPE_GEN1 0x08 |
28 | #define QPNP_TM_SUBTYPE_GEN2 0x09 |
29 | |
30 | #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) |
31 | #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) |
32 | #define STATUS_GEN2_STATE_SHIFT 4 |
33 | |
34 | #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) |
35 | #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) |
36 | |
37 | #define SHUTDOWN_CTRL1_RATE_25HZ BIT(3) |
38 | |
39 | #define ALARM_CTRL_FORCE_ENABLE BIT(7) |
40 | |
41 | #define THRESH_COUNT 4 |
42 | #define STAGE_COUNT 3 |
43 | |
44 | /* Over-temperature trip point values in mC */ |
45 | static const long temp_map_gen1[THRESH_COUNT][STAGE_COUNT] = { |
46 | { 105000, 125000, 145000 }, |
47 | { 110000, 130000, 150000 }, |
48 | { 115000, 135000, 155000 }, |
49 | { 120000, 140000, 160000 }, |
50 | }; |
51 | |
52 | static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = { |
53 | { 90000, 110000, 140000 }, |
54 | { 95000, 115000, 145000 }, |
55 | { 100000, 120000, 150000 }, |
56 | { 105000, 125000, 155000 }, |
57 | }; |
58 | |
59 | #define TEMP_THRESH_STEP 5000 /* Threshold step: 5 C */ |
60 | |
61 | #define THRESH_MIN 0 |
62 | #define THRESH_MAX 3 |
63 | |
64 | #define TEMP_STAGE_HYSTERESIS 2000 |
65 | |
66 | /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ |
67 | #define DEFAULT_TEMP 37000 |
68 | |
69 | struct qpnp_tm_chip { |
70 | struct regmap *map; |
71 | struct device *dev; |
72 | struct thermal_zone_device *tz_dev; |
73 | unsigned int subtype; |
74 | long temp; |
75 | unsigned int thresh; |
76 | unsigned int stage; |
77 | unsigned int prev_stage; |
78 | unsigned int base; |
79 | /* protects .thresh, .stage and chip registers */ |
80 | struct mutex lock; |
81 | bool initialized; |
82 | |
83 | struct iio_channel *adc; |
84 | const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; |
85 | }; |
86 | |
87 | /* This array maps from GEN2 alarm state to GEN1 alarm stage */ |
88 | static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3}; |
89 | |
90 | static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data) |
91 | { |
92 | unsigned int val; |
93 | int ret; |
94 | |
95 | ret = regmap_read(map: chip->map, reg: chip->base + addr, val: &val); |
96 | if (ret < 0) |
97 | return ret; |
98 | |
99 | *data = val; |
100 | return 0; |
101 | } |
102 | |
103 | static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data) |
104 | { |
105 | return regmap_write(map: chip->map, reg: chip->base + addr, val: data); |
106 | } |
107 | |
108 | /** |
109 | * qpnp_tm_decode_temp() - return temperature in mC corresponding to the |
110 | * specified over-temperature stage |
111 | * @chip: Pointer to the qpnp_tm chip |
112 | * @stage: Over-temperature stage |
113 | * |
114 | * Return: temperature in mC |
115 | */ |
116 | static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) |
117 | { |
118 | if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 || |
119 | stage > STAGE_COUNT) |
120 | return 0; |
121 | |
122 | return (*chip->temp_map)[chip->thresh][stage - 1]; |
123 | } |
124 | |
125 | /** |
126 | * qpnp_tm_get_temp_stage() - return over-temperature stage |
127 | * @chip: Pointer to the qpnp_tm chip |
128 | * |
129 | * Return: stage (GEN1) or state (GEN2) on success, or errno on failure. |
130 | */ |
131 | static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip) |
132 | { |
133 | int ret; |
134 | u8 reg = 0; |
135 | |
136 | ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, data: ®); |
137 | if (ret < 0) |
138 | return ret; |
139 | |
140 | if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) |
141 | ret = reg & STATUS_GEN1_STAGE_MASK; |
142 | else |
143 | ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT; |
144 | |
145 | return ret; |
146 | } |
147 | |
148 | /* |
149 | * This function updates the internal temp value based on the |
150 | * current thermal stage and threshold as well as the previous stage |
151 | */ |
152 | static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip) |
153 | { |
154 | unsigned int stage, stage_new, stage_old; |
155 | int ret; |
156 | |
157 | WARN_ON(!mutex_is_locked(&chip->lock)); |
158 | |
159 | ret = qpnp_tm_get_temp_stage(chip); |
160 | if (ret < 0) |
161 | return ret; |
162 | stage = ret; |
163 | |
164 | if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) { |
165 | stage_new = stage; |
166 | stage_old = chip->stage; |
167 | } else { |
168 | stage_new = alarm_state_map[stage]; |
169 | stage_old = alarm_state_map[chip->stage]; |
170 | } |
171 | |
172 | if (stage_new > stage_old) { |
173 | /* increasing stage, use lower bound */ |
174 | chip->temp = qpnp_tm_decode_temp(chip, stage: stage_new) |
175 | + TEMP_STAGE_HYSTERESIS; |
176 | } else if (stage_new < stage_old) { |
177 | /* decreasing stage, use upper bound */ |
178 | chip->temp = qpnp_tm_decode_temp(chip, stage: stage_new + 1) |
179 | - TEMP_STAGE_HYSTERESIS; |
180 | } |
181 | |
182 | chip->stage = stage; |
183 | |
184 | return 0; |
185 | } |
186 | |
187 | static int qpnp_tm_get_temp(struct thermal_zone_device *tz, int *temp) |
188 | { |
189 | struct qpnp_tm_chip *chip = thermal_zone_device_priv(tzd: tz); |
190 | int ret, mili_celsius; |
191 | |
192 | if (!temp) |
193 | return -EINVAL; |
194 | |
195 | if (!chip->initialized) { |
196 | *temp = DEFAULT_TEMP; |
197 | return 0; |
198 | } |
199 | |
200 | if (!chip->adc) { |
201 | mutex_lock(&chip->lock); |
202 | ret = qpnp_tm_update_temp_no_adc(chip); |
203 | mutex_unlock(lock: &chip->lock); |
204 | if (ret < 0) |
205 | return ret; |
206 | } else { |
207 | ret = iio_read_channel_processed(chan: chip->adc, val: &mili_celsius); |
208 | if (ret < 0) |
209 | return ret; |
210 | |
211 | chip->temp = mili_celsius; |
212 | } |
213 | |
214 | *temp = chip->temp; |
215 | |
216 | return 0; |
217 | } |
218 | |
219 | static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, |
220 | int temp) |
221 | { |
222 | long stage2_threshold_min = (*chip->temp_map)[THRESH_MIN][1]; |
223 | long stage2_threshold_max = (*chip->temp_map)[THRESH_MAX][1]; |
224 | bool disable_s2_shutdown = false; |
225 | u8 reg; |
226 | |
227 | WARN_ON(!mutex_is_locked(&chip->lock)); |
228 | |
229 | /* |
230 | * Default: S2 and S3 shutdown enabled, thresholds at |
231 | * lowest threshold set, monitoring at 25Hz |
232 | */ |
233 | reg = SHUTDOWN_CTRL1_RATE_25HZ; |
234 | |
235 | if (temp == THERMAL_TEMP_INVALID || |
236 | temp < stage2_threshold_min) { |
237 | chip->thresh = THRESH_MIN; |
238 | goto skip; |
239 | } |
240 | |
241 | if (temp <= stage2_threshold_max) { |
242 | chip->thresh = THRESH_MAX - |
243 | ((stage2_threshold_max - temp) / |
244 | TEMP_THRESH_STEP); |
245 | disable_s2_shutdown = true; |
246 | } else { |
247 | chip->thresh = THRESH_MAX; |
248 | |
249 | if (chip->adc) |
250 | disable_s2_shutdown = true; |
251 | else |
252 | dev_warn(chip->dev, |
253 | "No ADC is configured and critical temperature %d mC is above the maximum stage 2 threshold of %ld mC! Configuring stage 2 shutdown at %ld mC.\n" , |
254 | temp, stage2_threshold_max, stage2_threshold_max); |
255 | } |
256 | |
257 | skip: |
258 | reg |= chip->thresh; |
259 | if (disable_s2_shutdown) |
260 | reg |= SHUTDOWN_CTRL1_OVERRIDE_S2; |
261 | |
262 | return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, data: reg); |
263 | } |
264 | |
265 | static int qpnp_tm_set_trip_temp(struct thermal_zone_device *tz, int trip_id, int temp) |
266 | { |
267 | struct qpnp_tm_chip *chip = thermal_zone_device_priv(tzd: tz); |
268 | struct thermal_trip trip; |
269 | int ret; |
270 | |
271 | ret = __thermal_zone_get_trip(tz: chip->tz_dev, trip_id, trip: &trip); |
272 | if (ret) |
273 | return ret; |
274 | |
275 | if (trip.type != THERMAL_TRIP_CRITICAL) |
276 | return 0; |
277 | |
278 | mutex_lock(&chip->lock); |
279 | ret = qpnp_tm_update_critical_trip_temp(chip, temp); |
280 | mutex_unlock(lock: &chip->lock); |
281 | |
282 | return ret; |
283 | } |
284 | |
285 | static const struct thermal_zone_device_ops qpnp_tm_sensor_ops = { |
286 | .get_temp = qpnp_tm_get_temp, |
287 | .set_trip_temp = qpnp_tm_set_trip_temp, |
288 | }; |
289 | |
290 | static irqreturn_t qpnp_tm_isr(int irq, void *data) |
291 | { |
292 | struct qpnp_tm_chip *chip = data; |
293 | |
294 | thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED); |
295 | |
296 | return IRQ_HANDLED; |
297 | } |
298 | |
299 | static int qpnp_tm_get_critical_trip_temp(struct qpnp_tm_chip *chip) |
300 | { |
301 | struct thermal_trip trip; |
302 | int i, ret; |
303 | |
304 | for (i = 0; i < thermal_zone_get_num_trips(tz: chip->tz_dev); i++) { |
305 | |
306 | ret = thermal_zone_get_trip(tz: chip->tz_dev, trip_id: i, trip: &trip); |
307 | if (ret) |
308 | continue; |
309 | |
310 | if (trip.type == THERMAL_TRIP_CRITICAL) |
311 | return trip.temperature; |
312 | } |
313 | |
314 | return THERMAL_TEMP_INVALID; |
315 | } |
316 | |
317 | /* |
318 | * This function initializes the internal temp value based on only the |
319 | * current thermal stage and threshold. Setup threshold control and |
320 | * disable shutdown override. |
321 | */ |
322 | static int qpnp_tm_init(struct qpnp_tm_chip *chip) |
323 | { |
324 | unsigned int stage; |
325 | int ret; |
326 | u8 reg = 0; |
327 | int crit_temp; |
328 | |
329 | mutex_lock(&chip->lock); |
330 | |
331 | ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, data: ®); |
332 | if (ret < 0) |
333 | goto out; |
334 | |
335 | chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; |
336 | chip->temp = DEFAULT_TEMP; |
337 | |
338 | ret = qpnp_tm_get_temp_stage(chip); |
339 | if (ret < 0) |
340 | goto out; |
341 | chip->stage = ret; |
342 | |
343 | stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1 |
344 | ? chip->stage : alarm_state_map[chip->stage]; |
345 | |
346 | if (stage) |
347 | chip->temp = qpnp_tm_decode_temp(chip, stage); |
348 | |
349 | mutex_unlock(lock: &chip->lock); |
350 | |
351 | crit_temp = qpnp_tm_get_critical_trip_temp(chip); |
352 | |
353 | mutex_lock(&chip->lock); |
354 | |
355 | ret = qpnp_tm_update_critical_trip_temp(chip, temp: crit_temp); |
356 | if (ret < 0) |
357 | goto out; |
358 | |
359 | /* Enable the thermal alarm PMIC module in always-on mode. */ |
360 | reg = ALARM_CTRL_FORCE_ENABLE; |
361 | ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, data: reg); |
362 | |
363 | chip->initialized = true; |
364 | |
365 | out: |
366 | mutex_unlock(lock: &chip->lock); |
367 | return ret; |
368 | } |
369 | |
370 | static int qpnp_tm_probe(struct platform_device *pdev) |
371 | { |
372 | struct qpnp_tm_chip *chip; |
373 | struct device_node *node; |
374 | u8 type, subtype, dig_major; |
375 | u32 res; |
376 | int ret, irq; |
377 | |
378 | node = pdev->dev.of_node; |
379 | |
380 | chip = devm_kzalloc(dev: &pdev->dev, size: sizeof(*chip), GFP_KERNEL); |
381 | if (!chip) |
382 | return -ENOMEM; |
383 | |
384 | dev_set_drvdata(dev: &pdev->dev, data: chip); |
385 | chip->dev = &pdev->dev; |
386 | |
387 | mutex_init(&chip->lock); |
388 | |
389 | chip->map = dev_get_regmap(dev: pdev->dev.parent, NULL); |
390 | if (!chip->map) |
391 | return -ENXIO; |
392 | |
393 | ret = of_property_read_u32(np: node, propname: "reg" , out_value: &res); |
394 | if (ret < 0) |
395 | return ret; |
396 | |
397 | irq = platform_get_irq(pdev, 0); |
398 | if (irq < 0) |
399 | return irq; |
400 | |
401 | /* ADC based measurements are optional */ |
402 | chip->adc = devm_iio_channel_get(dev: &pdev->dev, consumer_channel: "thermal" ); |
403 | if (IS_ERR(ptr: chip->adc)) { |
404 | ret = PTR_ERR(ptr: chip->adc); |
405 | chip->adc = NULL; |
406 | if (ret == -EPROBE_DEFER) |
407 | return ret; |
408 | } |
409 | |
410 | chip->base = res; |
411 | |
412 | ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, data: &type); |
413 | if (ret < 0) |
414 | return dev_err_probe(dev: &pdev->dev, err: ret, |
415 | fmt: "could not read type\n" ); |
416 | |
417 | ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, data: &subtype); |
418 | if (ret < 0) |
419 | return dev_err_probe(dev: &pdev->dev, err: ret, |
420 | fmt: "could not read subtype\n" ); |
421 | |
422 | ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MAJOR, data: &dig_major); |
423 | if (ret < 0) |
424 | return dev_err_probe(dev: &pdev->dev, err: ret, |
425 | fmt: "could not read dig_major\n" ); |
426 | |
427 | if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 |
428 | && subtype != QPNP_TM_SUBTYPE_GEN2)) { |
429 | dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n" , |
430 | type, subtype); |
431 | return -ENODEV; |
432 | } |
433 | |
434 | chip->subtype = subtype; |
435 | if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1) |
436 | chip->temp_map = &temp_map_gen2_v1; |
437 | else |
438 | chip->temp_map = &temp_map_gen1; |
439 | |
440 | /* |
441 | * Register the sensor before initializing the hardware to be able to |
442 | * read the trip points. get_temp() returns the default temperature |
443 | * before the hardware initialization is completed. |
444 | */ |
445 | chip->tz_dev = devm_thermal_of_zone_register( |
446 | dev: &pdev->dev, id: 0, data: chip, ops: &qpnp_tm_sensor_ops); |
447 | if (IS_ERR(ptr: chip->tz_dev)) |
448 | return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: chip->tz_dev), |
449 | fmt: "failed to register sensor\n" ); |
450 | |
451 | ret = qpnp_tm_init(chip); |
452 | if (ret < 0) |
453 | return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "init failed\n" ); |
454 | |
455 | devm_thermal_add_hwmon_sysfs(dev: &pdev->dev, tz: chip->tz_dev); |
456 | |
457 | ret = devm_request_threaded_irq(dev: &pdev->dev, irq, NULL, thread_fn: qpnp_tm_isr, |
458 | IRQF_ONESHOT, devname: node->name, dev_id: chip); |
459 | if (ret < 0) |
460 | return ret; |
461 | |
462 | thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED); |
463 | |
464 | return 0; |
465 | } |
466 | |
467 | static const struct of_device_id qpnp_tm_match_table[] = { |
468 | { .compatible = "qcom,spmi-temp-alarm" }, |
469 | { } |
470 | }; |
471 | MODULE_DEVICE_TABLE(of, qpnp_tm_match_table); |
472 | |
473 | static struct platform_driver qpnp_tm_driver = { |
474 | .driver = { |
475 | .name = "spmi-temp-alarm" , |
476 | .of_match_table = qpnp_tm_match_table, |
477 | }, |
478 | .probe = qpnp_tm_probe, |
479 | }; |
480 | module_platform_driver(qpnp_tm_driver); |
481 | |
482 | MODULE_ALIAS("platform:spmi-temp-alarm" ); |
483 | MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver" ); |
484 | MODULE_LICENSE("GPL v2" ); |
485 | |