| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * OMAP5xxx bandgap registers, bitfields and temperature definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
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| 6 | * Contact: |
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| 7 | * Eduardo Valentin <eduardo.valentin@ti.com> |
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| 8 | */ |
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| 9 | #ifndef __OMAP5XXX_BANDGAP_H |
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| 10 | #define __OMAP5XXX_BANDGAP_H |
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| 11 | |
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| 12 | /** |
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| 13 | * *** OMAP5430 *** |
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| 14 | * |
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| 15 | * Below, in sequence, are the Register definitions, |
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| 16 | * the bitfields and the temperature definitions for OMAP5430. |
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| 17 | */ |
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| 18 | |
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| 19 | /** |
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| 20 | * OMAP5430 register definitions |
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| 21 | * |
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| 22 | * Registers are defined as offsets. The offsets are |
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| 23 | * relative to FUSE_OPP_BGAP_GPU on 5430. |
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| 24 | * |
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| 25 | * Register below are grouped by domain (not necessarily in offset order) |
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| 26 | */ |
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| 27 | |
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| 28 | /* OMAP5430.GPU register offsets */ |
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| 29 | #define OMAP5430_FUSE_OPP_BGAP_GPU 0x0 |
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| 30 | #define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150 |
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| 31 | #define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8 |
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| 32 | #define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4 |
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| 33 | #define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8 |
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| 34 | #define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC |
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| 35 | |
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| 36 | /* OMAP5430.MPU register offsets */ |
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| 37 | #define OMAP5430_FUSE_OPP_BGAP_MPU 0x4 |
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| 38 | #define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C |
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| 39 | #define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4 |
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| 40 | #define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0 |
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| 41 | #define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4 |
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| 42 | #define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8 |
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| 43 | |
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| 44 | /* OMAP5430.MPU register offsets */ |
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| 45 | #define OMAP5430_FUSE_OPP_BGAP_CORE 0x8 |
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| 46 | #define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154 |
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| 47 | #define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC |
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| 48 | #define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8 |
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| 49 | #define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C |
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| 50 | #define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210 |
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| 51 | |
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| 52 | /* OMAP5430.common register offsets */ |
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| 53 | #define OMAP5430_BGAP_CTRL_OFFSET 0x1A0 |
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| 54 | #define OMAP5430_BGAP_STATUS_OFFSET 0x1C8 |
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| 55 | |
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| 56 | /** |
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| 57 | * Register bitfields for OMAP5430 |
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| 58 | * |
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| 59 | * All the macros bellow define the required bits for |
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| 60 | * controlling temperature on OMAP5430. Bit defines are |
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| 61 | * grouped by register. |
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| 62 | */ |
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| 63 | |
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| 64 | /* OMAP5430.TEMP_SENSOR */ |
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| 65 | #define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12) |
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| 66 | #define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11) |
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| 67 | #define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10) |
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| 68 | #define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) |
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| 69 | |
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| 70 | /* OMAP5430.BANDGAP_CTRL */ |
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| 71 | #define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27) |
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| 72 | #define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23) |
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| 73 | #define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22) |
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| 74 | #define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21) |
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| 75 | #define OMAP5430_MASK_HOT_CORE_MASK BIT(5) |
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| 76 | #define OMAP5430_MASK_COLD_CORE_MASK BIT(4) |
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| 77 | #define OMAP5430_MASK_HOT_GPU_MASK BIT(3) |
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| 78 | #define OMAP5430_MASK_COLD_GPU_MASK BIT(2) |
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| 79 | #define OMAP5430_MASK_HOT_MPU_MASK BIT(1) |
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| 80 | #define OMAP5430_MASK_COLD_MPU_MASK BIT(0) |
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| 81 | |
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| 82 | /* OMAP5430.BANDGAP_COUNTER */ |
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| 83 | #define OMAP5430_COUNTER_MASK (0xffffff << 0) |
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| 84 | |
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| 85 | /* OMAP5430.BANDGAP_THRESHOLD */ |
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| 86 | #define OMAP5430_T_HOT_MASK (0x3ff << 16) |
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| 87 | #define OMAP5430_T_COLD_MASK (0x3ff << 0) |
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| 88 | |
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| 89 | /* OMAP5430.TSHUT_THRESHOLD */ |
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| 90 | #define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16) |
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| 91 | #define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0) |
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| 92 | |
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| 93 | /* OMAP5430.BANDGAP_STATUS */ |
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| 94 | #define OMAP5430_HOT_CORE_FLAG_MASK BIT(5) |
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| 95 | #define OMAP5430_COLD_CORE_FLAG_MASK BIT(4) |
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| 96 | #define OMAP5430_HOT_GPU_FLAG_MASK BIT(3) |
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| 97 | #define OMAP5430_COLD_GPU_FLAG_MASK BIT(2) |
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| 98 | #define OMAP5430_HOT_MPU_FLAG_MASK BIT(1) |
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| 99 | #define OMAP5430_COLD_MPU_FLAG_MASK BIT(0) |
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| 100 | |
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| 101 | /** |
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| 102 | * Temperature limits and thresholds for OMAP5430 |
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| 103 | * |
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| 104 | * All the macros bellow are definitions for handling the |
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| 105 | * ADC conversions and representation of temperature limits |
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| 106 | * and thresholds for OMAP5430. Definitions are grouped |
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| 107 | * by temperature domain. |
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| 108 | */ |
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| 109 | |
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| 110 | /* OMAP5430.common temperature definitions */ |
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| 111 | /* ADC conversion table limits */ |
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| 112 | #define OMAP5430_ADC_START_VALUE 540 |
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| 113 | #define OMAP5430_ADC_END_VALUE 945 |
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| 114 | |
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| 115 | /* OMAP5430.GPU temperature definitions */ |
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| 116 | /* bandgap clock limits */ |
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| 117 | #define OMAP5430_GPU_MAX_FREQ 1500000 |
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| 118 | #define OMAP5430_GPU_MIN_FREQ 1000000 |
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| 119 | /* interrupts thresholds */ |
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| 120 | #define OMAP5430_GPU_TSHUT_HOT 915 |
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| 121 | #define OMAP5430_GPU_TSHUT_COLD 900 |
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| 122 | #define OMAP5430_GPU_T_HOT 800 |
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| 123 | #define OMAP5430_GPU_T_COLD 795 |
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| 124 | |
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| 125 | /* OMAP5430.MPU temperature definitions */ |
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| 126 | /* bandgap clock limits */ |
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| 127 | #define OMAP5430_MPU_MAX_FREQ 1500000 |
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| 128 | #define OMAP5430_MPU_MIN_FREQ 1000000 |
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| 129 | /* interrupts thresholds */ |
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| 130 | #define OMAP5430_MPU_TSHUT_HOT 915 |
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| 131 | #define OMAP5430_MPU_TSHUT_COLD 900 |
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| 132 | #define OMAP5430_MPU_T_HOT 800 |
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| 133 | #define OMAP5430_MPU_T_COLD 795 |
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| 134 | |
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| 135 | /* OMAP5430.CORE temperature definitions */ |
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| 136 | /* bandgap clock limits */ |
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| 137 | #define OMAP5430_CORE_MAX_FREQ 1500000 |
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| 138 | #define OMAP5430_CORE_MIN_FREQ 1000000 |
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| 139 | /* interrupts thresholds */ |
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| 140 | #define OMAP5430_CORE_TSHUT_HOT 915 |
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| 141 | #define OMAP5430_CORE_TSHUT_COLD 900 |
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| 142 | #define OMAP5430_CORE_T_HOT 800 |
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| 143 | #define OMAP5430_CORE_T_COLD 795 |
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| 144 | |
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| 145 | #endif /* __OMAP5XXX_BANDGAP_H */ |
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| 146 | |
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