1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Thunderbolt driver - Port/Switch config area registers |
4 | * |
5 | * Every thunderbolt device consists (logically) of a switch with multiple |
6 | * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH, |
7 | * COUNTERS) which are used to configure the device. |
8 | * |
9 | * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> |
10 | * Copyright (C) 2018, Intel Corporation |
11 | */ |
12 | |
13 | #ifndef _TB_REGS |
14 | #define _TB_REGS |
15 | |
16 | #include <linux/types.h> |
17 | |
18 | |
19 | #define TB_ROUTE_SHIFT 8 /* number of bits in a port entry of a route */ |
20 | |
21 | |
22 | /* |
23 | * TODO: should be 63? But we do not know how to receive frames larger than 256 |
24 | * bytes at the frame level. (header + checksum = 16, 60*4 = 240) |
25 | */ |
26 | #define TB_MAX_CONFIG_RW_LENGTH 60 |
27 | |
28 | enum tb_switch_cap { |
29 | TB_SWITCH_CAP_TMU = 0x03, |
30 | TB_SWITCH_CAP_VSE = 0x05, |
31 | }; |
32 | |
33 | enum tb_switch_vse_cap { |
34 | TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */ |
35 | TB_VSE_CAP_TIME2 = 0x03, |
36 | TB_VSE_CAP_CP_LP = 0x04, |
37 | TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */ |
38 | }; |
39 | |
40 | enum tb_port_cap { |
41 | TB_PORT_CAP_PHY = 0x01, |
42 | TB_PORT_CAP_POWER = 0x02, |
43 | TB_PORT_CAP_TIME1 = 0x03, |
44 | TB_PORT_CAP_ADAP = 0x04, |
45 | TB_PORT_CAP_VSE = 0x05, |
46 | TB_PORT_CAP_USB4 = 0x06, |
47 | }; |
48 | |
49 | enum tb_port_state { |
50 | TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */ |
51 | TB_PORT_CONNECTING = 1, /* retry */ |
52 | TB_PORT_UP = 2, |
53 | TB_PORT_TX_CL0S = 3, |
54 | TB_PORT_RX_CL0S = 4, |
55 | TB_PORT_CL1 = 5, |
56 | TB_PORT_CL2 = 6, |
57 | TB_PORT_UNPLUGGED = 7, |
58 | }; |
59 | |
60 | /* capability headers */ |
61 | |
62 | struct tb_cap_basic { |
63 | u8 next; |
64 | /* enum tb_cap cap:8; prevent "narrower than values of its type" */ |
65 | u8 cap; /* if cap == 0x05 then we have a extended capability */ |
66 | } __packed; |
67 | |
68 | /** |
69 | * struct tb_cap_extended_short - Switch extended short capability |
70 | * @next: Pointer to the next capability. If @next and @length are zero |
71 | * then we have a long cap. |
72 | * @cap: Base capability ID (see &enum tb_switch_cap) |
73 | * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap) |
74 | * @length: Length of this capability |
75 | */ |
76 | struct tb_cap_extended_short { |
77 | u8 next; |
78 | u8 cap; |
79 | u8 vsec_id; |
80 | u8 length; |
81 | } __packed; |
82 | |
83 | /** |
84 | * struct tb_cap_extended_long - Switch extended long capability |
85 | * @zero1: This field should be zero |
86 | * @cap: Base capability ID (see &enum tb_switch_cap) |
87 | * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap) |
88 | * @zero2: This field should be zero |
89 | * @next: Pointer to the next capability |
90 | * @length: Length of this capability |
91 | */ |
92 | struct tb_cap_extended_long { |
93 | u8 zero1; |
94 | u8 cap; |
95 | u8 vsec_id; |
96 | u8 zero2; |
97 | u16 next; |
98 | u16 length; |
99 | } __packed; |
100 | |
101 | /** |
102 | * struct tb_cap_any - Structure capable of hold every capability |
103 | * @basic: Basic capability |
104 | * @extended_short: Vendor specific capability |
105 | * @extended_long: Vendor specific extended capability |
106 | */ |
107 | struct tb_cap_any { |
108 | union { |
109 | struct tb_cap_basic basic; |
110 | struct tb_cap_extended_short extended_short; |
111 | struct tb_cap_extended_long extended_long; |
112 | }; |
113 | } __packed; |
114 | |
115 | /* capabilities */ |
116 | |
117 | struct tb_cap_link_controller { |
118 | struct tb_cap_extended_long ; |
119 | u32 count:4; /* number of link controllers */ |
120 | u32 unknown1:4; |
121 | u32 base_offset:8; /* |
122 | * offset (into this capability) of the configuration |
123 | * area of the first link controller |
124 | */ |
125 | u32 length:12; /* link controller configuration area length */ |
126 | u32 unknown2:4; /* TODO check that length is correct */ |
127 | } __packed; |
128 | |
129 | struct tb_cap_phy { |
130 | struct tb_cap_basic ; |
131 | u32 unknown1:16; |
132 | u32 unknown2:14; |
133 | bool disable:1; |
134 | u32 unknown3:11; |
135 | enum tb_port_state state:4; |
136 | u32 unknown4:2; |
137 | } __packed; |
138 | |
139 | struct tb_eeprom_ctl { |
140 | bool fl_sk:1; /* send pulse to transfer one bit */ |
141 | bool fl_cs:1; /* set to 0 before access */ |
142 | bool fl_di:1; /* to eeprom */ |
143 | bool fl_do:1; /* from eeprom */ |
144 | bool bit_banging_enable:1; /* set to 1 before access */ |
145 | bool not_present:1; /* should be 0 */ |
146 | bool unknown1:1; |
147 | bool present:1; /* should be 1 */ |
148 | u32 unknown2:24; |
149 | } __packed; |
150 | |
151 | struct tb_cap_plug_events { |
152 | struct tb_cap_extended_short ; |
153 | u32 __unknown1:2; /* VSC_CS_1 */ |
154 | u32 plug_events:5; /* VSC_CS_1 */ |
155 | u32 __unknown2:25; /* VSC_CS_1 */ |
156 | u32 vsc_cs_2; |
157 | u32 vsc_cs_3; |
158 | struct tb_eeprom_ctl eeprom_ctl; |
159 | u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */ |
160 | u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */ |
161 | } __packed; |
162 | |
163 | /* device headers */ |
164 | |
165 | /* Present on port 0 in TB_CFG_SWITCH at address zero. */ |
166 | struct { |
167 | /* DWORD 0 */ |
168 | u16 ; |
169 | u16 ; |
170 | /* DWORD 1 */ |
171 | u32 :8; |
172 | u32 :6; |
173 | u32 :6; |
174 | u32 :3; |
175 | u32 :1; |
176 | u32 :8; |
177 | /* DWORD 2 */ |
178 | u32 ; |
179 | /* DWORD 3 */ |
180 | u32 :31; |
181 | bool :1; |
182 | /* DWORD 4 */ |
183 | u32 :8; /* |
184 | * RW, pause between plug events in |
185 | * milliseconds. Writing 0x00 is interpreted |
186 | * as 255ms. |
187 | */ |
188 | u32 :8; |
189 | u32 :8; |
190 | u32 :8; |
191 | } __packed; |
192 | |
193 | /* Used with the router thunderbolt_version */ |
194 | #define USB4_VERSION_MAJOR_MASK GENMASK(7, 5) |
195 | |
196 | #define ROUTER_CS_1 0x01 |
197 | #define ROUTER_CS_4 0x04 |
198 | /* Used with the router cmuv field */ |
199 | #define ROUTER_CS_4_CMUV_V1 0x10 |
200 | #define ROUTER_CS_4_CMUV_V2 0x20 |
201 | #define ROUTER_CS_5 0x05 |
202 | #define ROUTER_CS_5_SLP BIT(0) |
203 | #define ROUTER_CS_5_WOP BIT(1) |
204 | #define ROUTER_CS_5_WOU BIT(2) |
205 | #define ROUTER_CS_5_WOD BIT(3) |
206 | #define ROUTER_CS_5_C3S BIT(23) |
207 | #define ROUTER_CS_5_PTO BIT(24) |
208 | #define ROUTER_CS_5_UTO BIT(25) |
209 | #define ROUTER_CS_5_HCO BIT(26) |
210 | #define ROUTER_CS_5_CV BIT(31) |
211 | #define ROUTER_CS_6 0x06 |
212 | #define ROUTER_CS_6_SLPR BIT(0) |
213 | #define ROUTER_CS_6_TNS BIT(1) |
214 | #define ROUTER_CS_6_WOPS BIT(2) |
215 | #define ROUTER_CS_6_WOUS BIT(3) |
216 | #define ROUTER_CS_6_HCI BIT(18) |
217 | #define ROUTER_CS_6_CR BIT(25) |
218 | #define ROUTER_CS_7 0x07 |
219 | #define ROUTER_CS_9 0x09 |
220 | #define ROUTER_CS_25 0x19 |
221 | #define ROUTER_CS_26 0x1a |
222 | #define ROUTER_CS_26_OPCODE_MASK GENMASK(15, 0) |
223 | #define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24) |
224 | #define ROUTER_CS_26_STATUS_SHIFT 24 |
225 | #define ROUTER_CS_26_ONS BIT(30) |
226 | #define ROUTER_CS_26_OV BIT(31) |
227 | |
228 | /* USB4 router operations opcodes */ |
229 | enum usb4_switch_op { |
230 | USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10, |
231 | USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11, |
232 | USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12, |
233 | USB4_SWITCH_OP_NVM_WRITE = 0x20, |
234 | USB4_SWITCH_OP_NVM_AUTH = 0x21, |
235 | USB4_SWITCH_OP_NVM_READ = 0x22, |
236 | USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23, |
237 | USB4_SWITCH_OP_DROM_READ = 0x24, |
238 | USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25, |
239 | USB4_SWITCH_OP_BUFFER_ALLOC = 0x33, |
240 | }; |
241 | |
242 | /* Router TMU configuration */ |
243 | #define TMU_RTR_CS_0 0x00 |
244 | #define TMU_RTR_CS_0_FREQ_WIND_MASK GENMASK(26, 16) |
245 | #define TMU_RTR_CS_0_TD BIT(27) |
246 | #define TMU_RTR_CS_0_UCAP BIT(30) |
247 | #define TMU_RTR_CS_1 0x01 |
248 | #define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK GENMASK(31, 16) |
249 | #define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT 16 |
250 | #define TMU_RTR_CS_2 0x02 |
251 | #define TMU_RTR_CS_3 0x03 |
252 | #define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0) |
253 | #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16) |
254 | #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT 16 |
255 | #define TMU_RTR_CS_15 0x0f |
256 | #define TMU_RTR_CS_15_FREQ_AVG_MASK GENMASK(5, 0) |
257 | #define TMU_RTR_CS_15_DELAY_AVG_MASK GENMASK(11, 6) |
258 | #define TMU_RTR_CS_15_OFFSET_AVG_MASK GENMASK(17, 12) |
259 | #define TMU_RTR_CS_15_ERROR_AVG_MASK GENMASK(23, 18) |
260 | #define TMU_RTR_CS_18 0x12 |
261 | #define TMU_RTR_CS_18_DELTA_AVG_CONST_MASK GENMASK(23, 16) |
262 | #define TMU_RTR_CS_22 0x16 |
263 | #define TMU_RTR_CS_24 0x18 |
264 | #define TMU_RTR_CS_25 0x19 |
265 | |
266 | enum tb_port_type { |
267 | TB_TYPE_INACTIVE = 0x000000, |
268 | TB_TYPE_PORT = 0x000001, |
269 | TB_TYPE_NHI = 0x000002, |
270 | /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */ |
271 | /* TB_TYPE_SATA = 0x080000, lower order bits are not known */ |
272 | TB_TYPE_DP_HDMI_IN = 0x0e0101, |
273 | TB_TYPE_DP_HDMI_OUT = 0x0e0102, |
274 | TB_TYPE_PCIE_DOWN = 0x100101, |
275 | TB_TYPE_PCIE_UP = 0x100102, |
276 | TB_TYPE_USB3_DOWN = 0x200101, |
277 | TB_TYPE_USB3_UP = 0x200102, |
278 | }; |
279 | |
280 | /* Present on every port in TB_CF_PORT at address zero. */ |
281 | struct { |
282 | /* DWORD 0 */ |
283 | u16 ; |
284 | u16 ; |
285 | /* DWORD 1 */ |
286 | u32 :8; |
287 | u32 :11; |
288 | u32 :1; |
289 | u32 :4; |
290 | u32 :8; |
291 | /* DWORD 2 */ |
292 | enum tb_port_type :24; |
293 | u32 :8; |
294 | /* DWORD 3 */ |
295 | u32 :20; |
296 | u32 :6; |
297 | u32 :6; |
298 | /* DWORD 4 */ |
299 | u32 ; |
300 | /* DWORD 5 */ |
301 | u32 :11; |
302 | u32 :11; |
303 | u32 :10; |
304 | /* DWORD 6 */ |
305 | u32 ; |
306 | /* DWORD 7 */ |
307 | u32 ; |
308 | |
309 | } __packed; |
310 | |
311 | /* Basic adapter configuration registers */ |
312 | #define ADP_CS_4 0x04 |
313 | #define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0) |
314 | #define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20) |
315 | #define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20 |
316 | #define ADP_CS_4_LCK BIT(31) |
317 | #define ADP_CS_5 0x05 |
318 | #define ADP_CS_5_LCA_MASK GENMASK(28, 22) |
319 | #define ADP_CS_5_LCA_SHIFT 22 |
320 | #define ADP_CS_5_DHP BIT(31) |
321 | |
322 | /* TMU adapter registers */ |
323 | #define TMU_ADP_CS_3 0x03 |
324 | #define TMU_ADP_CS_3_UDM BIT(29) |
325 | #define TMU_ADP_CS_6 0x06 |
326 | #define TMU_ADP_CS_6_DTS BIT(1) |
327 | #define TMU_ADP_CS_8 0x08 |
328 | #define TMU_ADP_CS_8_REPL_TIMEOUT_MASK GENMASK(14, 0) |
329 | #define TMU_ADP_CS_8_EUDM BIT(15) |
330 | #define TMU_ADP_CS_8_REPL_THRESHOLD_MASK GENMASK(25, 16) |
331 | #define TMU_ADP_CS_9 0x09 |
332 | #define TMU_ADP_CS_9_REPL_N_MASK GENMASK(7, 0) |
333 | #define TMU_ADP_CS_9_DIRSWITCH_N_MASK GENMASK(15, 8) |
334 | #define TMU_ADP_CS_9_ADP_TS_INTERVAL_MASK GENMASK(31, 16) |
335 | |
336 | /* Lane adapter registers */ |
337 | #define LANE_ADP_CS_0 0x00 |
338 | #define LANE_ADP_CS_0_SUPPORTED_SPEED_MASK GENMASK(19, 16) |
339 | #define LANE_ADP_CS_0_SUPPORTED_SPEED_SHIFT 16 |
340 | #define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20) |
341 | #define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT 20 |
342 | #define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL 0x2 |
343 | #define LANE_ADP_CS_0_CL0S_SUPPORT BIT(26) |
344 | #define LANE_ADP_CS_0_CL1_SUPPORT BIT(27) |
345 | #define LANE_ADP_CS_0_CL2_SUPPORT BIT(28) |
346 | #define LANE_ADP_CS_1 0x01 |
347 | #define LANE_ADP_CS_1_TARGET_SPEED_MASK GENMASK(3, 0) |
348 | #define LANE_ADP_CS_1_TARGET_SPEED_GEN3 0xc |
349 | #define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(5, 4) |
350 | #define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4 |
351 | #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1 |
352 | #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3 |
353 | #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK GENMASK(7, 6) |
354 | #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX 0x1 |
355 | #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX 0x2 |
356 | #define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL 0x0 |
357 | #define LANE_ADP_CS_1_CL0S_ENABLE BIT(10) |
358 | #define LANE_ADP_CS_1_CL1_ENABLE BIT(11) |
359 | #define LANE_ADP_CS_1_CL2_ENABLE BIT(12) |
360 | #define LANE_ADP_CS_1_LD BIT(14) |
361 | #define LANE_ADP_CS_1_LB BIT(15) |
362 | #define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16) |
363 | #define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT 16 |
364 | #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8 |
365 | #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4 |
366 | #define LANE_ADP_CS_1_CURRENT_SPEED_GEN4 0x2 |
367 | #define LANE_ADP_CS_1_CURRENT_WIDTH_MASK GENMASK(25, 20) |
368 | #define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT 20 |
369 | #define LANE_ADP_CS_1_PMS BIT(30) |
370 | |
371 | /* USB4 port registers */ |
372 | #define PORT_CS_1 0x01 |
373 | #define PORT_CS_1_LENGTH_SHIFT 8 |
374 | #define PORT_CS_1_TARGET_MASK GENMASK(18, 16) |
375 | #define PORT_CS_1_TARGET_SHIFT 16 |
376 | #define PORT_CS_1_RETIMER_INDEX_SHIFT 20 |
377 | #define PORT_CS_1_WNR_WRITE BIT(24) |
378 | #define PORT_CS_1_NR BIT(25) |
379 | #define PORT_CS_1_RC BIT(26) |
380 | #define PORT_CS_1_PND BIT(31) |
381 | #define PORT_CS_2 0x02 |
382 | #define PORT_CS_18 0x12 |
383 | #define PORT_CS_18_BE BIT(8) |
384 | #define PORT_CS_18_TCM BIT(9) |
385 | #define PORT_CS_18_CPS BIT(10) |
386 | #define PORT_CS_18_WOCS BIT(16) |
387 | #define PORT_CS_18_WODS BIT(17) |
388 | #define PORT_CS_18_WOU4S BIT(18) |
389 | #define PORT_CS_18_CSA BIT(22) |
390 | #define PORT_CS_18_TIP BIT(24) |
391 | #define PORT_CS_19 0x13 |
392 | #define PORT_CS_19_PC BIT(3) |
393 | #define PORT_CS_19_PID BIT(4) |
394 | #define PORT_CS_19_WOC BIT(16) |
395 | #define PORT_CS_19_WOD BIT(17) |
396 | #define PORT_CS_19_WOU4 BIT(18) |
397 | #define PORT_CS_19_START_ASYM BIT(24) |
398 | |
399 | /* Display Port adapter registers */ |
400 | #define ADP_DP_CS_0 0x00 |
401 | #define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16) |
402 | #define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16 |
403 | #define ADP_DP_CS_0_AE BIT(30) |
404 | #define ADP_DP_CS_0_VE BIT(31) |
405 | #define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0) |
406 | #define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11) |
407 | #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11 |
408 | #define ADP_DP_CS_2 0x02 |
409 | #define ADP_DP_CS_2_NRD_MLC_MASK GENMASK(2, 0) |
410 | #define ADP_DP_CS_2_HPD BIT(6) |
411 | #define ADP_DP_CS_2_NRD_MLR_MASK GENMASK(9, 7) |
412 | #define ADP_DP_CS_2_NRD_MLR_SHIFT 7 |
413 | #define ADP_DP_CS_2_CA BIT(10) |
414 | #define ADP_DP_CS_2_GR_MASK GENMASK(12, 11) |
415 | #define ADP_DP_CS_2_GR_SHIFT 11 |
416 | #define ADP_DP_CS_2_GR_0_25G 0x0 |
417 | #define ADP_DP_CS_2_GR_0_5G 0x1 |
418 | #define ADP_DP_CS_2_GR_1G 0x2 |
419 | #define ADP_DP_CS_2_GROUP_ID_MASK GENMASK(15, 13) |
420 | #define ADP_DP_CS_2_GROUP_ID_SHIFT 13 |
421 | #define ADP_DP_CS_2_CM_ID_MASK GENMASK(19, 16) |
422 | #define ADP_DP_CS_2_CM_ID_SHIFT 16 |
423 | #define ADP_DP_CS_2_CMMS BIT(20) |
424 | #define ADP_DP_CS_2_ESTIMATED_BW_MASK GENMASK(31, 24) |
425 | #define ADP_DP_CS_2_ESTIMATED_BW_SHIFT 24 |
426 | #define ADP_DP_CS_3 0x03 |
427 | #define ADP_DP_CS_3_HPDC BIT(9) |
428 | #define DP_LOCAL_CAP 0x04 |
429 | #define DP_REMOTE_CAP 0x05 |
430 | /* For DP IN adapter */ |
431 | #define DP_STATUS 0x06 |
432 | #define DP_STATUS_ALLOCATED_BW_MASK GENMASK(31, 24) |
433 | #define DP_STATUS_ALLOCATED_BW_SHIFT 24 |
434 | /* For DP OUT adapter */ |
435 | #define DP_STATUS_CTRL 0x06 |
436 | #define DP_STATUS_CTRL_CMHS BIT(25) |
437 | #define DP_STATUS_CTRL_UF BIT(26) |
438 | #define DP_COMMON_CAP 0x07 |
439 | /* Only if DP IN supports BW allocation mode */ |
440 | #define ADP_DP_CS_8 0x08 |
441 | #define ADP_DP_CS_8_REQUESTED_BW_MASK GENMASK(7, 0) |
442 | #define ADP_DP_CS_8_DPME BIT(30) |
443 | #define ADP_DP_CS_8_DR BIT(31) |
444 | |
445 | /* |
446 | * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP |
447 | * with exception of DPRX done. |
448 | */ |
449 | #define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8) |
450 | #define DP_COMMON_CAP_RATE_SHIFT 8 |
451 | #define DP_COMMON_CAP_RATE_RBR 0x0 |
452 | #define DP_COMMON_CAP_RATE_HBR 0x1 |
453 | #define DP_COMMON_CAP_RATE_HBR2 0x2 |
454 | #define DP_COMMON_CAP_RATE_HBR3 0x3 |
455 | #define DP_COMMON_CAP_LANES_MASK GENMASK(14, 12) |
456 | #define DP_COMMON_CAP_LANES_SHIFT 12 |
457 | #define DP_COMMON_CAP_1_LANE 0x0 |
458 | #define DP_COMMON_CAP_2_LANES 0x1 |
459 | #define DP_COMMON_CAP_4_LANES 0x2 |
460 | #define DP_COMMON_CAP_UHBR10 BIT(17) |
461 | #define DP_COMMON_CAP_UHBR20 BIT(18) |
462 | #define DP_COMMON_CAP_UHBR13_5 BIT(19) |
463 | #define DP_COMMON_CAP_LTTPR_NS BIT(27) |
464 | #define DP_COMMON_CAP_BW_MODE BIT(28) |
465 | #define DP_COMMON_CAP_DPRX_DONE BIT(31) |
466 | /* Only present if DP IN supports BW allocation mode */ |
467 | #define ADP_DP_CS_8 0x08 |
468 | #define ADP_DP_CS_8_DPME BIT(30) |
469 | #define ADP_DP_CS_8_DR BIT(31) |
470 | |
471 | /* PCIe adapter registers */ |
472 | #define ADP_PCIE_CS_0 0x00 |
473 | #define ADP_PCIE_CS_0_PE BIT(31) |
474 | #define ADP_PCIE_CS_1 0x01 |
475 | #define ADP_PCIE_CS_1_EE BIT(0) |
476 | |
477 | /* USB adapter registers */ |
478 | #define ADP_USB3_CS_0 0x00 |
479 | #define ADP_USB3_CS_0_V BIT(30) |
480 | #define ADP_USB3_CS_0_PE BIT(31) |
481 | #define ADP_USB3_CS_1 0x01 |
482 | #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0) |
483 | #define ADP_USB3_CS_1_CDBW_MASK GENMASK(23, 12) |
484 | #define ADP_USB3_CS_1_CDBW_SHIFT 12 |
485 | #define ADP_USB3_CS_1_HCA BIT(31) |
486 | #define ADP_USB3_CS_2 0x02 |
487 | #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0) |
488 | #define ADP_USB3_CS_2_ADBW_MASK GENMASK(23, 12) |
489 | #define ADP_USB3_CS_2_ADBW_SHIFT 12 |
490 | #define ADP_USB3_CS_2_CMR BIT(31) |
491 | #define ADP_USB3_CS_3 0x03 |
492 | #define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0) |
493 | #define ADP_USB3_CS_4 0x04 |
494 | #define ADP_USB3_CS_4_MSLR_MASK GENMASK(18, 12) |
495 | #define ADP_USB3_CS_4_MSLR_SHIFT 12 |
496 | #define ADP_USB3_CS_4_MSLR_20G 0x1 |
497 | |
498 | /* Hop register from TB_CFG_HOPS. 8 byte per entry. */ |
499 | struct tb_regs_hop { |
500 | /* DWORD 0 */ |
501 | u32 next_hop:11; /* |
502 | * hop to take after sending the packet through |
503 | * out_port (on the incoming port of the next switch) |
504 | */ |
505 | u32 out_port:6; /* next port of the path (on the same switch) */ |
506 | u32 initial_credits:7; |
507 | u32 pmps:1; |
508 | u32 unknown1:6; /* set to zero */ |
509 | bool enable:1; |
510 | |
511 | /* DWORD 1 */ |
512 | u32 weight:4; |
513 | u32 unknown2:4; /* set to zero */ |
514 | u32 priority:3; |
515 | bool drop_packages:1; |
516 | u32 counter:11; /* index into TB_CFG_COUNTERS on this port */ |
517 | bool counter_enable:1; |
518 | bool ingress_fc:1; |
519 | bool egress_fc:1; |
520 | bool ingress_shared_buffer:1; |
521 | bool egress_shared_buffer:1; |
522 | bool pending:1; |
523 | u32 unknown3:3; /* set to zero */ |
524 | } __packed; |
525 | |
526 | /* TMU Thunderbolt 3 registers */ |
527 | #define TB_TIME_VSEC_3_CS_9 0x9 |
528 | #define TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK GENMASK(17, 16) |
529 | #define TB_TIME_VSEC_3_CS_26 0x1a |
530 | #define TB_TIME_VSEC_3_CS_26_TD BIT(22) |
531 | |
532 | /* |
533 | * Used for Titan Ridge only. Bits are part of the same register: TMU_ADP_CS_6 |
534 | * (see above) as in USB4 spec, but these specific bits used for Titan Ridge |
535 | * only and reserved in USB4 spec. |
536 | */ |
537 | #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK GENMASK(3, 2) |
538 | #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1 BIT(2) |
539 | #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 BIT(3) |
540 | |
541 | /* Plug Events registers */ |
542 | #define TB_PLUG_EVENTS_USB_DISABLE BIT(2) |
543 | #define TB_PLUG_EVENTS_CS_1_LANE_DISABLE BIT(3) |
544 | #define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE BIT(4) |
545 | #define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE BIT(5) |
546 | #define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE BIT(6) |
547 | |
548 | #define TB_PLUG_EVENTS_PCIE_WR_DATA 0x1b |
549 | #define TB_PLUG_EVENTS_PCIE_CMD 0x1c |
550 | #define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK GENMASK(9, 0) |
551 | #define TB_PLUG_EVENTS_PCIE_CMD_BR_SHIFT 10 |
552 | #define TB_PLUG_EVENTS_PCIE_CMD_BR_MASK GENMASK(17, 10) |
553 | #define TB_PLUG_EVENTS_PCIE_CMD_RD_WR_MASK BIT(21) |
554 | #define TB_PLUG_EVENTS_PCIE_CMD_WR 0x1 |
555 | #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_SHIFT 22 |
556 | #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_MASK GENMASK(24, 22) |
557 | #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_VAL 0x2 |
558 | #define TB_PLUG_EVENTS_PCIE_CMD_REQ_ACK_MASK BIT(30) |
559 | #define TB_PLUG_EVENTS_PCIE_CMD_TIMEOUT_MASK BIT(31) |
560 | #define TB_PLUG_EVENTS_PCIE_CMD_RD_DATA 0x1d |
561 | |
562 | /* CP Low Power registers */ |
563 | #define TB_LOW_PWR_C1_CL1 0x1 |
564 | #define TB_LOW_PWR_C1_CL1_OBJ_MASK GENMASK(4, 1) |
565 | #define TB_LOW_PWR_C1_CL2_OBJ_MASK GENMASK(4, 1) |
566 | #define TB_LOW_PWR_C1_PORT_A_MASK GENMASK(2, 1) |
567 | #define TB_LOW_PWR_C0_PORT_B_MASK GENMASK(4, 3) |
568 | #define TB_LOW_PWR_C3_CL1 0x3 |
569 | |
570 | /* Common link controller registers */ |
571 | #define TB_LC_DESC 0x02 |
572 | #define TB_LC_DESC_NLC_MASK GENMASK(3, 0) |
573 | #define TB_LC_DESC_SIZE_SHIFT 8 |
574 | #define TB_LC_DESC_SIZE_MASK GENMASK(15, 8) |
575 | #define TB_LC_DESC_PORT_SIZE_SHIFT 16 |
576 | #define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16) |
577 | #define TB_LC_FUSE 0x03 |
578 | #define TB_LC_SNK_ALLOCATION 0x10 |
579 | #define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0) |
580 | #define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1 |
581 | #define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4 |
582 | #define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4) |
583 | #define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1 |
584 | #define TB_LC_POWER 0x740 |
585 | |
586 | /* Link controller registers */ |
587 | #define TB_LC_CS_42 0x2a |
588 | #define TB_LC_CS_42_USB_PLUGGED BIT(31) |
589 | |
590 | #define TB_LC_PORT_ATTR 0x8d |
591 | #define TB_LC_PORT_ATTR_BE BIT(12) |
592 | |
593 | #define TB_LC_SX_CTRL 0x96 |
594 | #define TB_LC_SX_CTRL_WOC BIT(1) |
595 | #define TB_LC_SX_CTRL_WOD BIT(2) |
596 | #define TB_LC_SX_CTRL_WODPC BIT(3) |
597 | #define TB_LC_SX_CTRL_WODPD BIT(4) |
598 | #define TB_LC_SX_CTRL_WOU4 BIT(5) |
599 | #define TB_LC_SX_CTRL_WOP BIT(6) |
600 | #define TB_LC_SX_CTRL_L1C BIT(16) |
601 | #define TB_LC_SX_CTRL_L1D BIT(17) |
602 | #define TB_LC_SX_CTRL_L2C BIT(20) |
603 | #define TB_LC_SX_CTRL_L2D BIT(21) |
604 | #define TB_LC_SX_CTRL_SLI BIT(29) |
605 | #define TB_LC_SX_CTRL_UPSTREAM BIT(30) |
606 | #define TB_LC_SX_CTRL_SLP BIT(31) |
607 | #define TB_LC_LINK_ATTR 0x97 |
608 | #define TB_LC_LINK_ATTR_CPS BIT(18) |
609 | |
610 | #define TB_LC_LINK_REQ 0xad |
611 | #define TB_LC_LINK_REQ_XHCI_CONNECT BIT(31) |
612 | |
613 | #endif |
614 | |