1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | |
3 | #include <linux/bitfield.h> |
4 | #include <linux/bits.h> |
5 | #include <linux/clk.h> |
6 | #include <linux/console.h> |
7 | #include <linux/delay.h> |
8 | #include <linux/io.h> |
9 | #include <linux/irq.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/property.h> |
14 | #include <linux/serial_core.h> |
15 | #include <linux/slab.h> |
16 | #include <linux/tty_flip.h> |
17 | #include <asm/serial.h> |
18 | |
19 | #define DRIVER_NAME "esp32-uart" |
20 | #define DEV_NAME "ttyS" |
21 | #define UART_NR 3 |
22 | |
23 | #define ESP32_UART_TX_FIFO_SIZE 127 |
24 | #define ESP32_UART_RX_FIFO_SIZE 127 |
25 | |
26 | #define UART_FIFO_REG 0x00 |
27 | #define UART_INT_RAW_REG 0x04 |
28 | #define UART_INT_ST_REG 0x08 |
29 | #define UART_INT_ENA_REG 0x0c |
30 | #define UART_INT_CLR_REG 0x10 |
31 | #define UART_RXFIFO_FULL_INT BIT(0) |
32 | #define UART_TXFIFO_EMPTY_INT BIT(1) |
33 | #define UART_BRK_DET_INT BIT(7) |
34 | #define UART_CLKDIV_REG 0x14 |
35 | #define ESP32_UART_CLKDIV GENMASK(19, 0) |
36 | #define ESP32S3_UART_CLKDIV GENMASK(11, 0) |
37 | #define UART_CLKDIV_SHIFT 0 |
38 | #define UART_CLKDIV_FRAG GENMASK(23, 20) |
39 | #define UART_STATUS_REG 0x1c |
40 | #define ESP32_UART_RXFIFO_CNT GENMASK(7, 0) |
41 | #define ESP32S3_UART_RXFIFO_CNT GENMASK(9, 0) |
42 | #define UART_RXFIFO_CNT_SHIFT 0 |
43 | #define UART_DSRN BIT(13) |
44 | #define UART_CTSN BIT(14) |
45 | #define ESP32_UART_TXFIFO_CNT GENMASK(23, 16) |
46 | #define ESP32S3_UART_TXFIFO_CNT GENMASK(25, 16) |
47 | #define UART_TXFIFO_CNT_SHIFT 16 |
48 | #define UART_CONF0_REG 0x20 |
49 | #define UART_PARITY BIT(0) |
50 | #define UART_PARITY_EN BIT(1) |
51 | #define UART_BIT_NUM GENMASK(3, 2) |
52 | #define UART_BIT_NUM_5 0 |
53 | #define UART_BIT_NUM_6 1 |
54 | #define UART_BIT_NUM_7 2 |
55 | #define UART_BIT_NUM_8 3 |
56 | #define UART_STOP_BIT_NUM GENMASK(5, 4) |
57 | #define UART_STOP_BIT_NUM_1 1 |
58 | #define UART_STOP_BIT_NUM_2 3 |
59 | #define UART_SW_RTS BIT(6) |
60 | #define UART_SW_DTR BIT(7) |
61 | #define UART_LOOPBACK BIT(14) |
62 | #define UART_TX_FLOW_EN BIT(15) |
63 | #define UART_RTS_INV BIT(23) |
64 | #define UART_DTR_INV BIT(24) |
65 | #define UART_CONF1_REG 0x24 |
66 | #define UART_RXFIFO_FULL_THRHD_SHIFT 0 |
67 | #define ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT 8 |
68 | #define ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT 10 |
69 | #define ESP32_UART_RX_FLOW_EN BIT(23) |
70 | #define ESP32S3_UART_RX_FLOW_EN BIT(22) |
71 | #define ESP32S3_UART_CLK_CONF_REG 0x78 |
72 | #define ESP32S3_UART_SCLK_DIV_B GENMASK(5, 0) |
73 | #define ESP32S3_UART_SCLK_DIV_A GENMASK(11, 6) |
74 | #define ESP32S3_UART_SCLK_DIV_NUM GENMASK(19, 12) |
75 | #define ESP32S3_UART_SCLK_SEL GENMASK(21, 20) |
76 | #define APB_CLK 1 |
77 | #define RC_FAST_CLK 2 |
78 | #define XTAL_CLK 3 |
79 | #define ESP32S3_UART_SCLK_EN BIT(22) |
80 | #define ESP32S3_UART_RST_CORE BIT(23) |
81 | #define ESP32S3_UART_TX_SCLK_EN BIT(24) |
82 | #define ESP32S3_UART_RX_SCLK_EN BIT(25) |
83 | #define ESP32S3_UART_TX_RST_CORE BIT(26) |
84 | #define ESP32S3_UART_RX_RST_CORE BIT(27) |
85 | |
86 | #define ESP32S3_UART_CLK_CONF_DEFAULT \ |
87 | (ESP32S3_UART_RX_SCLK_EN | \ |
88 | ESP32S3_UART_TX_SCLK_EN | \ |
89 | ESP32S3_UART_SCLK_EN | \ |
90 | FIELD_PREP(ESP32S3_UART_SCLK_SEL, XTAL_CLK)) |
91 | |
92 | struct esp32_port { |
93 | struct uart_port port; |
94 | struct clk *clk; |
95 | }; |
96 | |
97 | struct esp32_uart_variant { |
98 | u32 clkdiv_mask; |
99 | u32 rxfifo_cnt_mask; |
100 | u32 txfifo_cnt_mask; |
101 | u32 txfifo_empty_thrhd_shift; |
102 | u32 rx_flow_en; |
103 | const char *type; |
104 | bool has_clkconf; |
105 | }; |
106 | |
107 | static const struct esp32_uart_variant esp32_variant = { |
108 | .clkdiv_mask = ESP32_UART_CLKDIV, |
109 | .rxfifo_cnt_mask = ESP32_UART_RXFIFO_CNT, |
110 | .txfifo_cnt_mask = ESP32_UART_TXFIFO_CNT, |
111 | .txfifo_empty_thrhd_shift = ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT, |
112 | .rx_flow_en = ESP32_UART_RX_FLOW_EN, |
113 | .type = "ESP32 UART" , |
114 | }; |
115 | |
116 | static const struct esp32_uart_variant esp32s3_variant = { |
117 | .clkdiv_mask = ESP32S3_UART_CLKDIV, |
118 | .rxfifo_cnt_mask = ESP32S3_UART_RXFIFO_CNT, |
119 | .txfifo_cnt_mask = ESP32S3_UART_TXFIFO_CNT, |
120 | .txfifo_empty_thrhd_shift = ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT, |
121 | .rx_flow_en = ESP32S3_UART_RX_FLOW_EN, |
122 | .type = "ESP32S3 UART" , |
123 | .has_clkconf = true, |
124 | }; |
125 | |
126 | static const struct of_device_id esp32_uart_dt_ids[] = { |
127 | { |
128 | .compatible = "esp,esp32-uart" , |
129 | .data = &esp32_variant, |
130 | }, { |
131 | .compatible = "esp,esp32s3-uart" , |
132 | .data = &esp32s3_variant, |
133 | }, { /* sentinel */ } |
134 | }; |
135 | MODULE_DEVICE_TABLE(of, esp32_uart_dt_ids); |
136 | |
137 | static struct esp32_port *esp32_uart_ports[UART_NR]; |
138 | |
139 | static const struct esp32_uart_variant *port_variant(struct uart_port *port) |
140 | { |
141 | return port->private_data; |
142 | } |
143 | |
144 | static void esp32_uart_write(struct uart_port *port, unsigned long reg, u32 v) |
145 | { |
146 | writel(val: v, addr: port->membase + reg); |
147 | } |
148 | |
149 | static u32 esp32_uart_read(struct uart_port *port, unsigned long reg) |
150 | { |
151 | return readl(addr: port->membase + reg); |
152 | } |
153 | |
154 | static u32 esp32_uart_tx_fifo_cnt(struct uart_port *port) |
155 | { |
156 | u32 status = esp32_uart_read(port, UART_STATUS_REG); |
157 | |
158 | return (status & port_variant(port)->txfifo_cnt_mask) >> UART_TXFIFO_CNT_SHIFT; |
159 | } |
160 | |
161 | static u32 esp32_uart_rx_fifo_cnt(struct uart_port *port) |
162 | { |
163 | u32 status = esp32_uart_read(port, UART_STATUS_REG); |
164 | |
165 | return (status & port_variant(port)->rxfifo_cnt_mask) >> UART_RXFIFO_CNT_SHIFT; |
166 | } |
167 | |
168 | /* return TIOCSER_TEMT when transmitter is not busy */ |
169 | static unsigned int esp32_uart_tx_empty(struct uart_port *port) |
170 | { |
171 | return esp32_uart_tx_fifo_cnt(port) ? 0 : TIOCSER_TEMT; |
172 | } |
173 | |
174 | static void esp32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
175 | { |
176 | u32 conf0 = esp32_uart_read(port, UART_CONF0_REG); |
177 | |
178 | conf0 &= ~(UART_LOOPBACK | |
179 | UART_SW_RTS | UART_RTS_INV | |
180 | UART_SW_DTR | UART_DTR_INV); |
181 | |
182 | if (mctrl & TIOCM_RTS) |
183 | conf0 |= UART_SW_RTS; |
184 | if (mctrl & TIOCM_DTR) |
185 | conf0 |= UART_SW_DTR; |
186 | if (mctrl & TIOCM_LOOP) |
187 | conf0 |= UART_LOOPBACK; |
188 | |
189 | esp32_uart_write(port, UART_CONF0_REG, v: conf0); |
190 | } |
191 | |
192 | static unsigned int esp32_uart_get_mctrl(struct uart_port *port) |
193 | { |
194 | u32 status = esp32_uart_read(port, UART_STATUS_REG); |
195 | unsigned int ret = TIOCM_CAR; |
196 | |
197 | if (status & UART_DSRN) |
198 | ret |= TIOCM_DSR; |
199 | if (status & UART_CTSN) |
200 | ret |= TIOCM_CTS; |
201 | |
202 | return ret; |
203 | } |
204 | |
205 | static void esp32_uart_stop_tx(struct uart_port *port) |
206 | { |
207 | u32 int_ena; |
208 | |
209 | int_ena = esp32_uart_read(port, UART_INT_ENA_REG); |
210 | int_ena &= ~UART_TXFIFO_EMPTY_INT; |
211 | esp32_uart_write(port, UART_INT_ENA_REG, v: int_ena); |
212 | } |
213 | |
214 | static void esp32_uart_rxint(struct uart_port *port) |
215 | { |
216 | struct tty_port *tty_port = &port->state->port; |
217 | u32 rx_fifo_cnt = esp32_uart_rx_fifo_cnt(port); |
218 | unsigned long flags; |
219 | u32 i; |
220 | |
221 | if (!rx_fifo_cnt) |
222 | return; |
223 | |
224 | spin_lock_irqsave(&port->lock, flags); |
225 | |
226 | for (i = 0; i < rx_fifo_cnt; ++i) { |
227 | u32 rx = esp32_uart_read(port, UART_FIFO_REG); |
228 | |
229 | if (!rx && |
230 | (esp32_uart_read(port, UART_INT_ST_REG) & UART_BRK_DET_INT)) { |
231 | esp32_uart_write(port, UART_INT_CLR_REG, UART_BRK_DET_INT); |
232 | ++port->icount.brk; |
233 | uart_handle_break(port); |
234 | } else { |
235 | if (uart_handle_sysrq_char(port, ch: (unsigned char)rx)) |
236 | continue; |
237 | tty_insert_flip_char(port: tty_port, ch: rx, TTY_NORMAL); |
238 | ++port->icount.rx; |
239 | } |
240 | } |
241 | spin_unlock_irqrestore(lock: &port->lock, flags); |
242 | |
243 | tty_flip_buffer_push(port: tty_port); |
244 | } |
245 | |
246 | static void esp32_uart_put_char(struct uart_port *port, u8 c) |
247 | { |
248 | esp32_uart_write(port, UART_FIFO_REG, v: c); |
249 | } |
250 | |
251 | static void esp32_uart_put_char_sync(struct uart_port *port, u8 c) |
252 | { |
253 | unsigned long timeout = jiffies + HZ; |
254 | |
255 | while (esp32_uart_tx_fifo_cnt(port) >= ESP32_UART_TX_FIFO_SIZE) { |
256 | if (time_after(jiffies, timeout)) { |
257 | dev_warn(port->dev, "timeout waiting for TX FIFO\n" ); |
258 | return; |
259 | } |
260 | cpu_relax(); |
261 | } |
262 | esp32_uart_put_char(port, c); |
263 | } |
264 | |
265 | static void esp32_uart_transmit_buffer(struct uart_port *port) |
266 | { |
267 | u32 tx_fifo_used = esp32_uart_tx_fifo_cnt(port); |
268 | unsigned int pending; |
269 | u8 ch; |
270 | |
271 | if (tx_fifo_used >= ESP32_UART_TX_FIFO_SIZE) |
272 | return; |
273 | |
274 | pending = uart_port_tx_limited(port, ch, |
275 | ESP32_UART_TX_FIFO_SIZE - tx_fifo_used, |
276 | true, esp32_uart_put_char(port, ch), |
277 | ({})); |
278 | if (pending) { |
279 | u32 int_ena; |
280 | |
281 | int_ena = esp32_uart_read(port, UART_INT_ENA_REG); |
282 | int_ena |= UART_TXFIFO_EMPTY_INT; |
283 | esp32_uart_write(port, UART_INT_ENA_REG, v: int_ena); |
284 | } |
285 | } |
286 | |
287 | static void esp32_uart_txint(struct uart_port *port) |
288 | { |
289 | esp32_uart_transmit_buffer(port); |
290 | } |
291 | |
292 | static irqreturn_t esp32_uart_int(int irq, void *dev_id) |
293 | { |
294 | struct uart_port *port = dev_id; |
295 | u32 status; |
296 | |
297 | status = esp32_uart_read(port, UART_INT_ST_REG); |
298 | |
299 | if (status & (UART_RXFIFO_FULL_INT | UART_BRK_DET_INT)) |
300 | esp32_uart_rxint(port); |
301 | if (status & UART_TXFIFO_EMPTY_INT) |
302 | esp32_uart_txint(port); |
303 | |
304 | esp32_uart_write(port, UART_INT_CLR_REG, v: status); |
305 | |
306 | return IRQ_RETVAL(status); |
307 | } |
308 | |
309 | static void esp32_uart_start_tx(struct uart_port *port) |
310 | { |
311 | esp32_uart_transmit_buffer(port); |
312 | } |
313 | |
314 | static void esp32_uart_stop_rx(struct uart_port *port) |
315 | { |
316 | u32 int_ena; |
317 | |
318 | int_ena = esp32_uart_read(port, UART_INT_ENA_REG); |
319 | int_ena &= ~UART_RXFIFO_FULL_INT; |
320 | esp32_uart_write(port, UART_INT_ENA_REG, v: int_ena); |
321 | } |
322 | |
323 | static int esp32_uart_startup(struct uart_port *port) |
324 | { |
325 | int ret = 0; |
326 | unsigned long flags; |
327 | struct esp32_port *sport = container_of(port, struct esp32_port, port); |
328 | |
329 | ret = clk_prepare_enable(clk: sport->clk); |
330 | if (ret) |
331 | return ret; |
332 | |
333 | ret = request_irq(irq: port->irq, handler: esp32_uart_int, flags: 0, DRIVER_NAME, dev: port); |
334 | if (ret) { |
335 | clk_disable_unprepare(clk: sport->clk); |
336 | return ret; |
337 | } |
338 | |
339 | spin_lock_irqsave(&port->lock, flags); |
340 | if (port_variant(port)->has_clkconf) |
341 | esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG, |
342 | ESP32S3_UART_CLK_CONF_DEFAULT); |
343 | esp32_uart_write(port, UART_CONF1_REG, |
344 | v: (1 << UART_RXFIFO_FULL_THRHD_SHIFT) | |
345 | (1 << port_variant(port)->txfifo_empty_thrhd_shift)); |
346 | esp32_uart_write(port, UART_INT_CLR_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); |
347 | esp32_uart_write(port, UART_INT_ENA_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); |
348 | spin_unlock_irqrestore(lock: &port->lock, flags); |
349 | |
350 | return ret; |
351 | } |
352 | |
353 | static void esp32_uart_shutdown(struct uart_port *port) |
354 | { |
355 | struct esp32_port *sport = container_of(port, struct esp32_port, port); |
356 | |
357 | esp32_uart_write(port, UART_INT_ENA_REG, v: 0); |
358 | free_irq(port->irq, port); |
359 | clk_disable_unprepare(clk: sport->clk); |
360 | } |
361 | |
362 | static bool esp32_uart_set_baud(struct uart_port *port, u32 baud) |
363 | { |
364 | u32 sclk = port->uartclk; |
365 | u32 div = sclk / baud; |
366 | |
367 | if (port_variant(port)->has_clkconf) { |
368 | u32 sclk_div = div / port_variant(port)->clkdiv_mask; |
369 | |
370 | if (div > port_variant(port)->clkdiv_mask) { |
371 | sclk /= (sclk_div + 1); |
372 | div = sclk / baud; |
373 | } |
374 | esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG, |
375 | FIELD_PREP(ESP32S3_UART_SCLK_DIV_NUM, sclk_div) | |
376 | ESP32S3_UART_CLK_CONF_DEFAULT); |
377 | } |
378 | |
379 | if (div <= port_variant(port)->clkdiv_mask) { |
380 | u32 frag = (sclk * 16) / baud - div * 16; |
381 | |
382 | esp32_uart_write(port, UART_CLKDIV_REG, |
383 | v: div | FIELD_PREP(UART_CLKDIV_FRAG, frag)); |
384 | return true; |
385 | } |
386 | |
387 | return false; |
388 | } |
389 | |
390 | static void esp32_uart_set_termios(struct uart_port *port, |
391 | struct ktermios *termios, |
392 | const struct ktermios *old) |
393 | { |
394 | unsigned long flags; |
395 | u32 conf0, conf1; |
396 | u32 baud; |
397 | const u32 rx_flow_en = port_variant(port)->rx_flow_en; |
398 | u32 max_div = port_variant(port)->clkdiv_mask; |
399 | |
400 | termios->c_cflag &= ~CMSPAR; |
401 | |
402 | if (port_variant(port)->has_clkconf) |
403 | max_div *= FIELD_MAX(ESP32S3_UART_SCLK_DIV_NUM); |
404 | |
405 | baud = uart_get_baud_rate(port, termios, old, |
406 | min: port->uartclk / max_div, |
407 | max: port->uartclk / 16); |
408 | |
409 | spin_lock_irqsave(&port->lock, flags); |
410 | |
411 | conf0 = esp32_uart_read(port, UART_CONF0_REG); |
412 | conf0 &= ~(UART_PARITY_EN | UART_PARITY | UART_BIT_NUM | UART_STOP_BIT_NUM); |
413 | |
414 | conf1 = esp32_uart_read(port, UART_CONF1_REG); |
415 | conf1 &= ~rx_flow_en; |
416 | |
417 | if (termios->c_cflag & PARENB) { |
418 | conf0 |= UART_PARITY_EN; |
419 | if (termios->c_cflag & PARODD) |
420 | conf0 |= UART_PARITY; |
421 | } |
422 | |
423 | switch (termios->c_cflag & CSIZE) { |
424 | case CS5: |
425 | conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_5); |
426 | break; |
427 | case CS6: |
428 | conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_6); |
429 | break; |
430 | case CS7: |
431 | conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_7); |
432 | break; |
433 | case CS8: |
434 | conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_8); |
435 | break; |
436 | } |
437 | |
438 | if (termios->c_cflag & CSTOPB) |
439 | conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_2); |
440 | else |
441 | conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_1); |
442 | |
443 | if (termios->c_cflag & CRTSCTS) |
444 | conf1 |= rx_flow_en; |
445 | |
446 | esp32_uart_write(port, UART_CONF0_REG, v: conf0); |
447 | esp32_uart_write(port, UART_CONF1_REG, v: conf1); |
448 | |
449 | if (baud) { |
450 | esp32_uart_set_baud(port, baud); |
451 | uart_update_timeout(port, cflag: termios->c_cflag, baud); |
452 | } else { |
453 | if (esp32_uart_set_baud(port, baud: 115200)) { |
454 | baud = 115200; |
455 | tty_termios_encode_baud_rate(termios, ibaud: baud, obaud: baud); |
456 | uart_update_timeout(port, cflag: termios->c_cflag, baud); |
457 | } else { |
458 | dev_warn(port->dev, |
459 | "unable to set speed to %d baud or the default 115200\n" , |
460 | baud); |
461 | } |
462 | } |
463 | spin_unlock_irqrestore(lock: &port->lock, flags); |
464 | } |
465 | |
466 | static const char *esp32_uart_type(struct uart_port *port) |
467 | { |
468 | return port_variant(port)->type; |
469 | } |
470 | |
471 | /* configure/auto-configure the port */ |
472 | static void esp32_uart_config_port(struct uart_port *port, int flags) |
473 | { |
474 | if (flags & UART_CONFIG_TYPE) |
475 | port->type = PORT_GENERIC; |
476 | } |
477 | |
478 | #ifdef CONFIG_CONSOLE_POLL |
479 | static int esp32_uart_poll_init(struct uart_port *port) |
480 | { |
481 | struct esp32_port *sport = container_of(port, struct esp32_port, port); |
482 | |
483 | return clk_prepare_enable(clk: sport->clk); |
484 | } |
485 | |
486 | static void esp32_uart_poll_put_char(struct uart_port *port, unsigned char c) |
487 | { |
488 | esp32_uart_put_char_sync(port, c); |
489 | } |
490 | |
491 | static int esp32_uart_poll_get_char(struct uart_port *port) |
492 | { |
493 | if (esp32_uart_rx_fifo_cnt(port)) |
494 | return esp32_uart_read(port, UART_FIFO_REG); |
495 | else |
496 | return NO_POLL_CHAR; |
497 | |
498 | } |
499 | #endif |
500 | |
501 | static const struct uart_ops esp32_uart_pops = { |
502 | .tx_empty = esp32_uart_tx_empty, |
503 | .set_mctrl = esp32_uart_set_mctrl, |
504 | .get_mctrl = esp32_uart_get_mctrl, |
505 | .stop_tx = esp32_uart_stop_tx, |
506 | .start_tx = esp32_uart_start_tx, |
507 | .stop_rx = esp32_uart_stop_rx, |
508 | .startup = esp32_uart_startup, |
509 | .shutdown = esp32_uart_shutdown, |
510 | .set_termios = esp32_uart_set_termios, |
511 | .type = esp32_uart_type, |
512 | .config_port = esp32_uart_config_port, |
513 | #ifdef CONFIG_CONSOLE_POLL |
514 | .poll_init = esp32_uart_poll_init, |
515 | .poll_put_char = esp32_uart_poll_put_char, |
516 | .poll_get_char = esp32_uart_poll_get_char, |
517 | #endif |
518 | }; |
519 | |
520 | static void esp32_uart_console_putchar(struct uart_port *port, u8 c) |
521 | { |
522 | esp32_uart_put_char_sync(port, c); |
523 | } |
524 | |
525 | static void esp32_uart_string_write(struct uart_port *port, const char *s, |
526 | unsigned int count) |
527 | { |
528 | uart_console_write(port, s, count, putchar: esp32_uart_console_putchar); |
529 | } |
530 | |
531 | static void |
532 | esp32_uart_console_write(struct console *co, const char *s, unsigned int count) |
533 | { |
534 | struct esp32_port *sport = esp32_uart_ports[co->index]; |
535 | struct uart_port *port = &sport->port; |
536 | unsigned long flags; |
537 | bool locked = true; |
538 | |
539 | if (port->sysrq) |
540 | locked = false; |
541 | else if (oops_in_progress) |
542 | locked = spin_trylock_irqsave(&port->lock, flags); |
543 | else |
544 | spin_lock_irqsave(&port->lock, flags); |
545 | |
546 | esp32_uart_string_write(port, s, count); |
547 | |
548 | if (locked) |
549 | spin_unlock_irqrestore(lock: &port->lock, flags); |
550 | } |
551 | |
552 | static int __init esp32_uart_console_setup(struct console *co, char *options) |
553 | { |
554 | struct esp32_port *sport; |
555 | int baud = 115200; |
556 | int bits = 8; |
557 | int parity = 'n'; |
558 | int flow = 'n'; |
559 | int ret; |
560 | |
561 | /* |
562 | * check whether an invalid uart number has been specified, and |
563 | * if so, search for the first available port that does have |
564 | * console support. |
565 | */ |
566 | if (co->index == -1 || co->index >= ARRAY_SIZE(esp32_uart_ports)) |
567 | co->index = 0; |
568 | |
569 | sport = esp32_uart_ports[co->index]; |
570 | if (!sport) |
571 | return -ENODEV; |
572 | |
573 | ret = clk_prepare_enable(clk: sport->clk); |
574 | if (ret) |
575 | return ret; |
576 | |
577 | if (options) |
578 | uart_parse_options(options, baud: &baud, parity: &parity, bits: &bits, flow: &flow); |
579 | |
580 | return uart_set_options(port: &sport->port, co, baud, parity, bits, flow); |
581 | } |
582 | |
583 | static int esp32_uart_console_exit(struct console *co) |
584 | { |
585 | struct esp32_port *sport = esp32_uart_ports[co->index]; |
586 | |
587 | clk_disable_unprepare(clk: sport->clk); |
588 | return 0; |
589 | } |
590 | |
591 | static struct uart_driver esp32_uart_reg; |
592 | static struct console esp32_uart_console = { |
593 | .name = DEV_NAME, |
594 | .write = esp32_uart_console_write, |
595 | .device = uart_console_device, |
596 | .setup = esp32_uart_console_setup, |
597 | .exit = esp32_uart_console_exit, |
598 | .flags = CON_PRINTBUFFER, |
599 | .index = -1, |
600 | .data = &esp32_uart_reg, |
601 | }; |
602 | |
603 | static void esp32_uart_earlycon_putchar(struct uart_port *port, u8 c) |
604 | { |
605 | esp32_uart_put_char_sync(port, c); |
606 | } |
607 | |
608 | static void esp32_uart_earlycon_write(struct console *con, const char *s, |
609 | unsigned int n) |
610 | { |
611 | struct earlycon_device *dev = con->data; |
612 | |
613 | uart_console_write(port: &dev->port, s, count: n, putchar: esp32_uart_earlycon_putchar); |
614 | } |
615 | |
616 | #ifdef CONFIG_CONSOLE_POLL |
617 | static int esp32_uart_earlycon_read(struct console *con, char *s, unsigned int n) |
618 | { |
619 | struct earlycon_device *dev = con->data; |
620 | unsigned int num_read = 0; |
621 | |
622 | while (num_read < n) { |
623 | int c = esp32_uart_poll_get_char(port: &dev->port); |
624 | |
625 | if (c == NO_POLL_CHAR) |
626 | break; |
627 | s[num_read++] = c; |
628 | } |
629 | return num_read; |
630 | } |
631 | #endif |
632 | |
633 | static int __init esp32xx_uart_early_console_setup(struct earlycon_device *device, |
634 | const char *options) |
635 | { |
636 | if (!device->port.membase) |
637 | return -ENODEV; |
638 | |
639 | device->con->write = esp32_uart_earlycon_write; |
640 | #ifdef CONFIG_CONSOLE_POLL |
641 | device->con->read = esp32_uart_earlycon_read; |
642 | #endif |
643 | if (device->port.uartclk != BASE_BAUD * 16) |
644 | esp32_uart_set_baud(port: &device->port, baud: device->baud); |
645 | |
646 | return 0; |
647 | } |
648 | |
649 | static int __init esp32_uart_early_console_setup(struct earlycon_device *device, |
650 | const char *options) |
651 | { |
652 | device->port.private_data = (void *)&esp32_variant; |
653 | |
654 | return esp32xx_uart_early_console_setup(device, options); |
655 | } |
656 | |
657 | OF_EARLYCON_DECLARE(esp32uart, "esp,esp32-uart" , |
658 | esp32_uart_early_console_setup); |
659 | |
660 | static int __init esp32s3_uart_early_console_setup(struct earlycon_device *device, |
661 | const char *options) |
662 | { |
663 | device->port.private_data = (void *)&esp32s3_variant; |
664 | |
665 | return esp32xx_uart_early_console_setup(device, options); |
666 | } |
667 | |
668 | OF_EARLYCON_DECLARE(esp32s3uart, "esp,esp32s3-uart" , |
669 | esp32s3_uart_early_console_setup); |
670 | |
671 | static struct uart_driver esp32_uart_reg = { |
672 | .owner = THIS_MODULE, |
673 | .driver_name = DRIVER_NAME, |
674 | .dev_name = DEV_NAME, |
675 | .nr = ARRAY_SIZE(esp32_uart_ports), |
676 | .cons = &esp32_uart_console, |
677 | }; |
678 | |
679 | static int esp32_uart_probe(struct platform_device *pdev) |
680 | { |
681 | struct device_node *np = pdev->dev.of_node; |
682 | struct uart_port *port; |
683 | struct esp32_port *sport; |
684 | struct resource *res; |
685 | int ret; |
686 | |
687 | sport = devm_kzalloc(dev: &pdev->dev, size: sizeof(*sport), GFP_KERNEL); |
688 | if (!sport) |
689 | return -ENOMEM; |
690 | |
691 | port = &sport->port; |
692 | |
693 | ret = of_alias_get_id(np, stem: "serial" ); |
694 | if (ret < 0) { |
695 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n" , ret); |
696 | return ret; |
697 | } |
698 | if (ret >= UART_NR) { |
699 | dev_err(&pdev->dev, "driver limited to %d serial ports\n" , UART_NR); |
700 | return -ENOMEM; |
701 | } |
702 | |
703 | port->line = ret; |
704 | |
705 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
706 | if (!res) |
707 | return -ENODEV; |
708 | |
709 | port->mapbase = res->start; |
710 | port->membase = devm_ioremap_resource(dev: &pdev->dev, res); |
711 | if (IS_ERR(ptr: port->membase)) |
712 | return PTR_ERR(ptr: port->membase); |
713 | |
714 | sport->clk = devm_clk_get(dev: &pdev->dev, NULL); |
715 | if (IS_ERR(ptr: sport->clk)) |
716 | return PTR_ERR(ptr: sport->clk); |
717 | |
718 | port->uartclk = clk_get_rate(clk: sport->clk); |
719 | port->dev = &pdev->dev; |
720 | port->type = PORT_GENERIC; |
721 | port->iotype = UPIO_MEM; |
722 | port->irq = platform_get_irq(pdev, 0); |
723 | port->ops = &esp32_uart_pops; |
724 | port->flags = UPF_BOOT_AUTOCONF; |
725 | port->has_sysrq = 1; |
726 | port->fifosize = ESP32_UART_TX_FIFO_SIZE; |
727 | port->private_data = (void *)device_get_match_data(dev: &pdev->dev); |
728 | |
729 | esp32_uart_ports[port->line] = sport; |
730 | |
731 | platform_set_drvdata(pdev, data: port); |
732 | |
733 | return uart_add_one_port(reg: &esp32_uart_reg, port); |
734 | } |
735 | |
736 | static void esp32_uart_remove(struct platform_device *pdev) |
737 | { |
738 | struct uart_port *port = platform_get_drvdata(pdev); |
739 | |
740 | uart_remove_one_port(reg: &esp32_uart_reg, port); |
741 | } |
742 | |
743 | |
744 | static struct platform_driver esp32_uart_driver = { |
745 | .probe = esp32_uart_probe, |
746 | .remove_new = esp32_uart_remove, |
747 | .driver = { |
748 | .name = DRIVER_NAME, |
749 | .of_match_table = esp32_uart_dt_ids, |
750 | }, |
751 | }; |
752 | |
753 | static int __init esp32_uart_init(void) |
754 | { |
755 | int ret; |
756 | |
757 | ret = uart_register_driver(uart: &esp32_uart_reg); |
758 | if (ret) |
759 | return ret; |
760 | |
761 | ret = platform_driver_register(&esp32_uart_driver); |
762 | if (ret) |
763 | uart_unregister_driver(uart: &esp32_uart_reg); |
764 | |
765 | return ret; |
766 | } |
767 | |
768 | static void __exit esp32_uart_exit(void) |
769 | { |
770 | platform_driver_unregister(&esp32_uart_driver); |
771 | uart_unregister_driver(uart: &esp32_uart_reg); |
772 | } |
773 | |
774 | module_init(esp32_uart_init); |
775 | module_exit(esp32_uart_exit); |
776 | |
777 | MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>" ); |
778 | MODULE_LICENSE("GPL" ); |
779 | |