1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2010 Google, Inc. |
4 | * Copyright (C) 2013 NVIDIA Corporation |
5 | * |
6 | * Author: |
7 | * Erik Gilling <konkers@google.com> |
8 | * Benoit Goby <benoit@android.com> |
9 | * Venu Byravarasu <vbyravarasu@nvidia.com> |
10 | */ |
11 | |
12 | #include <linux/delay.h> |
13 | #include <linux/err.h> |
14 | #include <linux/export.h> |
15 | #include <linux/gpio/consumer.h> |
16 | #include <linux/iopoll.h> |
17 | #include <linux/module.h> |
18 | #include <linux/of.h> |
19 | #include <linux/of_platform.h> |
20 | #include <linux/platform_device.h> |
21 | #include <linux/resource.h> |
22 | #include <linux/slab.h> |
23 | #include <linux/spinlock.h> |
24 | |
25 | #include <linux/regulator/consumer.h> |
26 | |
27 | #include <linux/usb/ehci_def.h> |
28 | #include <linux/usb/of.h> |
29 | #include <linux/usb/tegra_usb_phy.h> |
30 | #include <linux/usb/ulpi.h> |
31 | |
32 | #define ULPI_VIEWPORT 0x170 |
33 | |
34 | /* PORTSC PTS/PHCD bits, Tegra20 only */ |
35 | #define TEGRA_USB_PORTSC1 0x184 |
36 | #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) |
37 | #define TEGRA_USB_PORTSC1_PHCD BIT(23) |
38 | |
39 | /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */ |
40 | #define TEGRA_USB_HOSTPC1_DEVLC 0x1b4 |
41 | #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) |
42 | #define TEGRA_USB_HOSTPC1_DEVLC_PHCD BIT(22) |
43 | |
44 | /* Bits of PORTSC1, which will get cleared by writing 1 into them */ |
45 | #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) |
46 | |
47 | #define USB_SUSP_CTRL 0x400 |
48 | #define USB_WAKE_ON_RESUME_EN BIT(2) |
49 | #define USB_WAKE_ON_CNNT_EN_DEV BIT(3) |
50 | #define USB_WAKE_ON_DISCON_EN_DEV BIT(4) |
51 | #define USB_SUSP_CLR BIT(5) |
52 | #define USB_PHY_CLK_VALID BIT(7) |
53 | #define UTMIP_RESET BIT(11) |
54 | #define UHSIC_RESET BIT(11) |
55 | #define UTMIP_PHY_ENABLE BIT(12) |
56 | #define ULPI_PHY_ENABLE BIT(13) |
57 | #define USB_SUSP_SET BIT(14) |
58 | #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) |
59 | |
60 | #define USB_PHY_VBUS_SENSORS 0x404 |
61 | #define B_SESS_VLD_WAKEUP_EN BIT(14) |
62 | #define A_SESS_VLD_WAKEUP_EN BIT(22) |
63 | #define A_VBUS_VLD_WAKEUP_EN BIT(30) |
64 | |
65 | #define USB_PHY_VBUS_WAKEUP_ID 0x408 |
66 | #define ID_INT_EN BIT(0) |
67 | #define ID_CHG_DET BIT(1) |
68 | #define VBUS_WAKEUP_INT_EN BIT(8) |
69 | #define VBUS_WAKEUP_CHG_DET BIT(9) |
70 | #define VBUS_WAKEUP_STS BIT(10) |
71 | #define VBUS_WAKEUP_WAKEUP_EN BIT(30) |
72 | |
73 | #define USB1_LEGACY_CTRL 0x410 |
74 | #define USB1_NO_LEGACY_MODE BIT(0) |
75 | #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) |
76 | #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) |
77 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ |
78 | (1 << 1) |
79 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) |
80 | #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) |
81 | |
82 | #define ULPI_TIMING_CTRL_0 0x424 |
83 | #define ULPI_OUTPUT_PINMUX_BYP BIT(10) |
84 | #define ULPI_CLKOUT_PINMUX_BYP BIT(11) |
85 | |
86 | #define ULPI_TIMING_CTRL_1 0x428 |
87 | #define ULPI_DATA_TRIMMER_LOAD BIT(0) |
88 | #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) |
89 | #define ULPI_STPDIRNXT_TRIMMER_LOAD BIT(16) |
90 | #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) |
91 | #define ULPI_DIR_TRIMMER_LOAD BIT(24) |
92 | #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) |
93 | |
94 | #define UTMIP_PLL_CFG1 0x804 |
95 | #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) |
96 | #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) |
97 | |
98 | #define UTMIP_XCVR_CFG0 0x808 |
99 | #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) |
100 | #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) |
101 | #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) |
102 | #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) |
103 | #define UTMIP_FORCE_PD_POWERDOWN BIT(14) |
104 | #define UTMIP_FORCE_PD2_POWERDOWN BIT(16) |
105 | #define UTMIP_FORCE_PDZI_POWERDOWN BIT(18) |
106 | #define UTMIP_XCVR_LSBIAS_SEL BIT(21) |
107 | #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) |
108 | #define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) |
109 | |
110 | #define UTMIP_BIAS_CFG0 0x80c |
111 | #define UTMIP_OTGPD BIT(11) |
112 | #define UTMIP_BIASPD BIT(10) |
113 | #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0) |
114 | #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2) |
115 | #define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24) |
116 | |
117 | #define UTMIP_HSRX_CFG0 0x810 |
118 | #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) |
119 | #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) |
120 | |
121 | #define UTMIP_HSRX_CFG1 0x814 |
122 | #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) |
123 | |
124 | #define UTMIP_TX_CFG0 0x820 |
125 | #define UTMIP_FS_PREABMLE_J BIT(19) |
126 | #define UTMIP_HS_DISCON_DISABLE BIT(8) |
127 | |
128 | #define UTMIP_MISC_CFG0 0x824 |
129 | #define UTMIP_DPDM_OBSERVE BIT(26) |
130 | #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) |
131 | #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) |
132 | #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) |
133 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) |
134 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) |
135 | #define UTMIP_SUSPEND_EXIT_ON_EDGE BIT(22) |
136 | |
137 | #define UTMIP_MISC_CFG1 0x828 |
138 | #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) |
139 | #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) |
140 | |
141 | #define UTMIP_DEBOUNCE_CFG0 0x82c |
142 | #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) |
143 | |
144 | #define UTMIP_BAT_CHRG_CFG0 0x830 |
145 | #define UTMIP_PD_CHRG BIT(0) |
146 | |
147 | #define UTMIP_SPARE_CFG0 0x834 |
148 | #define FUSE_SETUP_SEL BIT(3) |
149 | |
150 | #define UTMIP_XCVR_CFG1 0x838 |
151 | #define UTMIP_FORCE_PDDISC_POWERDOWN BIT(0) |
152 | #define UTMIP_FORCE_PDCHRP_POWERDOWN BIT(2) |
153 | #define UTMIP_FORCE_PDDR_POWERDOWN BIT(4) |
154 | #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) |
155 | |
156 | #define UTMIP_BIAS_CFG1 0x83c |
157 | #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) |
158 | |
159 | /* For Tegra30 and above only, the address is different in Tegra20 */ |
160 | #define USB_USBMODE 0x1f8 |
161 | #define USB_USBMODE_MASK (3 << 0) |
162 | #define USB_USBMODE_HOST (3 << 0) |
163 | #define USB_USBMODE_DEVICE (2 << 0) |
164 | |
165 | #define PMC_USB_AO 0xf0 |
166 | #define VBUS_WAKEUP_PD_P0 BIT(2) |
167 | #define ID_PD_P0 BIT(3) |
168 | |
169 | static DEFINE_SPINLOCK(utmip_pad_lock); |
170 | static unsigned int utmip_pad_count; |
171 | |
172 | struct tegra_xtal_freq { |
173 | unsigned int freq; |
174 | u8 enable_delay; |
175 | u8 stable_count; |
176 | u8 active_delay; |
177 | u8 xtal_freq_count; |
178 | u16 debounce; |
179 | }; |
180 | |
181 | static const struct tegra_xtal_freq tegra_freq_table[] = { |
182 | { |
183 | .freq = 12000000, |
184 | .enable_delay = 0x02, |
185 | .stable_count = 0x2F, |
186 | .active_delay = 0x04, |
187 | .xtal_freq_count = 0x76, |
188 | .debounce = 0x7530, |
189 | }, |
190 | { |
191 | .freq = 13000000, |
192 | .enable_delay = 0x02, |
193 | .stable_count = 0x33, |
194 | .active_delay = 0x05, |
195 | .xtal_freq_count = 0x7F, |
196 | .debounce = 0x7EF4, |
197 | }, |
198 | { |
199 | .freq = 19200000, |
200 | .enable_delay = 0x03, |
201 | .stable_count = 0x4B, |
202 | .active_delay = 0x06, |
203 | .xtal_freq_count = 0xBB, |
204 | .debounce = 0xBB80, |
205 | }, |
206 | { |
207 | .freq = 26000000, |
208 | .enable_delay = 0x04, |
209 | .stable_count = 0x66, |
210 | .active_delay = 0x09, |
211 | .xtal_freq_count = 0xFE, |
212 | .debounce = 0xFDE8, |
213 | }, |
214 | }; |
215 | |
216 | static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy) |
217 | { |
218 | return container_of(u_phy, struct tegra_usb_phy, u_phy); |
219 | } |
220 | |
221 | static void set_pts(struct tegra_usb_phy *phy, u8 pts_val) |
222 | { |
223 | void __iomem *base = phy->regs; |
224 | u32 val; |
225 | |
226 | if (phy->soc_config->has_hostpc) { |
227 | val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); |
228 | val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); |
229 | val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); |
230 | writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); |
231 | } else { |
232 | val = readl_relaxed(base + TEGRA_USB_PORTSC1); |
233 | val &= ~TEGRA_PORTSC1_RWC_BITS; |
234 | val &= ~TEGRA_USB_PORTSC1_PTS(~0); |
235 | val |= TEGRA_USB_PORTSC1_PTS(pts_val); |
236 | writel_relaxed(val, base + TEGRA_USB_PORTSC1); |
237 | } |
238 | } |
239 | |
240 | static void set_phcd(struct tegra_usb_phy *phy, bool enable) |
241 | { |
242 | void __iomem *base = phy->regs; |
243 | u32 val; |
244 | |
245 | if (phy->soc_config->has_hostpc) { |
246 | val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); |
247 | if (enable) |
248 | val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD; |
249 | else |
250 | val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD; |
251 | writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); |
252 | } else { |
253 | val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; |
254 | if (enable) |
255 | val |= TEGRA_USB_PORTSC1_PHCD; |
256 | else |
257 | val &= ~TEGRA_USB_PORTSC1_PHCD; |
258 | writel_relaxed(val, base + TEGRA_USB_PORTSC1); |
259 | } |
260 | } |
261 | |
262 | static int utmip_pad_open(struct tegra_usb_phy *phy) |
263 | { |
264 | int ret; |
265 | |
266 | ret = clk_prepare_enable(clk: phy->pad_clk); |
267 | if (ret) { |
268 | dev_err(phy->u_phy.dev, |
269 | "Failed to enable UTMI-pads clock: %d\n" , ret); |
270 | return ret; |
271 | } |
272 | |
273 | spin_lock(lock: &utmip_pad_lock); |
274 | |
275 | ret = reset_control_deassert(rstc: phy->pad_rst); |
276 | if (ret) { |
277 | dev_err(phy->u_phy.dev, |
278 | "Failed to initialize UTMI-pads reset: %d\n" , ret); |
279 | goto unlock; |
280 | } |
281 | |
282 | ret = reset_control_assert(rstc: phy->pad_rst); |
283 | if (ret) { |
284 | dev_err(phy->u_phy.dev, |
285 | "Failed to assert UTMI-pads reset: %d\n" , ret); |
286 | goto unlock; |
287 | } |
288 | |
289 | udelay(1); |
290 | |
291 | ret = reset_control_deassert(rstc: phy->pad_rst); |
292 | if (ret) |
293 | dev_err(phy->u_phy.dev, |
294 | "Failed to deassert UTMI-pads reset: %d\n" , ret); |
295 | unlock: |
296 | spin_unlock(lock: &utmip_pad_lock); |
297 | |
298 | clk_disable_unprepare(clk: phy->pad_clk); |
299 | |
300 | return ret; |
301 | } |
302 | |
303 | static int utmip_pad_close(struct tegra_usb_phy *phy) |
304 | { |
305 | int ret; |
306 | |
307 | ret = clk_prepare_enable(clk: phy->pad_clk); |
308 | if (ret) { |
309 | dev_err(phy->u_phy.dev, |
310 | "Failed to enable UTMI-pads clock: %d\n" , ret); |
311 | return ret; |
312 | } |
313 | |
314 | ret = reset_control_assert(rstc: phy->pad_rst); |
315 | if (ret) |
316 | dev_err(phy->u_phy.dev, |
317 | "Failed to assert UTMI-pads reset: %d\n" , ret); |
318 | |
319 | udelay(1); |
320 | |
321 | clk_disable_unprepare(clk: phy->pad_clk); |
322 | |
323 | return ret; |
324 | } |
325 | |
326 | static int utmip_pad_power_on(struct tegra_usb_phy *phy) |
327 | { |
328 | struct tegra_utmip_config *config = phy->config; |
329 | void __iomem *base = phy->pad_regs; |
330 | u32 val; |
331 | int err; |
332 | |
333 | err = clk_prepare_enable(clk: phy->pad_clk); |
334 | if (err) |
335 | return err; |
336 | |
337 | spin_lock(lock: &utmip_pad_lock); |
338 | |
339 | if (utmip_pad_count++ == 0) { |
340 | val = readl_relaxed(base + UTMIP_BIAS_CFG0); |
341 | val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); |
342 | |
343 | if (phy->soc_config->requires_extra_tuning_parameters) { |
344 | val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | |
345 | UTMIP_HSDISCON_LEVEL(~0) | |
346 | UTMIP_HSDISCON_LEVEL_MSB(~0)); |
347 | |
348 | val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level); |
349 | val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level); |
350 | val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level); |
351 | } |
352 | writel_relaxed(val, base + UTMIP_BIAS_CFG0); |
353 | } |
354 | |
355 | if (phy->pad_wakeup) { |
356 | phy->pad_wakeup = false; |
357 | utmip_pad_count--; |
358 | } |
359 | |
360 | spin_unlock(lock: &utmip_pad_lock); |
361 | |
362 | clk_disable_unprepare(clk: phy->pad_clk); |
363 | |
364 | return 0; |
365 | } |
366 | |
367 | static int utmip_pad_power_off(struct tegra_usb_phy *phy) |
368 | { |
369 | void __iomem *base = phy->pad_regs; |
370 | u32 val; |
371 | int ret; |
372 | |
373 | ret = clk_prepare_enable(clk: phy->pad_clk); |
374 | if (ret) |
375 | return ret; |
376 | |
377 | spin_lock(lock: &utmip_pad_lock); |
378 | |
379 | if (!utmip_pad_count) { |
380 | dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n" ); |
381 | ret = -EINVAL; |
382 | goto ulock; |
383 | } |
384 | |
385 | /* |
386 | * In accordance to TRM, OTG and Bias pad circuits could be turned off |
387 | * to save power if wake is enabled, but the VBUS-change detection |
388 | * method is board-specific and these circuits may need to be enabled |
389 | * to generate wakeup event, hence we will just keep them both enabled. |
390 | */ |
391 | if (phy->wakeup_enabled) { |
392 | phy->pad_wakeup = true; |
393 | utmip_pad_count++; |
394 | } |
395 | |
396 | if (--utmip_pad_count == 0) { |
397 | val = readl_relaxed(base + UTMIP_BIAS_CFG0); |
398 | val |= UTMIP_OTGPD | UTMIP_BIASPD; |
399 | writel_relaxed(val, base + UTMIP_BIAS_CFG0); |
400 | } |
401 | ulock: |
402 | spin_unlock(lock: &utmip_pad_lock); |
403 | |
404 | clk_disable_unprepare(clk: phy->pad_clk); |
405 | |
406 | return ret; |
407 | } |
408 | |
409 | static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) |
410 | { |
411 | u32 tmp; |
412 | |
413 | return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result, |
414 | 2000, 6000); |
415 | } |
416 | |
417 | static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) |
418 | { |
419 | void __iomem *base = phy->regs; |
420 | u32 val; |
421 | |
422 | /* |
423 | * The USB driver may have already initiated the phy clock |
424 | * disable so wait to see if the clock turns off and if not |
425 | * then proceed with gating the clock. |
426 | */ |
427 | if (utmi_wait_register(reg: base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, result: 0) == 0) |
428 | return; |
429 | |
430 | if (phy->is_legacy_phy) { |
431 | val = readl_relaxed(base + USB_SUSP_CTRL); |
432 | val |= USB_SUSP_SET; |
433 | writel_relaxed(val, base + USB_SUSP_CTRL); |
434 | |
435 | usleep_range(min: 10, max: 100); |
436 | |
437 | val = readl_relaxed(base + USB_SUSP_CTRL); |
438 | val &= ~USB_SUSP_SET; |
439 | writel_relaxed(val, base + USB_SUSP_CTRL); |
440 | } else { |
441 | set_phcd(phy, enable: true); |
442 | } |
443 | |
444 | if (utmi_wait_register(reg: base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, result: 0)) |
445 | dev_err(phy->u_phy.dev, |
446 | "Timeout waiting for PHY to stabilize on disable\n" ); |
447 | } |
448 | |
449 | static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) |
450 | { |
451 | void __iomem *base = phy->regs; |
452 | u32 val; |
453 | |
454 | /* |
455 | * The USB driver may have already initiated the phy clock |
456 | * enable so wait to see if the clock turns on and if not |
457 | * then proceed with ungating the clock. |
458 | */ |
459 | if (utmi_wait_register(reg: base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, |
460 | USB_PHY_CLK_VALID) == 0) |
461 | return; |
462 | |
463 | if (phy->is_legacy_phy) { |
464 | val = readl_relaxed(base + USB_SUSP_CTRL); |
465 | val |= USB_SUSP_CLR; |
466 | writel_relaxed(val, base + USB_SUSP_CTRL); |
467 | |
468 | usleep_range(min: 10, max: 100); |
469 | |
470 | val = readl_relaxed(base + USB_SUSP_CTRL); |
471 | val &= ~USB_SUSP_CLR; |
472 | writel_relaxed(val, base + USB_SUSP_CTRL); |
473 | } else { |
474 | set_phcd(phy, enable: false); |
475 | } |
476 | |
477 | if (utmi_wait_register(reg: base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, |
478 | USB_PHY_CLK_VALID)) |
479 | dev_err(phy->u_phy.dev, |
480 | "Timeout waiting for PHY to stabilize on enable\n" ); |
481 | } |
482 | |
483 | static int utmi_phy_power_on(struct tegra_usb_phy *phy) |
484 | { |
485 | struct tegra_utmip_config *config = phy->config; |
486 | void __iomem *base = phy->regs; |
487 | u32 val; |
488 | int err; |
489 | |
490 | val = readl_relaxed(base + USB_SUSP_CTRL); |
491 | val |= UTMIP_RESET; |
492 | writel_relaxed(val, base + USB_SUSP_CTRL); |
493 | |
494 | if (phy->is_legacy_phy) { |
495 | val = readl_relaxed(base + USB1_LEGACY_CTRL); |
496 | val |= USB1_NO_LEGACY_MODE; |
497 | writel_relaxed(val, base + USB1_LEGACY_CTRL); |
498 | } |
499 | |
500 | val = readl_relaxed(base + UTMIP_TX_CFG0); |
501 | val |= UTMIP_FS_PREABMLE_J; |
502 | writel_relaxed(val, base + UTMIP_TX_CFG0); |
503 | |
504 | val = readl_relaxed(base + UTMIP_HSRX_CFG0); |
505 | val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); |
506 | val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); |
507 | val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); |
508 | writel_relaxed(val, base + UTMIP_HSRX_CFG0); |
509 | |
510 | val = readl_relaxed(base + UTMIP_HSRX_CFG1); |
511 | val &= ~UTMIP_HS_SYNC_START_DLY(~0); |
512 | val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); |
513 | writel_relaxed(val, base + UTMIP_HSRX_CFG1); |
514 | |
515 | val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0); |
516 | val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); |
517 | val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); |
518 | writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0); |
519 | |
520 | val = readl_relaxed(base + UTMIP_MISC_CFG0); |
521 | val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; |
522 | writel_relaxed(val, base + UTMIP_MISC_CFG0); |
523 | |
524 | if (!phy->soc_config->utmi_pll_config_in_car_module) { |
525 | val = readl_relaxed(base + UTMIP_MISC_CFG1); |
526 | val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | |
527 | UTMIP_PLLU_STABLE_COUNT(~0)); |
528 | val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | |
529 | UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); |
530 | writel_relaxed(val, base + UTMIP_MISC_CFG1); |
531 | |
532 | val = readl_relaxed(base + UTMIP_PLL_CFG1); |
533 | val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | |
534 | UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); |
535 | val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | |
536 | UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); |
537 | writel_relaxed(val, base + UTMIP_PLL_CFG1); |
538 | } |
539 | |
540 | val = readl_relaxed(base + USB_SUSP_CTRL); |
541 | val &= ~USB_WAKE_ON_RESUME_EN; |
542 | writel_relaxed(val, base + USB_SUSP_CTRL); |
543 | |
544 | if (phy->mode != USB_DR_MODE_HOST) { |
545 | val = readl_relaxed(base + USB_SUSP_CTRL); |
546 | val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); |
547 | writel_relaxed(val, base + USB_SUSP_CTRL); |
548 | |
549 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); |
550 | val &= ~VBUS_WAKEUP_WAKEUP_EN; |
551 | val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET); |
552 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); |
553 | |
554 | val = readl_relaxed(base + USB_PHY_VBUS_SENSORS); |
555 | val &= ~(A_VBUS_VLD_WAKEUP_EN | A_SESS_VLD_WAKEUP_EN); |
556 | val &= ~(B_SESS_VLD_WAKEUP_EN); |
557 | writel_relaxed(val, base + USB_PHY_VBUS_SENSORS); |
558 | |
559 | val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); |
560 | val &= ~UTMIP_PD_CHRG; |
561 | writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); |
562 | } else { |
563 | val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); |
564 | val |= UTMIP_PD_CHRG; |
565 | writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); |
566 | } |
567 | |
568 | err = utmip_pad_power_on(phy); |
569 | if (err) |
570 | return err; |
571 | |
572 | val = readl_relaxed(base + UTMIP_XCVR_CFG0); |
573 | val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | |
574 | UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL | |
575 | UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) | |
576 | UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0)); |
577 | |
578 | if (!config->xcvr_setup_use_fuses) { |
579 | val |= UTMIP_XCVR_SETUP(config->xcvr_setup); |
580 | val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); |
581 | } |
582 | val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); |
583 | val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); |
584 | |
585 | if (phy->soc_config->requires_extra_tuning_parameters) { |
586 | val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); |
587 | val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew); |
588 | val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew); |
589 | } |
590 | writel_relaxed(val, base + UTMIP_XCVR_CFG0); |
591 | |
592 | val = readl_relaxed(base + UTMIP_XCVR_CFG1); |
593 | val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | |
594 | UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); |
595 | val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); |
596 | writel_relaxed(val, base + UTMIP_XCVR_CFG1); |
597 | |
598 | val = readl_relaxed(base + UTMIP_BIAS_CFG1); |
599 | val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); |
600 | val |= UTMIP_BIAS_PDTRK_COUNT(0x5); |
601 | writel_relaxed(val, base + UTMIP_BIAS_CFG1); |
602 | |
603 | val = readl_relaxed(base + UTMIP_SPARE_CFG0); |
604 | if (config->xcvr_setup_use_fuses) |
605 | val |= FUSE_SETUP_SEL; |
606 | else |
607 | val &= ~FUSE_SETUP_SEL; |
608 | writel_relaxed(val, base + UTMIP_SPARE_CFG0); |
609 | |
610 | if (!phy->is_legacy_phy) { |
611 | val = readl_relaxed(base + USB_SUSP_CTRL); |
612 | val |= UTMIP_PHY_ENABLE; |
613 | writel_relaxed(val, base + USB_SUSP_CTRL); |
614 | } |
615 | |
616 | val = readl_relaxed(base + USB_SUSP_CTRL); |
617 | val &= ~UTMIP_RESET; |
618 | writel_relaxed(val, base + USB_SUSP_CTRL); |
619 | |
620 | if (phy->is_legacy_phy) { |
621 | val = readl_relaxed(base + USB1_LEGACY_CTRL); |
622 | val &= ~USB1_VBUS_SENSE_CTL_MASK; |
623 | val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; |
624 | writel_relaxed(val, base + USB1_LEGACY_CTRL); |
625 | |
626 | val = readl_relaxed(base + USB_SUSP_CTRL); |
627 | val &= ~USB_SUSP_SET; |
628 | writel_relaxed(val, base + USB_SUSP_CTRL); |
629 | } |
630 | |
631 | utmi_phy_clk_enable(phy); |
632 | |
633 | if (phy->soc_config->requires_usbmode_setup) { |
634 | val = readl_relaxed(base + USB_USBMODE); |
635 | val &= ~USB_USBMODE_MASK; |
636 | if (phy->mode == USB_DR_MODE_HOST) |
637 | val |= USB_USBMODE_HOST; |
638 | else |
639 | val |= USB_USBMODE_DEVICE; |
640 | writel_relaxed(val, base + USB_USBMODE); |
641 | } |
642 | |
643 | if (!phy->is_legacy_phy) |
644 | set_pts(phy, pts_val: 0); |
645 | |
646 | return 0; |
647 | } |
648 | |
649 | static int utmi_phy_power_off(struct tegra_usb_phy *phy) |
650 | { |
651 | void __iomem *base = phy->regs; |
652 | u32 val; |
653 | |
654 | /* |
655 | * Give hardware time to settle down after VBUS disconnection, |
656 | * otherwise PHY will immediately wake up from suspend. |
657 | */ |
658 | if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST) |
659 | readl_relaxed_poll_timeout(base + USB_PHY_VBUS_WAKEUP_ID, |
660 | val, !(val & VBUS_WAKEUP_STS), |
661 | 5000, 100000); |
662 | |
663 | utmi_phy_clk_disable(phy); |
664 | |
665 | /* PHY won't resume if reset is asserted */ |
666 | if (!phy->wakeup_enabled) { |
667 | val = readl_relaxed(base + USB_SUSP_CTRL); |
668 | val |= UTMIP_RESET; |
669 | writel_relaxed(val, base + USB_SUSP_CTRL); |
670 | } |
671 | |
672 | val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); |
673 | val |= UTMIP_PD_CHRG; |
674 | writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); |
675 | |
676 | if (!phy->wakeup_enabled) { |
677 | val = readl_relaxed(base + UTMIP_XCVR_CFG0); |
678 | val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | |
679 | UTMIP_FORCE_PDZI_POWERDOWN; |
680 | writel_relaxed(val, base + UTMIP_XCVR_CFG0); |
681 | } |
682 | |
683 | val = readl_relaxed(base + UTMIP_XCVR_CFG1); |
684 | val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | |
685 | UTMIP_FORCE_PDDR_POWERDOWN; |
686 | writel_relaxed(val, base + UTMIP_XCVR_CFG1); |
687 | |
688 | if (phy->wakeup_enabled) { |
689 | val = readl_relaxed(base + USB_SUSP_CTRL); |
690 | val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); |
691 | val |= USB_WAKEUP_DEBOUNCE_COUNT(5); |
692 | val |= USB_WAKE_ON_RESUME_EN; |
693 | writel_relaxed(val, base + USB_SUSP_CTRL); |
694 | |
695 | /* |
696 | * Ask VBUS sensor to generate wake event once cable is |
697 | * connected. |
698 | */ |
699 | if (phy->mode != USB_DR_MODE_HOST) { |
700 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); |
701 | val |= VBUS_WAKEUP_WAKEUP_EN; |
702 | val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET); |
703 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); |
704 | |
705 | val = readl_relaxed(base + USB_PHY_VBUS_SENSORS); |
706 | val |= A_VBUS_VLD_WAKEUP_EN; |
707 | writel_relaxed(val, base + USB_PHY_VBUS_SENSORS); |
708 | } |
709 | } |
710 | |
711 | return utmip_pad_power_off(phy); |
712 | } |
713 | |
714 | static void utmi_phy_preresume(struct tegra_usb_phy *phy) |
715 | { |
716 | void __iomem *base = phy->regs; |
717 | u32 val; |
718 | |
719 | val = readl_relaxed(base + UTMIP_TX_CFG0); |
720 | val |= UTMIP_HS_DISCON_DISABLE; |
721 | writel_relaxed(val, base + UTMIP_TX_CFG0); |
722 | } |
723 | |
724 | static void utmi_phy_postresume(struct tegra_usb_phy *phy) |
725 | { |
726 | void __iomem *base = phy->regs; |
727 | u32 val; |
728 | |
729 | val = readl_relaxed(base + UTMIP_TX_CFG0); |
730 | val &= ~UTMIP_HS_DISCON_DISABLE; |
731 | writel_relaxed(val, base + UTMIP_TX_CFG0); |
732 | } |
733 | |
734 | static void utmi_phy_restore_start(struct tegra_usb_phy *phy, |
735 | enum tegra_usb_phy_port_speed port_speed) |
736 | { |
737 | void __iomem *base = phy->regs; |
738 | u32 val; |
739 | |
740 | val = readl_relaxed(base + UTMIP_MISC_CFG0); |
741 | val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); |
742 | if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) |
743 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; |
744 | else |
745 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; |
746 | writel_relaxed(val, base + UTMIP_MISC_CFG0); |
747 | usleep_range(min: 1, max: 10); |
748 | |
749 | val = readl_relaxed(base + UTMIP_MISC_CFG0); |
750 | val |= UTMIP_DPDM_OBSERVE; |
751 | writel_relaxed(val, base + UTMIP_MISC_CFG0); |
752 | usleep_range(min: 10, max: 100); |
753 | } |
754 | |
755 | static void utmi_phy_restore_end(struct tegra_usb_phy *phy) |
756 | { |
757 | void __iomem *base = phy->regs; |
758 | u32 val; |
759 | |
760 | val = readl_relaxed(base + UTMIP_MISC_CFG0); |
761 | val &= ~UTMIP_DPDM_OBSERVE; |
762 | writel_relaxed(val, base + UTMIP_MISC_CFG0); |
763 | usleep_range(min: 10, max: 100); |
764 | } |
765 | |
766 | static int ulpi_phy_power_on(struct tegra_usb_phy *phy) |
767 | { |
768 | void __iomem *base = phy->regs; |
769 | u32 val; |
770 | int err; |
771 | |
772 | gpiod_set_value_cansleep(desc: phy->reset_gpio, value: 1); |
773 | |
774 | err = clk_prepare_enable(clk: phy->clk); |
775 | if (err) |
776 | return err; |
777 | |
778 | usleep_range(min: 5000, max: 6000); |
779 | |
780 | gpiod_set_value_cansleep(desc: phy->reset_gpio, value: 0); |
781 | |
782 | usleep_range(min: 1000, max: 2000); |
783 | |
784 | val = readl_relaxed(base + USB_SUSP_CTRL); |
785 | val |= UHSIC_RESET; |
786 | writel_relaxed(val, base + USB_SUSP_CTRL); |
787 | |
788 | val = readl_relaxed(base + ULPI_TIMING_CTRL_0); |
789 | val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; |
790 | writel_relaxed(val, base + ULPI_TIMING_CTRL_0); |
791 | |
792 | val = readl_relaxed(base + USB_SUSP_CTRL); |
793 | val |= ULPI_PHY_ENABLE; |
794 | writel_relaxed(val, base + USB_SUSP_CTRL); |
795 | |
796 | val = 0; |
797 | writel_relaxed(val, base + ULPI_TIMING_CTRL_1); |
798 | |
799 | val |= ULPI_DATA_TRIMMER_SEL(4); |
800 | val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); |
801 | val |= ULPI_DIR_TRIMMER_SEL(4); |
802 | writel_relaxed(val, base + ULPI_TIMING_CTRL_1); |
803 | usleep_range(min: 10, max: 100); |
804 | |
805 | val |= ULPI_DATA_TRIMMER_LOAD; |
806 | val |= ULPI_STPDIRNXT_TRIMMER_LOAD; |
807 | val |= ULPI_DIR_TRIMMER_LOAD; |
808 | writel_relaxed(val, base + ULPI_TIMING_CTRL_1); |
809 | |
810 | /* Fix VbusInvalid due to floating VBUS */ |
811 | err = usb_phy_io_write(x: phy->ulpi, val: 0x40, reg: 0x08); |
812 | if (err) { |
813 | dev_err(phy->u_phy.dev, "ULPI write failed: %d\n" , err); |
814 | goto disable_clk; |
815 | } |
816 | |
817 | err = usb_phy_io_write(x: phy->ulpi, val: 0x80, reg: 0x0B); |
818 | if (err) { |
819 | dev_err(phy->u_phy.dev, "ULPI write failed: %d\n" , err); |
820 | goto disable_clk; |
821 | } |
822 | |
823 | val = readl_relaxed(base + USB_SUSP_CTRL); |
824 | val |= USB_SUSP_CLR; |
825 | writel_relaxed(val, base + USB_SUSP_CTRL); |
826 | usleep_range(min: 100, max: 1000); |
827 | |
828 | val = readl_relaxed(base + USB_SUSP_CTRL); |
829 | val &= ~USB_SUSP_CLR; |
830 | writel_relaxed(val, base + USB_SUSP_CTRL); |
831 | |
832 | return 0; |
833 | |
834 | disable_clk: |
835 | clk_disable_unprepare(clk: phy->clk); |
836 | |
837 | return err; |
838 | } |
839 | |
840 | static int ulpi_phy_power_off(struct tegra_usb_phy *phy) |
841 | { |
842 | gpiod_set_value_cansleep(desc: phy->reset_gpio, value: 1); |
843 | usleep_range(min: 5000, max: 6000); |
844 | clk_disable_unprepare(clk: phy->clk); |
845 | |
846 | /* |
847 | * Wakeup currently unimplemented for ULPI, thus PHY needs to be |
848 | * force-resumed. |
849 | */ |
850 | if (WARN_ON_ONCE(phy->wakeup_enabled)) { |
851 | ulpi_phy_power_on(phy); |
852 | return -EOPNOTSUPP; |
853 | } |
854 | |
855 | return 0; |
856 | } |
857 | |
858 | static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) |
859 | { |
860 | int err; |
861 | |
862 | if (phy->powered_on) |
863 | return 0; |
864 | |
865 | if (phy->is_ulpi_phy) |
866 | err = ulpi_phy_power_on(phy); |
867 | else |
868 | err = utmi_phy_power_on(phy); |
869 | if (err) |
870 | return err; |
871 | |
872 | phy->powered_on = true; |
873 | |
874 | /* Let PHY settle down */ |
875 | usleep_range(min: 2000, max: 2500); |
876 | |
877 | return 0; |
878 | } |
879 | |
880 | static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) |
881 | { |
882 | int err; |
883 | |
884 | if (!phy->powered_on) |
885 | return 0; |
886 | |
887 | if (phy->is_ulpi_phy) |
888 | err = ulpi_phy_power_off(phy); |
889 | else |
890 | err = utmi_phy_power_off(phy); |
891 | if (err) |
892 | return err; |
893 | |
894 | phy->powered_on = false; |
895 | |
896 | return 0; |
897 | } |
898 | |
899 | static void tegra_usb_phy_shutdown(struct usb_phy *u_phy) |
900 | { |
901 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
902 | |
903 | if (WARN_ON(!phy->freq)) |
904 | return; |
905 | |
906 | usb_phy_set_wakeup(x: u_phy, enabled: false); |
907 | tegra_usb_phy_power_off(phy); |
908 | |
909 | if (!phy->is_ulpi_phy) |
910 | utmip_pad_close(phy); |
911 | |
912 | regulator_disable(regulator: phy->vbus); |
913 | clk_disable_unprepare(clk: phy->pll_u); |
914 | |
915 | phy->freq = NULL; |
916 | } |
917 | |
918 | static irqreturn_t tegra_usb_phy_isr(int irq, void *data) |
919 | { |
920 | u32 val, int_mask = ID_CHG_DET | VBUS_WAKEUP_CHG_DET; |
921 | struct tegra_usb_phy *phy = data; |
922 | void __iomem *base = phy->regs; |
923 | |
924 | /* |
925 | * The PHY interrupt also wakes the USB controller driver since |
926 | * interrupt is shared. We don't do anything in the PHY driver, |
927 | * so just clear the interrupt. |
928 | */ |
929 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); |
930 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); |
931 | |
932 | return val & int_mask ? IRQ_HANDLED : IRQ_NONE; |
933 | } |
934 | |
935 | static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable) |
936 | { |
937 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
938 | void __iomem *base = phy->regs; |
939 | int ret = 0; |
940 | u32 val; |
941 | |
942 | if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST && |
943 | phy->irq > 0) { |
944 | disable_irq(irq: phy->irq); |
945 | |
946 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); |
947 | val &= ~(ID_INT_EN | VBUS_WAKEUP_INT_EN); |
948 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); |
949 | |
950 | enable_irq(irq: phy->irq); |
951 | |
952 | free_irq(phy->irq, phy); |
953 | |
954 | phy->wakeup_enabled = false; |
955 | } |
956 | |
957 | if (enable && phy->mode != USB_DR_MODE_HOST && phy->irq > 0) { |
958 | ret = request_irq(irq: phy->irq, handler: tegra_usb_phy_isr, IRQF_SHARED, |
959 | name: dev_name(dev: phy->u_phy.dev), dev: phy); |
960 | if (!ret) { |
961 | disable_irq(irq: phy->irq); |
962 | |
963 | /* |
964 | * USB clock will be resumed once wake event will be |
965 | * generated. The ID-change event requires to have |
966 | * interrupts enabled, otherwise it won't be generated. |
967 | */ |
968 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); |
969 | val |= ID_INT_EN | VBUS_WAKEUP_INT_EN; |
970 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); |
971 | |
972 | enable_irq(irq: phy->irq); |
973 | } else { |
974 | dev_err(phy->u_phy.dev, |
975 | "Failed to request interrupt: %d" , ret); |
976 | enable = false; |
977 | } |
978 | } |
979 | |
980 | phy->wakeup_enabled = enable; |
981 | |
982 | return ret; |
983 | } |
984 | |
985 | static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend) |
986 | { |
987 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
988 | int ret; |
989 | |
990 | if (WARN_ON(!phy->freq)) |
991 | return -EINVAL; |
992 | |
993 | /* |
994 | * PHY is sharing IRQ with the CI driver, hence here we either |
995 | * disable interrupt for both PHY and CI or for CI only. The |
996 | * interrupt needs to be disabled while hardware is reprogrammed |
997 | * because interrupt touches the programmed registers, and thus, |
998 | * there could be a race condition. |
999 | */ |
1000 | if (phy->irq > 0) |
1001 | disable_irq(irq: phy->irq); |
1002 | |
1003 | if (suspend) |
1004 | ret = tegra_usb_phy_power_off(phy); |
1005 | else |
1006 | ret = tegra_usb_phy_power_on(phy); |
1007 | |
1008 | if (phy->irq > 0) |
1009 | enable_irq(irq: phy->irq); |
1010 | |
1011 | return ret; |
1012 | } |
1013 | |
1014 | static int tegra_usb_phy_configure_pmc(struct tegra_usb_phy *phy) |
1015 | { |
1016 | int err, val = 0; |
1017 | |
1018 | /* older device-trees don't have PMC regmap */ |
1019 | if (!phy->pmc_regmap) |
1020 | return 0; |
1021 | |
1022 | /* |
1023 | * Tegra20 has a different layout of PMC USB register bits and AO is |
1024 | * enabled by default after system reset on Tegra20, so assume nothing |
1025 | * to do on Tegra20. |
1026 | */ |
1027 | if (!phy->soc_config->requires_pmc_ao_power_up) |
1028 | return 0; |
1029 | |
1030 | /* enable VBUS wake-up detector */ |
1031 | if (phy->mode != USB_DR_MODE_HOST) |
1032 | val |= VBUS_WAKEUP_PD_P0 << phy->instance * 4; |
1033 | |
1034 | /* enable ID-pin ACC detector for OTG mode switching */ |
1035 | if (phy->mode == USB_DR_MODE_OTG) |
1036 | val |= ID_PD_P0 << phy->instance * 4; |
1037 | |
1038 | /* disable detectors to reset them */ |
1039 | err = regmap_set_bits(map: phy->pmc_regmap, PMC_USB_AO, bits: val); |
1040 | if (err) { |
1041 | dev_err(phy->u_phy.dev, "Failed to disable PMC AO: %d\n" , err); |
1042 | return err; |
1043 | } |
1044 | |
1045 | usleep_range(min: 10, max: 100); |
1046 | |
1047 | /* enable detectors */ |
1048 | err = regmap_clear_bits(map: phy->pmc_regmap, PMC_USB_AO, bits: val); |
1049 | if (err) { |
1050 | dev_err(phy->u_phy.dev, "Failed to enable PMC AO: %d\n" , err); |
1051 | return err; |
1052 | } |
1053 | |
1054 | /* detectors starts to work after 10ms */ |
1055 | usleep_range(min: 10000, max: 15000); |
1056 | |
1057 | return 0; |
1058 | } |
1059 | |
1060 | static int tegra_usb_phy_init(struct usb_phy *u_phy) |
1061 | { |
1062 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
1063 | unsigned long parent_rate; |
1064 | unsigned int i; |
1065 | int err; |
1066 | |
1067 | if (WARN_ON(phy->freq)) |
1068 | return 0; |
1069 | |
1070 | err = clk_prepare_enable(clk: phy->pll_u); |
1071 | if (err) |
1072 | return err; |
1073 | |
1074 | parent_rate = clk_get_rate(clk: clk_get_parent(clk: phy->pll_u)); |
1075 | for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { |
1076 | if (tegra_freq_table[i].freq == parent_rate) { |
1077 | phy->freq = &tegra_freq_table[i]; |
1078 | break; |
1079 | } |
1080 | } |
1081 | if (!phy->freq) { |
1082 | dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n" , |
1083 | parent_rate); |
1084 | err = -EINVAL; |
1085 | goto disable_clk; |
1086 | } |
1087 | |
1088 | err = regulator_enable(regulator: phy->vbus); |
1089 | if (err) { |
1090 | dev_err(phy->u_phy.dev, |
1091 | "Failed to enable USB VBUS regulator: %d\n" , err); |
1092 | goto disable_clk; |
1093 | } |
1094 | |
1095 | if (!phy->is_ulpi_phy) { |
1096 | err = utmip_pad_open(phy); |
1097 | if (err) |
1098 | goto disable_vbus; |
1099 | } |
1100 | |
1101 | err = tegra_usb_phy_configure_pmc(phy); |
1102 | if (err) |
1103 | goto close_phy; |
1104 | |
1105 | err = tegra_usb_phy_power_on(phy); |
1106 | if (err) |
1107 | goto close_phy; |
1108 | |
1109 | return 0; |
1110 | |
1111 | close_phy: |
1112 | if (!phy->is_ulpi_phy) |
1113 | utmip_pad_close(phy); |
1114 | |
1115 | disable_vbus: |
1116 | regulator_disable(regulator: phy->vbus); |
1117 | |
1118 | disable_clk: |
1119 | clk_disable_unprepare(clk: phy->pll_u); |
1120 | |
1121 | phy->freq = NULL; |
1122 | |
1123 | return err; |
1124 | } |
1125 | |
1126 | void tegra_usb_phy_preresume(struct usb_phy *u_phy) |
1127 | { |
1128 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
1129 | |
1130 | if (!phy->is_ulpi_phy) |
1131 | utmi_phy_preresume(phy); |
1132 | } |
1133 | EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); |
1134 | |
1135 | void tegra_usb_phy_postresume(struct usb_phy *u_phy) |
1136 | { |
1137 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
1138 | |
1139 | if (!phy->is_ulpi_phy) |
1140 | utmi_phy_postresume(phy); |
1141 | } |
1142 | EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); |
1143 | |
1144 | void tegra_ehci_phy_restore_start(struct usb_phy *u_phy, |
1145 | enum tegra_usb_phy_port_speed port_speed) |
1146 | { |
1147 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
1148 | |
1149 | if (!phy->is_ulpi_phy) |
1150 | utmi_phy_restore_start(phy, port_speed); |
1151 | } |
1152 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); |
1153 | |
1154 | void tegra_ehci_phy_restore_end(struct usb_phy *u_phy) |
1155 | { |
1156 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
1157 | |
1158 | if (!phy->is_ulpi_phy) |
1159 | utmi_phy_restore_end(phy); |
1160 | } |
1161 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); |
1162 | |
1163 | static int read_utmi_param(struct platform_device *pdev, const char *param, |
1164 | u8 *dest) |
1165 | { |
1166 | u32 value; |
1167 | int err; |
1168 | |
1169 | err = of_property_read_u32(np: pdev->dev.of_node, propname: param, out_value: &value); |
1170 | if (err) |
1171 | dev_err(&pdev->dev, |
1172 | "Failed to read USB UTMI parameter %s: %d\n" , |
1173 | param, err); |
1174 | else |
1175 | *dest = value; |
1176 | |
1177 | return err; |
1178 | } |
1179 | |
1180 | static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy, |
1181 | struct platform_device *pdev) |
1182 | { |
1183 | struct tegra_utmip_config *config; |
1184 | struct resource *res; |
1185 | int err; |
1186 | |
1187 | tegra_phy->is_ulpi_phy = false; |
1188 | |
1189 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1190 | if (!res) { |
1191 | dev_err(&pdev->dev, "Failed to get UTMI pad regs\n" ); |
1192 | return -ENXIO; |
1193 | } |
1194 | |
1195 | /* |
1196 | * Note that UTMI pad registers are shared by all PHYs, therefore |
1197 | * devm_platform_ioremap_resource() can't be used here. |
1198 | */ |
1199 | tegra_phy->pad_regs = devm_ioremap(dev: &pdev->dev, offset: res->start, |
1200 | size: resource_size(res)); |
1201 | if (!tegra_phy->pad_regs) { |
1202 | dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n" ); |
1203 | return -ENOMEM; |
1204 | } |
1205 | |
1206 | tegra_phy->config = devm_kzalloc(dev: &pdev->dev, size: sizeof(*config), |
1207 | GFP_KERNEL); |
1208 | if (!tegra_phy->config) |
1209 | return -ENOMEM; |
1210 | |
1211 | config = tegra_phy->config; |
1212 | |
1213 | err = read_utmi_param(pdev, param: "nvidia,hssync-start-delay" , |
1214 | dest: &config->hssync_start_delay); |
1215 | if (err) |
1216 | return err; |
1217 | |
1218 | err = read_utmi_param(pdev, param: "nvidia,elastic-limit" , |
1219 | dest: &config->elastic_limit); |
1220 | if (err) |
1221 | return err; |
1222 | |
1223 | err = read_utmi_param(pdev, param: "nvidia,idle-wait-delay" , |
1224 | dest: &config->idle_wait_delay); |
1225 | if (err) |
1226 | return err; |
1227 | |
1228 | err = read_utmi_param(pdev, param: "nvidia,term-range-adj" , |
1229 | dest: &config->term_range_adj); |
1230 | if (err) |
1231 | return err; |
1232 | |
1233 | err = read_utmi_param(pdev, param: "nvidia,xcvr-lsfslew" , |
1234 | dest: &config->xcvr_lsfslew); |
1235 | if (err) |
1236 | return err; |
1237 | |
1238 | err = read_utmi_param(pdev, param: "nvidia,xcvr-lsrslew" , |
1239 | dest: &config->xcvr_lsrslew); |
1240 | if (err) |
1241 | return err; |
1242 | |
1243 | if (tegra_phy->soc_config->requires_extra_tuning_parameters) { |
1244 | err = read_utmi_param(pdev, param: "nvidia,xcvr-hsslew" , |
1245 | dest: &config->xcvr_hsslew); |
1246 | if (err) |
1247 | return err; |
1248 | |
1249 | err = read_utmi_param(pdev, param: "nvidia,hssquelch-level" , |
1250 | dest: &config->hssquelch_level); |
1251 | if (err) |
1252 | return err; |
1253 | |
1254 | err = read_utmi_param(pdev, param: "nvidia,hsdiscon-level" , |
1255 | dest: &config->hsdiscon_level); |
1256 | if (err) |
1257 | return err; |
1258 | } |
1259 | |
1260 | config->xcvr_setup_use_fuses = of_property_read_bool( |
1261 | np: pdev->dev.of_node, propname: "nvidia,xcvr-setup-use-fuses" ); |
1262 | |
1263 | if (!config->xcvr_setup_use_fuses) { |
1264 | err = read_utmi_param(pdev, param: "nvidia,xcvr-setup" , |
1265 | dest: &config->xcvr_setup); |
1266 | if (err) |
1267 | return err; |
1268 | } |
1269 | |
1270 | return 0; |
1271 | } |
1272 | |
1273 | static void tegra_usb_phy_put_pmc_device(void *dev) |
1274 | { |
1275 | put_device(dev); |
1276 | } |
1277 | |
1278 | static int tegra_usb_phy_parse_pmc(struct device *dev, |
1279 | struct tegra_usb_phy *phy) |
1280 | { |
1281 | struct platform_device *pmc_pdev; |
1282 | struct of_phandle_args args; |
1283 | int err; |
1284 | |
1285 | err = of_parse_phandle_with_fixed_args(np: dev->of_node, list_name: "nvidia,pmc" , |
1286 | cell_count: 1, index: 0, out_args: &args); |
1287 | if (err) { |
1288 | if (err != -ENOENT) |
1289 | return err; |
1290 | |
1291 | dev_warn_once(dev, "nvidia,pmc is missing, please update your device-tree\n" ); |
1292 | return 0; |
1293 | } |
1294 | |
1295 | pmc_pdev = of_find_device_by_node(np: args.np); |
1296 | of_node_put(node: args.np); |
1297 | if (!pmc_pdev) |
1298 | return -ENODEV; |
1299 | |
1300 | err = devm_add_action_or_reset(dev, tegra_usb_phy_put_pmc_device, |
1301 | &pmc_pdev->dev); |
1302 | if (err) |
1303 | return err; |
1304 | |
1305 | if (!platform_get_drvdata(pdev: pmc_pdev)) |
1306 | return -EPROBE_DEFER; |
1307 | |
1308 | phy->pmc_regmap = dev_get_regmap(dev: &pmc_pdev->dev, name: "usb_sleepwalk" ); |
1309 | if (!phy->pmc_regmap) |
1310 | return -EINVAL; |
1311 | |
1312 | phy->instance = args.args[0]; |
1313 | |
1314 | return 0; |
1315 | } |
1316 | |
1317 | static const struct tegra_phy_soc_config tegra20_soc_config = { |
1318 | .utmi_pll_config_in_car_module = false, |
1319 | .has_hostpc = false, |
1320 | .requires_usbmode_setup = false, |
1321 | .requires_extra_tuning_parameters = false, |
1322 | .requires_pmc_ao_power_up = false, |
1323 | }; |
1324 | |
1325 | static const struct tegra_phy_soc_config tegra30_soc_config = { |
1326 | .utmi_pll_config_in_car_module = true, |
1327 | .has_hostpc = true, |
1328 | .requires_usbmode_setup = true, |
1329 | .requires_extra_tuning_parameters = true, |
1330 | .requires_pmc_ao_power_up = true, |
1331 | }; |
1332 | |
1333 | static const struct of_device_id tegra_usb_phy_id_table[] = { |
1334 | { .compatible = "nvidia,tegra30-usb-phy" , .data = &tegra30_soc_config }, |
1335 | { .compatible = "nvidia,tegra20-usb-phy" , .data = &tegra20_soc_config }, |
1336 | { }, |
1337 | }; |
1338 | MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table); |
1339 | |
1340 | static int tegra_usb_phy_probe(struct platform_device *pdev) |
1341 | { |
1342 | struct device_node *np = pdev->dev.of_node; |
1343 | struct tegra_usb_phy *tegra_phy; |
1344 | enum usb_phy_interface phy_type; |
1345 | struct reset_control *reset; |
1346 | struct gpio_desc *gpiod; |
1347 | struct resource *res; |
1348 | struct usb_phy *phy; |
1349 | int err; |
1350 | |
1351 | tegra_phy = devm_kzalloc(dev: &pdev->dev, size: sizeof(*tegra_phy), GFP_KERNEL); |
1352 | if (!tegra_phy) |
1353 | return -ENOMEM; |
1354 | |
1355 | tegra_phy->soc_config = of_device_get_match_data(dev: &pdev->dev); |
1356 | tegra_phy->irq = platform_get_irq_optional(pdev, 0); |
1357 | |
1358 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1359 | if (!res) { |
1360 | dev_err(&pdev->dev, "Failed to get I/O memory\n" ); |
1361 | return -ENXIO; |
1362 | } |
1363 | |
1364 | /* |
1365 | * Note that PHY and USB controller are using shared registers, |
1366 | * therefore devm_platform_ioremap_resource() can't be used here. |
1367 | */ |
1368 | tegra_phy->regs = devm_ioremap(dev: &pdev->dev, offset: res->start, |
1369 | size: resource_size(res)); |
1370 | if (!tegra_phy->regs) { |
1371 | dev_err(&pdev->dev, "Failed to remap I/O memory\n" ); |
1372 | return -ENOMEM; |
1373 | } |
1374 | |
1375 | tegra_phy->is_legacy_phy = |
1376 | of_property_read_bool(np, propname: "nvidia,has-legacy-mode" ); |
1377 | |
1378 | if (of_property_present(np, propname: "dr_mode" )) |
1379 | tegra_phy->mode = usb_get_dr_mode(dev: &pdev->dev); |
1380 | else |
1381 | tegra_phy->mode = USB_DR_MODE_HOST; |
1382 | |
1383 | if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) { |
1384 | dev_err(&pdev->dev, "dr_mode is invalid\n" ); |
1385 | return -EINVAL; |
1386 | } |
1387 | |
1388 | /* On some boards, the VBUS regulator doesn't need to be controlled */ |
1389 | tegra_phy->vbus = devm_regulator_get(dev: &pdev->dev, id: "vbus" ); |
1390 | if (IS_ERR(ptr: tegra_phy->vbus)) |
1391 | return PTR_ERR(ptr: tegra_phy->vbus); |
1392 | |
1393 | tegra_phy->pll_u = devm_clk_get(dev: &pdev->dev, id: "pll_u" ); |
1394 | err = PTR_ERR_OR_ZERO(ptr: tegra_phy->pll_u); |
1395 | if (err) { |
1396 | dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n" , err); |
1397 | return err; |
1398 | } |
1399 | |
1400 | err = tegra_usb_phy_parse_pmc(dev: &pdev->dev, phy: tegra_phy); |
1401 | if (err) { |
1402 | dev_err_probe(dev: &pdev->dev, err, fmt: "Failed to get PMC regmap\n" ); |
1403 | return err; |
1404 | } |
1405 | |
1406 | phy_type = of_usb_get_phy_mode(np); |
1407 | switch (phy_type) { |
1408 | case USBPHY_INTERFACE_MODE_UTMI: |
1409 | err = utmi_phy_probe(tegra_phy, pdev); |
1410 | if (err) |
1411 | return err; |
1412 | |
1413 | tegra_phy->pad_clk = devm_clk_get(dev: &pdev->dev, id: "utmi-pads" ); |
1414 | err = PTR_ERR_OR_ZERO(ptr: tegra_phy->pad_clk); |
1415 | if (err) { |
1416 | dev_err(&pdev->dev, |
1417 | "Failed to get UTMIP pad clock: %d\n" , err); |
1418 | return err; |
1419 | } |
1420 | |
1421 | reset = devm_reset_control_get_optional_shared(dev: &pdev->dev, |
1422 | id: "utmi-pads" ); |
1423 | err = PTR_ERR_OR_ZERO(ptr: reset); |
1424 | if (err) { |
1425 | dev_err(&pdev->dev, |
1426 | "Failed to get UTMI-pads reset: %d\n" , err); |
1427 | return err; |
1428 | } |
1429 | tegra_phy->pad_rst = reset; |
1430 | break; |
1431 | |
1432 | case USBPHY_INTERFACE_MODE_ULPI: |
1433 | tegra_phy->is_ulpi_phy = true; |
1434 | |
1435 | tegra_phy->clk = devm_clk_get(dev: &pdev->dev, id: "ulpi-link" ); |
1436 | err = PTR_ERR_OR_ZERO(ptr: tegra_phy->clk); |
1437 | if (err) { |
1438 | dev_err(&pdev->dev, |
1439 | "Failed to get ULPI clock: %d\n" , err); |
1440 | return err; |
1441 | } |
1442 | |
1443 | gpiod = devm_gpiod_get(dev: &pdev->dev, con_id: "nvidia,phy-reset" , |
1444 | flags: GPIOD_OUT_HIGH); |
1445 | err = PTR_ERR_OR_ZERO(ptr: gpiod); |
1446 | if (err) { |
1447 | dev_err(&pdev->dev, |
1448 | "Request failed for reset GPIO: %d\n" , err); |
1449 | return err; |
1450 | } |
1451 | |
1452 | err = gpiod_set_consumer_name(desc: gpiod, name: "ulpi_phy_reset_b" ); |
1453 | if (err) { |
1454 | dev_err(&pdev->dev, |
1455 | "Failed to set up reset GPIO name: %d\n" , err); |
1456 | return err; |
1457 | } |
1458 | |
1459 | tegra_phy->reset_gpio = gpiod; |
1460 | |
1461 | phy = devm_otg_ulpi_create(dev: &pdev->dev, |
1462 | ops: &ulpi_viewport_access_ops, flags: 0); |
1463 | if (!phy) { |
1464 | dev_err(&pdev->dev, "Failed to create ULPI OTG\n" ); |
1465 | return -ENOMEM; |
1466 | } |
1467 | |
1468 | tegra_phy->ulpi = phy; |
1469 | tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT; |
1470 | break; |
1471 | |
1472 | default: |
1473 | dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n" , |
1474 | phy_type); |
1475 | return -EINVAL; |
1476 | } |
1477 | |
1478 | tegra_phy->u_phy.dev = &pdev->dev; |
1479 | tegra_phy->u_phy.init = tegra_usb_phy_init; |
1480 | tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown; |
1481 | tegra_phy->u_phy.set_wakeup = tegra_usb_phy_set_wakeup; |
1482 | tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend; |
1483 | |
1484 | platform_set_drvdata(pdev, data: tegra_phy); |
1485 | |
1486 | return usb_add_phy_dev(&tegra_phy->u_phy); |
1487 | } |
1488 | |
1489 | static void tegra_usb_phy_remove(struct platform_device *pdev) |
1490 | { |
1491 | struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev); |
1492 | |
1493 | usb_remove_phy(&tegra_phy->u_phy); |
1494 | } |
1495 | |
1496 | static struct platform_driver tegra_usb_phy_driver = { |
1497 | .probe = tegra_usb_phy_probe, |
1498 | .remove_new = tegra_usb_phy_remove, |
1499 | .driver = { |
1500 | .name = "tegra-phy" , |
1501 | .of_match_table = tegra_usb_phy_id_table, |
1502 | }, |
1503 | }; |
1504 | module_platform_driver(tegra_usb_phy_driver); |
1505 | |
1506 | MODULE_DESCRIPTION("Tegra USB PHY driver" ); |
1507 | MODULE_LICENSE("GPL v2" ); |
1508 | |