1 | // SPDX-License-Identifier: GPL-2.0 |
2 | |
3 | /* |
4 | * ATI Mach64 CT/VT/GT/LT Support |
5 | */ |
6 | |
7 | #include <linux/fb.h> |
8 | #include <linux/delay.h> |
9 | #include <asm/io.h> |
10 | #include <video/mach64.h> |
11 | #include "atyfb.h" |
12 | #ifdef CONFIG_PPC |
13 | #include <asm/machdep.h> |
14 | #endif |
15 | |
16 | #undef DEBUG |
17 | |
18 | static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll); |
19 | static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll); |
20 | static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll); |
21 | static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll); |
22 | |
23 | u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par) |
24 | { |
25 | |
26 | /* write addr byte */ |
27 | aty_st_8(CLOCK_CNTL_ADDR, val: (offset << 2) & PLL_ADDR, par); |
28 | /* read the register value */ |
29 | return aty_ld_8(CLOCK_CNTL_DATA, par); |
30 | } |
31 | |
32 | static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par) |
33 | { |
34 | /* write addr byte */ |
35 | aty_st_8(CLOCK_CNTL_ADDR, val: ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par); |
36 | /* write the register value */ |
37 | aty_st_8(CLOCK_CNTL_DATA, val: val & PLL_DATA, par); |
38 | aty_st_8(CLOCK_CNTL_ADDR, val: ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par); |
39 | } |
40 | |
41 | /* |
42 | * by Daniel Mantione |
43 | * <daniel.mantione@freepascal.org> |
44 | * |
45 | * |
46 | * ATI Mach64 CT clock synthesis description. |
47 | * |
48 | * All clocks on the Mach64 can be calculated using the same principle: |
49 | * |
50 | * XTALIN * x * FB_DIV |
51 | * CLK = ---------------------- |
52 | * PLL_REF_DIV * POST_DIV |
53 | * |
54 | * XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz. |
55 | * PLL_REF_DIV can be set by the user, but is the same for all clocks. |
56 | * FB_DIV can be set by the user for each clock individually, it should be set |
57 | * between 128 and 255, the chip will generate a bad clock signal for too low |
58 | * values. |
59 | * x depends on the type of clock; usually it is 2, but for the MCLK it can also |
60 | * be set to 4. |
61 | * POST_DIV can be set by the user for each clock individually, Possible values |
62 | * are 1,2,4,8 and for some clocks other values are available too. |
63 | * CLK is of course the clock speed that is generated. |
64 | * |
65 | * The Mach64 has these clocks: |
66 | * |
67 | * MCLK The clock rate of the chip |
68 | * XCLK The clock rate of the on-chip memory |
69 | * VCLK0 First pixel clock of first CRT controller |
70 | * VCLK1 Second pixel clock of first CRT controller |
71 | * VCLK2 Third pixel clock of first CRT controller |
72 | * VCLK3 Fourth pixel clock of first CRT controller |
73 | * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3 |
74 | * V2CLK Pixel clock of the second CRT controller. |
75 | * SCLK Multi-purpose clock |
76 | * |
77 | * - MCLK and XCLK use the same FB_DIV |
78 | * - VCLK0 .. VCLK3 use the same FB_DIV |
79 | * - V2CLK is needed when the second CRTC is used (can be used for dualhead); |
80 | * i.e. CRT monitor connected to laptop has different resolution than built |
81 | * in LCD monitor. |
82 | * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO, |
83 | * Rage XL and Rage Mobility. It is know not to exist on the Mach64 VT. |
84 | * - V2CLK is not available on all cards, most likely only the Rage LT-PRO, |
85 | * the Rage XL and the Rage Mobility |
86 | * |
87 | * SCLK can be used to: |
88 | * - Clock the chip instead of MCLK |
89 | * - Replace XTALIN with a user defined frequency |
90 | * - Generate the pixel clock for the LCD monitor (instead of VCLK) |
91 | */ |
92 | |
93 | /* |
94 | * It can be quite hard to calculate XCLK and MCLK if they don't run at the |
95 | * same frequency. Luckily, until now all cards that need asynchrone clock |
96 | * speeds seem to have SCLK. |
97 | * So this driver uses SCLK to clock the chip and XCLK to clock the memory. |
98 | */ |
99 | |
100 | /* ------------------------------------------------------------------------- */ |
101 | |
102 | /* |
103 | * PLL programming (Mach64 CT family) |
104 | * |
105 | * |
106 | * This procedure sets the display fifo. The display fifo is a buffer that |
107 | * contains data read from the video memory that waits to be processed by |
108 | * the CRT controller. |
109 | * |
110 | * On the more modern Mach64 variants, the chip doesn't calculate the |
111 | * interval after which the display fifo has to be reloaded from memory |
112 | * automatically, the driver has to do it instead. |
113 | */ |
114 | |
115 | #define Maximum_DSP_PRECISION 7 |
116 | const u8 aty_postdividers[8] = {1,2,4,8,3,5,6,12}; |
117 | |
118 | static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) |
119 | { |
120 | u32 dsp_off, dsp_on, dsp_xclks; |
121 | u32 multiplier, divider, ras_multiplier, ras_divider, tmp; |
122 | u8 vshift, xshift; |
123 | s8 dsp_precision; |
124 | |
125 | multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; |
126 | divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; |
127 | |
128 | ras_multiplier = pll->xclkmaxrasdelay; |
129 | ras_divider = 1; |
130 | |
131 | if (bpp>=8) |
132 | divider = divider * (bpp >> 2); |
133 | |
134 | vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ |
135 | |
136 | if (bpp == 0) |
137 | vshift--; /* ... but only 32 bits in VGA mode. */ |
138 | |
139 | #ifdef CONFIG_FB_ATY_GENERIC_LCD |
140 | if (pll->xres != 0) { |
141 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
142 | |
143 | multiplier = multiplier * par->lcd_width; |
144 | divider = divider * pll->xres & ~7; |
145 | |
146 | ras_multiplier = ras_multiplier * par->lcd_width; |
147 | ras_divider = ras_divider * pll->xres & ~7; |
148 | } |
149 | #endif |
150 | /* If we don't do this, 32 bits for multiplier & divider won't be |
151 | enough in certain situations! */ |
152 | while (((multiplier | divider) & 1) == 0) { |
153 | multiplier = multiplier >> 1; |
154 | divider = divider >> 1; |
155 | } |
156 | |
157 | /* Determine DSP precision first */ |
158 | tmp = ((multiplier * pll->fifo_size) << vshift) / divider; |
159 | |
160 | for (dsp_precision = -5; tmp; dsp_precision++) |
161 | tmp >>= 1; |
162 | if (dsp_precision < 0) |
163 | dsp_precision = 0; |
164 | else if (dsp_precision > Maximum_DSP_PRECISION) |
165 | dsp_precision = Maximum_DSP_PRECISION; |
166 | |
167 | xshift = 6 - dsp_precision; |
168 | vshift += xshift; |
169 | |
170 | /* Move on to dsp_off */ |
171 | dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - |
172 | (1 << (vshift - xshift)); |
173 | |
174 | /* if (bpp == 0) |
175 | dsp_on = ((multiplier * 20 << vshift) + divider) / divider; |
176 | else */ |
177 | { |
178 | dsp_on = ((multiplier << vshift) + divider) / divider; |
179 | tmp = ((ras_multiplier << xshift) + ras_divider) / ras_divider; |
180 | if (dsp_on < tmp) |
181 | dsp_on = tmp; |
182 | dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift); |
183 | } |
184 | |
185 | /* Calculate rounding factor and apply it to dsp_on */ |
186 | tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1; |
187 | dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1); |
188 | |
189 | if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1))) { |
190 | dsp_on = dsp_off - (multiplier << vshift) / divider; |
191 | dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1); |
192 | } |
193 | |
194 | /* Last but not least: dsp_xclks */ |
195 | dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider; |
196 | |
197 | /* Get register values. */ |
198 | pll->dsp_on_off = (dsp_on << 16) + dsp_off; |
199 | pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks; |
200 | #ifdef DEBUG |
201 | printk("atyfb(%s): dsp_config 0x%08x, dsp_on_off 0x%08x\n" , |
202 | __func__, pll->dsp_config, pll->dsp_on_off); |
203 | #endif |
204 | return 0; |
205 | } |
206 | |
207 | static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll) |
208 | { |
209 | u32 q; |
210 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
211 | int pllvclk; |
212 | |
213 | /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */ |
214 | q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per; |
215 | if (q < 16*8 || q > 255*8) { |
216 | printk(KERN_CRIT "atyfb: vclk out of range\n" ); |
217 | return -EINVAL; |
218 | } else { |
219 | pll->vclk_post_div = (q < 128*8); |
220 | pll->vclk_post_div += (q < 64*8); |
221 | pll->vclk_post_div += (q < 32*8); |
222 | } |
223 | pll->vclk_post_div_real = aty_postdividers[pll->vclk_post_div]; |
224 | // pll->vclk_post_div <<= 6; |
225 | pll->vclk_fb_div = q * pll->vclk_post_div_real / 8; |
226 | pllvclk = (1000000 * 2 * pll->vclk_fb_div) / |
227 | (par->ref_clk_per * pll->pll_ref_div); |
228 | #ifdef DEBUG |
229 | printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n" , |
230 | __func__, pllvclk, pllvclk / pll->vclk_post_div_real); |
231 | #endif |
232 | pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ |
233 | |
234 | /* Set ECP (scaler/overlay clock) divider */ |
235 | if (par->pll_limits.ecp_max) { |
236 | int ecp = pllvclk / pll->vclk_post_div_real; |
237 | int ecp_div = 0; |
238 | |
239 | while (ecp > par->pll_limits.ecp_max && ecp_div < 2) { |
240 | ecp >>= 1; |
241 | ecp_div++; |
242 | } |
243 | pll->pll_vclk_cntl |= ecp_div << 4; |
244 | } |
245 | |
246 | return 0; |
247 | } |
248 | |
249 | static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) |
250 | { |
251 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
252 | int err; |
253 | |
254 | if ((err = aty_valid_pll_ct(info, vclk_per, pll: &pll->ct))) |
255 | return err; |
256 | if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, pll: &pll->ct))) |
257 | return err; |
258 | /*aty_calc_pll_ct(info, &pll->ct);*/ |
259 | return 0; |
260 | } |
261 | |
262 | static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll) |
263 | { |
264 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
265 | u32 ret; |
266 | ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2; |
267 | #ifdef CONFIG_FB_ATY_GENERIC_LCD |
268 | if(pll->ct.xres > 0) { |
269 | ret *= par->lcd_width; |
270 | ret /= pll->ct.xres; |
271 | } |
272 | #endif |
273 | #ifdef DEBUG |
274 | printk("atyfb(%s): calculated 0x%08X(%i)\n" , __func__, ret, ret); |
275 | #endif |
276 | return ret; |
277 | } |
278 | |
279 | void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll) |
280 | { |
281 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
282 | u32 crtc_gen_cntl; |
283 | u8 tmp, tmp2; |
284 | |
285 | #ifdef CONFIG_FB_ATY_GENERIC_LCD |
286 | u32 lcd_gen_cntrl = 0; |
287 | #endif |
288 | |
289 | #ifdef DEBUG |
290 | printk("atyfb(%s): about to program:\n" |
291 | "pll_ext_cntl=0x%02x pll_gen_cntl=0x%02x pll_vclk_cntl=0x%02x\n" , |
292 | __func__, |
293 | pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl); |
294 | |
295 | printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n" , |
296 | __func__, |
297 | par->clk_wr_offset, pll->ct.vclk_fb_div, |
298 | pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real); |
299 | #endif |
300 | #ifdef CONFIG_FB_ATY_GENERIC_LCD |
301 | if (par->lcd_table != 0) { |
302 | /* turn off LCD */ |
303 | lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par); |
304 | aty_st_lcd(LCD_GEN_CNTL, val: lcd_gen_cntrl & ~LCD_ON, par); |
305 | } |
306 | #endif |
307 | aty_st_8(CLOCK_CNTL, val: par->clk_wr_offset | CLOCK_STROBE, par); |
308 | |
309 | /* Temporarily switch to accelerator mode */ |
310 | crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par); |
311 | if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN)) |
312 | aty_st_le32(CRTC_GEN_CNTL, val: crtc_gen_cntl | CRTC_EXT_DISP_EN, par); |
313 | |
314 | /* Reset VCLK generator */ |
315 | aty_st_pll_ct(PLL_VCLK_CNTL, val: pll->ct.pll_vclk_cntl, par); |
316 | |
317 | /* Set post-divider */ |
318 | tmp2 = par->clk_wr_offset << 1; |
319 | tmp = aty_ld_pll_ct(VCLK_POST_DIV, par); |
320 | tmp &= ~(0x03U << tmp2); |
321 | tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2); |
322 | aty_st_pll_ct(VCLK_POST_DIV, val: tmp, par); |
323 | |
324 | /* Set extended post-divider */ |
325 | tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par); |
326 | tmp &= ~(0x10U << par->clk_wr_offset); |
327 | tmp &= 0xF0U; |
328 | tmp |= pll->ct.pll_ext_cntl; |
329 | aty_st_pll_ct(PLL_EXT_CNTL, val: tmp, par); |
330 | |
331 | /* Set feedback divider */ |
332 | tmp = VCLK0_FB_DIV + par->clk_wr_offset; |
333 | aty_st_pll_ct(offset: tmp, val: (pll->ct.vclk_fb_div & 0xFFU), par); |
334 | |
335 | aty_st_pll_ct(PLL_GEN_CNTL, val: (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par); |
336 | |
337 | /* End VCLK generator reset */ |
338 | aty_st_pll_ct(PLL_VCLK_CNTL, val: pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par); |
339 | mdelay(5); |
340 | |
341 | aty_st_pll_ct(PLL_GEN_CNTL, val: pll->ct.pll_gen_cntl, par); |
342 | aty_st_pll_ct(PLL_VCLK_CNTL, val: pll->ct.pll_vclk_cntl, par); |
343 | mdelay(1); |
344 | |
345 | /* Restore mode register */ |
346 | if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN)) |
347 | aty_st_le32(CRTC_GEN_CNTL, val: crtc_gen_cntl, par); |
348 | |
349 | if (M64_HAS(GTB_DSP)) { |
350 | u8 dll_cntl; |
351 | |
352 | if (M64_HAS(XL_DLL)) |
353 | dll_cntl = 0x80; |
354 | else if (par->ram_type >= SDRAM) |
355 | dll_cntl = 0xa6; |
356 | else |
357 | dll_cntl = 0xa0; |
358 | aty_st_pll_ct(DLL_CNTL, val: dll_cntl, par); |
359 | aty_st_pll_ct(VFC_CNTL, val: 0x1b, par); |
360 | aty_st_le32(DSP_CONFIG, val: pll->ct.dsp_config, par); |
361 | aty_st_le32(DSP_ON_OFF, val: pll->ct.dsp_on_off, par); |
362 | |
363 | mdelay(10); |
364 | aty_st_pll_ct(DLL_CNTL, val: dll_cntl, par); |
365 | mdelay(10); |
366 | aty_st_pll_ct(DLL_CNTL, val: dll_cntl | 0x40, par); |
367 | mdelay(10); |
368 | aty_st_pll_ct(DLL_CNTL, val: dll_cntl & ~0x40, par); |
369 | } |
370 | #ifdef CONFIG_FB_ATY_GENERIC_LCD |
371 | if (par->lcd_table != 0) { |
372 | /* restore LCD */ |
373 | aty_st_lcd(LCD_GEN_CNTL, val: lcd_gen_cntrl, par); |
374 | } |
375 | #endif |
376 | } |
377 | |
378 | static void aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll) |
379 | { |
380 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
381 | u8 tmp, clock; |
382 | |
383 | clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U; |
384 | tmp = clock << 1; |
385 | pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U; |
386 | |
387 | pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU; |
388 | pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU; |
389 | pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); |
390 | pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); |
391 | |
392 | pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par); |
393 | pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par); |
394 | |
395 | if (M64_HAS(GTB_DSP)) { |
396 | pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par); |
397 | pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par); |
398 | } |
399 | } |
400 | |
401 | static int aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll) |
402 | { |
403 | struct atyfb_par *par = (struct atyfb_par *) info->par; |
404 | u8 mpost_div, xpost_div, sclk_post_div_real; |
405 | u32 q, memcntl, trp; |
406 | u32 dsp_config; |
407 | #ifdef DEBUG |
408 | int pllmclk, pllsclk; |
409 | #endif |
410 | pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); |
411 | pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07; |
412 | pll->ct.xclk_ref_div = 1; |
413 | switch (pll->ct.xclk_post_div) { |
414 | case 0: case 1: case 2: case 3: |
415 | break; |
416 | |
417 | case 4: |
418 | pll->ct.xclk_ref_div = 3; |
419 | pll->ct.xclk_post_div = 0; |
420 | break; |
421 | |
422 | default: |
423 | printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n" , pll->ct.xclk_post_div); |
424 | return -EINVAL; |
425 | } |
426 | pll->ct.mclk_fb_mult = 2; |
427 | if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) { |
428 | pll->ct.mclk_fb_mult = 4; |
429 | pll->ct.xclk_post_div -= 1; |
430 | } |
431 | |
432 | #ifdef DEBUG |
433 | printk("atyfb(%s): mclk_fb_mult=%d, xclk_post_div=%d\n" , |
434 | __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div); |
435 | #endif |
436 | |
437 | memcntl = aty_ld_le32(MEM_CNTL, par); |
438 | trp = (memcntl & 0x300) >> 8; |
439 | |
440 | pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2; |
441 | pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2; |
442 | |
443 | if (M64_HAS(FIFO_32)) { |
444 | pll->ct.fifo_size = 32; |
445 | } else { |
446 | pll->ct.fifo_size = 24; |
447 | pll->ct.xclkpagefaultdelay += 2; |
448 | pll->ct.xclkmaxrasdelay += 3; |
449 | } |
450 | |
451 | switch (par->ram_type) { |
452 | case DRAM: |
453 | if (info->fix.smem_len<=ONE_MB) { |
454 | pll->ct.dsp_loop_latency = 10; |
455 | } else { |
456 | pll->ct.dsp_loop_latency = 8; |
457 | pll->ct.xclkpagefaultdelay += 2; |
458 | } |
459 | break; |
460 | case EDO: |
461 | case PSEUDO_EDO: |
462 | if (info->fix.smem_len<=ONE_MB) { |
463 | pll->ct.dsp_loop_latency = 9; |
464 | } else { |
465 | pll->ct.dsp_loop_latency = 8; |
466 | pll->ct.xclkpagefaultdelay += 1; |
467 | } |
468 | break; |
469 | case SDRAM: |
470 | if (info->fix.smem_len<=ONE_MB) { |
471 | pll->ct.dsp_loop_latency = 11; |
472 | } else { |
473 | pll->ct.dsp_loop_latency = 10; |
474 | pll->ct.xclkpagefaultdelay += 1; |
475 | } |
476 | break; |
477 | case SGRAM: |
478 | pll->ct.dsp_loop_latency = 8; |
479 | pll->ct.xclkpagefaultdelay += 3; |
480 | break; |
481 | default: |
482 | pll->ct.dsp_loop_latency = 11; |
483 | pll->ct.xclkpagefaultdelay += 3; |
484 | break; |
485 | } |
486 | |
487 | if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay) |
488 | pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1; |
489 | |
490 | /* Allow BIOS to override */ |
491 | dsp_config = aty_ld_le32(DSP_CONFIG, par); |
492 | aty_ld_le32(DSP_ON_OFF, par); |
493 | aty_ld_le32(VGA_DSP_CONFIG, par); |
494 | aty_ld_le32(VGA_DSP_ON_OFF, par); |
495 | |
496 | if (dsp_config) |
497 | pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16; |
498 | #if 0 |
499 | FIXME: is it relevant for us? |
500 | if ((!dsp_on_off && !M64_HAS(RESET_3D)) || |
501 | ((dsp_on_off == vga_dsp_on_off) && |
502 | (!dsp_config || !((dsp_config ^ vga_dsp_config) & DSP_XCLKS_PER_QW)))) { |
503 | vga_dsp_on_off &= VGA_DSP_OFF; |
504 | vga_dsp_config &= VGA_DSP_XCLKS_PER_QW; |
505 | if (ATIDivide(vga_dsp_on_off, vga_dsp_config, 5, 1) > 24) |
506 | pll->ct.fifo_size = 32; |
507 | else |
508 | pll->ct.fifo_size = 24; |
509 | } |
510 | #endif |
511 | /* Exit if the user does not want us to tamper with the clock |
512 | rates of her chip. */ |
513 | if (par->mclk_per == 0) { |
514 | u8 mclk_fb_div, pll_ext_cntl; |
515 | pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); |
516 | pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par); |
517 | pll->ct.xclk_post_div_real = aty_postdividers[pll_ext_cntl & 0x07]; |
518 | mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par); |
519 | if (pll_ext_cntl & PLL_MFB_TIMES_4_2B) |
520 | mclk_fb_div <<= 1; |
521 | pll->ct.mclk_fb_div = mclk_fb_div; |
522 | return 0; |
523 | } |
524 | |
525 | pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per; |
526 | |
527 | /* FIXME: use the VTB/GTB /3 post divider if it's better suited */ |
528 | q = par->ref_clk_per * pll->ct.pll_ref_div * 8 / |
529 | (pll->ct.mclk_fb_mult * par->xclk_per); |
530 | |
531 | if (q < 16*8 || q > 255*8) { |
532 | printk(KERN_CRIT "atxfb: xclk out of range\n" ); |
533 | return -EINVAL; |
534 | } else { |
535 | xpost_div = (q < 128*8); |
536 | xpost_div += (q < 64*8); |
537 | xpost_div += (q < 32*8); |
538 | } |
539 | pll->ct.xclk_post_div_real = aty_postdividers[xpost_div]; |
540 | pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8; |
541 | |
542 | #ifdef CONFIG_PPC |
543 | if (machine_is(powermac)) { |
544 | /* Override PLL_EXT_CNTL & 0x07. */ |
545 | pll->ct.xclk_post_div = xpost_div; |
546 | pll->ct.xclk_ref_div = 1; |
547 | } |
548 | #endif |
549 | |
550 | #ifdef DEBUG |
551 | pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) / |
552 | (par->ref_clk_per * pll->ct.pll_ref_div); |
553 | printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n" , |
554 | __func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real); |
555 | #endif |
556 | |
557 | if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM)) |
558 | pll->ct.pll_gen_cntl = OSC_EN; |
559 | else |
560 | pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */; |
561 | |
562 | if (M64_HAS(MAGIC_POSTDIV)) |
563 | pll->ct.pll_ext_cntl = 0; |
564 | else |
565 | pll->ct.pll_ext_cntl = xpost_div; |
566 | |
567 | if (pll->ct.mclk_fb_mult == 4) |
568 | pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B; |
569 | |
570 | if (par->mclk_per == par->xclk_per) { |
571 | pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */ |
572 | } else { |
573 | /* |
574 | * The chip clock is not equal to the memory clock. |
575 | * Therefore we will use sclk to clock the chip. |
576 | */ |
577 | pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */ |
578 | |
579 | q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per; |
580 | if (q < 16*8 || q > 255*8) { |
581 | printk(KERN_CRIT "atyfb: mclk out of range\n" ); |
582 | return -EINVAL; |
583 | } else { |
584 | mpost_div = (q < 128*8); |
585 | mpost_div += (q < 64*8); |
586 | mpost_div += (q < 32*8); |
587 | } |
588 | sclk_post_div_real = aty_postdividers[mpost_div]; |
589 | pll->ct.sclk_fb_div = q * sclk_post_div_real / 8; |
590 | pll->ct.spll_cntl2 = mpost_div << 4; |
591 | #ifdef DEBUG |
592 | pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) / |
593 | (par->ref_clk_per * pll->ct.pll_ref_div); |
594 | printk("atyfb(%s): use sclk, pllsclk=%d MHz, sclk=mclk=%d MHz\n" , |
595 | __func__, pllsclk, pllsclk / sclk_post_div_real); |
596 | #endif |
597 | } |
598 | |
599 | /* Disable the extra precision pixel clock controls since we do not use them. */ |
600 | pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par); |
601 | pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC); |
602 | |
603 | return 0; |
604 | } |
605 | |
606 | static void aty_resume_pll_ct(const struct fb_info *info, |
607 | union aty_pll *pll) |
608 | { |
609 | struct atyfb_par *par = info->par; |
610 | |
611 | if (par->mclk_per != par->xclk_per) { |
612 | /* |
613 | * This disables the sclk, crashes the computer as reported: |
614 | * aty_st_pll_ct(SPLL_CNTL2, 3, info); |
615 | * |
616 | * So it seems the sclk must be enabled before it is used; |
617 | * so PLL_GEN_CNTL must be programmed *after* the sclk. |
618 | */ |
619 | aty_st_pll_ct(SCLK_FB_DIV, val: pll->ct.sclk_fb_div, par); |
620 | aty_st_pll_ct(SPLL_CNTL2, val: pll->ct.spll_cntl2, par); |
621 | /* |
622 | * SCLK has been started. Wait for the PLL to lock. 5 ms |
623 | * should be enough according to mach64 programmer's guide. |
624 | */ |
625 | mdelay(5); |
626 | } |
627 | |
628 | aty_st_pll_ct(PLL_REF_DIV, val: pll->ct.pll_ref_div, par); |
629 | aty_st_pll_ct(PLL_GEN_CNTL, val: pll->ct.pll_gen_cntl, par); |
630 | aty_st_pll_ct(MCLK_FB_DIV, val: pll->ct.mclk_fb_div, par); |
631 | aty_st_pll_ct(PLL_EXT_CNTL, val: pll->ct.pll_ext_cntl, par); |
632 | aty_st_pll_ct(EXT_VPLL_CNTL, val: pll->ct.ext_vpll_cntl, par); |
633 | } |
634 | |
635 | static int dummy(void) |
636 | { |
637 | return 0; |
638 | } |
639 | |
640 | const struct aty_dac_ops aty_dac_ct = { |
641 | .set_dac = (void *) dummy, |
642 | }; |
643 | |
644 | const struct aty_pll_ops aty_pll_ct = { |
645 | .var_to_pll = aty_var_to_pll_ct, |
646 | .pll_to_var = aty_pll_to_var_ct, |
647 | .set_pll = aty_set_pll_ct, |
648 | .get_pll = aty_get_pll_ct, |
649 | .init_pll = aty_init_pll_ct, |
650 | .resume_pll = aty_resume_pll_ct, |
651 | }; |
652 | |