1 | // SPDX-License-Identifier: GPL-2.0 |
2 | #include "radeonfb.h" |
3 | |
4 | /* the accelerated functions here are patterned after the |
5 | * "ACCEL_MMIO" ifdef branches in XFree86 |
6 | * --dte |
7 | */ |
8 | |
9 | static void radeon_fixup_offset(struct radeonfb_info *rinfo) |
10 | { |
11 | u32 local_base; |
12 | |
13 | /* *** Ugly workaround *** */ |
14 | /* |
15 | * On some platforms, the video memory is mapped at 0 in radeon chip space |
16 | * (like PPCs) by the firmware. X will always move it up so that it's seen |
17 | * by the chip to be at the same address as the PCI BAR. |
18 | * That means that when switching back from X, there is a mismatch between |
19 | * the offsets programmed into the engine. This means that potentially, |
20 | * accel operations done before radeonfb has a chance to re-init the engine |
21 | * will have incorrect offsets, and potentially trash system memory ! |
22 | * |
23 | * The correct fix is for fbcon to never call any accel op before the engine |
24 | * has properly been re-initialized (by a call to set_var), but this is a |
25 | * complex fix. This workaround in the meantime, called before every accel |
26 | * operation, makes sure the offsets are in sync. |
27 | */ |
28 | |
29 | radeon_fifo_wait (1); |
30 | local_base = INREG(MC_FB_LOCATION) << 16; |
31 | if (local_base == rinfo->fb_local_base) |
32 | return; |
33 | |
34 | rinfo->fb_local_base = local_base; |
35 | |
36 | radeon_fifo_wait (3); |
37 | OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) | |
38 | (rinfo->fb_local_base >> 10)); |
39 | OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); |
40 | OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); |
41 | } |
42 | |
43 | static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo, |
44 | const struct fb_fillrect *region) |
45 | { |
46 | radeon_fifo_wait(4); |
47 | |
48 | OUTREG(DP_GUI_MASTER_CNTL, |
49 | rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */ |
50 | | GMC_BRUSH_SOLID_COLOR |
51 | | ROP3_P); |
52 | if (radeon_get_dstbpp(depth: rinfo->depth) != DST_8BPP) |
53 | OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]); |
54 | else |
55 | OUTREG(DP_BRUSH_FRGD_CLR, region->color); |
56 | OUTREG(DP_WRITE_MSK, 0xffffffff); |
57 | OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); |
58 | |
59 | radeon_fifo_wait(2); |
60 | OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); |
61 | OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); |
62 | |
63 | radeon_fifo_wait(2); |
64 | OUTREG(DST_Y_X, (region->dy << 16) | region->dx); |
65 | OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height); |
66 | } |
67 | |
68 | void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region) |
69 | { |
70 | struct radeonfb_info *rinfo = info->par; |
71 | struct fb_fillrect modded; |
72 | int vxres, vyres; |
73 | |
74 | if (info->state != FBINFO_STATE_RUNNING) |
75 | return; |
76 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
77 | cfb_fillrect(info, rect: region); |
78 | return; |
79 | } |
80 | |
81 | radeon_fixup_offset(rinfo); |
82 | |
83 | vxres = info->var.xres_virtual; |
84 | vyres = info->var.yres_virtual; |
85 | |
86 | memcpy(&modded, region, sizeof(struct fb_fillrect)); |
87 | |
88 | if(!modded.width || !modded.height || |
89 | modded.dx >= vxres || modded.dy >= vyres) |
90 | return; |
91 | |
92 | if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; |
93 | if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; |
94 | |
95 | radeonfb_prim_fillrect(rinfo, region: &modded); |
96 | } |
97 | |
98 | static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo, |
99 | const struct fb_copyarea *area) |
100 | { |
101 | int xdir, ydir; |
102 | u32 sx, sy, dx, dy, w, h; |
103 | |
104 | w = area->width; h = area->height; |
105 | dx = area->dx; dy = area->dy; |
106 | sx = area->sx; sy = area->sy; |
107 | xdir = sx - dx; |
108 | ydir = sy - dy; |
109 | |
110 | if ( xdir < 0 ) { sx += w-1; dx += w-1; } |
111 | if ( ydir < 0 ) { sy += h-1; dy += h-1; } |
112 | |
113 | radeon_fifo_wait(3); |
114 | OUTREG(DP_GUI_MASTER_CNTL, |
115 | rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */ |
116 | | GMC_BRUSH_NONE |
117 | | GMC_SRC_DSTCOLOR |
118 | | ROP3_S |
119 | | DP_SRC_SOURCE_MEMORY ); |
120 | OUTREG(DP_WRITE_MSK, 0xffffffff); |
121 | OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) |
122 | | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0)); |
123 | |
124 | radeon_fifo_wait(2); |
125 | OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); |
126 | OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); |
127 | |
128 | radeon_fifo_wait(3); |
129 | OUTREG(SRC_Y_X, (sy << 16) | sx); |
130 | OUTREG(DST_Y_X, (dy << 16) | dx); |
131 | OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w); |
132 | } |
133 | |
134 | |
135 | void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) |
136 | { |
137 | struct radeonfb_info *rinfo = info->par; |
138 | struct fb_copyarea modded; |
139 | u32 vxres, vyres; |
140 | modded.sx = area->sx; |
141 | modded.sy = area->sy; |
142 | modded.dx = area->dx; |
143 | modded.dy = area->dy; |
144 | modded.width = area->width; |
145 | modded.height = area->height; |
146 | |
147 | if (info->state != FBINFO_STATE_RUNNING) |
148 | return; |
149 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
150 | cfb_copyarea(info, area); |
151 | return; |
152 | } |
153 | |
154 | radeon_fixup_offset(rinfo); |
155 | |
156 | vxres = info->var.xres_virtual; |
157 | vyres = info->var.yres_virtual; |
158 | |
159 | if(!modded.width || !modded.height || |
160 | modded.sx >= vxres || modded.sy >= vyres || |
161 | modded.dx >= vxres || modded.dy >= vyres) |
162 | return; |
163 | |
164 | if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx; |
165 | if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; |
166 | if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy; |
167 | if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; |
168 | |
169 | radeonfb_prim_copyarea(rinfo, area: &modded); |
170 | } |
171 | |
172 | void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image) |
173 | { |
174 | struct radeonfb_info *rinfo = info->par; |
175 | |
176 | if (info->state != FBINFO_STATE_RUNNING) |
177 | return; |
178 | radeon_engine_idle(); |
179 | |
180 | cfb_imageblit(info, image); |
181 | } |
182 | |
183 | int radeonfb_sync(struct fb_info *info) |
184 | { |
185 | struct radeonfb_info *rinfo = info->par; |
186 | |
187 | if (info->state != FBINFO_STATE_RUNNING) |
188 | return 0; |
189 | radeon_engine_idle(); |
190 | |
191 | return 0; |
192 | } |
193 | |
194 | void radeonfb_engine_reset(struct radeonfb_info *rinfo) |
195 | { |
196 | u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; |
197 | u32 host_path_cntl; |
198 | |
199 | radeon_engine_flush (rinfo); |
200 | |
201 | clock_cntl_index = INREG(CLOCK_CNTL_INDEX); |
202 | mclk_cntl = INPLL(MCLK_CNTL); |
203 | |
204 | OUTPLL(MCLK_CNTL, (mclk_cntl | |
205 | FORCEON_MCLKA | |
206 | FORCEON_MCLKB | |
207 | FORCEON_YCLKA | |
208 | FORCEON_YCLKB | |
209 | FORCEON_MC | |
210 | FORCEON_AIC)); |
211 | |
212 | host_path_cntl = INREG(HOST_PATH_CNTL); |
213 | rbbm_soft_reset = INREG(RBBM_SOFT_RESET); |
214 | |
215 | if (IS_R300_VARIANT(rinfo)) { |
216 | u32 tmp; |
217 | |
218 | OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset | |
219 | SOFT_RESET_CP | |
220 | SOFT_RESET_HI | |
221 | SOFT_RESET_E2)); |
222 | INREG(RBBM_SOFT_RESET); |
223 | OUTREG(RBBM_SOFT_RESET, 0); |
224 | tmp = INREG(RB2D_DSTCACHE_MODE); |
225 | OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */ |
226 | } else { |
227 | OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | |
228 | SOFT_RESET_CP | |
229 | SOFT_RESET_HI | |
230 | SOFT_RESET_SE | |
231 | SOFT_RESET_RE | |
232 | SOFT_RESET_PP | |
233 | SOFT_RESET_E2 | |
234 | SOFT_RESET_RB); |
235 | INREG(RBBM_SOFT_RESET); |
236 | OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32) |
237 | ~(SOFT_RESET_CP | |
238 | SOFT_RESET_HI | |
239 | SOFT_RESET_SE | |
240 | SOFT_RESET_RE | |
241 | SOFT_RESET_PP | |
242 | SOFT_RESET_E2 | |
243 | SOFT_RESET_RB)); |
244 | INREG(RBBM_SOFT_RESET); |
245 | } |
246 | |
247 | OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET); |
248 | INREG(HOST_PATH_CNTL); |
249 | OUTREG(HOST_PATH_CNTL, host_path_cntl); |
250 | |
251 | if (!IS_R300_VARIANT(rinfo)) |
252 | OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); |
253 | |
254 | OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); |
255 | OUTPLL(MCLK_CNTL, mclk_cntl); |
256 | } |
257 | |
258 | void radeonfb_engine_init (struct radeonfb_info *rinfo) |
259 | { |
260 | unsigned long temp; |
261 | |
262 | /* disable 3D engine */ |
263 | OUTREG(RB3D_CNTL, 0); |
264 | |
265 | radeonfb_engine_reset(rinfo); |
266 | |
267 | radeon_fifo_wait (1); |
268 | if (IS_R300_VARIANT(rinfo)) { |
269 | OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | |
270 | RB2D_DC_AUTOFLUSH_ENABLE | |
271 | RB2D_DC_DC_DISABLE_IGNORE_PE); |
272 | } else { |
273 | /* This needs to be double checked with ATI. Latest X driver |
274 | * completely "forgets" to set this register on < r3xx, and |
275 | * we used to just write 0 there... I'll keep the 0 and update |
276 | * that when we have sorted things out on X side. |
277 | */ |
278 | OUTREG(RB2D_DSTCACHE_MODE, 0); |
279 | } |
280 | |
281 | radeon_fifo_wait (3); |
282 | /* We re-read MC_FB_LOCATION from card as it can have been |
283 | * modified by XFree drivers (ouch !) |
284 | */ |
285 | rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; |
286 | |
287 | OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) | |
288 | (rinfo->fb_local_base >> 10)); |
289 | OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); |
290 | OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); |
291 | |
292 | radeon_fifo_wait (1); |
293 | #if defined(__BIG_ENDIAN) |
294 | OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); |
295 | #else |
296 | OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); |
297 | #endif |
298 | radeon_fifo_wait (2); |
299 | OUTREG(DEFAULT_SC_TOP_LEFT, 0); |
300 | OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
301 | DEFAULT_SC_BOTTOM_MAX)); |
302 | |
303 | temp = radeon_get_dstbpp(depth: rinfo->depth); |
304 | rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS); |
305 | |
306 | radeon_fifo_wait (1); |
307 | OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | |
308 | GMC_BRUSH_SOLID_COLOR | |
309 | GMC_SRC_DATATYPE_COLOR)); |
310 | |
311 | radeon_fifo_wait (7); |
312 | |
313 | /* clear line drawing regs */ |
314 | OUTREG(DST_LINE_START, 0); |
315 | OUTREG(DST_LINE_END, 0); |
316 | |
317 | /* set brush color regs */ |
318 | OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); |
319 | OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); |
320 | |
321 | /* set source color regs */ |
322 | OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); |
323 | OUTREG(DP_SRC_BKGD_CLR, 0x00000000); |
324 | |
325 | /* default write mask */ |
326 | OUTREG(DP_WRITE_MSK, 0xffffffff); |
327 | |
328 | radeon_engine_idle (); |
329 | } |
330 | |