| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef CARMINE_CARMINE_H |
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| 3 | #define CARMINE_CARMINE_H |
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| 4 | |
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| 5 | #define CARMINE_MEMORY_BAR 2 |
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| 6 | #define CARMINE_CONFIG_BAR 3 |
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| 7 | |
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| 8 | #define MAX_DISPLAY 2 |
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| 9 | #define CARMINE_DISPLAY_MEM (800 * 600 * 4) |
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| 10 | #define CARMINE_TOTAL_DIPLAY_MEM (CARMINE_DISPLAY_MEM * MAX_DISPLAY) |
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| 11 | |
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| 12 | #define CARMINE_USE_DISPLAY0 (1 << 0) |
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| 13 | #define CARMINE_USE_DISPLAY1 (1 << 1) |
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| 14 | |
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| 15 | /* |
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| 16 | * This values work on the eval card. Custom boards may use different timings, |
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| 17 | * here an example :) |
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| 18 | */ |
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| 19 | |
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| 20 | /* DRAM initialization values */ |
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| 21 | #ifdef CONFIG_FB_CARMINE_DRAM_EVAL |
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| 22 | |
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| 23 | #define CARMINE_DFLT_IP_CLOCK_ENABLE (0x03ff) |
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| 24 | #define CARMINE_DFLT_IP_DCTL_ADD (0x05c3) |
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| 25 | #define CARMINE_DFLT_IP_DCTL_MODE (0x0121) |
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| 26 | #define CARMINE_DFLT_IP_DCTL_EMODE (0x8000) |
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| 27 | #define CARMINE_DFLT_IP_DCTL_SET_TIME1 (0x4749) |
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| 28 | #define CARMINE_DFLT_IP_DCTL_SET_TIME2 (0x2a22) |
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| 29 | #define CARMINE_DFLT_IP_DCTL_REFRESH (0x0042) |
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| 30 | #define CARMINE_DFLT_IP_DCTL_STATES (0x0003) |
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| 31 | #define CARMINE_DFLT_IP_DCTL_RESERVE0 (0x0020) |
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| 32 | #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH (0x000f) |
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| 33 | #define CARMINE_DFLT_IP_DCTL_RESERVE2 (0x0000) |
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| 34 | #define CARMINE_DFLT_IP_DCTL_DDRIF1 (0x6646) |
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| 35 | #define CARMINE_DFLT_IP_DCTL_DDRIF2 (0x0055) |
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| 36 | #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST (0x0021) |
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| 37 | #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST (0x0002) |
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| 38 | #define CARMINE_DFLT_IP_DCTL_IO_CONT0 (0x0555) |
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| 39 | #define CARMINE_DFLT_IP_DCTL_IO_CONT1 (0x0555) |
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| 40 | #define CARMINE_DCTL_DLL_RESET (1) |
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| 41 | #endif |
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| 42 | |
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| 43 | #ifdef CONFIG_CARMINE_DRAM_CUSTOM |
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| 44 | |
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| 45 | #define CARMINE_DFLT_IP_CLOCK_ENABLE (0x03ff) |
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| 46 | #define CARMINE_DFLT_IP_DCTL_ADD (0x03b2) |
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| 47 | #define CARMINE_DFLT_IP_DCTL_MODE (0x0161) |
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| 48 | #define CARMINE_DFLT_IP_DCTL_EMODE (0x8000) |
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| 49 | #define CARMINE_DFLT_IP_DCTL_SET_TIME1 (0x2628) |
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| 50 | #define CARMINE_DFLT_IP_DCTL_SET_TIME2 (0x1a09) |
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| 51 | #define CARMINE_DFLT_IP_DCTL_REFRESH (0x00fe) |
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| 52 | #define CARMINE_DFLT_IP_DCTL_STATES (0x0003) |
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| 53 | #define CARMINE_DFLT_IP_DCTL_RESERVE0 (0x0020) |
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| 54 | #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH (0x000f) |
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| 55 | #define CARMINE_DFLT_IP_DCTL_RESERVE2 (0x0000) |
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| 56 | #define CARMINE_DFLT_IP_DCTL_DDRIF1 (0x0646) |
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| 57 | #define CARMINE_DFLT_IP_DCTL_DDRIF2 (0x55aa) |
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| 58 | #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST (0x0061) |
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| 59 | #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST (0x0002) |
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| 60 | #define CARMINE_DFLT_IP_DCTL_IO_CONT0 (0x0555) |
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| 61 | #define CARMINE_DFLT_IP_DCTL_IO_CONT1 (0x0555) |
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| 62 | #define CARMINE_DCTL_DLL_RESET (1) |
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| 63 | #endif |
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| 64 | |
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| 65 | #endif |
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| 66 | |
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