| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef _CARMINEFB_REGS_H |
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| 3 | #define _CARMINEFB_REGS_H |
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| 4 | |
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| 5 | #define CARMINE_OVERLAY_EXT_MODE (0x00000002) |
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| 6 | #define CARMINE_GRAPH_REG (0x00000000) |
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| 7 | #define CARMINE_DISP0_REG (0x00100000) |
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| 8 | #define CARMINE_DISP1_REG (0x00140000) |
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| 9 | #define CARMINE_WB_REG (0x00180000) |
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| 10 | #define CARMINE_DCTL_REG (0x00300000) |
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| 11 | #define CARMINE_CTL_REG (0x00400000) |
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| 12 | #define CARMINE_WINDOW_MODE (0x00000001) |
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| 13 | #define CARMINE_EXTEND_MODE (CARMINE_WINDOW_MODE | \ |
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| 14 | CARMINE_OVERLAY_EXT_MODE) |
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| 15 | #define CARMINE_L0E (1 << 16) |
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| 16 | #define CARMINE_L2E (1 << 18) |
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| 17 | #define CARMINE_DEN (1 << 31) |
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| 18 | |
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| 19 | #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000) |
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| 20 | #define CARMINE_DCTL_REG_MODE_ADD (0x00) |
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| 21 | #define CARMINE_DCTL_REG_SETTIME1_EMODE (0x04) |
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| 22 | #define CARMINE_DCTL_REG_REFRESH_SETTIME2 (0x08) |
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| 23 | #define CARMINE_DCTL_REG_RSV0_STATES (0x0C) |
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| 24 | #define CARMINE_DCTL_REG_RSV2_RSV1 (0x10) |
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| 25 | #define CARMINE_DCTL_REG_DDRIF2_DDRIF1 (0x14) |
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| 26 | #define CARMINE_DCTL_REG_IOCONT1_IOCONT0 (0x24) |
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| 27 | #define CARMINE_DCTL_REG_STATES_MASK (0x000F) |
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| 28 | #define CARMINE_DCTL_INIT_WAIT_INTERVAL (1) |
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| 29 | #define CARMINE_DCTL_INIT_WAIT_LIMIT (5000) |
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| 30 | #define CARMINE_WB_REG_WBM_DEFAULT (0x0001c020) |
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| 31 | #define CARMINE_DISP_REG_L0RM (0x1880) |
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| 32 | #define CARMINE_DISP_REG_L0PX (0x1884) |
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| 33 | #define CARMINE_DISP_REG_L0PY (0x1888) |
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| 34 | #define CARMINE_DISP_REG_L2RM (0x18A0) |
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| 35 | #define CARMINE_DISP_REG_L2PX (0x18A4) |
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| 36 | #define CARMINE_DISP_REG_L2PY (0x18A8) |
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| 37 | #define CARMINE_DISP_REG_L3RM (0x18B0) |
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| 38 | #define CARMINE_DISP_REG_L3PX (0x18B4) |
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| 39 | #define CARMINE_DISP_REG_L3PY (0x18B8) |
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| 40 | #define CARMINE_DISP_REG_L4RM (0x18C0) |
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| 41 | #define CARMINE_DISP_REG_L4PX (0x18C4) |
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| 42 | #define CARMINE_DISP_REG_L4PY (0x18C8) |
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| 43 | #define CARMINE_DISP_REG_L5RM (0x18D0) |
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| 44 | #define CARMINE_DISP_REG_L5PX (0x18D4) |
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| 45 | #define CARMINE_DISP_REG_L5PY (0x18D8) |
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| 46 | #define CARMINE_DISP_REG_L6RM (0x1924) |
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| 47 | #define CARMINE_DISP_REG_L6PX (0x1928) |
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| 48 | #define CARMINE_DISP_REG_L6PY (0x192C) |
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| 49 | #define CARMINE_DISP_REG_L7RM (0x1964) |
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| 50 | #define CARMINE_DISP_REG_L7PX (0x1968) |
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| 51 | #define CARMINE_DISP_REG_L7PY (0x196C) |
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| 52 | #define CARMINE_WB_REG_WBM (0x0004) |
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| 53 | #define CARMINE_DISP_HTP_SHIFT (16) |
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| 54 | #define CARMINE_DISP_HDB_SHIFT (16) |
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| 55 | #define CARMINE_DISP_HSW_SHIFT (16) |
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| 56 | #define CARMINE_DISP_VSW_SHIFT (24) |
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| 57 | #define CARMINE_DISP_VTR_SHIFT (16) |
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| 58 | #define CARMINE_DISP_VDP_SHIFT (16) |
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| 59 | #define CARMINE_CURSOR_CUTZ_MASK (0x00000100) |
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| 60 | #define CARMINE_CURSOR0_PRIORITY_MASK (0x00010000) |
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| 61 | #define CARMINE_CURSOR1_PRIORITY_MASK (0x00020000) |
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| 62 | #define CARMINE_DISP_WIDTH_SHIFT (16) |
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| 63 | #define CARMINE_DISP_WIN_H_SHIFT (16) |
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| 64 | #define CARMINE_DISP_REG_H_TOTAL (0x0004) |
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| 65 | #define CARMINE_DISP_REG_H_PERIOD (0x0008) |
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| 66 | #define CARMINE_DISP_REG_V_H_W_H_POS (0x000C) |
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| 67 | #define CARMINE_DISP_REG_V_TOTAL (0x0010) |
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| 68 | #define CARMINE_DISP_REG_V_PERIOD_POS (0x0014) |
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| 69 | #define CARMINE_DISP_REG_L0_MODE_W_H (0x0020) |
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| 70 | #define CARMINE_DISP_REG_L0_ORG_ADR (0x0024) |
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| 71 | #define CARMINE_DISP_REG_L0_DISP_ADR (0x0028) |
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| 72 | #define CARMINE_DISP_REG_L0_DISP_POS (0x002C) |
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| 73 | #define CARMINE_DISP_REG_L1_WIDTH (0x0030) |
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| 74 | #define CARMINE_DISP_REG_L1_ORG_ADR (0x0034) |
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| 75 | #define CARMINE_DISP_REG_L2_MODE_W_H (0x0040) |
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| 76 | #define CARMINE_DISP_REG_L2_ORG_ADR1 (0x0044) |
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| 77 | #define CARMINE_DISP_REG_L2_DISP_ADR1 (0x0048) |
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| 78 | #define CARMINE_DISP_REG_L2_DISP_POS (0x0054) |
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| 79 | #define CARMINE_DISP_REG_L3_MODE_W_H (0x0058) |
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| 80 | #define CARMINE_DISP_REG_L3_ORG_ADR1 (0x005C) |
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| 81 | #define CARMINE_DISP_REG_L3_DISP_ADR1 (0x0060) |
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| 82 | #define CARMINE_DISP_REG_L3_DISP_POS (0x006C) |
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| 83 | #define CARMINE_DISP_REG_L4_MODE_W_H (0x0070) |
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| 84 | #define CARMINE_DISP_REG_L4_ORG_ADR1 (0x0074) |
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| 85 | #define CARMINE_DISP_REG_L4_DISP_ADR1 (0x0078) |
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| 86 | #define CARMINE_DISP_REG_L4_DISP_POS (0x0084) |
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| 87 | #define CARMINE_DISP_REG_L5_MODE_W_H (0x0088) |
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| 88 | #define CARMINE_DISP_REG_L5_ORG_ADR1 (0x008C) |
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| 89 | #define CARMINE_DISP_REG_L5_DISP_ADR1 (0x0090) |
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| 90 | #define CARMINE_DISP_REG_L5_DISP_POS (0x009C) |
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| 91 | #define CARMINE_DISP_REG_CURSOR_MODE (0x00A0) |
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| 92 | #define CARMINE_DISP_REG_CUR1_POS (0x00A8) |
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| 93 | #define CARMINE_DISP_REG_CUR2_POS (0x00B0) |
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| 94 | #define CARMINE_DISP_REG_C_TRANS (0x00BC) |
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| 95 | #define CARMINE_DISP_REG_MLMR_TRANS (0x00C0) |
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| 96 | #define CARMINE_DISP_REG_L0_EXT_MODE (0x0110) |
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| 97 | #define CARMINE_DISP_REG_L0_WIN_POS (0x0114) |
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| 98 | #define CARMINE_DISP_REG_L0_WIN_SIZE (0x0118) |
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| 99 | #define CARMINE_DISP_REG_L1_EXT_MODE (0x0120) |
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| 100 | #define CARMINE_DISP_REG_L1_WIN_POS (0x0124) |
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| 101 | #define CARMINE_DISP_REG_L1_WIN_SIZE (0x0128) |
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| 102 | #define CARMINE_DISP_REG_L2_EXT_MODE (0x0130) |
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| 103 | #define CARMINE_DISP_REG_L2_WIN_POS (0x0134) |
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| 104 | #define CARMINE_DISP_REG_L2_WIN_SIZE (0x0138) |
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| 105 | #define CARMINE_DISP_REG_L3_EXT_MODE (0x0140) |
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| 106 | #define CARMINE_DISP_REG_L3_WIN_POS (0x0144) |
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| 107 | #define CARMINE_DISP_REG_L3_WIN_SIZE (0x0148) |
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| 108 | #define CARMINE_DISP_REG_L4_EXT_MODE (0x0150) |
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| 109 | #define CARMINE_DISP_REG_L4_WIN_POS (0x0154) |
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| 110 | #define CARMINE_DISP_REG_L4_WIN_SIZE (0x0158) |
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| 111 | #define CARMINE_DISP_REG_L5_EXT_MODE (0x0160) |
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| 112 | #define CARMINE_DISP_REG_L5_WIN_POS (0x0164) |
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| 113 | #define CARMINE_DISP_REG_L5_WIN_SIZE (0x0168) |
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| 114 | #define CARMINE_DISP_REG_L6_EXT_MODE (0x1918) |
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| 115 | #define CARMINE_DISP_REG_L6_WIN_POS (0x191c) |
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| 116 | #define CARMINE_DISP_REG_L6_WIN_SIZE (0x1920) |
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| 117 | #define CARMINE_DISP_REG_L7_EXT_MODE (0x1958) |
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| 118 | #define CARMINE_DISP_REG_L7_WIN_POS (0x195c) |
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| 119 | #define CARMINE_DISP_REG_L7_WIN_SIZE (0x1960) |
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| 120 | #define CARMINE_DISP_REG_BLEND_MODE_L0 (0x00B4) |
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| 121 | #define CARMINE_DISP_REG_BLEND_MODE_L1 (0x0188) |
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| 122 | #define CARMINE_DISP_REG_BLEND_MODE_L2 (0x018C) |
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| 123 | #define CARMINE_DISP_REG_BLEND_MODE_L3 (0x0190) |
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| 124 | #define CARMINE_DISP_REG_BLEND_MODE_L4 (0x0194) |
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| 125 | #define CARMINE_DISP_REG_BLEND_MODE_L5 (0x0198) |
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| 126 | #define CARMINE_DISP_REG_BLEND_MODE_L6 (0x1990) |
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| 127 | #define CARMINE_DISP_REG_BLEND_MODE_L7 (0x1994) |
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| 128 | #define CARMINE_DISP_REG_L0_TRANS (0x01A0) |
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| 129 | #define CARMINE_DISP_REG_L1_TRANS (0x01A4) |
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| 130 | #define CARMINE_DISP_REG_L2_TRANS (0x01A8) |
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| 131 | #define CARMINE_DISP_REG_L3_TRANS (0x01AC) |
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| 132 | #define CARMINE_DISP_REG_L4_TRANS (0x01B0) |
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| 133 | #define CARMINE_DISP_REG_L5_TRANS (0x01B4) |
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| 134 | #define CARMINE_DISP_REG_L6_TRANS (0x1998) |
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| 135 | #define CARMINE_DISP_REG_L7_TRANS (0x199c) |
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| 136 | #define CARMINE_EXTEND_MODE_MASK (0x00000003) |
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| 137 | #define CARMINE_DISP_DCM_MASK (0x0000FFFF) |
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| 138 | #define CARMINE_DISP_REG_DCM1 (0x0100) |
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| 139 | #define CARMINE_DISP_WIDTH_UNIT (64) |
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| 140 | #define CARMINE_DISP_REG_L6_MODE_W_H (0x1900) |
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| 141 | #define CARMINE_DISP_REG_L6_ORG_ADR1 (0x1904) |
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| 142 | #define CARMINE_DISP_REG_L6_DISP_ADR0 (0x1908) |
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| 143 | #define CARMINE_DISP_REG_L6_DISP_POS (0x1914) |
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| 144 | #define CARMINE_DISP_REG_L7_MODE_W_H (0x1940) |
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| 145 | #define CARMINE_DISP_REG_L7_ORG_ADR1 (0x1944) |
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| 146 | #define CARMINE_DISP_REG_L7_DISP_ADR0 (0x1948) |
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| 147 | #define CARMINE_DISP_REG_L7_DISP_POS (0x1954) |
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| 148 | #define CARMINE_CTL_REG_CLOCK_ENABLE (0x000C) |
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| 149 | #define CARMINE_CTL_REG_SOFTWARE_RESET (0x0010) |
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| 150 | #define CARMINE_CTL_REG_IST_MASK_ALL (0x07FFFFFF) |
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| 151 | #define CARMINE_GRAPH_REG_VRINTM (0x00028064) |
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| 152 | #define CARMINE_GRAPH_REG_VRERRM (0x0002806C) |
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| 153 | #define CARMINE_GRAPH_REG_DC_OFFSET_PX (0x0004005C) |
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| 154 | #define CARMINE_GRAPH_REG_DC_OFFSET_PY (0x00040060) |
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| 155 | #define CARMINE_GRAPH_REG_DC_OFFSET_LX (0x00040064) |
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| 156 | #define CARMINE_GRAPH_REG_DC_OFFSET_LY (0x00040068) |
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| 157 | #define CARMINE_GRAPH_REG_DC_OFFSET_TX (0x0004006C) |
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| 158 | #define CARMINE_GRAPH_REG_DC_OFFSET_TY (0x00040070) |
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| 159 | |
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| 160 | #endif |
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| 161 | |
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